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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK13// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s4// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK15// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK36// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s7// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK38 9// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"10// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s11// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"12// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"13// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s14// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"15 16// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK917// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s18// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++  -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK919 20// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"21// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s22// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++  -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"23 24// expected-no-diagnostics25#ifndef HEADER26#define HEADER27 28struct St {29  int a, b;30  St() : a(0), b(0) {}31  St(const St &st) : a(st.a + st.b), b(0) {}32  ~St() {}33};34 35volatile int g = 1212;36volatile int &g1 = g;37 38template <class T>39struct S {40  T f;41  S(T a) : f(a + g) {}42  S() : f(g) {}43  S(const S &s, St t = St()) : f(s.f + t.a) {}44  operator T() { return T(); }45  ~S() {}46};47 48 49template <typename T>50T tmain() {51  S<T> test;52  T t_var = T();53  T vec[] = {1, 2};54  S<T> s_arr[] = {1, 2};55  S<T> &var = test;56#pragma omp target teams distribute firstprivate(t_var, vec, s_arr, var)57  for (int i = 0; i < 2; ++i) {58    vec[i] = t_var;59    s_arr[i] = var;60  }61  return T();62}63 64S<float> test;65int t_var = 333;66int vec[] = {1, 2};67S<float> s_arr[] = {1, 2};68S<float> var(3);69 70int main() {71  static int sivar;72#ifdef LAMBDA73  [&]() {74#pragma omp target teams distribute firstprivate(g, g1, sivar)75  for (int i = 0; i < 2; ++i) {76 77    // Skip global and bound tid vars78    // skip loop vars79    g = 1;80    g1 = 1;81    sivar = 2;82    [&]() {83      g = 2;84      g1 = 2;85      sivar = 4;86 87    }();88  }89  }();90  return 0;91#else92#pragma omp target teams distribute firstprivate(t_var, vec, s_arr, var, sivar)93  for (int i = 0; i < 2; ++i) {94    vec[i] = t_var;95    s_arr[i] = var;96    sivar += i;97  }98  return tmain<int>();99#endif100}101 102 103 104 105 106// Skip global and bound tid vars107// Skip temp vars for loop108 109// param copy110 111// T_VAR and SIVAR112 113// preparation vars114 115// firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2116 117// firstprivate(s_arr)118 119// firstprivate(var)120 121 122 123 124 125 126// Skip global and bound tid vars127// Skip temp vars for loop128 129// param copy130 131// T_VAR and preparation variables132 133 134// firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2135 136// firstprivate(s_arr)137 138// firstprivate(var)139 140 141#endif142// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init143// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {144// CHECK1-NEXT:  entry:145// CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)146// CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]147// CHECK1-NEXT:    ret void148//149//150// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev151// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {152// CHECK1-NEXT:  entry:153// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8154// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8155// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8156// CHECK1-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])157// CHECK1-NEXT:    ret void158//159//160// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev161// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {162// CHECK1-NEXT:  entry:163// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8164// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8165// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8166// CHECK1-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]167// CHECK1-NEXT:    ret void168//169//170// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev171// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {172// CHECK1-NEXT:  entry:173// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8174// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8175// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8176// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0177// CHECK1-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4178// CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float179// CHECK1-NEXT:    store float [[CONV]], ptr [[F]], align 4180// CHECK1-NEXT:    ret void181//182//183// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev184// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {185// CHECK1-NEXT:  entry:186// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8187// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8188// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8189// CHECK1-NEXT:    ret void190//191//192// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1193// CHECK1-SAME: () #[[ATTR0]] {194// CHECK1-NEXT:  entry:195// CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)196// CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)197// CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]198// CHECK1-NEXT:    ret void199//200//201// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef202// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {203// CHECK1-NEXT:  entry:204// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8205// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4206// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8207// CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4208// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8209// CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4210// CHECK1-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])211// CHECK1-NEXT:    ret void212//213//214// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor215// CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {216// CHECK1-NEXT:  entry:217// CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8218// CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8219// CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]220// CHECK1:       arraydestroy.body:221// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]222// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1223// CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]224// CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr225// CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]226// CHECK1:       arraydestroy.done1:227// CHECK1-NEXT:    ret void228//229//230// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef231// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {232// CHECK1-NEXT:  entry:233// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8234// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4235// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8236// CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4237// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8238// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0239// CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4240// CHECK1-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4241// CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float242// CHECK1-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]243// CHECK1-NEXT:    store float [[ADD]], ptr [[F]], align 4244// CHECK1-NEXT:    ret void245//246//247// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2248// CHECK1-SAME: () #[[ATTR0]] {249// CHECK1-NEXT:  entry:250// CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)251// CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]252// CHECK1-NEXT:    ret void253//254//255// CHECK1-LABEL: define {{[^@]+}}@main256// CHECK1-SAME: () #[[ATTR3:[0-9]+]] {257// CHECK1-NEXT:  entry:258// CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4259// CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8260// CHECK1-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 8261// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8262// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8263// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8264// CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4265// CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8266// CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4267// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr @t_var, align 4268// CHECK1-NEXT:    store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4269// CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8270// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4271// CHECK1-NEXT:    store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4272// CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8273// CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0274// CHECK1-NEXT:    store ptr @vec, ptr [[TMP4]], align 8275// CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0276// CHECK1-NEXT:    store ptr @vec, ptr [[TMP5]], align 8277// CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0278// CHECK1-NEXT:    store ptr null, ptr [[TMP6]], align 8279// CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1280// CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP7]], align 8281// CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1282// CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP8]], align 8283// CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1284// CHECK1-NEXT:    store ptr null, ptr [[TMP9]], align 8285// CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2286// CHECK1-NEXT:    store ptr @s_arr, ptr [[TMP10]], align 8287// CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2288// CHECK1-NEXT:    store ptr @s_arr, ptr [[TMP11]], align 8289// CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2290// CHECK1-NEXT:    store ptr null, ptr [[TMP12]], align 8291// CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3292// CHECK1-NEXT:    store ptr @var, ptr [[TMP13]], align 8293// CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3294// CHECK1-NEXT:    store ptr @var, ptr [[TMP14]], align 8295// CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3296// CHECK1-NEXT:    store ptr null, ptr [[TMP15]], align 8297// CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4298// CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP16]], align 8299// CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4300// CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP17]], align 8301// CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4302// CHECK1-NEXT:    store ptr null, ptr [[TMP18]], align 8303// CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0304// CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0305// CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0306// CHECK1-NEXT:    store i32 3, ptr [[TMP21]], align 4307// CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1308// CHECK1-NEXT:    store i32 5, ptr [[TMP22]], align 4309// CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2310// CHECK1-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 8311// CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3312// CHECK1-NEXT:    store ptr [[TMP20]], ptr [[TMP24]], align 8313// CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4314// CHECK1-NEXT:    store ptr @.offload_sizes, ptr [[TMP25]], align 8315// CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5316// CHECK1-NEXT:    store ptr @.offload_maptypes, ptr [[TMP26]], align 8317// CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6318// CHECK1-NEXT:    store ptr null, ptr [[TMP27]], align 8319// CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7320// CHECK1-NEXT:    store ptr null, ptr [[TMP28]], align 8321// CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8322// CHECK1-NEXT:    store i64 2, ptr [[TMP29]], align 8323// CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9324// CHECK1-NEXT:    store i64 0, ptr [[TMP30]], align 8325// CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10326// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4327// CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11328// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4329// CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12330// CHECK1-NEXT:    store i32 0, ptr [[TMP33]], align 4331// CHECK1-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.region_id, ptr [[KERNEL_ARGS]])332// CHECK1-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0333// CHECK1-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]334// CHECK1:       omp_offload.failed:335// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92(ptr @vec, i64 [[TMP1]], ptr @s_arr, ptr @var, i64 [[TMP3]]) #[[ATTR2]]336// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]337// CHECK1:       omp_offload.cont:338// CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()339// CHECK1-NEXT:    ret i32 [[CALL]]340//341//342// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92343// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {344// CHECK1-NEXT:  entry:345// CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8346// CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8347// CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8348// CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8349// CHECK1-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8350// CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8351// CHECK1-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 8352// CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8353// CHECK1-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8354// CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8355// CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8356// CHECK1-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8357// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]]358// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]359// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]360// CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4361// CHECK1-NEXT:    store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4362// CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8363// CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4364// CHECK1-NEXT:    store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4365// CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8366// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i64 [[TMP6]])367// CHECK1-NEXT:    ret void368//369//370// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.omp_outlined371// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] {372// CHECK1-NEXT:  entry:373// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8374// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8375// CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8376// CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8377// CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8378// CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8379// CHECK1-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8380// CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4381// CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4382// CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4383// CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4384// CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4385// CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4386// CHECK1-NEXT:    [[VEC1:%.*]] = alloca [2 x i32], align 4387// CHECK1-NEXT:    [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4388// CHECK1-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4389// CHECK1-NEXT:    [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4390// CHECK1-NEXT:    [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4391// CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4392// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8393// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8394// CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8395// CHECK1-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8396// CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8397// CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8398// CHECK1-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8399// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]400// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]401// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]402// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4403// CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4404// CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4405// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4406// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false)407// CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0408// CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2409// CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]410// CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]411// CHECK1:       omp.arraycpy.body:412// CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]413// CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]414// CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])415// CHECK1-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])416// CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]417// CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1418// CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1419// CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]420// CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]421// CHECK1:       omp.arraycpy.done3:422// CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]])423// CHECK1-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]])424// CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]425// CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8426// CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4427// CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)428// CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4429// CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1430// CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]431// CHECK1:       cond.true:432// CHECK1-NEXT:    br label [[COND_END:%.*]]433// CHECK1:       cond.false:434// CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4435// CHECK1-NEXT:    br label [[COND_END]]436// CHECK1:       cond.end:437// CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]438// CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4439// CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4440// CHECK1-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4441// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]442// CHECK1:       omp.inner.for.cond:443// CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4444// CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4445// CHECK1-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]446// CHECK1-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]447// CHECK1:       omp.inner.for.cond.cleanup:448// CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]449// CHECK1:       omp.inner.for.body:450// CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4451// CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1452// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]453// CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4454// CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4455// CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4456// CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64457// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 [[IDXPROM]]458// CHECK1-NEXT:    store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4459// CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I]], align 4460// CHECK1-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64461// CHECK1-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i64 0, i64 [[IDXPROM7]]462// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[VAR4]], i64 4, i1 false)463// CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4464// CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4465// CHECK1-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]466// CHECK1-NEXT:    store i32 [[ADD9]], ptr [[SIVAR_ADDR]], align 4467// CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]468// CHECK1:       omp.body.continue:469// CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]470// CHECK1:       omp.inner.for.inc:471// CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4472// CHECK1-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP17]], 1473// CHECK1-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4474// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]475// CHECK1:       omp.inner.for.end:476// CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]477// CHECK1:       omp.loop.exit:478// CHECK1-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8479// CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4480// CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]])481// CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]482// CHECK1-NEXT:    [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0483// CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2484// CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]485// CHECK1:       arraydestroy.body:486// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]487// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1488// CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]489// CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]490// CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]491// CHECK1:       arraydestroy.done12:492// CHECK1-NEXT:    ret void493//494//495// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev496// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {497// CHECK1-NEXT:  entry:498// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8499// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8500// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8501// CHECK1-NEXT:    call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])502// CHECK1-NEXT:    ret void503//504//505// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St506// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {507// CHECK1-NEXT:  entry:508// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8509// CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8510// CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8511// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8512// CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8513// CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8514// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8515// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8516// CHECK1-NEXT:    call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])517// CHECK1-NEXT:    ret void518//519//520// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev521// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {522// CHECK1-NEXT:  entry:523// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8524// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8525// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8526// CHECK1-NEXT:    call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]527// CHECK1-NEXT:    ret void528//529//530// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v531// CHECK1-SAME: () #[[ATTR1]] comdat {532// CHECK1-NEXT:  entry:533// CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4534// CHECK1-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4535// CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4536// CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4537// CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4538// CHECK1-NEXT:    [[VAR:%.*]] = alloca ptr, align 8539// CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 8540// CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8541// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8542// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8543// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8544// CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4545// CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8546// CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])547// CHECK1-NEXT:    store i32 0, ptr [[T_VAR]], align 4548// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)549// CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1)550// CHECK1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1551// CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)552// CHECK1-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8553// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META7]], !align [[META8]]554// CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 8555// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4556// CHECK1-NEXT:    store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4557// CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8558// CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]559// CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0560// CHECK1-NEXT:    store ptr [[VEC]], ptr [[TMP4]], align 8561// CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0562// CHECK1-NEXT:    store ptr [[VEC]], ptr [[TMP5]], align 8563// CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0564// CHECK1-NEXT:    store ptr null, ptr [[TMP6]], align 8565// CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1566// CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP7]], align 8567// CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1568// CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP8]], align 8569// CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1570// CHECK1-NEXT:    store ptr null, ptr [[TMP9]], align 8571// CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2572// CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[TMP10]], align 8573// CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2574// CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[TMP11]], align 8575// CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2576// CHECK1-NEXT:    store ptr null, ptr [[TMP12]], align 8577// CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3578// CHECK1-NEXT:    store ptr [[TMP3]], ptr [[TMP13]], align 8579// CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3580// CHECK1-NEXT:    store ptr [[TMP3]], ptr [[TMP14]], align 8581// CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3582// CHECK1-NEXT:    store ptr null, ptr [[TMP15]], align 8583// CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0584// CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0585// CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0586// CHECK1-NEXT:    store i32 3, ptr [[TMP18]], align 4587// CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1588// CHECK1-NEXT:    store i32 4, ptr [[TMP19]], align 4589// CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2590// CHECK1-NEXT:    store ptr [[TMP16]], ptr [[TMP20]], align 8591// CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3592// CHECK1-NEXT:    store ptr [[TMP17]], ptr [[TMP21]], align 8593// CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4594// CHECK1-NEXT:    store ptr @.offload_sizes.3, ptr [[TMP22]], align 8595// CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5596// CHECK1-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP23]], align 8597// CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6598// CHECK1-NEXT:    store ptr null, ptr [[TMP24]], align 8599// CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7600// CHECK1-NEXT:    store ptr null, ptr [[TMP25]], align 8601// CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8602// CHECK1-NEXT:    store i64 2, ptr [[TMP26]], align 8603// CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9604// CHECK1-NEXT:    store i64 0, ptr [[TMP27]], align 8605// CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10606// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4607// CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11608// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP29]], align 4609// CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12610// CHECK1-NEXT:    store i32 0, ptr [[TMP30]], align 4611// CHECK1-NEXT:    [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])612// CHECK1-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0613// CHECK1-NEXT:    br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]614// CHECK1:       omp_offload.failed:615// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(ptr [[VEC]], i64 [[TMP2]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]]616// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]617// CHECK1:       omp_offload.cont:618// CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4619// CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0620// CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2621// CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]622// CHECK1:       arraydestroy.body:623// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]624// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1625// CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]626// CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]627// CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]628// CHECK1:       arraydestroy.done2:629// CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]630// CHECK1-NEXT:    [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4631// CHECK1-NEXT:    ret i32 [[TMP34]]632//633//634// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev635// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {636// CHECK1-NEXT:  entry:637// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8638// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8639// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8640// CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0641// CHECK1-NEXT:    store i32 0, ptr [[A]], align 4642// CHECK1-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1643// CHECK1-NEXT:    store i32 0, ptr [[B]], align 4644// CHECK1-NEXT:    ret void645//646//647// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St648// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {649// CHECK1-NEXT:  entry:650// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8651// CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8652// CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8653// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8654// CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8655// CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8656// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8657// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0658// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]659// CHECK1-NEXT:    [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0660// CHECK1-NEXT:    [[TMP1:%.*]] = load float, ptr [[F2]], align 4661// CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0662// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 4663// CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP2]] to float664// CHECK1-NEXT:    [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]665// CHECK1-NEXT:    store float [[ADD]], ptr [[F]], align 4666// CHECK1-NEXT:    ret void667//668//669// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev670// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {671// CHECK1-NEXT:  entry:672// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8673// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8674// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8675// CHECK1-NEXT:    ret void676//677//678// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev679// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {680// CHECK1-NEXT:  entry:681// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8682// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8683// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8684// CHECK1-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])685// CHECK1-NEXT:    ret void686//687//688// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei689// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {690// CHECK1-NEXT:  entry:691// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8692// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4693// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8694// CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4695// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8696// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4697// CHECK1-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])698// CHECK1-NEXT:    ret void699//700//701// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56702// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {703// CHECK1-NEXT:  entry:704// CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8705// CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8706// CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8707// CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8708// CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 8709// CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8710// CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8711// CHECK1-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8712// CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8713// CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8714// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]715// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]716// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]717// CHECK1-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 8718// CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4719// CHECK1-NEXT:    store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4720// CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8721// CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]722// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]])723// CHECK1-NEXT:    ret void724//725//726// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined727// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {728// CHECK1-NEXT:  entry:729// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8730// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8731// CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8732// CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8733// CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8734// CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8735// CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 8736// CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4737// CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4738// CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4739// CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4740// CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4741// CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4742// CHECK1-NEXT:    [[VEC2:%.*]] = alloca [2 x i32], align 4743// CHECK1-NEXT:    [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4744// CHECK1-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4745// CHECK1-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4746// CHECK1-NEXT:    [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4747// CHECK1-NEXT:    [[_TMP7:%.*]] = alloca ptr, align 8748// CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4749// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8750// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8751// CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8752// CHECK1-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8753// CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8754// CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8755// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]756// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]757// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]758// CHECK1-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 8759// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4760// CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4761// CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4762// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4763// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false)764// CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0765// CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2766// CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]767// CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]768// CHECK1:       omp.arraycpy.body:769// CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]770// CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]771// CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])772// CHECK1-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])773// CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]774// CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1775// CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1776// CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]777// CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]778// CHECK1:       omp.arraycpy.done4:779// CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]780// CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])781// CHECK1-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]])782// CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]783// CHECK1-NEXT:    store ptr [[VAR5]], ptr [[_TMP7]], align 8784// CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8785// CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4786// CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)787// CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4788// CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1789// CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]790// CHECK1:       cond.true:791// CHECK1-NEXT:    br label [[COND_END:%.*]]792// CHECK1:       cond.false:793// CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4794// CHECK1-NEXT:    br label [[COND_END]]795// CHECK1:       cond.end:796// CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]797// CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4798// CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4799// CHECK1-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4800// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]801// CHECK1:       omp.inner.for.cond:802// CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4803// CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4804// CHECK1-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]805// CHECK1-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]806// CHECK1:       omp.inner.for.cond.cleanup:807// CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]808// CHECK1:       omp.inner.for.body:809// CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4810// CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1811// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]812// CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4813// CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4814// CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I]], align 4815// CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64816// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]]817// CHECK1-NEXT:    store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4818// CHECK1-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]]819// CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4820// CHECK1-NEXT:    [[IDXPROM9:%.*]] = sext i32 [[TMP16]] to i64821// CHECK1-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM9]]822// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP15]], i64 4, i1 false)823// CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]824// CHECK1:       omp.body.continue:825// CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]826// CHECK1:       omp.inner.for.inc:827// CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4828// CHECK1-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1829// CHECK1-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4830// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]831// CHECK1:       omp.inner.for.end:832// CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]833// CHECK1:       omp.loop.exit:834// CHECK1-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8835// CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4836// CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]])837// CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]838// CHECK1-NEXT:    [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0839// CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2840// CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]841// CHECK1:       arraydestroy.body:842// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]843// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1844// CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]845// CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]846// CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]847// CHECK1:       arraydestroy.done13:848// CHECK1-NEXT:    ret void849//850//851// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St852// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {853// CHECK1-NEXT:  entry:854// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8855// CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8856// CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8857// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8858// CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8859// CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8860// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8861// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8862// CHECK1-NEXT:    call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])863// CHECK1-NEXT:    ret void864//865//866// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev867// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {868// CHECK1-NEXT:  entry:869// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8870// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8871// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8872// CHECK1-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]873// CHECK1-NEXT:    ret void874//875//876// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev877// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {878// CHECK1-NEXT:  entry:879// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8880// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8881// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8882// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0883// CHECK1-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4884// CHECK1-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4885// CHECK1-NEXT:    ret void886//887//888// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei889// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {890// CHECK1-NEXT:  entry:891// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8892// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4893// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8894// CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4895// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8896// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0897// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4898// CHECK1-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4899// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]900// CHECK1-NEXT:    store i32 [[ADD]], ptr [[F]], align 4901// CHECK1-NEXT:    ret void902//903//904// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St905// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {906// CHECK1-NEXT:  entry:907// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8908// CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8909// CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8910// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8911// CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8912// CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8913// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8914// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0915// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]916// CHECK1-NEXT:    [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0917// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[F2]], align 4918// CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0919// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 4920// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]921// CHECK1-NEXT:    store i32 [[ADD]], ptr [[F]], align 4922// CHECK1-NEXT:    ret void923//924//925// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev926// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {927// CHECK1-NEXT:  entry:928// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8929// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8930// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8931// CHECK1-NEXT:    ret void932//933//934// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp935// CHECK1-SAME: () #[[ATTR0]] {936// CHECK1-NEXT:  entry:937// CHECK1-NEXT:    call void @__cxx_global_var_init()938// CHECK1-NEXT:    call void @__cxx_global_var_init.1()939// CHECK1-NEXT:    call void @__cxx_global_var_init.2()940// CHECK1-NEXT:    ret void941//942//943// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init944// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {945// CHECK3-NEXT:  entry:946// CHECK3-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)947// CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]948// CHECK3-NEXT:    ret void949//950//951// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev952// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {953// CHECK3-NEXT:  entry:954// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4955// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4956// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4957// CHECK3-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])958// CHECK3-NEXT:    ret void959//960//961// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev962// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {963// CHECK3-NEXT:  entry:964// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4965// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4966// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4967// CHECK3-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]968// CHECK3-NEXT:    ret void969//970//971// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev972// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {973// CHECK3-NEXT:  entry:974// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4975// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4976// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4977// CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0978// CHECK3-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4979// CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float980// CHECK3-NEXT:    store float [[CONV]], ptr [[F]], align 4981// CHECK3-NEXT:    ret void982//983//984// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev985// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {986// CHECK3-NEXT:  entry:987// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4988// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4989// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4990// CHECK3-NEXT:    ret void991//992//993// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1994// CHECK3-SAME: () #[[ATTR0]] {995// CHECK3-NEXT:  entry:996// CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)997// CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00)998// CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]999// CHECK3-NEXT:    ret void1000//1001//1002// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef1003// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1004// CHECK3-NEXT:  entry:1005// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41006// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca float, align 41007// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41008// CHECK3-NEXT:    store float [[A]], ptr [[A_ADDR]], align 41009// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41010// CHECK3-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41011// CHECK3-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])1012// CHECK3-NEXT:    ret void1013//1014//1015// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor1016// CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {1017// CHECK3-NEXT:  entry:1018// CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 41019// CHECK3-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 41020// CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1021// CHECK3:       arraydestroy.body:1022// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1023// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11024// CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1025// CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr1026// CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]1027// CHECK3:       arraydestroy.done1:1028// CHECK3-NEXT:    ret void1029//1030//1031// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef1032// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1033// CHECK3-NEXT:  entry:1034// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41035// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca float, align 41036// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41037// CHECK3-NEXT:    store float [[A]], ptr [[A_ADDR]], align 41038// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41039// CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01040// CHECK3-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41041// CHECK3-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 41042// CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float1043// CHECK3-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]1044// CHECK3-NEXT:    store float [[ADD]], ptr [[F]], align 41045// CHECK3-NEXT:    ret void1046//1047//1048// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.21049// CHECK3-SAME: () #[[ATTR0]] {1050// CHECK3-NEXT:  entry:1051// CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)1052// CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]1053// CHECK3-NEXT:    ret void1054//1055//1056// CHECK3-LABEL: define {{[^@]+}}@main1057// CHECK3-SAME: () #[[ATTR3:[0-9]+]] {1058// CHECK3-NEXT:  entry:1059// CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 41060// CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 41061// CHECK3-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i32, align 41062// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 41063// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 41064// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 41065// CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 41066// CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81067// CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 41068// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr @t_var, align 41069// CHECK3-NEXT:    store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 41070// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41071// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 41072// CHECK3-NEXT:    store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 41073// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 41074// CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01075// CHECK3-NEXT:    store ptr @vec, ptr [[TMP4]], align 41076// CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01077// CHECK3-NEXT:    store ptr @vec, ptr [[TMP5]], align 41078// CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 01079// CHECK3-NEXT:    store ptr null, ptr [[TMP6]], align 41080// CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11081// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP7]], align 41082// CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11083// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP8]], align 41084// CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 11085// CHECK3-NEXT:    store ptr null, ptr [[TMP9]], align 41086// CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21087// CHECK3-NEXT:    store ptr @s_arr, ptr [[TMP10]], align 41088// CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21089// CHECK3-NEXT:    store ptr @s_arr, ptr [[TMP11]], align 41090// CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 21091// CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 41092// CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31093// CHECK3-NEXT:    store ptr @var, ptr [[TMP13]], align 41094// CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31095// CHECK3-NEXT:    store ptr @var, ptr [[TMP14]], align 41096// CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 31097// CHECK3-NEXT:    store ptr null, ptr [[TMP15]], align 41098// CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 41099// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP16]], align 41100// CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 41101// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP17]], align 41102// CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 41103// CHECK3-NEXT:    store ptr null, ptr [[TMP18]], align 41104// CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01105// CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01106// CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01107// CHECK3-NEXT:    store i32 3, ptr [[TMP21]], align 41108// CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11109// CHECK3-NEXT:    store i32 5, ptr [[TMP22]], align 41110// CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21111// CHECK3-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 41112// CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31113// CHECK3-NEXT:    store ptr [[TMP20]], ptr [[TMP24]], align 41114// CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41115// CHECK3-NEXT:    store ptr @.offload_sizes, ptr [[TMP25]], align 41116// CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51117// CHECK3-NEXT:    store ptr @.offload_maptypes, ptr [[TMP26]], align 41118// CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61119// CHECK3-NEXT:    store ptr null, ptr [[TMP27]], align 41120// CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71121// CHECK3-NEXT:    store ptr null, ptr [[TMP28]], align 41122// CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81123// CHECK3-NEXT:    store i64 2, ptr [[TMP29]], align 81124// CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91125// CHECK3-NEXT:    store i64 0, ptr [[TMP30]], align 81126// CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101127// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP31]], align 41128// CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111129// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP32]], align 41130// CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121131// CHECK3-NEXT:    store i32 0, ptr [[TMP33]], align 41132// CHECK3-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.region_id, ptr [[KERNEL_ARGS]])1133// CHECK3-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 01134// CHECK3-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1135// CHECK3:       omp_offload.failed:1136// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92(ptr @vec, i32 [[TMP1]], ptr @s_arr, ptr @var, i32 [[TMP3]]) #[[ATTR2]]1137// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]1138// CHECK3:       omp_offload.cont:1139// CHECK3-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()1140// CHECK3-NEXT:    ret i32 [[CALL]]1141//1142//1143// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l921144// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {1145// CHECK3-NEXT:  entry:1146// CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 41147// CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 41148// CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 41149// CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 41150// CHECK3-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i32, align 41151// CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 41152// CHECK3-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i32, align 41153// CHECK3-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 41154// CHECK3-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41155// CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41156// CHECK3-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 41157// CHECK3-NEXT:    store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 41158// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]]1159// CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1160// CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1161// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 41162// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 41163// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41164// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 41165// CHECK3-NEXT:    store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 41166// CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 41167// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i32 [[TMP6]])1168// CHECK3-NEXT:    ret void1169//1170//1171// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.omp_outlined1172// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] {1173// CHECK3-NEXT:  entry:1174// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41175// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41176// CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 41177// CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 41178// CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 41179// CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 41180// CHECK3-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i32, align 41181// CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41182// CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 41183// CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41184// CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41185// CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41186// CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41187// CHECK3-NEXT:    [[VEC1:%.*]] = alloca [2 x i32], align 41188// CHECK3-NEXT:    [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 41189// CHECK3-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 41190// CHECK3-NEXT:    [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 41191// CHECK3-NEXT:    [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 41192// CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 41193// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41194// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41195// CHECK3-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 41196// CHECK3-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41197// CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41198// CHECK3-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 41199// CHECK3-NEXT:    store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 41200// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1201// CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1202// CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1203// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41204// CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 41205// CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41206// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41207// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false)1208// CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 01209// CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 21210// CHECK3-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]1211// CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1212// CHECK3:       omp.arraycpy.body:1213// CHECK3-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1214// CHECK3-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1215// CHECK3-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])1216// CHECK3-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])1217// CHECK3-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]1218// CHECK3-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11219// CHECK3-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11220// CHECK3-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]1221// CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]1222// CHECK3:       omp.arraycpy.done3:1223// CHECK3-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]])1224// CHECK3-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]])1225// CHECK3-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]1226// CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41227// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 41228// CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1229// CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41230// CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 11231// CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1232// CHECK3:       cond.true:1233// CHECK3-NEXT:    br label [[COND_END:%.*]]1234// CHECK3:       cond.false:1235// CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41236// CHECK3-NEXT:    br label [[COND_END]]1237// CHECK3:       cond.end:1238// CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]1239// CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 41240// CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41241// CHECK3-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 41242// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1243// CHECK3:       omp.inner.for.cond:1244// CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41245// CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41246// CHECK3-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]1247// CHECK3-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1248// CHECK3:       omp.inner.for.cond.cleanup:1249// CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]1250// CHECK3:       omp.inner.for.body:1251// CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41252// CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 11253// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1254// CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 41255// CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 41256// CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 41257// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP13]]1258// CHECK3-NEXT:    store i32 [[TMP12]], ptr [[ARRAYIDX]], align 41259// CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I]], align 41260// CHECK3-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP14]]1261// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false)1262// CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 41263// CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 41264// CHECK3-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]1265// CHECK3-NEXT:    store i32 [[ADD8]], ptr [[SIVAR_ADDR]], align 41266// CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1267// CHECK3:       omp.body.continue:1268// CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1269// CHECK3:       omp.inner.for.inc:1270// CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41271// CHECK3-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP17]], 11272// CHECK3-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 41273// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]1274// CHECK3:       omp.inner.for.end:1275// CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]1276// CHECK3:       omp.loop.exit:1277// CHECK3-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41278// CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 41279// CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]])1280// CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]1281// CHECK3-NEXT:    [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 01282// CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 21283// CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1284// CHECK3:       arraydestroy.body:1285// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1286// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11287// CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1288// CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]1289// CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]1290// CHECK3:       arraydestroy.done11:1291// CHECK3-NEXT:    ret void1292//1293//1294// CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev1295// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1296// CHECK3-NEXT:  entry:1297// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41298// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41299// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41300// CHECK3-NEXT:    call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])1301// CHECK3-NEXT:    ret void1302//1303//1304// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St1305// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1306// CHECK3-NEXT:  entry:1307// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41308// CHECK3-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 41309// CHECK3-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 41310// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41311// CHECK3-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 41312// CHECK3-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 41313// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41314// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 41315// CHECK3-NEXT:    call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])1316// CHECK3-NEXT:    ret void1317//1318//1319// CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev1320// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1321// CHECK3-NEXT:  entry:1322// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41323// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41324// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41325// CHECK3-NEXT:    call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]1326// CHECK3-NEXT:    ret void1327//1328//1329// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v1330// CHECK3-SAME: () #[[ATTR1]] comdat {1331// CHECK3-NEXT:  entry:1332// CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 41333// CHECK3-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41334// CHECK3-NEXT:    [[T_VAR:%.*]] = alloca i32, align 41335// CHECK3-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 41336// CHECK3-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 41337// CHECK3-NEXT:    [[VAR:%.*]] = alloca ptr, align 41338// CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 41339// CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 41340// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 41341// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 41342// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 41343// CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41344// CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81345// CHECK3-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])1346// CHECK3-NEXT:    store i32 0, ptr [[T_VAR]], align 41347// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)1348// CHECK3-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)1349// CHECK3-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 11350// CHECK3-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)1351// CHECK3-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 41352// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META8]], !align [[META9]]1353// CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 41354// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 41355// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 41356// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41357// CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1358// CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01359// CHECK3-NEXT:    store ptr [[VEC]], ptr [[TMP4]], align 41360// CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01361// CHECK3-NEXT:    store ptr [[VEC]], ptr [[TMP5]], align 41362// CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 01363// CHECK3-NEXT:    store ptr null, ptr [[TMP6]], align 41364// CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11365// CHECK3-NEXT:    store i32 [[TMP2]], ptr [[TMP7]], align 41366// CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11367// CHECK3-NEXT:    store i32 [[TMP2]], ptr [[TMP8]], align 41368// CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 11369// CHECK3-NEXT:    store ptr null, ptr [[TMP9]], align 41370// CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21371// CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[TMP10]], align 41372// CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21373// CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[TMP11]], align 41374// CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 21375// CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 41376// CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31377// CHECK3-NEXT:    store ptr [[TMP3]], ptr [[TMP13]], align 41378// CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31379// CHECK3-NEXT:    store ptr [[TMP3]], ptr [[TMP14]], align 41380// CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 31381// CHECK3-NEXT:    store ptr null, ptr [[TMP15]], align 41382// CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01383// CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01384// CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01385// CHECK3-NEXT:    store i32 3, ptr [[TMP18]], align 41386// CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11387// CHECK3-NEXT:    store i32 4, ptr [[TMP19]], align 41388// CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21389// CHECK3-NEXT:    store ptr [[TMP16]], ptr [[TMP20]], align 41390// CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31391// CHECK3-NEXT:    store ptr [[TMP17]], ptr [[TMP21]], align 41392// CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41393// CHECK3-NEXT:    store ptr @.offload_sizes.3, ptr [[TMP22]], align 41394// CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51395// CHECK3-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP23]], align 41396// CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61397// CHECK3-NEXT:    store ptr null, ptr [[TMP24]], align 41398// CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71399// CHECK3-NEXT:    store ptr null, ptr [[TMP25]], align 41400// CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81401// CHECK3-NEXT:    store i64 2, ptr [[TMP26]], align 81402// CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91403// CHECK3-NEXT:    store i64 0, ptr [[TMP27]], align 81404// CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101405// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP28]], align 41406// CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111407// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP29]], align 41408// CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121409// CHECK3-NEXT:    store i32 0, ptr [[TMP30]], align 41410// CHECK3-NEXT:    [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])1411// CHECK3-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 01412// CHECK3-NEXT:    br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1413// CHECK3:       omp_offload.failed:1414// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(ptr [[VEC]], i32 [[TMP2]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]]1415// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]1416// CHECK3:       omp_offload.cont:1417// CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 41418// CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01419// CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 21420// CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1421// CHECK3:       arraydestroy.body:1422// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1423// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11424// CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1425// CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]1426// CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]1427// CHECK3:       arraydestroy.done2:1428// CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]1429// CHECK3-NEXT:    [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 41430// CHECK3-NEXT:    ret i32 [[TMP34]]1431//1432//1433// CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev1434// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1435// CHECK3-NEXT:  entry:1436// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41437// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41438// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41439// CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 01440// CHECK3-NEXT:    store i32 0, ptr [[A]], align 41441// CHECK3-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 11442// CHECK3-NEXT:    store i32 0, ptr [[B]], align 41443// CHECK3-NEXT:    ret void1444//1445//1446// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St1447// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1448// CHECK3-NEXT:  entry:1449// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41450// CHECK3-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 41451// CHECK3-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 41452// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41453// CHECK3-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 41454// CHECK3-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 41455// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41456// CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01457// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1458// CHECK3-NEXT:    [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 01459// CHECK3-NEXT:    [[TMP1:%.*]] = load float, ptr [[F2]], align 41460// CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 01461// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 41462// CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP2]] to float1463// CHECK3-NEXT:    [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]1464// CHECK3-NEXT:    store float [[ADD]], ptr [[F]], align 41465// CHECK3-NEXT:    ret void1466//1467//1468// CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev1469// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1470// CHECK3-NEXT:  entry:1471// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41472// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41473// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41474// CHECK3-NEXT:    ret void1475//1476//1477// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev1478// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1479// CHECK3-NEXT:  entry:1480// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41481// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41482// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41483// CHECK3-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1484// CHECK3-NEXT:    ret void1485//1486//1487// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei1488// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1489// CHECK3-NEXT:  entry:1490// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41491// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 41492// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41493// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 41494// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41495// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41496// CHECK3-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])1497// CHECK3-NEXT:    ret void1498//1499//1500// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l561501// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {1502// CHECK3-NEXT:  entry:1503// CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 41504// CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 41505// CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 41506// CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 41507// CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 41508// CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 41509// CHECK3-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 41510// CHECK3-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41511// CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41512// CHECK3-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 41513// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1514// CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1515// CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1516// CHECK3-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 41517// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 41518// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 41519// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41520// CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1521// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]])1522// CHECK3-NEXT:    ret void1523//1524//1525// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined1526// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {1527// CHECK3-NEXT:  entry:1528// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41529// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41530// CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 41531// CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 41532// CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 41533// CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 41534// CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 41535// CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41536// CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41537// CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41538// CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41539// CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41540// CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41541// CHECK3-NEXT:    [[VEC2:%.*]] = alloca [2 x i32], align 41542// CHECK3-NEXT:    [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 41543// CHECK3-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 41544// CHECK3-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41545// CHECK3-NEXT:    [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 41546// CHECK3-NEXT:    [[_TMP7:%.*]] = alloca ptr, align 41547// CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 41548// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41549// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41550// CHECK3-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 41551// CHECK3-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41552// CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41553// CHECK3-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 41554// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1555// CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1556// CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1557// CHECK3-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 41558// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41559// CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 41560// CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41561// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41562// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false)1563// CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 01564// CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 21565// CHECK3-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]1566// CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1567// CHECK3:       omp.arraycpy.body:1568// CHECK3-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1569// CHECK3-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1570// CHECK3-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])1571// CHECK3-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])1572// CHECK3-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]1573// CHECK3-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11574// CHECK3-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11575// CHECK3-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]1576// CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]1577// CHECK3:       omp.arraycpy.done4:1578// CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1579// CHECK3-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])1580// CHECK3-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]])1581// CHECK3-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]1582// CHECK3-NEXT:    store ptr [[VAR5]], ptr [[_TMP7]], align 41583// CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41584// CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 41585// CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1586// CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41587// CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 11588// CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1589// CHECK3:       cond.true:1590// CHECK3-NEXT:    br label [[COND_END:%.*]]1591// CHECK3:       cond.false:1592// CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41593// CHECK3-NEXT:    br label [[COND_END]]1594// CHECK3:       cond.end:1595// CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]1596// CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 41597// CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41598// CHECK3-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 41599// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1600// CHECK3:       omp.inner.for.cond:1601// CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41602// CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41603// CHECK3-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]1604// CHECK3-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1605// CHECK3:       omp.inner.for.cond.cleanup:1606// CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]1607// CHECK3:       omp.inner.for.body:1608// CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41609// CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 11610// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1611// CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 41612// CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 41613// CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I]], align 41614// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP14]]1615// CHECK3-NEXT:    store i32 [[TMP13]], ptr [[ARRAYIDX]], align 41616// CHECK3-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META8]], !align [[META9]]1617// CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 41618// CHECK3-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP16]]1619// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP15]], i32 4, i1 false)1620// CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1621// CHECK3:       omp.body.continue:1622// CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1623// CHECK3:       omp.inner.for.inc:1624// CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41625// CHECK3-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP17]], 11626// CHECK3-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 41627// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]1628// CHECK3:       omp.inner.for.end:1629// CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]1630// CHECK3:       omp.loop.exit:1631// CHECK3-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41632// CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 41633// CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]])1634// CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]1635// CHECK3-NEXT:    [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 01636// CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 21637// CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1638// CHECK3:       arraydestroy.body:1639// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1640// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11641// CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1642// CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]1643// CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]1644// CHECK3:       arraydestroy.done12:1645// CHECK3-NEXT:    ret void1646//1647//1648// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St1649// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1650// CHECK3-NEXT:  entry:1651// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41652// CHECK3-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 41653// CHECK3-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 41654// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41655// CHECK3-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 41656// CHECK3-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 41657// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41658// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 41659// CHECK3-NEXT:    call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])1660// CHECK3-NEXT:    ret void1661//1662//1663// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev1664// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1665// CHECK3-NEXT:  entry:1666// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41667// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41668// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41669// CHECK3-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]1670// CHECK3-NEXT:    ret void1671//1672//1673// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev1674// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1675// CHECK3-NEXT:  entry:1676// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41677// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41678// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41679// CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01680// CHECK3-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 41681// CHECK3-NEXT:    store i32 [[TMP0]], ptr [[F]], align 41682// CHECK3-NEXT:    ret void1683//1684//1685// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei1686// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1687// CHECK3-NEXT:  entry:1688// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41689// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 41690// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41691// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 41692// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41693// CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01694// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41695// CHECK3-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 41696// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]1697// CHECK3-NEXT:    store i32 [[ADD]], ptr [[F]], align 41698// CHECK3-NEXT:    ret void1699//1700//1701// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St1702// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1703// CHECK3-NEXT:  entry:1704// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41705// CHECK3-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 41706// CHECK3-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 41707// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41708// CHECK3-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 41709// CHECK3-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 41710// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41711// CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01712// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1713// CHECK3-NEXT:    [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 01714// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[F2]], align 41715// CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 01716// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 41717// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]1718// CHECK3-NEXT:    store i32 [[ADD]], ptr [[F]], align 41719// CHECK3-NEXT:    ret void1720//1721//1722// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev1723// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1724// CHECK3-NEXT:  entry:1725// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41726// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41727// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41728// CHECK3-NEXT:    ret void1729//1730//1731// CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp1732// CHECK3-SAME: () #[[ATTR0]] {1733// CHECK3-NEXT:  entry:1734// CHECK3-NEXT:    call void @__cxx_global_var_init()1735// CHECK3-NEXT:    call void @__cxx_global_var_init.1()1736// CHECK3-NEXT:    call void @__cxx_global_var_init.2()1737// CHECK3-NEXT:    ret void1738//1739//1740// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init1741// CHECK9-SAME: () #[[ATTR0:[0-9]+]] {1742// CHECK9-NEXT:  entry:1743// CHECK9-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)1744// CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]1745// CHECK9-NEXT:    ret void1746//1747//1748// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev1749// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {1750// CHECK9-NEXT:  entry:1751// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81752// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81753// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81754// CHECK9-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1755// CHECK9-NEXT:    ret void1756//1757//1758// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev1759// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1760// CHECK9-NEXT:  entry:1761// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81762// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81763// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81764// CHECK9-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]1765// CHECK9-NEXT:    ret void1766//1767//1768// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev1769// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1770// CHECK9-NEXT:  entry:1771// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81772// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81773// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81774// CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01775// CHECK9-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 41776// CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float1777// CHECK9-NEXT:    store float [[CONV]], ptr [[F]], align 41778// CHECK9-NEXT:    ret void1779//1780//1781// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev1782// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1783// CHECK9-NEXT:  entry:1784// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81785// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81786// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81787// CHECK9-NEXT:    ret void1788//1789//1790// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.11791// CHECK9-SAME: () #[[ATTR0]] {1792// CHECK9-NEXT:  entry:1793// CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)1794// CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)1795// CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]1796// CHECK9-NEXT:    ret void1797//1798//1799// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef1800// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1801// CHECK9-NEXT:  entry:1802// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81803// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca float, align 41804// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81805// CHECK9-NEXT:    store float [[A]], ptr [[A_ADDR]], align 41806// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81807// CHECK9-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41808// CHECK9-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])1809// CHECK9-NEXT:    ret void1810//1811//1812// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor1813// CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {1814// CHECK9-NEXT:  entry:1815// CHECK9-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 81816// CHECK9-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 81817// CHECK9-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1818// CHECK9:       arraydestroy.body:1819// CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1820// CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11821// CHECK9-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1822// CHECK9-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr1823// CHECK9-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]1824// CHECK9:       arraydestroy.done1:1825// CHECK9-NEXT:    ret void1826//1827//1828// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef1829// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1830// CHECK9-NEXT:  entry:1831// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81832// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca float, align 41833// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81834// CHECK9-NEXT:    store float [[A]], ptr [[A_ADDR]], align 41835// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81836// CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01837// CHECK9-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41838// CHECK9-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 41839// CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float1840// CHECK9-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]1841// CHECK9-NEXT:    store float [[ADD]], ptr [[F]], align 41842// CHECK9-NEXT:    ret void1843//1844//1845// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.21846// CHECK9-SAME: () #[[ATTR0]] {1847// CHECK9-NEXT:  entry:1848// CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)1849// CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]1850// CHECK9-NEXT:    ret void1851//1852//1853// CHECK9-LABEL: define {{[^@]+}}@main1854// CHECK9-SAME: () #[[ATTR3:[0-9]+]] {1855// CHECK9-NEXT:  entry:1856// CHECK9-NEXT:    [[RETVAL:%.*]] = alloca i32, align 41857// CHECK9-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 11858// CHECK9-NEXT:    store i32 0, ptr [[RETVAL]], align 41859// CHECK9-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])1860// CHECK9-NEXT:    ret i32 01861//1862//1863// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l741864// CHECK9-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {1865// CHECK9-NEXT:  entry:1866// CHECK9-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 81867// CHECK9-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 81868// CHECK9-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 81869// CHECK9-NEXT:    [[TMP:%.*]] = alloca ptr, align 81870// CHECK9-NEXT:    [[G_CASTED:%.*]] = alloca i64, align 81871// CHECK9-NEXT:    [[G1_CASTED:%.*]] = alloca i64, align 81872// CHECK9-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 81873// CHECK9-NEXT:    store i64 [[G]], ptr [[G_ADDR]], align 81874// CHECK9-NEXT:    store i64 [[G1]], ptr [[G1_ADDR]], align 81875// CHECK9-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 81876// CHECK9-NEXT:    store ptr [[G1_ADDR]], ptr [[TMP]], align 81877// CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[G_ADDR]], align 41878// CHECK9-NEXT:    store i32 [[TMP0]], ptr [[G_CASTED]], align 41879// CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 81880// CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]1881// CHECK9-NEXT:    [[TMP3:%.*]] = load volatile i32, ptr [[TMP2]], align 41882// CHECK9-NEXT:    store i32 [[TMP3]], ptr [[G1_CASTED]], align 41883// CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[G1_CASTED]], align 81884// CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 41885// CHECK9-NEXT:    store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 41886// CHECK9-NEXT:    [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 81887// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined, i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])1888// CHECK9-NEXT:    ret void1889//1890//1891// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined1892// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] {1893// CHECK9-NEXT:  entry:1894// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81895// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81896// CHECK9-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 81897// CHECK9-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 81898// CHECK9-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 81899// CHECK9-NEXT:    [[TMP:%.*]] = alloca ptr, align 81900// CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41901// CHECK9-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41902// CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41903// CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41904// CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41905// CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41906// CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 41907// CHECK9-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 81908// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81909// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81910// CHECK9-NEXT:    store i64 [[G]], ptr [[G_ADDR]], align 81911// CHECK9-NEXT:    store i64 [[G1]], ptr [[G1_ADDR]], align 81912// CHECK9-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 81913// CHECK9-NEXT:    store ptr [[G1_ADDR]], ptr [[TMP]], align 81914// CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41915// CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 41916// CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41917// CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41918// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81919// CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41920// CHECK9-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1921// CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41922// CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 11923// CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1924// CHECK9:       cond.true:1925// CHECK9-NEXT:    br label [[COND_END:%.*]]1926// CHECK9:       cond.false:1927// CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41928// CHECK9-NEXT:    br label [[COND_END]]1929// CHECK9:       cond.end:1930// CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]1931// CHECK9-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 41932// CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41933// CHECK9-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 41934// CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1935// CHECK9:       omp.inner.for.cond:1936// CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41937// CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41938// CHECK9-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]1939// CHECK9-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1940// CHECK9:       omp.inner.for.body:1941// CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41942// CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 11943// CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1944// CHECK9-NEXT:    store i32 [[ADD]], ptr [[I]], align 41945// CHECK9-NEXT:    store i32 1, ptr [[G_ADDR]], align 41946// CHECK9-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]]1947// CHECK9-NEXT:    store volatile i32 1, ptr [[TMP8]], align 41948// CHECK9-NEXT:    store i32 2, ptr [[SIVAR_ADDR]], align 41949// CHECK9-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 01950// CHECK9-NEXT:    store ptr [[G_ADDR]], ptr [[TMP9]], align 81951// CHECK9-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 11952// CHECK9-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]]1953// CHECK9-NEXT:    store ptr [[TMP11]], ptr [[TMP10]], align 81954// CHECK9-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 21955// CHECK9-NEXT:    store ptr [[SIVAR_ADDR]], ptr [[TMP12]], align 81956// CHECK9-NEXT:    call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]])1957// CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1958// CHECK9:       omp.body.continue:1959// CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1960// CHECK9:       omp.inner.for.inc:1961// CHECK9-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41962// CHECK9-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP13]], 11963// CHECK9-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 41964// CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]]1965// CHECK9:       omp.inner.for.end:1966// CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]1967// CHECK9:       omp.loop.exit:1968// CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])1969// CHECK9-NEXT:    ret void1970//1971//1972// CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp1973// CHECK9-SAME: () #[[ATTR0]] {1974// CHECK9-NEXT:  entry:1975// CHECK9-NEXT:    call void @__cxx_global_var_init()1976// CHECK9-NEXT:    call void @__cxx_global_var_init.1()1977// CHECK9-NEXT:    call void @__cxx_global_var_init.2()1978// CHECK9-NEXT:    ret void1979//1980