1390 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s4// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK36// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s7// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK38 9// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"10// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s11// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"12// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"13// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s14// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"15 16// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK917// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s18// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK919 20// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"21// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s22// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"23 24// expected-no-diagnostics25#ifndef HEADER26#define HEADER27 28struct St {29 int a, b;30 St() : a(0), b(0) {}31 St(const St &st) : a(st.a + st.b), b(0) {}32 ~St() {}33};34 35volatile int g = 1212;36volatile int &g1 = g;37 38template <class T>39struct S {40 T f;41 S(T a) : f(a + g) {}42 S() : f(g) {}43 S(const S &s, St t = St()) : f(s.f + t.a) {}44 operator T() { return T(); }45 ~S() {}46};47 48 49template <typename T>50T tmain() {51 S<T> test;52 T t_var = T();53 T vec[] = {1, 2};54 S<T> s_arr[] = {1, 2};55 S<T> &var = test;56#pragma omp target teams distribute private(t_var, vec, s_arr, var)57 for (int i = 0; i < 2; ++i) {58 vec[i] = t_var;59 s_arr[i] = var;60 }61 return T();62}63 64S<float> test;65int t_var = 333;66int vec[] = {1, 2};67S<float> s_arr[] = {1, 2};68S<float> var(3);69 70int main() {71 static int sivar;72#ifdef LAMBDA73 [&]() {74#pragma omp target teams distribute private(g, g1, sivar)75 for (int i = 0; i < 2; ++i) {76 77 // Skip global, bound tid and loop vars78 g = 1;79 g1 = 1;80 sivar = 2;81 [&]() {82 g = 2;83 g1 = 2;84 sivar = 4;85 86 }();87 }88 }();89 return 0;90#else91#pragma omp target teams distribute private(t_var, vec, s_arr, var, sivar)92 for (int i = 0; i < 2; ++i) {93 vec[i] = t_var;94 s_arr[i] = var;95 sivar += i;96 }97 return tmain<int>();98#endif99}100 101 102 103// Skip global, bound tid and loop vars104 105// private(s_arr)106 107// private(var)108 109 110 111 112 113// Skip global, bound tid and loop vars114 115// private(s_arr)116 117 118// private(var)119 120 121#endif122// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init123// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {124// CHECK1-NEXT: entry:125// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)126// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]127// CHECK1-NEXT: ret void128//129//130// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev131// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {132// CHECK1-NEXT: entry:133// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8134// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8135// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8136// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])137// CHECK1-NEXT: ret void138//139//140// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev141// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {142// CHECK1-NEXT: entry:143// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8144// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8145// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8146// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]147// CHECK1-NEXT: ret void148//149//150// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev151// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {152// CHECK1-NEXT: entry:153// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8154// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8155// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8156// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0157// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4158// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float159// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4160// CHECK1-NEXT: ret void161//162//163// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev164// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {165// CHECK1-NEXT: entry:166// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8167// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8168// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8169// CHECK1-NEXT: ret void170//171//172// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1173// CHECK1-SAME: () #[[ATTR0]] {174// CHECK1-NEXT: entry:175// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)176// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)177// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]178// CHECK1-NEXT: ret void179//180//181// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef182// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {183// CHECK1-NEXT: entry:184// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8185// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4186// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8187// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4188// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8189// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4190// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])191// CHECK1-NEXT: ret void192//193//194// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor195// CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {196// CHECK1-NEXT: entry:197// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8198// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8199// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]200// CHECK1: arraydestroy.body:201// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]202// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1203// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]204// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr205// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]206// CHECK1: arraydestroy.done1:207// CHECK1-NEXT: ret void208//209//210// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef211// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {212// CHECK1-NEXT: entry:213// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8214// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4215// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8216// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4217// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8218// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0219// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4220// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4221// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float222// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]223// CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4224// CHECK1-NEXT: ret void225//226//227// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2228// CHECK1-SAME: () #[[ATTR0]] {229// CHECK1-NEXT: entry:230// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)231// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]232// CHECK1-NEXT: ret void233//234//235// CHECK1-LABEL: define {{[^@]+}}@main236// CHECK1-SAME: () #[[ATTR3:[0-9]+]] {237// CHECK1-NEXT: entry:238// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4239// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4240// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8241// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4242// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0243// CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4244// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1245// CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4246// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2247// CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8248// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3249// CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8250// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4251// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8252// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5253// CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8254// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6255// CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8256// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7257// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8258// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8259// CHECK1-NEXT: store i64 2, ptr [[TMP8]], align 8260// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9261// CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8262// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10263// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4264// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11265// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4266// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12267// CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4268// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.region_id, ptr [[KERNEL_ARGS]])269// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0270// CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]271// CHECK1: omp_offload.failed:272// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]]273// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]274// CHECK1: omp_offload.cont:275// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()276// CHECK1-NEXT: ret i32 [[CALL]]277//278//279// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91280// CHECK1-SAME: () #[[ATTR4:[0-9]+]] {281// CHECK1-NEXT: entry:282// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.omp_outlined)283// CHECK1-NEXT: ret void284//285//286// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.omp_outlined287// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {288// CHECK1-NEXT: entry:289// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8290// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8291// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4292// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4293// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4294// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4295// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4296// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4297// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4298// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4299// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4300// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4301// CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4302// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4303// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8304// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8305// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4306// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4307// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4308// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4309// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0310// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2311// CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]312// CHECK1: arrayctor.loop:313// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]314// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])315// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1316// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]317// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]318// CHECK1: arrayctor.cont:319// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])320// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8321// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4322// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)323// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4324// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1325// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]326// CHECK1: cond.true:327// CHECK1-NEXT: br label [[COND_END:%.*]]328// CHECK1: cond.false:329// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4330// CHECK1-NEXT: br label [[COND_END]]331// CHECK1: cond.end:332// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]333// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4334// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4335// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4336// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]337// CHECK1: omp.inner.for.cond:338// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4339// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4340// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]341// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]342// CHECK1: omp.inner.for.cond.cleanup:343// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]344// CHECK1: omp.inner.for.body:345// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4346// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1347// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]348// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4349// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4350// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4351// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64352// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]353// CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4354// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4355// CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64356// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]]357// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false)358// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4359// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4360// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]361// CHECK1-NEXT: store i32 [[ADD4]], ptr [[SIVAR]], align 4362// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]363// CHECK1: omp.body.continue:364// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]365// CHECK1: omp.inner.for.inc:366// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4367// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1368// CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4369// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]370// CHECK1: omp.inner.for.end:371// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]372// CHECK1: omp.loop.exit:373// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8374// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4375// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]])376// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]377// CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0378// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 2379// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]380// CHECK1: arraydestroy.body:381// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]382// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1383// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]384// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]385// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]386// CHECK1: arraydestroy.done7:387// CHECK1-NEXT: ret void388//389//390// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v391// CHECK1-SAME: () #[[ATTR1]] comdat {392// CHECK1-NEXT: entry:393// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4394// CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4395// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4396// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4397// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4398// CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8399// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4400// CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8401// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8402// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])403// CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4404// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)405// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1)406// CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1407// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)408// CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8409// CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8410// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0411// CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4412// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1413// CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4414// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2415// CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8416// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3417// CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8418// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4419// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8420// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5421// CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8422// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6423// CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8424// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7425// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8426// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8427// CHECK1-NEXT: store i64 2, ptr [[TMP8]], align 8428// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9429// CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8430// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10431// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4432// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11433// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4434// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12435// CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4436// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])437// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0438// CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]439// CHECK1: omp_offload.failed:440// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]441// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]442// CHECK1: omp_offload.cont:443// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4444// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0445// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2446// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]447// CHECK1: arraydestroy.body:448// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]449// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1450// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]451// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]452// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]453// CHECK1: arraydestroy.done2:454// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]455// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4456// CHECK1-NEXT: ret i32 [[TMP16]]457//458//459// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev460// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {461// CHECK1-NEXT: entry:462// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8463// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8464// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8465// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])466// CHECK1-NEXT: ret void467//468//469// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei470// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {471// CHECK1-NEXT: entry:472// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8473// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4474// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8475// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4476// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8477// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4478// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])479// CHECK1-NEXT: ret void480//481//482// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56483// CHECK1-SAME: () #[[ATTR4]] {484// CHECK1-NEXT: entry:485// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined)486// CHECK1-NEXT: ret void487//488//489// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined490// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {491// CHECK1-NEXT: entry:492// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8493// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8494// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4495// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4496// CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8497// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4498// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4499// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4500// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4501// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4502// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4503// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4504// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4505// CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8506// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4507// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8508// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8509// CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8510// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4511// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4512// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4513// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4514// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0515// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2516// CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]517// CHECK1: arrayctor.loop:518// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]519// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])520// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1521// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]522// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]523// CHECK1: arrayctor.cont:524// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])525// CHECK1-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 8526// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8527// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4528// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)529// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4530// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1531// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]532// CHECK1: cond.true:533// CHECK1-NEXT: br label [[COND_END:%.*]]534// CHECK1: cond.false:535// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4536// CHECK1-NEXT: br label [[COND_END]]537// CHECK1: cond.end:538// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]539// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4540// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4541// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4542// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]543// CHECK1: omp.inner.for.cond:544// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4545// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4546// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]547// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]548// CHECK1: omp.inner.for.cond.cleanup:549// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]550// CHECK1: omp.inner.for.body:551// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4552// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1553// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]554// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4555// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4556// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4557// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64558// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]559// CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4560// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8561// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4562// CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64563// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]]564// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false)565// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]566// CHECK1: omp.body.continue:567// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]568// CHECK1: omp.inner.for.inc:569// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4570// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1571// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4572// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]573// CHECK1: omp.inner.for.end:574// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]575// CHECK1: omp.loop.exit:576// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8577// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4578// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]])579// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]580// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0581// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2582// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]583// CHECK1: arraydestroy.body:584// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]585// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1586// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]587// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]588// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]589// CHECK1: arraydestroy.done8:590// CHECK1-NEXT: ret void591//592//593// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev594// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {595// CHECK1-NEXT: entry:596// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8597// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8598// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8599// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]600// CHECK1-NEXT: ret void601//602//603// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev604// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {605// CHECK1-NEXT: entry:606// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8607// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8608// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8609// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0610// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4611// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4612// CHECK1-NEXT: ret void613//614//615// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei616// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {617// CHECK1-NEXT: entry:618// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8619// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4620// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8621// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4622// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8623// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0624// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4625// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4626// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]627// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4628// CHECK1-NEXT: ret void629//630//631// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev632// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {633// CHECK1-NEXT: entry:634// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8635// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8636// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8637// CHECK1-NEXT: ret void638//639//640// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp641// CHECK1-SAME: () #[[ATTR0]] {642// CHECK1-NEXT: entry:643// CHECK1-NEXT: call void @__cxx_global_var_init()644// CHECK1-NEXT: call void @__cxx_global_var_init.1()645// CHECK1-NEXT: call void @__cxx_global_var_init.2()646// CHECK1-NEXT: ret void647//648//649// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init650// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {651// CHECK3-NEXT: entry:652// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)653// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]654// CHECK3-NEXT: ret void655//656//657// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev658// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {659// CHECK3-NEXT: entry:660// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4661// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4662// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4663// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])664// CHECK3-NEXT: ret void665//666//667// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev668// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {669// CHECK3-NEXT: entry:670// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4671// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4672// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4673// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]674// CHECK3-NEXT: ret void675//676//677// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev678// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {679// CHECK3-NEXT: entry:680// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4681// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4682// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4683// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0684// CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4685// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float686// CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4687// CHECK3-NEXT: ret void688//689//690// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev691// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {692// CHECK3-NEXT: entry:693// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4694// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4695// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4696// CHECK3-NEXT: ret void697//698//699// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1700// CHECK3-SAME: () #[[ATTR0]] {701// CHECK3-NEXT: entry:702// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)703// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00)704// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]705// CHECK3-NEXT: ret void706//707//708// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef709// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {710// CHECK3-NEXT: entry:711// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4712// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4713// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4714// CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4715// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4716// CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4717// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])718// CHECK3-NEXT: ret void719//720//721// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor722// CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {723// CHECK3-NEXT: entry:724// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4725// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4726// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]727// CHECK3: arraydestroy.body:728// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]729// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1730// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]731// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr732// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]733// CHECK3: arraydestroy.done1:734// CHECK3-NEXT: ret void735//736//737// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef738// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {739// CHECK3-NEXT: entry:740// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4741// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4742// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4743// CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4744// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4745// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0746// CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4747// CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4748// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float749// CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]750// CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4751// CHECK3-NEXT: ret void752//753//754// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2755// CHECK3-SAME: () #[[ATTR0]] {756// CHECK3-NEXT: entry:757// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)758// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]759// CHECK3-NEXT: ret void760//761//762// CHECK3-LABEL: define {{[^@]+}}@main763// CHECK3-SAME: () #[[ATTR3:[0-9]+]] {764// CHECK3-NEXT: entry:765// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4766// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4767// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8768// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4769// CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0770// CHECK3-NEXT: store i32 3, ptr [[TMP0]], align 4771// CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1772// CHECK3-NEXT: store i32 0, ptr [[TMP1]], align 4773// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2774// CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4775// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3776// CHECK3-NEXT: store ptr null, ptr [[TMP3]], align 4777// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4778// CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4779// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5780// CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4781// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6782// CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4783// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7784// CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4785// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8786// CHECK3-NEXT: store i64 2, ptr [[TMP8]], align 8787// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9788// CHECK3-NEXT: store i64 0, ptr [[TMP9]], align 8789// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10790// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4791// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11792// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4793// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12794// CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4795// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.region_id, ptr [[KERNEL_ARGS]])796// CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0797// CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]798// CHECK3: omp_offload.failed:799// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]]800// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]801// CHECK3: omp_offload.cont:802// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()803// CHECK3-NEXT: ret i32 [[CALL]]804//805//806// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91807// CHECK3-SAME: () #[[ATTR4:[0-9]+]] {808// CHECK3-NEXT: entry:809// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.omp_outlined)810// CHECK3-NEXT: ret void811//812//813// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.omp_outlined814// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {815// CHECK3-NEXT: entry:816// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4817// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4818// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4819// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4820// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4821// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4822// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4823// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4824// CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4825// CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4826// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4827// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4828// CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4829// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4830// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4831// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4832// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4833// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4834// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4835// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4836// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0837// CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2838// CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]839// CHECK3: arrayctor.loop:840// CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]841// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])842// CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1843// CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]844// CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]845// CHECK3: arrayctor.cont:846// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])847// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4848// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4849// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)850// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4851// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1852// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]853// CHECK3: cond.true:854// CHECK3-NEXT: br label [[COND_END:%.*]]855// CHECK3: cond.false:856// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4857// CHECK3-NEXT: br label [[COND_END]]858// CHECK3: cond.end:859// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]860// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4861// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4862// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4863// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]864// CHECK3: omp.inner.for.cond:865// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4866// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4867// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]868// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]869// CHECK3: omp.inner.for.cond.cleanup:870// CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]871// CHECK3: omp.inner.for.body:872// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4873// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1874// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]875// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4876// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4877// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4878// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]]879// CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4880// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4881// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]]882// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false)883// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4884// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4885// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]886// CHECK3-NEXT: store i32 [[ADD3]], ptr [[SIVAR]], align 4887// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]888// CHECK3: omp.body.continue:889// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]890// CHECK3: omp.inner.for.inc:891// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4892// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1893// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4894// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]895// CHECK3: omp.inner.for.end:896// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]897// CHECK3: omp.loop.exit:898// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4899// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4900// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]])901// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]902// CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0903// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2904// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]905// CHECK3: arraydestroy.body:906// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]907// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1908// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]909// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]910// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]911// CHECK3: arraydestroy.done6:912// CHECK3-NEXT: ret void913//914//915// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v916// CHECK3-SAME: () #[[ATTR1]] comdat {917// CHECK3-NEXT: entry:918// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4919// CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4920// CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4921// CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4922// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4923// CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4924// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4925// CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4926// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8927// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])928// CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4929// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)930// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)931// CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1932// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)933// CHECK3-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4934// CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4935// CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0936// CHECK3-NEXT: store i32 3, ptr [[TMP0]], align 4937// CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1938// CHECK3-NEXT: store i32 0, ptr [[TMP1]], align 4939// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2940// CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4941// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3942// CHECK3-NEXT: store ptr null, ptr [[TMP3]], align 4943// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4944// CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4945// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5946// CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4947// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6948// CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4949// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7950// CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4951// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8952// CHECK3-NEXT: store i64 2, ptr [[TMP8]], align 8953// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9954// CHECK3-NEXT: store i64 0, ptr [[TMP9]], align 8955// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10956// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4957// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11958// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4959// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12960// CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4961// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])962// CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0963// CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]964// CHECK3: omp_offload.failed:965// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]966// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]967// CHECK3: omp_offload.cont:968// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4969// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0970// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2971// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]972// CHECK3: arraydestroy.body:973// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]974// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1975// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]976// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]977// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]978// CHECK3: arraydestroy.done2:979// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]980// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4981// CHECK3-NEXT: ret i32 [[TMP16]]982//983//984// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev985// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {986// CHECK3-NEXT: entry:987// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4988// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4989// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4990// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])991// CHECK3-NEXT: ret void992//993//994// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei995// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {996// CHECK3-NEXT: entry:997// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4998// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4999// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41000// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 41001// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41002// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41003// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])1004// CHECK3-NEXT: ret void1005//1006//1007// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l561008// CHECK3-SAME: () #[[ATTR4]] {1009// CHECK3-NEXT: entry:1010// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined)1011// CHECK3-NEXT: ret void1012//1013//1014// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined1015// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {1016// CHECK3-NEXT: entry:1017// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41018// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41019// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41020// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 41021// CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 41022// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41023// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41024// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41025// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41026// CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 41027// CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 41028// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 41029// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41030// CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 41031// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 41032// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41033// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41034// CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 41035// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41036// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 41037// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41038// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41039// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01040// CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 21041// CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]1042// CHECK3: arrayctor.loop:1043// CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]1044// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])1045// CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 11046// CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]1047// CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]1048// CHECK3: arrayctor.cont:1049// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])1050// CHECK3-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 41051// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41052// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41053// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1054// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41055// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 11056// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1057// CHECK3: cond.true:1058// CHECK3-NEXT: br label [[COND_END:%.*]]1059// CHECK3: cond.false:1060// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41061// CHECK3-NEXT: br label [[COND_END]]1062// CHECK3: cond.end:1063// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]1064// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41065// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41066// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 41067// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1068// CHECK3: omp.inner.for.cond:1069// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41070// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41071// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]1072// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1073// CHECK3: omp.inner.for.cond.cleanup:1074// CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]1075// CHECK3: omp.inner.for.body:1076// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41077// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 11078// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1079// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 41080// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 41081// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 41082// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]]1083// CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 41084// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 41085// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 41086// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]]1087// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false)1088// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1089// CHECK3: omp.body.continue:1090// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1091// CHECK3: omp.inner.for.inc:1092// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41093// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], 11094// CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 41095// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]1096// CHECK3: omp.inner.for.end:1097// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1098// CHECK3: omp.loop.exit:1099// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41100// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 41101// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]])1102// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]1103// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01104// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 21105// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1106// CHECK3: arraydestroy.body:1107// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1108// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11109// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1110// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]1111// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]1112// CHECK3: arraydestroy.done7:1113// CHECK3-NEXT: ret void1114//1115//1116// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev1117// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1118// CHECK3-NEXT: entry:1119// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41120// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41121// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41122// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]1123// CHECK3-NEXT: ret void1124//1125//1126// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev1127// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1128// CHECK3-NEXT: entry:1129// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41130// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41131// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41132// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01133// CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 41134// CHECK3-NEXT: store i32 [[TMP0]], ptr [[F]], align 41135// CHECK3-NEXT: ret void1136//1137//1138// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei1139// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1140// CHECK3-NEXT: entry:1141// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41142// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 41143// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41144// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 41145// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41146// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01147// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41148// CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 41149// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]1150// CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 41151// CHECK3-NEXT: ret void1152//1153//1154// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev1155// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1156// CHECK3-NEXT: entry:1157// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41158// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41159// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41160// CHECK3-NEXT: ret void1161//1162//1163// CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp1164// CHECK3-SAME: () #[[ATTR0]] {1165// CHECK3-NEXT: entry:1166// CHECK3-NEXT: call void @__cxx_global_var_init()1167// CHECK3-NEXT: call void @__cxx_global_var_init.1()1168// CHECK3-NEXT: call void @__cxx_global_var_init.2()1169// CHECK3-NEXT: ret void1170//1171//1172// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init1173// CHECK9-SAME: () #[[ATTR0:[0-9]+]] {1174// CHECK9-NEXT: entry:1175// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)1176// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]1177// CHECK9-NEXT: ret void1178//1179//1180// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev1181// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {1182// CHECK9-NEXT: entry:1183// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81184// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81185// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81186// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1187// CHECK9-NEXT: ret void1188//1189//1190// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev1191// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1192// CHECK9-NEXT: entry:1193// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81194// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81195// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81196// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]1197// CHECK9-NEXT: ret void1198//1199//1200// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev1201// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1202// CHECK9-NEXT: entry:1203// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81204// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81205// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81206// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01207// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 41208// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float1209// CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 41210// CHECK9-NEXT: ret void1211//1212//1213// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev1214// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1215// CHECK9-NEXT: entry:1216// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81217// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81218// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81219// CHECK9-NEXT: ret void1220//1221//1222// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.11223// CHECK9-SAME: () #[[ATTR0]] {1224// CHECK9-NEXT: entry:1225// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)1226// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)1227// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]1228// CHECK9-NEXT: ret void1229//1230//1231// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef1232// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1233// CHECK9-NEXT: entry:1234// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81235// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 41236// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81237// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 41238// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81239// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41240// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])1241// CHECK9-NEXT: ret void1242//1243//1244// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor1245// CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {1246// CHECK9-NEXT: entry:1247// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 81248// CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 81249// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1250// CHECK9: arraydestroy.body:1251// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1252// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11253// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1254// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr1255// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]1256// CHECK9: arraydestroy.done1:1257// CHECK9-NEXT: ret void1258//1259//1260// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef1261// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1262// CHECK9-NEXT: entry:1263// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81264// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 41265// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81266// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 41267// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81268// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01269// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41270// CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 41271// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float1272// CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]1273// CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 41274// CHECK9-NEXT: ret void1275//1276//1277// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.21278// CHECK9-SAME: () #[[ATTR0]] {1279// CHECK9-NEXT: entry:1280// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)1281// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]1282// CHECK9-NEXT: ret void1283//1284//1285// CHECK9-LABEL: define {{[^@]+}}@main1286// CHECK9-SAME: () #[[ATTR3:[0-9]+]] {1287// CHECK9-NEXT: entry:1288// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 41289// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 11290// CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 41291// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])1292// CHECK9-NEXT: ret i32 01293//1294//1295// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l741296// CHECK9-SAME: () #[[ATTR4:[0-9]+]] {1297// CHECK9-NEXT: entry:1298// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined)1299// CHECK9-NEXT: ret void1300//1301//1302// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined1303// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {1304// CHECK9-NEXT: entry:1305// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81306// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81307// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41308// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 41309// CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 81310// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41311// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41312// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41313// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41314// CHECK9-NEXT: [[G:%.*]] = alloca i32, align 41315// CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 41316// CHECK9-NEXT: [[_TMP2:%.*]] = alloca ptr, align 81317// CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 41318// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 41319// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 81320// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81321// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81322// CHECK9-NEXT: store ptr undef, ptr [[_TMP1]], align 81323// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41324// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 41325// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41326// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41327// CHECK9-NEXT: store ptr [[G1]], ptr [[_TMP2]], align 81328// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81329// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41330// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1331// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41332// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 11333// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1334// CHECK9: cond.true:1335// CHECK9-NEXT: br label [[COND_END:%.*]]1336// CHECK9: cond.false:1337// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41338// CHECK9-NEXT: br label [[COND_END]]1339// CHECK9: cond.end:1340// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]1341// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41342// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41343// CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 41344// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1345// CHECK9: omp.inner.for.cond:1346// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41347// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41348// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]1349// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1350// CHECK9: omp.inner.for.body:1351// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41352// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 11353// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1354// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 41355// CHECK9-NEXT: store i32 1, ptr [[G]], align 41356// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 81357// CHECK9-NEXT: store volatile i32 1, ptr [[TMP8]], align 41358// CHECK9-NEXT: store i32 2, ptr [[SIVAR]], align 41359// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 01360// CHECK9-NEXT: store ptr [[G]], ptr [[TMP9]], align 81361// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 11362// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 81363// CHECK9-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 81364// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 21365// CHECK9-NEXT: store ptr [[SIVAR]], ptr [[TMP12]], align 81366// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]])1367// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1368// CHECK9: omp.body.continue:1369// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1370// CHECK9: omp.inner.for.inc:1371// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41372// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 11373// CHECK9-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 41374// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]1375// CHECK9: omp.inner.for.end:1376// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1377// CHECK9: omp.loop.exit:1378// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])1379// CHECK9-NEXT: ret void1380//1381//1382// CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp1383// CHECK9-SAME: () #[[ATTR0]] {1384// CHECK9-NEXT: entry:1385// CHECK9-NEXT: call void @__cxx_global_var_init()1386// CHECK9-NEXT: call void @__cxx_global_var_init.1()1387// CHECK9-NEXT: call void @__cxx_global_var_init.2()1388// CHECK9-NEXT: ret void1389//1390