13145 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// Test host codegen.3// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK14// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s5// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK37// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s8// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK39// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK510// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s11// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK512// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK713// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s14// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK715 16// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK917// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s18// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK919// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1120// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s21// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1122// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1323// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s24// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1325// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1526// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s27// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1528 29// Test target codegen - host bc file has to be created first.30// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc31// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK1732// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s33// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1734// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc35// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK1936// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s37// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1938// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc39// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK2140// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s41// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2142// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc43// RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK2344// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s45// RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2346 47// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc48// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK949// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s50// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK951// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc52// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK1153// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s54// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1155// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc56// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK1357// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s58// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1359// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc60// RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK1561// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s62// RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1563// expected-no-diagnostics64 65#ifndef HEADER66#define HEADER67 68 69 70 71// We have 8 target regions, but only 7 that actually will generate offloading72// code, only 6 will have mapped arguments, and only 4 have all-constant map73// sizes.74 75 76 77// Check target registration is registered as a Ctor.78 79 80template<typename tx, typename ty>81struct TT{82 tx X;83 ty Y;84};85 86int global;87 88int foo(int n) {89 int a = 0;90 short aa = 0;91 float b[10];92 float bn[n];93 double c[5][10];94 double cn[5][n];95 TT<long long, char> d;96 97 #pragma omp target teams distribute simd num_teams(a) thread_limit(a) firstprivate(aa) simdlen(16) nowait98 for (int i = 0; i < 10; ++i) {99 }100 101#ifdef OMP5102 #pragma omp target teams distribute simd if(target: 0) safelen(32) linear(a) if(simd: 1) nontemporal(a)103#else104 #pragma omp target teams distribute simd if(target: 0) safelen(32) linear(a)105#endif // OMP5106 for (a = 0; a < 10; ++a) {107 a += 1;108 }109 110 111 #pragma omp target teams distribute simd if(target: 1)112 for (int i = 0; i < 10; ++i) {113 aa += 1;114 }115 116 117 118 #pragma omp target teams distribute simd if(target: n>10)119 for (int i = 0; i < 10; ++i) {120 a += 1;121 aa += 1;122 }123 124 // We capture 3 VLA sizes in this target region125 126 127 128 129 130 // The names below are not necessarily consistent with the names used for the131 // addresses above as some are repeated.132 133 134 135 136 137 138 139 140 141 142 #pragma omp target teams distribute simd if(target: n>20) aligned(b)143 for (int i = 0; i < 10; ++i) {144 a += 1;145 b[2] += 1.0;146 bn[3] += 1.0;147 c[1][2] += 1.0;148 cn[1][3] += 1.0;149 d.X += 1;150 d.Y += 1;151 }152 153 return a;154}155 156// Check that the offloading functions are emitted and that the arguments are157// correct and loaded correctly for the target regions in foo().158 159 160 161 162// Create stack storage and store argument in there.163 164// Create stack storage and store argument in there.165 166// Create stack storage and store argument in there.167 168// Create local storage for each capture.169 170 171 172// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.173 174template<typename tx>175tx ftemplate(int n) {176 tx a = 0;177 short aa = 0;178 tx b[10];179 180 #pragma omp target teams distribute simd if(target: n>40)181 for (int i = 0; i < 10; ++i) {182 a += 1;183 aa += 1;184 b[2] += 1;185 }186 187 return a;188}189 190static191int fstatic(int n) {192 int a = 0;193 short aa = 0;194 char aaa = 0;195 int b[10];196 197 #pragma omp target teams distribute simd if(target: n>50)198 for (int i = a; i < n; ++i) {199 a += 1;200 aa += 1;201 aaa += 1;202 b[2] += 1;203 }204 205 return a;206}207 208struct S1 {209 double a;210 211 int r1(int n){212 int b = n+1;213 short int c[2][n];214 215 #pragma omp target teams distribute simd if(n>60)216 for (int i = 0; i < 10; ++i) {217 this->a = (double)b + 1.5;218 c[1][1] = ++a;219 }220 221 return c[1][1] + (int)b;222 }223};224 225int bar(int n){226 int a = 0;227 228 a += foo(n);229 230 S1 S;231 a += S.r1(n);232 233 a += fstatic(n);234 235 a += ftemplate<int>(n);236 237 return a;238}239 240 241 242// We capture 2 VLA sizes in this target region243 244 245// The names below are not necessarily consistent with the names used for the246// addresses above as some are repeated.247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269// Check that the offloading functions are emitted and that the arguments are270// correct and loaded correctly for the target regions of the callees of bar().271 272// Create local storage for each capture.273// Store captures in the context.274 275 276// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.277 278 279// Create local storage for each capture.280// Store captures in the context.281 282 283 284 285// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.286 287// Create local storage for each capture.288// Store captures in the context.289 290 291 292// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.293 294 295#endif296// CHECK1-LABEL: define {{[^@]+}}@_Z3fooi297// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {298// CHECK1-NEXT: entry:299// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4300// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4301// CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2302// CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4303// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8304// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8305// CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8306// CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8307// CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8308// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4309// CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4310// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8311// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8312// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i64, align 8313// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8314// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8315// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8316// CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4317// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8318// CHECK1-NEXT: [[AA_CASTED4:%.*]] = alloca i64, align 8319// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x ptr], align 8320// CHECK1-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x ptr], align 8321// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x ptr], align 8322// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4323// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8324// CHECK1-NEXT: [[A_CASTED8:%.*]] = alloca i64, align 8325// CHECK1-NEXT: [[AA_CASTED9:%.*]] = alloca i64, align 8326// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x ptr], align 8327// CHECK1-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x ptr], align 8328// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x ptr], align 8329// CHECK1-NEXT: [[_TMP13:%.*]] = alloca i32, align 4330// CHECK1-NEXT: [[KERNEL_ARGS14:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8331// CHECK1-NEXT: [[A_CASTED17:%.*]] = alloca i64, align 8332// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x ptr], align 8333// CHECK1-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x ptr], align 8334// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x ptr], align 8335// CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8336// CHECK1-NEXT: [[_TMP23:%.*]] = alloca i32, align 4337// CHECK1-NEXT: [[KERNEL_ARGS24:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8338// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])339// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4340// CHECK1-NEXT: store i32 0, ptr [[A]], align 4341// CHECK1-NEXT: store i16 0, ptr [[AA]], align 2342// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4343// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64344// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()345// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8346// CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4347// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8348// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4349// CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64350// CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]351// CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8352// CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8353// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4354// CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4355// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4356// CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_2]], align 4357// CHECK1-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA]], align 2358// CHECK1-NEXT: store i16 [[TMP9]], ptr [[AA_CASTED]], align 2359// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[AA_CASTED]], align 8360// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4361// CHECK1-NEXT: store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4362// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8363// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4364// CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTCAPTURE_EXPR__CASTED3]], align 4365// CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED3]], align 8366// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0367// CHECK1-NEXT: store i64 [[TMP10]], ptr [[TMP15]], align 8368// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0369// CHECK1-NEXT: store i64 [[TMP10]], ptr [[TMP16]], align 8370// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0371// CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8372// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1373// CHECK1-NEXT: store i64 [[TMP12]], ptr [[TMP18]], align 8374// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1375// CHECK1-NEXT: store i64 [[TMP12]], ptr [[TMP19]], align 8376// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1377// CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 8378// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2379// CHECK1-NEXT: store i64 [[TMP14]], ptr [[TMP21]], align 8380// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2381// CHECK1-NEXT: store i64 [[TMP14]], ptr [[TMP22]], align 8382// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2383// CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8384// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0385// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0386// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0387// CHECK1-NEXT: [[TMP27:%.*]] = load i16, ptr [[AA]], align 2388// CHECK1-NEXT: store i16 [[TMP27]], ptr [[TMP26]], align 4389// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1390// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4391// CHECK1-NEXT: store i32 [[TMP29]], ptr [[TMP28]], align 4392// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2393// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4394// CHECK1-NEXT: store i32 [[TMP31]], ptr [[TMP30]], align 4395// CHECK1-NEXT: [[TMP32:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, ptr @.omp_task_entry., i64 -1)396// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP32]], i32 0, i32 0397// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP33]], i32 0, i32 0398// CHECK1-NEXT: [[TMP35:%.*]] = load ptr, ptr [[TMP34]], align 8399// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP35]], ptr align 4 [[AGG_CAPTURED]], i64 12, i1 false)400// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP32]], i32 0, i32 1401// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP36]], i32 0, i32 0402// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP37]], ptr align 8 [[TMP24]], i64 24, i1 false)403// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 1404// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP38]], ptr align 8 [[TMP25]], i64 24, i1 false)405// CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 2406// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP39]], ptr align 8 @.offload_sizes, i64 24, i1 false)407// CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 3408// CHECK1-NEXT: [[TMP41:%.*]] = load i16, ptr [[AA]], align 2409// CHECK1-NEXT: store i16 [[TMP41]], ptr [[TMP40]], align 8410// CHECK1-NEXT: [[TMP42:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP32]])411// CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[A]], align 4412// CHECK1-NEXT: store i32 [[TMP43]], ptr [[A_CASTED]], align 4413// CHECK1-NEXT: [[TMP44:%.*]] = load i64, ptr [[A_CASTED]], align 8414// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP44]]) #[[ATTR3:[0-9]+]]415// CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[AA]], align 2416// CHECK1-NEXT: store i16 [[TMP45]], ptr [[AA_CASTED4]], align 2417// CHECK1-NEXT: [[TMP46:%.*]] = load i64, ptr [[AA_CASTED4]], align 8418// CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0419// CHECK1-NEXT: store i64 [[TMP46]], ptr [[TMP47]], align 8420// CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0421// CHECK1-NEXT: store i64 [[TMP46]], ptr [[TMP48]], align 8422// CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0423// CHECK1-NEXT: store ptr null, ptr [[TMP49]], align 8424// CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0425// CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0426// CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0427// CHECK1-NEXT: store i32 3, ptr [[TMP52]], align 4428// CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1429// CHECK1-NEXT: store i32 1, ptr [[TMP53]], align 4430// CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2431// CHECK1-NEXT: store ptr [[TMP50]], ptr [[TMP54]], align 8432// CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3433// CHECK1-NEXT: store ptr [[TMP51]], ptr [[TMP55]], align 8434// CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4435// CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP56]], align 8436// CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5437// CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP57]], align 8438// CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6439// CHECK1-NEXT: store ptr null, ptr [[TMP58]], align 8440// CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7441// CHECK1-NEXT: store ptr null, ptr [[TMP59]], align 8442// CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8443// CHECK1-NEXT: store i64 10, ptr [[TMP60]], align 8444// CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9445// CHECK1-NEXT: store i64 0, ptr [[TMP61]], align 8446// CHECK1-NEXT: [[TMP62:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10447// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP62]], align 4448// CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11449// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP63]], align 4450// CHECK1-NEXT: [[TMP64:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12451// CHECK1-NEXT: store i32 0, ptr [[TMP64]], align 4452// CHECK1-NEXT: [[TMP65:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, ptr [[KERNEL_ARGS]])453// CHECK1-NEXT: [[TMP66:%.*]] = icmp ne i32 [[TMP65]], 0454// CHECK1-NEXT: br i1 [[TMP66]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]455// CHECK1: omp_offload.failed:456// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP46]]) #[[ATTR3]]457// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]458// CHECK1: omp_offload.cont:459// CHECK1-NEXT: [[TMP67:%.*]] = load i32, ptr [[A]], align 4460// CHECK1-NEXT: store i32 [[TMP67]], ptr [[A_CASTED8]], align 4461// CHECK1-NEXT: [[TMP68:%.*]] = load i64, ptr [[A_CASTED8]], align 8462// CHECK1-NEXT: [[TMP69:%.*]] = load i16, ptr [[AA]], align 2463// CHECK1-NEXT: store i16 [[TMP69]], ptr [[AA_CASTED9]], align 2464// CHECK1-NEXT: [[TMP70:%.*]] = load i64, ptr [[AA_CASTED9]], align 8465// CHECK1-NEXT: [[TMP71:%.*]] = load i32, ptr [[N_ADDR]], align 4466// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP71]], 10467// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]468// CHECK1: omp_if.then:469// CHECK1-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0470// CHECK1-NEXT: store i64 [[TMP68]], ptr [[TMP72]], align 8471// CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0472// CHECK1-NEXT: store i64 [[TMP68]], ptr [[TMP73]], align 8473// CHECK1-NEXT: [[TMP74:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0474// CHECK1-NEXT: store ptr null, ptr [[TMP74]], align 8475// CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1476// CHECK1-NEXT: store i64 [[TMP70]], ptr [[TMP75]], align 8477// CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 1478// CHECK1-NEXT: store i64 [[TMP70]], ptr [[TMP76]], align 8479// CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1480// CHECK1-NEXT: store ptr null, ptr [[TMP77]], align 8481// CHECK1-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0482// CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0483// CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 0484// CHECK1-NEXT: store i32 3, ptr [[TMP80]], align 4485// CHECK1-NEXT: [[TMP81:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 1486// CHECK1-NEXT: store i32 2, ptr [[TMP81]], align 4487// CHECK1-NEXT: [[TMP82:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 2488// CHECK1-NEXT: store ptr [[TMP78]], ptr [[TMP82]], align 8489// CHECK1-NEXT: [[TMP83:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 3490// CHECK1-NEXT: store ptr [[TMP79]], ptr [[TMP83]], align 8491// CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 4492// CHECK1-NEXT: store ptr @.offload_sizes.3, ptr [[TMP84]], align 8493// CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 5494// CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP85]], align 8495// CHECK1-NEXT: [[TMP86:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 6496// CHECK1-NEXT: store ptr null, ptr [[TMP86]], align 8497// CHECK1-NEXT: [[TMP87:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 7498// CHECK1-NEXT: store ptr null, ptr [[TMP87]], align 8499// CHECK1-NEXT: [[TMP88:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 8500// CHECK1-NEXT: store i64 10, ptr [[TMP88]], align 8501// CHECK1-NEXT: [[TMP89:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 9502// CHECK1-NEXT: store i64 0, ptr [[TMP89]], align 8503// CHECK1-NEXT: [[TMP90:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 10504// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP90]], align 4505// CHECK1-NEXT: [[TMP91:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 11506// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP91]], align 4507// CHECK1-NEXT: [[TMP92:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 12508// CHECK1-NEXT: store i32 0, ptr [[TMP92]], align 4509// CHECK1-NEXT: [[TMP93:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, ptr [[KERNEL_ARGS14]])510// CHECK1-NEXT: [[TMP94:%.*]] = icmp ne i32 [[TMP93]], 0511// CHECK1-NEXT: br i1 [[TMP94]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]512// CHECK1: omp_offload.failed15:513// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR3]]514// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT16]]515// CHECK1: omp_offload.cont16:516// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]517// CHECK1: omp_if.else:518// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR3]]519// CHECK1-NEXT: br label [[OMP_IF_END]]520// CHECK1: omp_if.end:521// CHECK1-NEXT: [[TMP95:%.*]] = load i32, ptr [[A]], align 4522// CHECK1-NEXT: store i32 [[TMP95]], ptr [[A_CASTED17]], align 4523// CHECK1-NEXT: [[TMP96:%.*]] = load i64, ptr [[A_CASTED17]], align 8524// CHECK1-NEXT: [[TMP97:%.*]] = load i32, ptr [[N_ADDR]], align 4525// CHECK1-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP97]], 20526// CHECK1-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE27:%.*]]527// CHECK1: omp_if.then19:528// CHECK1-NEXT: [[TMP98:%.*]] = mul nuw i64 [[TMP2]], 4529// CHECK1-NEXT: [[TMP99:%.*]] = mul nuw i64 5, [[TMP5]]530// CHECK1-NEXT: [[TMP100:%.*]] = mul nuw i64 [[TMP99]], 8531// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.5, i64 72, i1 false)532// CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0533// CHECK1-NEXT: store i64 [[TMP96]], ptr [[TMP101]], align 8534// CHECK1-NEXT: [[TMP102:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 0535// CHECK1-NEXT: store i64 [[TMP96]], ptr [[TMP102]], align 8536// CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0537// CHECK1-NEXT: store ptr null, ptr [[TMP103]], align 8538// CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1539// CHECK1-NEXT: store ptr [[B]], ptr [[TMP104]], align 8540// CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 1541// CHECK1-NEXT: store ptr [[B]], ptr [[TMP105]], align 8542// CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1543// CHECK1-NEXT: store ptr null, ptr [[TMP106]], align 8544// CHECK1-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2545// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP107]], align 8546// CHECK1-NEXT: [[TMP108:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 2547// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP108]], align 8548// CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2549// CHECK1-NEXT: store ptr null, ptr [[TMP109]], align 8550// CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3551// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP110]], align 8552// CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 3553// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP111]], align 8554// CHECK1-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3555// CHECK1-NEXT: store i64 [[TMP98]], ptr [[TMP112]], align 8556// CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3557// CHECK1-NEXT: store ptr null, ptr [[TMP113]], align 8558// CHECK1-NEXT: [[TMP114:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4559// CHECK1-NEXT: store ptr [[C]], ptr [[TMP114]], align 8560// CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 4561// CHECK1-NEXT: store ptr [[C]], ptr [[TMP115]], align 8562// CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4563// CHECK1-NEXT: store ptr null, ptr [[TMP116]], align 8564// CHECK1-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5565// CHECK1-NEXT: store i64 5, ptr [[TMP117]], align 8566// CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 5567// CHECK1-NEXT: store i64 5, ptr [[TMP118]], align 8568// CHECK1-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5569// CHECK1-NEXT: store ptr null, ptr [[TMP119]], align 8570// CHECK1-NEXT: [[TMP120:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6571// CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP120]], align 8572// CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 6573// CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP121]], align 8574// CHECK1-NEXT: [[TMP122:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6575// CHECK1-NEXT: store ptr null, ptr [[TMP122]], align 8576// CHECK1-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7577// CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP123]], align 8578// CHECK1-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 7579// CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP124]], align 8580// CHECK1-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7581// CHECK1-NEXT: store i64 [[TMP100]], ptr [[TMP125]], align 8582// CHECK1-NEXT: [[TMP126:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7583// CHECK1-NEXT: store ptr null, ptr [[TMP126]], align 8584// CHECK1-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8585// CHECK1-NEXT: store ptr [[D]], ptr [[TMP127]], align 8586// CHECK1-NEXT: [[TMP128:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 8587// CHECK1-NEXT: store ptr [[D]], ptr [[TMP128]], align 8588// CHECK1-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8589// CHECK1-NEXT: store ptr null, ptr [[TMP129]], align 8590// CHECK1-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0591// CHECK1-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 0592// CHECK1-NEXT: [[TMP132:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0593// CHECK1-NEXT: [[TMP133:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 0594// CHECK1-NEXT: store i32 3, ptr [[TMP133]], align 4595// CHECK1-NEXT: [[TMP134:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 1596// CHECK1-NEXT: store i32 9, ptr [[TMP134]], align 4597// CHECK1-NEXT: [[TMP135:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 2598// CHECK1-NEXT: store ptr [[TMP130]], ptr [[TMP135]], align 8599// CHECK1-NEXT: [[TMP136:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 3600// CHECK1-NEXT: store ptr [[TMP131]], ptr [[TMP136]], align 8601// CHECK1-NEXT: [[TMP137:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 4602// CHECK1-NEXT: store ptr [[TMP132]], ptr [[TMP137]], align 8603// CHECK1-NEXT: [[TMP138:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 5604// CHECK1-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP138]], align 8605// CHECK1-NEXT: [[TMP139:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 6606// CHECK1-NEXT: store ptr null, ptr [[TMP139]], align 8607// CHECK1-NEXT: [[TMP140:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 7608// CHECK1-NEXT: store ptr null, ptr [[TMP140]], align 8609// CHECK1-NEXT: [[TMP141:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 8610// CHECK1-NEXT: store i64 10, ptr [[TMP141]], align 8611// CHECK1-NEXT: [[TMP142:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 9612// CHECK1-NEXT: store i64 0, ptr [[TMP142]], align 8613// CHECK1-NEXT: [[TMP143:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 10614// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP143]], align 4615// CHECK1-NEXT: [[TMP144:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 11616// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP144]], align 4617// CHECK1-NEXT: [[TMP145:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 12618// CHECK1-NEXT: store i32 0, ptr [[TMP145]], align 4619// CHECK1-NEXT: [[TMP146:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, ptr [[KERNEL_ARGS24]])620// CHECK1-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0621// CHECK1-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]]622// CHECK1: omp_offload.failed25:623// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP96]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]624// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT26]]625// CHECK1: omp_offload.cont26:626// CHECK1-NEXT: br label [[OMP_IF_END28:%.*]]627// CHECK1: omp_if.else27:628// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP96]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]629// CHECK1-NEXT: br label [[OMP_IF_END28]]630// CHECK1: omp_if.end28:631// CHECK1-NEXT: [[TMP148:%.*]] = load i32, ptr [[A]], align 4632// CHECK1-NEXT: [[TMP149:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8633// CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP149]])634// CHECK1-NEXT: ret i32 [[TMP148]]635//636//637// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97638// CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {639// CHECK1-NEXT: entry:640// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8641// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8642// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8643// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8644// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])645// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8646// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8647// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8648// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4649// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4650// CHECK1-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])651// CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2652// CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2653// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8654// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i64 [[TMP4]])655// CHECK1-NEXT: ret void656//657//658// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined659// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {660// CHECK1-NEXT: entry:661// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8662// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8663// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8664// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4665// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4666// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4667// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4668// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4669// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4670// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4671// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8672// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8673// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8674// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4675// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4676// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4677// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4678// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8679// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4680// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)681// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4682// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9683// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]684// CHECK1: cond.true:685// CHECK1-NEXT: br label [[COND_END:%.*]]686// CHECK1: cond.false:687// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4688// CHECK1-NEXT: br label [[COND_END]]689// CHECK1: cond.end:690// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]691// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4692// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4693// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4694// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]695// CHECK1: omp.inner.for.cond:696// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]]697// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]]698// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]699// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]700// CHECK1: omp.inner.for.body:701// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]702// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1703// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]704// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]705// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]706// CHECK1: omp.body.continue:707// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]708// CHECK1: omp.inner.for.inc:709// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]710// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1711// CHECK1-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]712// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]713// CHECK1: omp.inner.for.end:714// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]715// CHECK1: omp.loop.exit:716// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])717// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4718// CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0719// CHECK1-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]720// CHECK1: .omp.final.then:721// CHECK1-NEXT: store i32 10, ptr [[I]], align 4722// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]723// CHECK1: .omp.final.done:724// CHECK1-NEXT: ret void725//726//727// CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map.728// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {729// CHECK1-NEXT: entry:730// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8731// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8732// CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8733// CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8734// CHECK1-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8735// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8736// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8737// CHECK1-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8738// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8739// CHECK1-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 8740// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8741// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0742// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8743// CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8744// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1745// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR3]], align 8746// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 8747// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2748// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR4]], align 8749// CHECK1-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 8750// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3751// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 8752// CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 8753// CHECK1-NEXT: ret void754//755//756// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry.757// CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {758// CHECK1-NEXT: entry:759// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4760// CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8761// CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8762// CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8763// CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8764// CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8765// CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8766// CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8767// CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 8768// CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 8769// CHECK1-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8770// CHECK1-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8771// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8772// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i64, align 8773// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4774// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8775// CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4776// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8777// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4778// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8779// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0780// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2781// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0782// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8783// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1784// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])785// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])786// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])787// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])788// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META26:![0-9]+]]789// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META26]]790// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META26]]791// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META26]]792// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META26]]793// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META26]]794// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META26]]795// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META26]]796// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META26]]797// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]798// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META26]]799// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META26]]800// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META26]]801// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META26]]802// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1803// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2804// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4805// CHECK1-NEXT: [[TMP19:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP18]], 0806// CHECK1-NEXT: store i32 3, ptr [[KERNEL_ARGS_I]], align 4, !noalias [[META26]]807// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1808// CHECK1-NEXT: store i32 3, ptr [[TMP20]], align 4, !noalias [[META26]]809// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2810// CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP21]], align 8, !noalias [[META26]]811// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3812// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP22]], align 8, !noalias [[META26]]813// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4814// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP23]], align 8, !noalias [[META26]]815// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5816// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP24]], align 8, !noalias [[META26]]817// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6818// CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8, !noalias [[META26]]819// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7820// CHECK1-NEXT: store ptr null, ptr [[TMP26]], align 8, !noalias [[META26]]821// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8822// CHECK1-NEXT: store i64 10, ptr [[TMP27]], align 8, !noalias [[META26]]823// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9824// CHECK1-NEXT: store i64 1, ptr [[TMP28]], align 8, !noalias [[META26]]825// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10826// CHECK1-NEXT: store [3 x i32] [[TMP19]], ptr [[TMP29]], align 4, !noalias [[META26]]827// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11828// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP30]], align 4, !noalias [[META26]]829// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12830// CHECK1-NEXT: store i32 0, ptr [[TMP31]], align 4, !noalias [[META26]]831// CHECK1-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 [[TMP18]], i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, ptr [[KERNEL_ARGS_I]])832// CHECK1-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0833// CHECK1-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]834// CHECK1: omp_offload.failed.i:835// CHECK1-NEXT: [[TMP34:%.*]] = load i16, ptr [[TMP12]], align 2836// CHECK1-NEXT: store i16 [[TMP34]], ptr [[AA_CASTED_I]], align 2, !noalias [[META26]]837// CHECK1-NEXT: [[TMP35:%.*]] = load i64, ptr [[AA_CASTED_I]], align 8, !noalias [[META26]]838// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP16]], align 4839// CHECK1-NEXT: store i32 [[TMP36]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias [[META26]]840// CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias [[META26]]841// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[TMP17]], align 4842// CHECK1-NEXT: store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias [[META26]]843// CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 8, !noalias [[META26]]844// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i64 [[TMP35]], i64 [[TMP37]], i64 [[TMP39]]) #[[ATTR3]]845// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]846// CHECK1: .omp_outlined..exit:847// CHECK1-NEXT: ret i32 0848//849//850// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104851// CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] {852// CHECK1-NEXT: entry:853// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8854// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8855// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8856// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4857// CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4858// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8859// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104.omp_outlined, i64 [[TMP1]])860// CHECK1-NEXT: ret void861//862//863// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104.omp_outlined864// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {865// CHECK1-NEXT: entry:866// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8867// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8868// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8869// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4870// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4871// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4872// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4873// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4874// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4875// CHECK1-NEXT: [[A1:%.*]] = alloca i32, align 4876// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8877// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8878// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8879// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4880// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4881// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4882// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4883// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8884// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4885// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)886// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4887// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9888// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]889// CHECK1: cond.true:890// CHECK1-NEXT: br label [[COND_END:%.*]]891// CHECK1: cond.false:892// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4893// CHECK1-NEXT: br label [[COND_END]]894// CHECK1: cond.end:895// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]896// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4897// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4898// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4899// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]900// CHECK1: omp.inner.for.cond:901// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4902// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4903// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]904// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]905// CHECK1: omp.inner.for.body:906// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4907// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1908// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]909// CHECK1-NEXT: store i32 [[ADD]], ptr [[A1]], align 4910// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 4911// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1912// CHECK1-NEXT: store i32 [[ADD3]], ptr [[A1]], align 4913// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]914// CHECK1: omp.body.continue:915// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]916// CHECK1: omp.inner.for.inc:917// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4918// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1919// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4920// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]921// CHECK1: omp.inner.for.end:922// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]923// CHECK1: omp.loop.exit:924// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])925// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4926// CHECK1-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0927// CHECK1-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]928// CHECK1: .omp.final.then:929// CHECK1-NEXT: store i32 10, ptr [[A_ADDR]], align 4930// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]931// CHECK1: .omp.final.done:932// CHECK1-NEXT: ret void933//934//935// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111936// CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] {937// CHECK1-NEXT: entry:938// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8939// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8940// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8941// CHECK1-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2942// CHECK1-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2943// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8944// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP1]])945// CHECK1-NEXT: ret void946//947//948// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined949// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {950// CHECK1-NEXT: entry:951// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8952// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8953// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8954// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4955// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4956// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4957// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4958// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4959// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4960// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4961// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8962// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8963// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8964// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4965// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4966// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4967// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4968// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8969// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4970// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)971// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4972// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9973// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]974// CHECK1: cond.true:975// CHECK1-NEXT: br label [[COND_END:%.*]]976// CHECK1: cond.false:977// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4978// CHECK1-NEXT: br label [[COND_END]]979// CHECK1: cond.end:980// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]981// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4982// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4983// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4984// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]985// CHECK1: omp.inner.for.cond:986// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29:![0-9]+]]987// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP29]]988// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]989// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]990// CHECK1: omp.inner.for.body:991// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]]992// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1993// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]994// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP29]]995// CHECK1-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]]996// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32997// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1998// CHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16999// CHECK1-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]]1000// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1001// CHECK1: omp.body.continue:1002// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1003// CHECK1: omp.inner.for.inc:1004// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]]1005// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 11006// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]]1007// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]1008// CHECK1: omp.inner.for.end:1009// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1010// CHECK1: omp.loop.exit:1011// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])1012// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41013// CHECK1-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 01014// CHECK1-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1015// CHECK1: .omp.final.then:1016// CHECK1-NEXT: store i32 10, ptr [[I]], align 41017// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]1018// CHECK1: .omp.final.done:1019// CHECK1-NEXT: ret void1020//1021//1022// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1181023// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {1024// CHECK1-NEXT: entry:1025// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81026// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 81027// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81028// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 81029// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81030// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 81031// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41032// CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 41033// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 81034// CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 21035// CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 21036// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 81037// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])1038// CHECK1-NEXT: ret void1039//1040//1041// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined1042// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {1043// CHECK1-NEXT: entry:1044// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81045// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81046// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81047// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 81048// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41049// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 41050// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41051// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41052// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41053// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41054// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 41055// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81056// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81057// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81058// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 81059// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41060// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 41061// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41062// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41063// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81064// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41065// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1066// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41067// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 91068// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1069// CHECK1: cond.true:1070// CHECK1-NEXT: br label [[COND_END:%.*]]1071// CHECK1: cond.false:1072// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41073// CHECK1-NEXT: br label [[COND_END]]1074// CHECK1: cond.end:1075// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]1076// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41077// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41078// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 41079// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1080// CHECK1: omp.inner.for.cond:1081// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32:![0-9]+]]1082// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP32]]1083// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]1084// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1085// CHECK1: omp.inner.for.body:1086// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]1087// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 11088// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1089// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP32]]1090// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]]1091// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 11092// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]]1093// CHECK1-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]]1094// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i321095// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 11096// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i161097// CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]]1098// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1099// CHECK1: omp.body.continue:1100// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1101// CHECK1: omp.inner.for.inc:1102// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]1103// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 11104// CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]1105// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]1106// CHECK1: omp.inner.for.end:1107// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1108// CHECK1: omp.loop.exit:1109// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])1110// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41111// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 01112// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1113// CHECK1: .omp.final.then:1114// CHECK1-NEXT: store i32 10, ptr [[I]], align 41115// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]1116// CHECK1: .omp.final.done:1117// CHECK1-NEXT: ret void1118//1119//1120// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1421121// CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {1122// CHECK1-NEXT: entry:1123// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81124// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81125// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 81126// CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 81127// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81128// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 81129// CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 81130// CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 81131// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 81132// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81133// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81134// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81135// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 81136// CHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 81137// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81138// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 81139// CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 81140// CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 81141// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 81142// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81143// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 81144// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 81145// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 81146// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 81147// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 81148// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 81149// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 81150// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 41151// CHECK1-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 41152// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 81153// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])1154// CHECK1-NEXT: ret void1155//1156//1157// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined1158// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {1159// CHECK1-NEXT: entry:1160// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81161// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81162// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81163// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81164// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 81165// CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 81166// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81167// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 81168// CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 81169// CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 81170// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 81171// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41172// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 41173// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41174// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41175// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41176// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41177// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 41178// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81179// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81180// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81181// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81182// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 81183// CHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 81184// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81185// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 81186// CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 81187// CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 81188// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 81189// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81190// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 81191// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 81192// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 81193// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 81194// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 81195// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 81196// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 81197// CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 01198// CHECK1-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i64 16) ]1199// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41200// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 41201// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41202// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41203// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81204// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 41205// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1206// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41207// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 91208// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1209// CHECK1: cond.true:1210// CHECK1-NEXT: br label [[COND_END:%.*]]1211// CHECK1: cond.false:1212// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41213// CHECK1-NEXT: br label [[COND_END]]1214// CHECK1: cond.end:1215// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]1216// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41217// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41218// CHECK1-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 41219// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1220// CHECK1: omp.inner.for.cond:1221// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35:![0-9]+]]1222// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP35]]1223// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]1224// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1225// CHECK1: omp.inner.for.body:1226// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]1227// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 11228// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1229// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP35]]1230// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]]1231// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 11232// CHECK1-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]]1233// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 21234// CHECK1-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]]1235// CHECK1-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double1236// CHECK1-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+001237// CHECK1-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float1238// CHECK1-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]]1239// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 31240// CHECK1-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP35]]1241// CHECK1-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double1242// CHECK1-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+001243// CHECK1-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float1244// CHECK1-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP35]]1245// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 11246// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i64 0, i64 21247// CHECK1-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP35]]1248// CHECK1-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+001249// CHECK1-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP35]]1250// CHECK1-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]]1251// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP20]]1252// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i64 31253// CHECK1-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP35]]1254// CHECK1-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+001255// CHECK1-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP35]]1256// CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 01257// CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP35]]1258// CHECK1-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 11259// CHECK1-NEXT: store i64 [[ADD19]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP35]]1260// CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 11261// CHECK1-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP35]]1262// CHECK1-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i321263// CHECK1-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 11264// CHECK1-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i81265// CHECK1-NEXT: store i8 [[CONV22]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP35]]1266// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1267// CHECK1: omp.body.continue:1268// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1269// CHECK1: omp.inner.for.inc:1270// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]1271// CHECK1-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 11272// CHECK1-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]1273// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]1274// CHECK1: omp.inner.for.end:1275// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1276// CHECK1: omp.loop.exit:1277// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP9]])1278// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41279// CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 01280// CHECK1-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1281// CHECK1: .omp.final.then:1282// CHECK1-NEXT: store i32 10, ptr [[I]], align 41283// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]1284// CHECK1: .omp.final.done:1285// CHECK1-NEXT: ret void1286//1287//1288// CHECK1-LABEL: define {{[^@]+}}@_Z3bari1289// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {1290// CHECK1-NEXT: entry:1291// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 41292// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 41293// CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 81294// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 41295// CHECK1-NEXT: store i32 0, ptr [[A]], align 41296// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 41297// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])1298// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 41299// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]1300// CHECK1-NEXT: store i32 [[ADD]], ptr [[A]], align 41301// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 41302// CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])1303// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 41304// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]1305// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A]], align 41306// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 41307// CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])1308// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 41309// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]1310// CHECK1-NEXT: store i32 [[ADD4]], ptr [[A]], align 41311// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 41312// CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])1313// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 41314// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]1315// CHECK1-NEXT: store i32 [[ADD6]], ptr [[A]], align 41316// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 41317// CHECK1-NEXT: ret i32 [[TMP8]]1318//1319//1320// CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei1321// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {1322// CHECK1-NEXT: entry:1323// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81324// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 41325// CHECK1-NEXT: [[B:%.*]] = alloca i32, align 41326// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 81327// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 81328// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 81329// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 81330// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 81331// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 81332// CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 81333// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 41334// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81335// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81336// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 41337// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81338// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 41339// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 11340// CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 41341// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 41342// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i641343// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()1344// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 81345// CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]1346// CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 21347// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 81348// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 41349// CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 41350// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 81351// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 41352// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 601353// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]1354// CHECK1: omp_if.then:1355// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 01356// CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]1357// CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 21358// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.7, i64 40, i1 false)1359// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01360// CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 81361// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01362// CHECK1-NEXT: store ptr [[A]], ptr [[TMP11]], align 81363// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 01364// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 81365// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11366// CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP13]], align 81367// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11368// CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP14]], align 81369// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 11370// CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 81371// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21372// CHECK1-NEXT: store i64 2, ptr [[TMP16]], align 81373// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21374// CHECK1-NEXT: store i64 2, ptr [[TMP17]], align 81375// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 21376// CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 81377// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31378// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP19]], align 81379// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31380// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP20]], align 81381// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 31382// CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 81383// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 41384// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 81385// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 41386// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 81387// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 41388// CHECK1-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 81389// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 41390// CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 81391// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01392// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01393// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 01394// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01395// CHECK1-NEXT: store i32 3, ptr [[TMP29]], align 41396// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11397// CHECK1-NEXT: store i32 5, ptr [[TMP30]], align 41398// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21399// CHECK1-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 81400// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31401// CHECK1-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 81402// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41403// CHECK1-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 81404// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51405// CHECK1-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP34]], align 81406// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61407// CHECK1-NEXT: store ptr null, ptr [[TMP35]], align 81408// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71409// CHECK1-NEXT: store ptr null, ptr [[TMP36]], align 81410// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81411// CHECK1-NEXT: store i64 10, ptr [[TMP37]], align 81412// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91413// CHECK1-NEXT: store i64 0, ptr [[TMP38]], align 81414// CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101415// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP39]], align 41416// CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111417// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP40]], align 41418// CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121419// CHECK1-NEXT: store i32 0, ptr [[TMP41]], align 41420// CHECK1-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.region_id, ptr [[KERNEL_ARGS]])1421// CHECK1-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 01422// CHECK1-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1423// CHECK1: omp_offload.failed:1424// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]1425// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]1426// CHECK1: omp_offload.cont:1427// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]1428// CHECK1: omp_if.else:1429// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]1430// CHECK1-NEXT: br label [[OMP_IF_END]]1431// CHECK1: omp_if.end:1432// CHECK1-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]]1433// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]]1434// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 11435// CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 21436// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i321437// CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 41438// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]1439// CHECK1-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 81440// CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])1441// CHECK1-NEXT: ret i32 [[ADD3]]1442//1443//1444// CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici1445// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {1446// CHECK1-NEXT: entry:1447// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 41448// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 41449// CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 21450// CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 11451// CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 41452// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81453// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 81454// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 81455// CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 81456// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 81457// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 81458// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 81459// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 41460// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 41461// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 41462// CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 41463// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81464// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 41465// CHECK1-NEXT: store i32 0, ptr [[A]], align 41466// CHECK1-NEXT: store i16 0, ptr [[AA]], align 21467// CHECK1-NEXT: store i8 0, ptr [[AAA]], align 11468// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 41469// CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 41470// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 81471// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 41472// CHECK1-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 41473// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[N_CASTED]], align 81474// CHECK1-NEXT: [[TMP4:%.*]] = load i16, ptr [[AA]], align 21475// CHECK1-NEXT: store i16 [[TMP4]], ptr [[AA_CASTED]], align 21476// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[AA_CASTED]], align 81477// CHECK1-NEXT: [[TMP6:%.*]] = load i8, ptr [[AAA]], align 11478// CHECK1-NEXT: store i8 [[TMP6]], ptr [[AAA_CASTED]], align 11479// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[AAA_CASTED]], align 81480// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[N_ADDR]], align 41481// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 501482// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]1483// CHECK1: omp_if.then:1484// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01485// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP9]], align 81486// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01487// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP10]], align 81488// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 01489// CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 81490// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11491// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP12]], align 81492// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11493// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP13]], align 81494// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 11495// CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 81496// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21497// CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP15]], align 81498// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21499// CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP16]], align 81500// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 21501// CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 81502// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31503// CHECK1-NEXT: store i64 [[TMP7]], ptr [[TMP18]], align 81504// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31505// CHECK1-NEXT: store i64 [[TMP7]], ptr [[TMP19]], align 81506// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 31507// CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 81508// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 41509// CHECK1-NEXT: store ptr [[B]], ptr [[TMP21]], align 81510// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 41511// CHECK1-NEXT: store ptr [[B]], ptr [[TMP22]], align 81512// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 41513// CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 81514// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01515// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01516// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[A]], align 41517// CHECK1-NEXT: store i32 [[TMP26]], ptr [[DOTCAPTURE_EXPR_]], align 41518// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[N_ADDR]], align 41519// CHECK1-NEXT: store i32 [[TMP27]], ptr [[DOTCAPTURE_EXPR_1]], align 41520// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 41521// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41522// CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP28]], [[TMP29]]1523// CHECK1-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 11524// CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 11525// CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 11526// CHECK1-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 11527// CHECK1-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 41528// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41529// CHECK1-NEXT: [[ADD5:%.*]] = add i32 [[TMP30]], 11530// CHECK1-NEXT: [[TMP31:%.*]] = zext i32 [[ADD5]] to i641531// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01532// CHECK1-NEXT: store i32 3, ptr [[TMP32]], align 41533// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11534// CHECK1-NEXT: store i32 5, ptr [[TMP33]], align 41535// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21536// CHECK1-NEXT: store ptr [[TMP24]], ptr [[TMP34]], align 81537// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31538// CHECK1-NEXT: store ptr [[TMP25]], ptr [[TMP35]], align 81539// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41540// CHECK1-NEXT: store ptr @.offload_sizes.9, ptr [[TMP36]], align 81541// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51542// CHECK1-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP37]], align 81543// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61544// CHECK1-NEXT: store ptr null, ptr [[TMP38]], align 81545// CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71546// CHECK1-NEXT: store ptr null, ptr [[TMP39]], align 81547// CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81548// CHECK1-NEXT: store i64 [[TMP31]], ptr [[TMP40]], align 81549// CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91550// CHECK1-NEXT: store i64 0, ptr [[TMP41]], align 81551// CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101552// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP42]], align 41553// CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111554// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP43]], align 41555// CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121556// CHECK1-NEXT: store i32 0, ptr [[TMP44]], align 41557// CHECK1-NEXT: [[TMP45:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.region_id, ptr [[KERNEL_ARGS]])1558// CHECK1-NEXT: [[TMP46:%.*]] = icmp ne i32 [[TMP45]], 01559// CHECK1-NEXT: br i1 [[TMP46]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1560// CHECK1: omp_offload.failed:1561// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], ptr [[B]]) #[[ATTR3]]1562// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]1563// CHECK1: omp_offload.cont:1564// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]1565// CHECK1: omp_if.else:1566// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], ptr [[B]]) #[[ATTR3]]1567// CHECK1-NEXT: br label [[OMP_IF_END]]1568// CHECK1: omp_if.end:1569// CHECK1-NEXT: [[TMP47:%.*]] = load i32, ptr [[A]], align 41570// CHECK1-NEXT: ret i32 [[TMP47]]1571//1572//1573// CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i1574// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {1575// CHECK1-NEXT: entry:1576// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 41577// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 41578// CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 21579// CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 41580// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81581// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 81582// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 81583// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 81584// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 81585// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 41586// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81587// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 41588// CHECK1-NEXT: store i32 0, ptr [[A]], align 41589// CHECK1-NEXT: store i16 0, ptr [[AA]], align 21590// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 41591// CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 41592// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 81593// CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 21594// CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 21595// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 81596// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 41597// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 401598// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]1599// CHECK1: omp_if.then:1600// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01601// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 81602// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01603// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP6]], align 81604// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 01605// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 81606// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11607// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP8]], align 81608// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11609// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP9]], align 81610// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 11611// CHECK1-NEXT: store ptr null, ptr [[TMP10]], align 81612// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21613// CHECK1-NEXT: store ptr [[B]], ptr [[TMP11]], align 81614// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21615// CHECK1-NEXT: store ptr [[B]], ptr [[TMP12]], align 81616// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 21617// CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 81618// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01619// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01620// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01621// CHECK1-NEXT: store i32 3, ptr [[TMP16]], align 41622// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11623// CHECK1-NEXT: store i32 3, ptr [[TMP17]], align 41624// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21625// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 81626// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31627// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 81628// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41629// CHECK1-NEXT: store ptr @.offload_sizes.11, ptr [[TMP20]], align 81630// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51631// CHECK1-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP21]], align 81632// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61633// CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 81634// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71635// CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 81636// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81637// CHECK1-NEXT: store i64 10, ptr [[TMP24]], align 81638// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91639// CHECK1-NEXT: store i64 0, ptr [[TMP25]], align 81640// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101641// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 41642// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111643// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 41644// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121645// CHECK1-NEXT: store i32 0, ptr [[TMP28]], align 41646// CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.region_id, ptr [[KERNEL_ARGS]])1647// CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 01648// CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1649// CHECK1: omp_offload.failed:1650// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]1651// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]1652// CHECK1: omp_offload.cont:1653// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]1654// CHECK1: omp_if.else:1655// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]1656// CHECK1-NEXT: br label [[OMP_IF_END]]1657// CHECK1: omp_if.end:1658// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 41659// CHECK1-NEXT: ret i32 [[TMP31]]1660//1661//1662// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2151663// CHECK1-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {1664// CHECK1-NEXT: entry:1665// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81666// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 81667// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 81668// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 81669// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81670// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 81671// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81672// CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 81673// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 81674// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 81675// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81676// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81677// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 81678// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 81679// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 81680// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 41681// CHECK1-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 41682// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 81683// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])1684// CHECK1-NEXT: ret void1685//1686//1687// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined1688// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {1689// CHECK1-NEXT: entry:1690// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81691// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81692// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81693// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 81694// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 81695// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 81696// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 81697// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41698// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 41699// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41700// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41701// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41702// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41703// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 41704// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81705// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81706// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81707// CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 81708// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 81709// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 81710// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 81711// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81712// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 81713// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 81714// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 81715// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41716// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 41717// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41718// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41719// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81720// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 41721// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1722// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41723// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 91724// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1725// CHECK1: cond.true:1726// CHECK1-NEXT: br label [[COND_END:%.*]]1727// CHECK1: cond.false:1728// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41729// CHECK1-NEXT: br label [[COND_END]]1730// CHECK1: cond.end:1731// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]1732// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41733// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41734// CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 41735// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1736// CHECK1: omp.inner.for.cond:1737// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38:![0-9]+]]1738// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP38]]1739// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]1740// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1741// CHECK1: omp.inner.for.body:1742// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]]1743// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 11744// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1745// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP38]]1746// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP38]]1747// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double1748// CHECK1-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+001749// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 01750// CHECK1-NEXT: store double [[ADD4]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP38]]1751// CHECK1-NEXT: [[A5:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 01752// CHECK1-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP38]]1753// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+001754// CHECK1-NEXT: store double [[INC]], ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP38]]1755// CHECK1-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i161756// CHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]1757// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]]1758// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 11759// CHECK1-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP38]]1760// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1761// CHECK1: omp.body.continue:1762// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1763// CHECK1: omp.inner.for.inc:1764// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]]1765// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 11766// CHECK1-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]]1767// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]]1768// CHECK1: omp.inner.for.end:1769// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1770// CHECK1: omp.loop.exit:1771// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])1772// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41773// CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 01774// CHECK1-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1775// CHECK1: .omp.final.then:1776// CHECK1-NEXT: store i32 10, ptr [[I]], align 41777// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]1778// CHECK1: .omp.final.done:1779// CHECK1-NEXT: ret void1780//1781//1782// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1971783// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {1784// CHECK1-NEXT: entry:1785// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81786// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 81787// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 81788// CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 81789// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81790// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81791// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 81792// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 81793// CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 81794// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81795// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 81796// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 81797// CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 81798// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81799// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81800// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 41801// CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 41802// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 81803// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 41804// CHECK1-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 41805// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 81806// CHECK1-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 21807// CHECK1-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 21808// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[AA_CASTED]], align 81809// CHECK1-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 11810// CHECK1-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 11811// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[AAA_CASTED]], align 81812// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], ptr [[TMP0]])1813// CHECK1-NEXT: ret void1814//1815//1816// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined1817// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {1818// CHECK1-NEXT: entry:1819// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81820// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81821// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81822// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 81823// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 81824// CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 81825// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81826// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41827// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 41828// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 41829// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 41830// CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 41831// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 41832// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41833// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41834// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41835// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41836// CHECK1-NEXT: [[I5:%.*]] = alloca i32, align 41837// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81838// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81839// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81840// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 81841// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 81842// CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 81843// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81844// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81845// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 41846// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 41847// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 41848// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 41849// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 41850// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41851// CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]1852// CHECK1-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 11853// CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 11854// CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 11855// CHECK1-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 11856// CHECK1-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 41857// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41858// CHECK1-NEXT: store i32 [[TMP5]], ptr [[I]], align 41859// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41860// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 41861// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]1862// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]1863// CHECK1: omp.precond.then:1864// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41865// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41866// CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 41867// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41868// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41869// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81870// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 41871// CHECK1-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1872// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41873// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41874// CHECK1-NEXT: [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]1875// CHECK1-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1876// CHECK1: cond.true:1877// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41878// CHECK1-NEXT: br label [[COND_END:%.*]]1879// CHECK1: cond.false:1880// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41881// CHECK1-NEXT: br label [[COND_END]]1882// CHECK1: cond.end:1883// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]1884// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41885// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41886// CHECK1-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 41887// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1888// CHECK1: omp.inner.for.cond:1889// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41:![0-9]+]]1890// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP41]]1891// CHECK1-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 11892// CHECK1-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]1893// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1894// CHECK1: omp.inner.for.body:1895// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP41]]1896// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41]]1897// CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 11898// CHECK1-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]1899// CHECK1-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP41]]1900// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP41]]1901// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 11902// CHECK1-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP41]]1903// CHECK1-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP41]]1904// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i321905// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 11906// CHECK1-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i161907// CHECK1-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP41]]1908// CHECK1-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP41]]1909// CHECK1-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i321910// CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 11911// CHECK1-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i81912// CHECK1-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP41]]1913// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 21914// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP41]]1915// CHECK1-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 11916// CHECK1-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP41]]1917// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1918// CHECK1: omp.body.continue:1919// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1920// CHECK1: omp.inner.for.inc:1921// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41]]1922// CHECK1-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 11923// CHECK1-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41]]1924// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]]1925// CHECK1: omp.inner.for.end:1926// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1927// CHECK1: omp.loop.exit:1928// CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81929// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 41930// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])1931// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41932// CHECK1-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 01933// CHECK1-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1934// CHECK1: .omp.final.then:1935// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41936// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 41937// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41938// CHECK1-NEXT: [[SUB18:%.*]] = sub i32 [[TMP30]], [[TMP31]]1939// CHECK1-NEXT: [[SUB19:%.*]] = sub i32 [[SUB18]], 11940// CHECK1-NEXT: [[ADD20:%.*]] = add i32 [[SUB19]], 11941// CHECK1-NEXT: [[DIV21:%.*]] = udiv i32 [[ADD20]], 11942// CHECK1-NEXT: [[MUL22:%.*]] = mul i32 [[DIV21]], 11943// CHECK1-NEXT: [[ADD23:%.*]] = add i32 [[TMP29]], [[MUL22]]1944// CHECK1-NEXT: store i32 [[ADD23]], ptr [[I5]], align 41945// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]1946// CHECK1: .omp.final.done:1947// CHECK1-NEXT: br label [[OMP_PRECOND_END]]1948// CHECK1: omp.precond.end:1949// CHECK1-NEXT: ret void1950//1951//1952// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1801953// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {1954// CHECK1-NEXT: entry:1955// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81956// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 81957// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81958// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 81959// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 81960// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81961// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 81962// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81963// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81964// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 41965// CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 41966// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 81967// CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 21968// CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 21969// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 81970// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])1971// CHECK1-NEXT: ret void1972//1973//1974// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined1975// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {1976// CHECK1-NEXT: entry:1977// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81978// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81979// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 81980// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 81981// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 81982// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41983// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 41984// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41985// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41986// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41987// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41988// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 41989// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81990// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81991// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 81992// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 81993// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 81994// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 81995// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41996// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 41997// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41998// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41999// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82000// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 42001// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2002// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42003// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 92004// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2005// CHECK1: cond.true:2006// CHECK1-NEXT: br label [[COND_END:%.*]]2007// CHECK1: cond.false:2008// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42009// CHECK1-NEXT: br label [[COND_END]]2010// CHECK1: cond.end:2011// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]2012// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 42013// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42014// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 42015// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2016// CHECK1: omp.inner.for.cond:2017// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44:![0-9]+]]2018// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP44]]2019// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]2020// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2021// CHECK1: omp.inner.for.body:2022// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]2023// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 12024// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2025// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP44]]2026// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]]2027// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 12028// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]]2029// CHECK1-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP44]]2030// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i322031// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 12032// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i162033// CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP44]]2034// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 22035// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]]2036// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 12037// CHECK1-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]]2038// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2039// CHECK1: omp.body.continue:2040// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2041// CHECK1: omp.inner.for.inc:2042// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]2043// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 12044// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]2045// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]]2046// CHECK1: omp.inner.for.end:2047// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2048// CHECK1: omp.loop.exit:2049// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])2050// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42051// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 02052// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]2053// CHECK1: .omp.final.then:2054// CHECK1-NEXT: store i32 10, ptr [[I]], align 42055// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]2056// CHECK1: .omp.final.done:2057// CHECK1-NEXT: ret void2058//2059//2060// CHECK3-LABEL: define {{[^@]+}}@_Z3fooi2061// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {2062// CHECK3-NEXT: entry:2063// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 42064// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 42065// CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 22066// CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 42067// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 42068// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 42069// CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 82070// CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 42071// CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 42072// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 42073// CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 42074// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 42075// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 42076// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 42077// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 42078// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 42079// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 42080// CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 42081// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 42082// CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 42083// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x ptr], align 42084// CHECK3-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x ptr], align 42085// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x ptr], align 42086// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 42087// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 82088// CHECK3-NEXT: [[A_CASTED8:%.*]] = alloca i32, align 42089// CHECK3-NEXT: [[AA_CASTED9:%.*]] = alloca i32, align 42090// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x ptr], align 42091// CHECK3-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x ptr], align 42092// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x ptr], align 42093// CHECK3-NEXT: [[_TMP13:%.*]] = alloca i32, align 42094// CHECK3-NEXT: [[KERNEL_ARGS14:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 82095// CHECK3-NEXT: [[A_CASTED17:%.*]] = alloca i32, align 42096// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x ptr], align 42097// CHECK3-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x ptr], align 42098// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x ptr], align 42099// CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 42100// CHECK3-NEXT: [[_TMP23:%.*]] = alloca i32, align 42101// CHECK3-NEXT: [[KERNEL_ARGS24:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 82102// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])2103// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 42104// CHECK3-NEXT: store i32 0, ptr [[A]], align 42105// CHECK3-NEXT: store i16 0, ptr [[AA]], align 22106// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 42107// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()2108// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 42109// CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 42110// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 42111// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 42112// CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]2113// CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 82114// CHECK3-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 42115// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 42116// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 42117// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 42118// CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_2]], align 42119// CHECK3-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 22120// CHECK3-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 22121// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 42122// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42123// CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 42124// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 42125// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 42126// CHECK3-NEXT: store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED3]], align 42127// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED3]], align 42128// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02129// CHECK3-NEXT: store i32 [[TMP8]], ptr [[TMP13]], align 42130// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 02131// CHECK3-NEXT: store i32 [[TMP8]], ptr [[TMP14]], align 42132// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 02133// CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 42134// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 12135// CHECK3-NEXT: store i32 [[TMP10]], ptr [[TMP16]], align 42136// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 12137// CHECK3-NEXT: store i32 [[TMP10]], ptr [[TMP17]], align 42138// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 12139// CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 42140// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 22141// CHECK3-NEXT: store i32 [[TMP12]], ptr [[TMP19]], align 42142// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 22143// CHECK3-NEXT: store i32 [[TMP12]], ptr [[TMP20]], align 42144// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 22145// CHECK3-NEXT: store ptr null, ptr [[TMP21]], align 42146// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 02147// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 02148// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 02149// CHECK3-NEXT: [[TMP25:%.*]] = load i16, ptr [[AA]], align 22150// CHECK3-NEXT: store i16 [[TMP25]], ptr [[TMP24]], align 42151// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 12152// CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 42153// CHECK3-NEXT: store i32 [[TMP27]], ptr [[TMP26]], align 42154// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 22155// CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 42156// CHECK3-NEXT: store i32 [[TMP29]], ptr [[TMP28]], align 42157// CHECK3-NEXT: [[TMP30:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, ptr @.omp_task_entry., i64 -1)2158// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP30]], i32 0, i32 02159// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP31]], i32 0, i32 02160// CHECK3-NEXT: [[TMP33:%.*]] = load ptr, ptr [[TMP32]], align 42161// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP33]], ptr align 4 [[AGG_CAPTURED]], i32 12, i1 false)2162// CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP30]], i32 0, i32 12163// CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP34]], i32 0, i32 02164// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP35]], ptr align 4 @.offload_sizes, i32 24, i1 false)2165// CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 12166// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP36]], ptr align 4 [[TMP22]], i32 12, i1 false)2167// CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 22168// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP37]], ptr align 4 [[TMP23]], i32 12, i1 false)2169// CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 32170// CHECK3-NEXT: [[TMP39:%.*]] = load i16, ptr [[AA]], align 22171// CHECK3-NEXT: store i16 [[TMP39]], ptr [[TMP38]], align 42172// CHECK3-NEXT: [[TMP40:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP30]])2173// CHECK3-NEXT: [[TMP41:%.*]] = load i32, ptr [[A]], align 42174// CHECK3-NEXT: store i32 [[TMP41]], ptr [[A_CASTED]], align 42175// CHECK3-NEXT: [[TMP42:%.*]] = load i32, ptr [[A_CASTED]], align 42176// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP42]]) #[[ATTR3:[0-9]+]]2177// CHECK3-NEXT: [[TMP43:%.*]] = load i16, ptr [[AA]], align 22178// CHECK3-NEXT: store i16 [[TMP43]], ptr [[AA_CASTED4]], align 22179// CHECK3-NEXT: [[TMP44:%.*]] = load i32, ptr [[AA_CASTED4]], align 42180// CHECK3-NEXT: [[TMP45:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 02181// CHECK3-NEXT: store i32 [[TMP44]], ptr [[TMP45]], align 42182// CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 02183// CHECK3-NEXT: store i32 [[TMP44]], ptr [[TMP46]], align 42184// CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 02185// CHECK3-NEXT: store ptr null, ptr [[TMP47]], align 42186// CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 02187// CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 02188// CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 02189// CHECK3-NEXT: store i32 3, ptr [[TMP50]], align 42190// CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12191// CHECK3-NEXT: store i32 1, ptr [[TMP51]], align 42192// CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 22193// CHECK3-NEXT: store ptr [[TMP48]], ptr [[TMP52]], align 42194// CHECK3-NEXT: [[TMP53:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 32195// CHECK3-NEXT: store ptr [[TMP49]], ptr [[TMP53]], align 42196// CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 42197// CHECK3-NEXT: store ptr @.offload_sizes.1, ptr [[TMP54]], align 42198// CHECK3-NEXT: [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 52199// CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP55]], align 42200// CHECK3-NEXT: [[TMP56:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 62201// CHECK3-NEXT: store ptr null, ptr [[TMP56]], align 42202// CHECK3-NEXT: [[TMP57:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 72203// CHECK3-NEXT: store ptr null, ptr [[TMP57]], align 42204// CHECK3-NEXT: [[TMP58:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 82205// CHECK3-NEXT: store i64 10, ptr [[TMP58]], align 82206// CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 92207// CHECK3-NEXT: store i64 0, ptr [[TMP59]], align 82208// CHECK3-NEXT: [[TMP60:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 102209// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP60]], align 42210// CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 112211// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP61]], align 42212// CHECK3-NEXT: [[TMP62:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 122213// CHECK3-NEXT: store i32 0, ptr [[TMP62]], align 42214// CHECK3-NEXT: [[TMP63:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, ptr [[KERNEL_ARGS]])2215// CHECK3-NEXT: [[TMP64:%.*]] = icmp ne i32 [[TMP63]], 02216// CHECK3-NEXT: br i1 [[TMP64]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]2217// CHECK3: omp_offload.failed:2218// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP44]]) #[[ATTR3]]2219// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]2220// CHECK3: omp_offload.cont:2221// CHECK3-NEXT: [[TMP65:%.*]] = load i32, ptr [[A]], align 42222// CHECK3-NEXT: store i32 [[TMP65]], ptr [[A_CASTED8]], align 42223// CHECK3-NEXT: [[TMP66:%.*]] = load i32, ptr [[A_CASTED8]], align 42224// CHECK3-NEXT: [[TMP67:%.*]] = load i16, ptr [[AA]], align 22225// CHECK3-NEXT: store i16 [[TMP67]], ptr [[AA_CASTED9]], align 22226// CHECK3-NEXT: [[TMP68:%.*]] = load i32, ptr [[AA_CASTED9]], align 42227// CHECK3-NEXT: [[TMP69:%.*]] = load i32, ptr [[N_ADDR]], align 42228// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP69]], 102229// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]2230// CHECK3: omp_if.then:2231// CHECK3-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 02232// CHECK3-NEXT: store i32 [[TMP66]], ptr [[TMP70]], align 42233// CHECK3-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 02234// CHECK3-NEXT: store i32 [[TMP66]], ptr [[TMP71]], align 42235// CHECK3-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 02236// CHECK3-NEXT: store ptr null, ptr [[TMP72]], align 42237// CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 12238// CHECK3-NEXT: store i32 [[TMP68]], ptr [[TMP73]], align 42239// CHECK3-NEXT: [[TMP74:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 12240// CHECK3-NEXT: store i32 [[TMP68]], ptr [[TMP74]], align 42241// CHECK3-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 12242// CHECK3-NEXT: store ptr null, ptr [[TMP75]], align 42243// CHECK3-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 02244// CHECK3-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 02245// CHECK3-NEXT: [[TMP78:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 02246// CHECK3-NEXT: store i32 3, ptr [[TMP78]], align 42247// CHECK3-NEXT: [[TMP79:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 12248// CHECK3-NEXT: store i32 2, ptr [[TMP79]], align 42249// CHECK3-NEXT: [[TMP80:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 22250// CHECK3-NEXT: store ptr [[TMP76]], ptr [[TMP80]], align 42251// CHECK3-NEXT: [[TMP81:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 32252// CHECK3-NEXT: store ptr [[TMP77]], ptr [[TMP81]], align 42253// CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 42254// CHECK3-NEXT: store ptr @.offload_sizes.3, ptr [[TMP82]], align 42255// CHECK3-NEXT: [[TMP83:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 52256// CHECK3-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP83]], align 42257// CHECK3-NEXT: [[TMP84:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 62258// CHECK3-NEXT: store ptr null, ptr [[TMP84]], align 42259// CHECK3-NEXT: [[TMP85:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 72260// CHECK3-NEXT: store ptr null, ptr [[TMP85]], align 42261// CHECK3-NEXT: [[TMP86:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 82262// CHECK3-NEXT: store i64 10, ptr [[TMP86]], align 82263// CHECK3-NEXT: [[TMP87:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 92264// CHECK3-NEXT: store i64 0, ptr [[TMP87]], align 82265// CHECK3-NEXT: [[TMP88:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 102266// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP88]], align 42267// CHECK3-NEXT: [[TMP89:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 112268// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP89]], align 42269// CHECK3-NEXT: [[TMP90:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 122270// CHECK3-NEXT: store i32 0, ptr [[TMP90]], align 42271// CHECK3-NEXT: [[TMP91:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, ptr [[KERNEL_ARGS14]])2272// CHECK3-NEXT: [[TMP92:%.*]] = icmp ne i32 [[TMP91]], 02273// CHECK3-NEXT: br i1 [[TMP92]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]2274// CHECK3: omp_offload.failed15:2275// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR3]]2276// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT16]]2277// CHECK3: omp_offload.cont16:2278// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]2279// CHECK3: omp_if.else:2280// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR3]]2281// CHECK3-NEXT: br label [[OMP_IF_END]]2282// CHECK3: omp_if.end:2283// CHECK3-NEXT: [[TMP93:%.*]] = load i32, ptr [[A]], align 42284// CHECK3-NEXT: store i32 [[TMP93]], ptr [[A_CASTED17]], align 42285// CHECK3-NEXT: [[TMP94:%.*]] = load i32, ptr [[A_CASTED17]], align 42286// CHECK3-NEXT: [[TMP95:%.*]] = load i32, ptr [[N_ADDR]], align 42287// CHECK3-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP95]], 202288// CHECK3-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE27:%.*]]2289// CHECK3: omp_if.then19:2290// CHECK3-NEXT: [[TMP96:%.*]] = mul nuw i32 [[TMP1]], 42291// CHECK3-NEXT: [[TMP97:%.*]] = sext i32 [[TMP96]] to i642292// CHECK3-NEXT: [[TMP98:%.*]] = mul nuw i32 5, [[TMP3]]2293// CHECK3-NEXT: [[TMP99:%.*]] = mul nuw i32 [[TMP98]], 82294// CHECK3-NEXT: [[TMP100:%.*]] = sext i32 [[TMP99]] to i642295// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.5, i32 72, i1 false)2296// CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 02297// CHECK3-NEXT: store i32 [[TMP94]], ptr [[TMP101]], align 42298// CHECK3-NEXT: [[TMP102:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 02299// CHECK3-NEXT: store i32 [[TMP94]], ptr [[TMP102]], align 42300// CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 02301// CHECK3-NEXT: store ptr null, ptr [[TMP103]], align 42302// CHECK3-NEXT: [[TMP104:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 12303// CHECK3-NEXT: store ptr [[B]], ptr [[TMP104]], align 42304// CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 12305// CHECK3-NEXT: store ptr [[B]], ptr [[TMP105]], align 42306// CHECK3-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 12307// CHECK3-NEXT: store ptr null, ptr [[TMP106]], align 42308// CHECK3-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 22309// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP107]], align 42310// CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 22311// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP108]], align 42312// CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 22313// CHECK3-NEXT: store ptr null, ptr [[TMP109]], align 42314// CHECK3-NEXT: [[TMP110:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 32315// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP110]], align 42316// CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 32317// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP111]], align 42318// CHECK3-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 32319// CHECK3-NEXT: store i64 [[TMP97]], ptr [[TMP112]], align 42320// CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 32321// CHECK3-NEXT: store ptr null, ptr [[TMP113]], align 42322// CHECK3-NEXT: [[TMP114:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 42323// CHECK3-NEXT: store ptr [[C]], ptr [[TMP114]], align 42324// CHECK3-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 42325// CHECK3-NEXT: store ptr [[C]], ptr [[TMP115]], align 42326// CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 42327// CHECK3-NEXT: store ptr null, ptr [[TMP116]], align 42328// CHECK3-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 52329// CHECK3-NEXT: store i32 5, ptr [[TMP117]], align 42330// CHECK3-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 52331// CHECK3-NEXT: store i32 5, ptr [[TMP118]], align 42332// CHECK3-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 52333// CHECK3-NEXT: store ptr null, ptr [[TMP119]], align 42334// CHECK3-NEXT: [[TMP120:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 62335// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP120]], align 42336// CHECK3-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 62337// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP121]], align 42338// CHECK3-NEXT: [[TMP122:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 62339// CHECK3-NEXT: store ptr null, ptr [[TMP122]], align 42340// CHECK3-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 72341// CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP123]], align 42342// CHECK3-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 72343// CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP124]], align 42344// CHECK3-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 72345// CHECK3-NEXT: store i64 [[TMP100]], ptr [[TMP125]], align 42346// CHECK3-NEXT: [[TMP126:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 72347// CHECK3-NEXT: store ptr null, ptr [[TMP126]], align 42348// CHECK3-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 82349// CHECK3-NEXT: store ptr [[D]], ptr [[TMP127]], align 42350// CHECK3-NEXT: [[TMP128:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 82351// CHECK3-NEXT: store ptr [[D]], ptr [[TMP128]], align 42352// CHECK3-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 82353// CHECK3-NEXT: store ptr null, ptr [[TMP129]], align 42354// CHECK3-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 02355// CHECK3-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 02356// CHECK3-NEXT: [[TMP132:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 02357// CHECK3-NEXT: [[TMP133:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 02358// CHECK3-NEXT: store i32 3, ptr [[TMP133]], align 42359// CHECK3-NEXT: [[TMP134:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 12360// CHECK3-NEXT: store i32 9, ptr [[TMP134]], align 42361// CHECK3-NEXT: [[TMP135:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 22362// CHECK3-NEXT: store ptr [[TMP130]], ptr [[TMP135]], align 42363// CHECK3-NEXT: [[TMP136:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 32364// CHECK3-NEXT: store ptr [[TMP131]], ptr [[TMP136]], align 42365// CHECK3-NEXT: [[TMP137:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 42366// CHECK3-NEXT: store ptr [[TMP132]], ptr [[TMP137]], align 42367// CHECK3-NEXT: [[TMP138:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 52368// CHECK3-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP138]], align 42369// CHECK3-NEXT: [[TMP139:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 62370// CHECK3-NEXT: store ptr null, ptr [[TMP139]], align 42371// CHECK3-NEXT: [[TMP140:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 72372// CHECK3-NEXT: store ptr null, ptr [[TMP140]], align 42373// CHECK3-NEXT: [[TMP141:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 82374// CHECK3-NEXT: store i64 10, ptr [[TMP141]], align 82375// CHECK3-NEXT: [[TMP142:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 92376// CHECK3-NEXT: store i64 0, ptr [[TMP142]], align 82377// CHECK3-NEXT: [[TMP143:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 102378// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP143]], align 42379// CHECK3-NEXT: [[TMP144:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 112380// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP144]], align 42381// CHECK3-NEXT: [[TMP145:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 122382// CHECK3-NEXT: store i32 0, ptr [[TMP145]], align 42383// CHECK3-NEXT: [[TMP146:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, ptr [[KERNEL_ARGS24]])2384// CHECK3-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 02385// CHECK3-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]]2386// CHECK3: omp_offload.failed25:2387// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP94]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]2388// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT26]]2389// CHECK3: omp_offload.cont26:2390// CHECK3-NEXT: br label [[OMP_IF_END28:%.*]]2391// CHECK3: omp_if.else27:2392// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP94]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]2393// CHECK3-NEXT: br label [[OMP_IF_END28]]2394// CHECK3: omp_if.end28:2395// CHECK3-NEXT: [[TMP148:%.*]] = load i32, ptr [[A]], align 42396// CHECK3-NEXT: [[TMP149:%.*]] = load ptr, ptr [[SAVED_STACK]], align 42397// CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP149]])2398// CHECK3-NEXT: ret i32 [[TMP148]]2399//2400//2401// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l972402// CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {2403// CHECK3-NEXT: entry:2404// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 42405// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 42406// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 42407// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 42408// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])2409// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 42410// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 42411// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 42412// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 42413// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 42414// CHECK3-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])2415// CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 22416// CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 22417// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 42418// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i32 [[TMP4]])2419// CHECK3-NEXT: ret void2420//2421//2422// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined2423// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {2424// CHECK3-NEXT: entry:2425// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42426// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42427// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 42428// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42429// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 42430// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42431// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42432// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42433// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42434// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 42435// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42436// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42437// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 42438// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42439// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 42440// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42441// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42442// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42443// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42444// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2445// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42446// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 92447// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2448// CHECK3: cond.true:2449// CHECK3-NEXT: br label [[COND_END:%.*]]2450// CHECK3: cond.false:2451// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42452// CHECK3-NEXT: br label [[COND_END]]2453// CHECK3: cond.end:2454// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2455// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 42456// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42457// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42458// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2459// CHECK3: omp.inner.for.cond:2460// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]2461// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]]2462// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2463// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2464// CHECK3: omp.inner.for.body:2465// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]2466// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12467// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2468// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]2469// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2470// CHECK3: omp.body.continue:2471// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2472// CHECK3: omp.inner.for.inc:2473// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]2474// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 12475// CHECK3-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]2476// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]2477// CHECK3: omp.inner.for.end:2478// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2479// CHECK3: omp.loop.exit:2480// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2481// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42482// CHECK3-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 02483// CHECK3-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]2484// CHECK3: .omp.final.then:2485// CHECK3-NEXT: store i32 10, ptr [[I]], align 42486// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]2487// CHECK3: .omp.final.done:2488// CHECK3-NEXT: ret void2489//2490//2491// CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map.2492// CHECK3-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {2493// CHECK3-NEXT: entry:2494// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 42495// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 42496// CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 42497// CHECK3-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 42498// CHECK3-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 42499// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 42500// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 42501// CHECK3-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 42502// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 42503// CHECK3-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 42504// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 42505// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 02506// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR4]], align 42507// CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 42508// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 12509// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 42510// CHECK3-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 42511// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 22512// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 42513// CHECK3-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 42514// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 32515// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 42516// CHECK3-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 42517// CHECK3-NEXT: ret void2518//2519//2520// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry.2521// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {2522// CHECK3-NEXT: entry:2523// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 42524// CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 42525// CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 42526// CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 42527// CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 42528// CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 42529// CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 42530// CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 42531// CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 42532// CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 42533// CHECK3-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 82534// CHECK3-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 42535// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 42536// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 42537// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 42538// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 42539// CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 42540// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 42541// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 42542// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 42543// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 02544// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 22545// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 02546// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 42547// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 12548// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])2549// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])2550// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])2551// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])2552// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META27:![0-9]+]]2553// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias [[META27]]2554// CHECK3-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META27]]2555// CHECK3-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META27]]2556// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias [[META27]]2557// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META27]]2558// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META27]]2559// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META27]]2560// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META27]]2561// CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]2562// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias [[META27]]2563// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias [[META27]]2564// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias [[META27]]2565// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias [[META27]]2566// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 12567// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 22568// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 42569// CHECK3-NEXT: [[TMP19:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP18]], 02570// CHECK3-NEXT: store i32 3, ptr [[KERNEL_ARGS_I]], align 4, !noalias [[META27]]2571// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12572// CHECK3-NEXT: store i32 3, ptr [[TMP20]], align 4, !noalias [[META27]]2573// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 22574// CHECK3-NEXT: store ptr [[TMP13]], ptr [[TMP21]], align 4, !noalias [[META27]]2575// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 32576// CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP22]], align 4, !noalias [[META27]]2577// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 42578// CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP23]], align 4, !noalias [[META27]]2579// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 52580// CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP24]], align 4, !noalias [[META27]]2581// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 62582// CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 4, !noalias [[META27]]2583// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 72584// CHECK3-NEXT: store ptr null, ptr [[TMP26]], align 4, !noalias [[META27]]2585// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 82586// CHECK3-NEXT: store i64 10, ptr [[TMP27]], align 8, !noalias [[META27]]2587// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 92588// CHECK3-NEXT: store i64 1, ptr [[TMP28]], align 8, !noalias [[META27]]2589// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 102590// CHECK3-NEXT: store [3 x i32] [[TMP19]], ptr [[TMP29]], align 4, !noalias [[META27]]2591// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 112592// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP30]], align 4, !noalias [[META27]]2593// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 122594// CHECK3-NEXT: store i32 0, ptr [[TMP31]], align 4, !noalias [[META27]]2595// CHECK3-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 [[TMP18]], i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, ptr [[KERNEL_ARGS_I]])2596// CHECK3-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 02597// CHECK3-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]2598// CHECK3: omp_offload.failed.i:2599// CHECK3-NEXT: [[TMP34:%.*]] = load i16, ptr [[TMP12]], align 22600// CHECK3-NEXT: store i16 [[TMP34]], ptr [[AA_CASTED_I]], align 2, !noalias [[META27]]2601// CHECK3-NEXT: [[TMP35:%.*]] = load i32, ptr [[AA_CASTED_I]], align 4, !noalias [[META27]]2602// CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP16]], align 42603// CHECK3-NEXT: store i32 [[TMP36]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias [[META27]]2604// CHECK3-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias [[META27]]2605// CHECK3-NEXT: [[TMP38:%.*]] = load i32, ptr [[TMP17]], align 42606// CHECK3-NEXT: store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias [[META27]]2607// CHECK3-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias [[META27]]2608// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i32 [[TMP35]], i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR3]]2609// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]2610// CHECK3: .omp_outlined..exit:2611// CHECK3-NEXT: ret i32 02612//2613//2614// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1042615// CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] {2616// CHECK3-NEXT: entry:2617// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42618// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 42619// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42620// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42621// CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 42622// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 42623// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104.omp_outlined, i32 [[TMP1]])2624// CHECK3-NEXT: ret void2625//2626//2627// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104.omp_outlined2628// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {2629// CHECK3-NEXT: entry:2630// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42631// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42632// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42633// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42634// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 42635// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42636// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42637// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42638// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42639// CHECK3-NEXT: [[A1:%.*]] = alloca i32, align 42640// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42641// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42642// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42643// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42644// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 42645// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42646// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42647// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42648// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42649// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2650// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42651// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 92652// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2653// CHECK3: cond.true:2654// CHECK3-NEXT: br label [[COND_END:%.*]]2655// CHECK3: cond.false:2656// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42657// CHECK3-NEXT: br label [[COND_END]]2658// CHECK3: cond.end:2659// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2660// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 42661// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42662// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42663// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2664// CHECK3: omp.inner.for.cond:2665// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42666// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42667// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2668// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2669// CHECK3: omp.inner.for.body:2670// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42671// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12672// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2673// CHECK3-NEXT: store i32 [[ADD]], ptr [[A1]], align 42674// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 42675// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 12676// CHECK3-NEXT: store i32 [[ADD3]], ptr [[A1]], align 42677// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2678// CHECK3: omp.body.continue:2679// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2680// CHECK3: omp.inner.for.inc:2681// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42682// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 12683// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 42684// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]2685// CHECK3: omp.inner.for.end:2686// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2687// CHECK3: omp.loop.exit:2688// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2689// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42690// CHECK3-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 02691// CHECK3-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]2692// CHECK3: .omp.final.then:2693// CHECK3-NEXT: store i32 10, ptr [[A_ADDR]], align 42694// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]2695// CHECK3: .omp.final.done:2696// CHECK3-NEXT: ret void2697//2698//2699// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1112700// CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] {2701// CHECK3-NEXT: entry:2702// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 42703// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 42704// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 42705// CHECK3-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 22706// CHECK3-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 22707// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 42708// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP1]])2709// CHECK3-NEXT: ret void2710//2711//2712// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined2713// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {2714// CHECK3-NEXT: entry:2715// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42716// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42717// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 42718// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42719// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 42720// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42721// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42722// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42723// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42724// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 42725// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42726// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42727// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 42728// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42729// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 42730// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42731// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42732// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42733// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42734// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2735// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42736// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 92737// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2738// CHECK3: cond.true:2739// CHECK3-NEXT: br label [[COND_END:%.*]]2740// CHECK3: cond.false:2741// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42742// CHECK3-NEXT: br label [[COND_END]]2743// CHECK3: cond.end:2744// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2745// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 42746// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42747// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42748// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2749// CHECK3: omp.inner.for.cond:2750// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30:![0-9]+]]2751// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP30]]2752// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2753// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2754// CHECK3: omp.inner.for.body:2755// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]]2756// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12757// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2758// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP30]]2759// CHECK3-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]]2760// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i322761// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 12762// CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i162763// CHECK3-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]]2764// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2765// CHECK3: omp.body.continue:2766// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2767// CHECK3: omp.inner.for.inc:2768// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]]2769// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 12770// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]]2771// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]2772// CHECK3: omp.inner.for.end:2773// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2774// CHECK3: omp.loop.exit:2775// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2776// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42777// CHECK3-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 02778// CHECK3-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]2779// CHECK3: .omp.final.then:2780// CHECK3-NEXT: store i32 10, ptr [[I]], align 42781// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]2782// CHECK3: .omp.final.done:2783// CHECK3-NEXT: ret void2784//2785//2786// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1182787// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {2788// CHECK3-NEXT: entry:2789// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42790// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 42791// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 42792// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 42793// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42794// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 42795// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42796// CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 42797// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 42798// CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 22799// CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 22800// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 42801// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])2802// CHECK3-NEXT: ret void2803//2804//2805// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined2806// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {2807// CHECK3-NEXT: entry:2808// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42809// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42810// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42811// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 42812// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42813// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 42814// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42815// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42816// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42817// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42818// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 42819// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42820// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42821// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42822// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 42823// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42824// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 42825// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42826// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42827// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42828// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42829// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2830// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42831// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 92832// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2833// CHECK3: cond.true:2834// CHECK3-NEXT: br label [[COND_END:%.*]]2835// CHECK3: cond.false:2836// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42837// CHECK3-NEXT: br label [[COND_END]]2838// CHECK3: cond.end:2839// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2840// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 42841// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42842// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42843// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2844// CHECK3: omp.inner.for.cond:2845// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]]2846// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]]2847// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2848// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2849// CHECK3: omp.inner.for.body:2850// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]2851// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12852// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2853// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]]2854// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]]2855// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 12856// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]]2857// CHECK3-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]]2858// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i322859// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 12860// CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i162861// CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]]2862// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2863// CHECK3: omp.body.continue:2864// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2865// CHECK3: omp.inner.for.inc:2866// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]2867// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 12868// CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]2869// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]2870// CHECK3: omp.inner.for.end:2871// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2872// CHECK3: omp.loop.exit:2873// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2874// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42875// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 02876// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]2877// CHECK3: .omp.final.then:2878// CHECK3-NEXT: store i32 10, ptr [[I]], align 42879// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]2880// CHECK3: .omp.final.done:2881// CHECK3-NEXT: ret void2882//2883//2884// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1422885// CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {2886// CHECK3-NEXT: entry:2887// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42888// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 42889// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 42890// CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 42891// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 42892// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 42893// CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 42894// CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 42895// CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 42896// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 42897// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42898// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 42899// CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 42900// CHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 42901// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 42902// CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 42903// CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 42904// CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 42905// CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 42906// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 42907// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 42908// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 42909// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 42910// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 42911// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 42912// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 42913// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 42914// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 42915// CHECK3-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 42916// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 42917// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])2918// CHECK3-NEXT: ret void2919//2920//2921// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined2922// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {2923// CHECK3-NEXT: entry:2924// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42925// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42926// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42927// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 42928// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 42929// CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 42930// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 42931// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 42932// CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 42933// CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 42934// CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 42935// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42936// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 42937// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42938// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42939// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42940// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42941// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 42942// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42943// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42944// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42945// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 42946// CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 42947// CHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 42948// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 42949// CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 42950// CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 42951// CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 42952// CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 42953// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 42954// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 42955// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 42956// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 42957// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 42958// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 42959// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 42960// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 42961// CHECK3-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 02962// CHECK3-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i32 16) ]2963// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42964// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 42965// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42966// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42967// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42968// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 42969// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2970// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42971// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 92972// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2973// CHECK3: cond.true:2974// CHECK3-NEXT: br label [[COND_END:%.*]]2975// CHECK3: cond.false:2976// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42977// CHECK3-NEXT: br label [[COND_END]]2978// CHECK3: cond.end:2979// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]2980// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 42981// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42982// CHECK3-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 42983// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2984// CHECK3: omp.inner.for.cond:2985// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]]2986// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP36]]2987// CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]2988// CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2989// CHECK3: omp.inner.for.body:2990// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]2991// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 12992// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2993// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP36]]2994// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]]2995// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 12996// CHECK3-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]]2997// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 22998// CHECK3-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]]2999// CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double3000// CHECK3-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+003001// CHECK3-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float3002// CHECK3-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]]3003// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 33004// CHECK3-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP36]]3005// CHECK3-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double3006// CHECK3-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+003007// CHECK3-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float3008// CHECK3-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP36]]3009// CHECK3-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 13010// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i32 0, i32 23011// CHECK3-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP36]]3012// CHECK3-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+003013// CHECK3-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP36]]3014// CHECK3-NEXT: [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]]3015// CHECK3-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP20]]3016// CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i32 33017// CHECK3-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP36]]3018// CHECK3-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+003019// CHECK3-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP36]]3020// CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 03021// CHECK3-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP36]]3022// CHECK3-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 13023// CHECK3-NEXT: store i64 [[ADD19]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP36]]3024// CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 13025// CHECK3-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP36]]3026// CHECK3-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i323027// CHECK3-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 13028// CHECK3-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i83029// CHECK3-NEXT: store i8 [[CONV22]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP36]]3030// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3031// CHECK3: omp.body.continue:3032// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3033// CHECK3: omp.inner.for.inc:3034// CHECK3-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]3035// CHECK3-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 13036// CHECK3-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]3037// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]3038// CHECK3: omp.inner.for.end:3039// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]3040// CHECK3: omp.loop.exit:3041// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP9]])3042// CHECK3-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 43043// CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 03044// CHECK3-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]3045// CHECK3: .omp.final.then:3046// CHECK3-NEXT: store i32 10, ptr [[I]], align 43047// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]3048// CHECK3: .omp.final.done:3049// CHECK3-NEXT: ret void3050//3051//3052// CHECK3-LABEL: define {{[^@]+}}@_Z3bari3053// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {3054// CHECK3-NEXT: entry:3055// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43056// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 43057// CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 43058// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 43059// CHECK3-NEXT: store i32 0, ptr [[A]], align 43060// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 43061// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])3062// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 43063// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]3064// CHECK3-NEXT: store i32 [[ADD]], ptr [[A]], align 43065// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 43066// CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])3067// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 43068// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]3069// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A]], align 43070// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 43071// CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])3072// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 43073// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]3074// CHECK3-NEXT: store i32 [[ADD4]], ptr [[A]], align 43075// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 43076// CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])3077// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 43078// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]3079// CHECK3-NEXT: store i32 [[ADD6]], ptr [[A]], align 43080// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 43081// CHECK3-NEXT: ret i32 [[TMP8]]3082//3083//3084// CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei3085// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {3086// CHECK3-NEXT: entry:3087// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 43088// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43089// CHECK3-NEXT: [[B:%.*]] = alloca i32, align 43090// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 43091// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 43092// CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 43093// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 43094// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 43095// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 43096// CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 43097// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 43098// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 83099// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 43100// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 43101// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43102// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 43103// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 13104// CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 43105// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 43106// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()3107// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 43108// CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]3109// CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 23110// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 43111// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 43112// CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 43113// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 43114// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 43115// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 603116// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]3117// CHECK3: omp_if.then:3118// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 03119// CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]3120// CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 23121// CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i643122// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.7, i32 40, i1 false)3123// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03124// CHECK3-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 43125// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03126// CHECK3-NEXT: store ptr [[A]], ptr [[TMP11]], align 43127// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 03128// CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 43129// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 13130// CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 43131// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 13132// CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 43133// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 13134// CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 43135// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 23136// CHECK3-NEXT: store i32 2, ptr [[TMP16]], align 43137// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 23138// CHECK3-NEXT: store i32 2, ptr [[TMP17]], align 43139// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 23140// CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 43141// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 33142// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP19]], align 43143// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 33144// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP20]], align 43145// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 33146// CHECK3-NEXT: store ptr null, ptr [[TMP21]], align 43147// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 43148// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 43149// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 43150// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 43151// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 43152// CHECK3-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 43153// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 43154// CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 43155// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03156// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03157// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 03158// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 03159// CHECK3-NEXT: store i32 3, ptr [[TMP29]], align 43160// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 13161// CHECK3-NEXT: store i32 5, ptr [[TMP30]], align 43162// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 23163// CHECK3-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 43164// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 33165// CHECK3-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 43166// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 43167// CHECK3-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 43168// CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 53169// CHECK3-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP34]], align 43170// CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 63171// CHECK3-NEXT: store ptr null, ptr [[TMP35]], align 43172// CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 73173// CHECK3-NEXT: store ptr null, ptr [[TMP36]], align 43174// CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 83175// CHECK3-NEXT: store i64 10, ptr [[TMP37]], align 83176// CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 93177// CHECK3-NEXT: store i64 0, ptr [[TMP38]], align 83178// CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 103179// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP39]], align 43180// CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 113181// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP40]], align 43182// CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 123183// CHECK3-NEXT: store i32 0, ptr [[TMP41]], align 43184// CHECK3-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.region_id, ptr [[KERNEL_ARGS]])3185// CHECK3-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 03186// CHECK3-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]3187// CHECK3: omp_offload.failed:3188// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]3189// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]3190// CHECK3: omp_offload.cont:3191// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]3192// CHECK3: omp_if.else:3193// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]3194// CHECK3-NEXT: br label [[OMP_IF_END]]3195// CHECK3: omp_if.end:3196// CHECK3-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]]3197// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]]3198// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 13199// CHECK3-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 23200// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i323201// CHECK3-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 43202// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]3203// CHECK3-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 43204// CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])3205// CHECK3-NEXT: ret i32 [[ADD3]]3206//3207//3208// CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici3209// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {3210// CHECK3-NEXT: entry:3211// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43212// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 43213// CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 23214// CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 13215// CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 43216// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 43217// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 43218// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 43219// CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 43220// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 43221// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 43222// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 43223// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 43224// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 43225// CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 43226// CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 43227// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 83228// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 43229// CHECK3-NEXT: store i32 0, ptr [[A]], align 43230// CHECK3-NEXT: store i16 0, ptr [[AA]], align 23231// CHECK3-NEXT: store i8 0, ptr [[AAA]], align 13232// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 43233// CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 43234// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 43235// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 43236// CHECK3-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 43237// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 43238// CHECK3-NEXT: [[TMP4:%.*]] = load i16, ptr [[AA]], align 23239// CHECK3-NEXT: store i16 [[TMP4]], ptr [[AA_CASTED]], align 23240// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[AA_CASTED]], align 43241// CHECK3-NEXT: [[TMP6:%.*]] = load i8, ptr [[AAA]], align 13242// CHECK3-NEXT: store i8 [[TMP6]], ptr [[AAA_CASTED]], align 13243// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[AAA_CASTED]], align 43244// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[N_ADDR]], align 43245// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 503246// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]3247// CHECK3: omp_if.then:3248// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03249// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP9]], align 43250// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03251// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP10]], align 43252// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 03253// CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 43254// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 13255// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP12]], align 43256// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 13257// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP13]], align 43258// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 13259// CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 43260// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 23261// CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP15]], align 43262// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 23263// CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP16]], align 43264// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 23265// CHECK3-NEXT: store ptr null, ptr [[TMP17]], align 43266// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 33267// CHECK3-NEXT: store i32 [[TMP7]], ptr [[TMP18]], align 43268// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 33269// CHECK3-NEXT: store i32 [[TMP7]], ptr [[TMP19]], align 43270// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 33271// CHECK3-NEXT: store ptr null, ptr [[TMP20]], align 43272// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 43273// CHECK3-NEXT: store ptr [[B]], ptr [[TMP21]], align 43274// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 43275// CHECK3-NEXT: store ptr [[B]], ptr [[TMP22]], align 43276// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 43277// CHECK3-NEXT: store ptr null, ptr [[TMP23]], align 43278// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03279// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03280// CHECK3-NEXT: [[TMP26:%.*]] = load i32, ptr [[A]], align 43281// CHECK3-NEXT: store i32 [[TMP26]], ptr [[DOTCAPTURE_EXPR_]], align 43282// CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[N_ADDR]], align 43283// CHECK3-NEXT: store i32 [[TMP27]], ptr [[DOTCAPTURE_EXPR_1]], align 43284// CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 43285// CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 43286// CHECK3-NEXT: [[SUB:%.*]] = sub i32 [[TMP28]], [[TMP29]]3287// CHECK3-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 13288// CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 13289// CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 13290// CHECK3-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 13291// CHECK3-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 43292// CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 43293// CHECK3-NEXT: [[ADD5:%.*]] = add i32 [[TMP30]], 13294// CHECK3-NEXT: [[TMP31:%.*]] = zext i32 [[ADD5]] to i643295// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 03296// CHECK3-NEXT: store i32 3, ptr [[TMP32]], align 43297// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 13298// CHECK3-NEXT: store i32 5, ptr [[TMP33]], align 43299// CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 23300// CHECK3-NEXT: store ptr [[TMP24]], ptr [[TMP34]], align 43301// CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 33302// CHECK3-NEXT: store ptr [[TMP25]], ptr [[TMP35]], align 43303// CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 43304// CHECK3-NEXT: store ptr @.offload_sizes.9, ptr [[TMP36]], align 43305// CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 53306// CHECK3-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP37]], align 43307// CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 63308// CHECK3-NEXT: store ptr null, ptr [[TMP38]], align 43309// CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 73310// CHECK3-NEXT: store ptr null, ptr [[TMP39]], align 43311// CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 83312// CHECK3-NEXT: store i64 [[TMP31]], ptr [[TMP40]], align 83313// CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 93314// CHECK3-NEXT: store i64 0, ptr [[TMP41]], align 83315// CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 103316// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP42]], align 43317// CHECK3-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 113318// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP43]], align 43319// CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 123320// CHECK3-NEXT: store i32 0, ptr [[TMP44]], align 43321// CHECK3-NEXT: [[TMP45:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.region_id, ptr [[KERNEL_ARGS]])3322// CHECK3-NEXT: [[TMP46:%.*]] = icmp ne i32 [[TMP45]], 03323// CHECK3-NEXT: br i1 [[TMP46]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]3324// CHECK3: omp_offload.failed:3325// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], ptr [[B]]) #[[ATTR3]]3326// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]3327// CHECK3: omp_offload.cont:3328// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]3329// CHECK3: omp_if.else:3330// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], ptr [[B]]) #[[ATTR3]]3331// CHECK3-NEXT: br label [[OMP_IF_END]]3332// CHECK3: omp_if.end:3333// CHECK3-NEXT: [[TMP47:%.*]] = load i32, ptr [[A]], align 43334// CHECK3-NEXT: ret i32 [[TMP47]]3335//3336//3337// CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i3338// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {3339// CHECK3-NEXT: entry:3340// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43341// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 43342// CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 23343// CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 43344// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 43345// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 43346// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 43347// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 43348// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 43349// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 43350// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 83351// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 43352// CHECK3-NEXT: store i32 0, ptr [[A]], align 43353// CHECK3-NEXT: store i16 0, ptr [[AA]], align 23354// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 43355// CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 43356// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 43357// CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 23358// CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 23359// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 43360// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 43361// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 403362// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]3363// CHECK3: omp_if.then:3364// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03365// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 43366// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03367// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP6]], align 43368// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 03369// CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 43370// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 13371// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP8]], align 43372// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 13373// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP9]], align 43374// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 13375// CHECK3-NEXT: store ptr null, ptr [[TMP10]], align 43376// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 23377// CHECK3-NEXT: store ptr [[B]], ptr [[TMP11]], align 43378// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 23379// CHECK3-NEXT: store ptr [[B]], ptr [[TMP12]], align 43380// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 23381// CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 43382// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03383// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03384// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 03385// CHECK3-NEXT: store i32 3, ptr [[TMP16]], align 43386// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 13387// CHECK3-NEXT: store i32 3, ptr [[TMP17]], align 43388// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 23389// CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 43390// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 33391// CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 43392// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 43393// CHECK3-NEXT: store ptr @.offload_sizes.11, ptr [[TMP20]], align 43394// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 53395// CHECK3-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP21]], align 43396// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 63397// CHECK3-NEXT: store ptr null, ptr [[TMP22]], align 43398// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 73399// CHECK3-NEXT: store ptr null, ptr [[TMP23]], align 43400// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 83401// CHECK3-NEXT: store i64 10, ptr [[TMP24]], align 83402// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 93403// CHECK3-NEXT: store i64 0, ptr [[TMP25]], align 83404// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 103405// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 43406// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 113407// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 43408// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 123409// CHECK3-NEXT: store i32 0, ptr [[TMP28]], align 43410// CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.region_id, ptr [[KERNEL_ARGS]])3411// CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 03412// CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]3413// CHECK3: omp_offload.failed:3414// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]3415// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]3416// CHECK3: omp_offload.cont:3417// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]3418// CHECK3: omp_if.else:3419// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]3420// CHECK3-NEXT: br label [[OMP_IF_END]]3421// CHECK3: omp_if.end:3422// CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 43423// CHECK3-NEXT: ret i32 [[TMP31]]3424//3425//3426// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2153427// CHECK3-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {3428// CHECK3-NEXT: entry:3429// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 43430// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 43431// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 43432// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 43433// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 43434// CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 43435// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 43436// CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 43437// CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 43438// CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 43439// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 43440// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43441// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 43442// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 43443// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 43444// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 43445// CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 43446// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 43447// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])3448// CHECK3-NEXT: ret void3449//3450//3451// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined3452// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {3453// CHECK3-NEXT: entry:3454// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43455// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43456// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 43457// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 43458// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 43459// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 43460// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 43461// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43462// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 43463// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 43464// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 43465// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 43466// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43467// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 43468// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43469// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43470// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 43471// CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 43472// CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 43473// CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 43474// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 43475// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 43476// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 43477// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 43478// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 43479// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 43480// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 43481// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 43482// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 43483// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 43484// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 43485// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)3486// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43487// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 93488// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3489// CHECK3: cond.true:3490// CHECK3-NEXT: br label [[COND_END:%.*]]3491// CHECK3: cond.false:3492// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43493// CHECK3-NEXT: br label [[COND_END]]3494// CHECK3: cond.end:3495// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]3496// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 43497// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43498// CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 43499// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3500// CHECK3: omp.inner.for.cond:3501// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39:![0-9]+]]3502// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]]3503// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]3504// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3505// CHECK3: omp.inner.for.body:3506// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]3507// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 13508// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]3509// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]]3510// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]]3511// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double3512// CHECK3-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+003513// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 03514// CHECK3-NEXT: store double [[ADD4]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP39]]3515// CHECK3-NEXT: [[A5:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 03516// CHECK3-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP39]]3517// CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+003518// CHECK3-NEXT: store double [[INC]], ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP39]]3519// CHECK3-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i163520// CHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]3521// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]]3522// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 13523// CHECK3-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP39]]3524// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3525// CHECK3: omp.body.continue:3526// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3527// CHECK3: omp.inner.for.inc:3528// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]3529// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 13530// CHECK3-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]3531// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]3532// CHECK3: omp.inner.for.end:3533// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]3534// CHECK3: omp.loop.exit:3535// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])3536// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 43537// CHECK3-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 03538// CHECK3-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]3539// CHECK3: .omp.final.then:3540// CHECK3-NEXT: store i32 10, ptr [[I]], align 43541// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]3542// CHECK3: .omp.final.done:3543// CHECK3-NEXT: ret void3544//3545//3546// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1973547// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {3548// CHECK3-NEXT: entry:3549// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 43550// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43551// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 43552// CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 43553// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 43554// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 43555// CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 43556// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 43557// CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 43558// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 43559// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 43560// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 43561// CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 43562// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 43563// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43564// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 43565// CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 43566// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 43567// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 43568// CHECK3-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 43569// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 43570// CHECK3-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 23571// CHECK3-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 23572// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[AA_CASTED]], align 43573// CHECK3-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 13574// CHECK3-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 13575// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[AAA_CASTED]], align 43576// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], ptr [[TMP0]])3577// CHECK3-NEXT: ret void3578//3579//3580// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined3581// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {3582// CHECK3-NEXT: entry:3583// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43584// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43585// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 43586// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43587// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 43588// CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 43589// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 43590// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43591// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 43592// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 43593// CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 43594// CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 43595// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 43596// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 43597// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 43598// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 43599// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43600// CHECK3-NEXT: [[I5:%.*]] = alloca i32, align 43601// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43602// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43603// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 43604// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 43605// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 43606// CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 43607// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 43608// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43609// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 43610// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 43611// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 43612// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 43613// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 43614// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 43615// CHECK3-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]3616// CHECK3-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 13617// CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 13618// CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 13619// CHECK3-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 13620// CHECK3-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 43621// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 43622// CHECK3-NEXT: store i32 [[TMP5]], ptr [[I]], align 43623// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 43624// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 43625// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]3626// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]3627// CHECK3: omp.precond.then:3628// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 43629// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 43630// CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 43631// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 43632// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 43633// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 43634// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 43635// CHECK3-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)3636// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43637// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 43638// CHECK3-NEXT: [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]3639// CHECK3-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3640// CHECK3: cond.true:3641// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 43642// CHECK3-NEXT: br label [[COND_END:%.*]]3643// CHECK3: cond.false:3644// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43645// CHECK3-NEXT: br label [[COND_END]]3646// CHECK3: cond.end:3647// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]3648// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 43649// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43650// CHECK3-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 43651// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3652// CHECK3: omp.inner.for.cond:3653// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42:![0-9]+]]3654// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP42]]3655// CHECK3-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 13656// CHECK3-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]3657// CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3658// CHECK3: omp.inner.for.body:3659// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP42]]3660// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]]3661// CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 13662// CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]3663// CHECK3-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP42]]3664// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP42]]3665// CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 13666// CHECK3-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP42]]3667// CHECK3-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP42]]3668// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i323669// CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 13670// CHECK3-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i163671// CHECK3-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP42]]3672// CHECK3-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP42]]3673// CHECK3-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i323674// CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 13675// CHECK3-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i83676// CHECK3-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP42]]3677// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 23678// CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP42]]3679// CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 13680// CHECK3-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP42]]3681// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3682// CHECK3: omp.body.continue:3683// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3684// CHECK3: omp.inner.for.inc:3685// CHECK3-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]]3686// CHECK3-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 13687// CHECK3-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]]3688// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]]3689// CHECK3: omp.inner.for.end:3690// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]3691// CHECK3: omp.loop.exit:3692// CHECK3-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 43693// CHECK3-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 43694// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])3695// CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 43696// CHECK3-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 03697// CHECK3-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]3698// CHECK3: .omp.final.then:3699// CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 43700// CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 43701// CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 43702// CHECK3-NEXT: [[SUB18:%.*]] = sub i32 [[TMP30]], [[TMP31]]3703// CHECK3-NEXT: [[SUB19:%.*]] = sub i32 [[SUB18]], 13704// CHECK3-NEXT: [[ADD20:%.*]] = add i32 [[SUB19]], 13705// CHECK3-NEXT: [[DIV21:%.*]] = udiv i32 [[ADD20]], 13706// CHECK3-NEXT: [[MUL22:%.*]] = mul i32 [[DIV21]], 13707// CHECK3-NEXT: [[ADD23:%.*]] = add i32 [[TMP29]], [[MUL22]]3708// CHECK3-NEXT: store i32 [[ADD23]], ptr [[I5]], align 43709// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]3710// CHECK3: .omp.final.done:3711// CHECK3-NEXT: br label [[OMP_PRECOND_END]]3712// CHECK3: omp.precond.end:3713// CHECK3-NEXT: ret void3714//3715//3716// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1803717// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {3718// CHECK3-NEXT: entry:3719// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 43720// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 43721// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 43722// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 43723// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 43724// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 43725// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 43726// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 43727// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43728// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 43729// CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 43730// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 43731// CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 23732// CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 23733// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 43734// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])3735// CHECK3-NEXT: ret void3736//3737//3738// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined3739// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {3740// CHECK3-NEXT: entry:3741// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 43742// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 43743// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 43744// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 43745// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 43746// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 43747// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 43748// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 43749// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 43750// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 43751// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 43752// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 43753// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 43754// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 43755// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 43756// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 43757// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 43758// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 43759// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 43760// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 43761// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 43762// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 43763// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 43764// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 43765// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)3766// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43767// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 93768// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]3769// CHECK3: cond.true:3770// CHECK3-NEXT: br label [[COND_END:%.*]]3771// CHECK3: cond.false:3772// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 43773// CHECK3-NEXT: br label [[COND_END]]3774// CHECK3: cond.end:3775// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]3776// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 43777// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 43778// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 43779// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]3780// CHECK3: omp.inner.for.cond:3781// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45:![0-9]+]]3782// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]]3783// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]3784// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]3785// CHECK3: omp.inner.for.body:3786// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]3787// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 13788// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]3789// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]]3790// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]3791// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 13792// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]3793// CHECK3-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP45]]3794// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i323795// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 13796// CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i163797// CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP45]]3798// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 23799// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]3800// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 13801// CHECK3-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]3802// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]3803// CHECK3: omp.body.continue:3804// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]3805// CHECK3: omp.inner.for.inc:3806// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]3807// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 13808// CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]3809// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]3810// CHECK3: omp.inner.for.end:3811// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]3812// CHECK3: omp.loop.exit:3813// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])3814// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 43815// CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 03816// CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]3817// CHECK3: .omp.final.then:3818// CHECK3-NEXT: store i32 10, ptr [[I]], align 43819// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]3820// CHECK3: .omp.final.done:3821// CHECK3-NEXT: ret void3822//3823//3824// CHECK5-LABEL: define {{[^@]+}}@_Z3fooi3825// CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {3826// CHECK5-NEXT: entry:3827// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 43828// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 43829// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 23830// CHECK5-NEXT: [[B:%.*]] = alloca [10 x float], align 43831// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 83832// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 83833// CHECK5-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 83834// CHECK5-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 83835// CHECK5-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 83836// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 43837// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 43838// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 83839// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 83840// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i64, align 83841// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 83842// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 83843// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 83844// CHECK5-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 43845// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 83846// CHECK5-NEXT: [[AA_CASTED4:%.*]] = alloca i64, align 83847// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x ptr], align 83848// CHECK5-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x ptr], align 83849// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x ptr], align 83850// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 43851// CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 83852// CHECK5-NEXT: [[A_CASTED8:%.*]] = alloca i64, align 83853// CHECK5-NEXT: [[AA_CASTED9:%.*]] = alloca i64, align 83854// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x ptr], align 83855// CHECK5-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x ptr], align 83856// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x ptr], align 83857// CHECK5-NEXT: [[_TMP13:%.*]] = alloca i32, align 43858// CHECK5-NEXT: [[KERNEL_ARGS14:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 83859// CHECK5-NEXT: [[A_CASTED17:%.*]] = alloca i64, align 83860// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x ptr], align 83861// CHECK5-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x ptr], align 83862// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x ptr], align 83863// CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 83864// CHECK5-NEXT: [[_TMP23:%.*]] = alloca i32, align 43865// CHECK5-NEXT: [[KERNEL_ARGS24:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 83866// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])3867// CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 43868// CHECK5-NEXT: store i32 0, ptr [[A]], align 43869// CHECK5-NEXT: store i16 0, ptr [[AA]], align 23870// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 43871// CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i643872// CHECK5-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()3873// CHECK5-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 83874// CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 43875// CHECK5-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 83876// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 43877// CHECK5-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i643878// CHECK5-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]3879// CHECK5-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 83880// CHECK5-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 83881// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 43882// CHECK5-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 43883// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 43884// CHECK5-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_2]], align 43885// CHECK5-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA]], align 23886// CHECK5-NEXT: store i16 [[TMP9]], ptr [[AA_CASTED]], align 23887// CHECK5-NEXT: [[TMP10:%.*]] = load i64, ptr [[AA_CASTED]], align 83888// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 43889// CHECK5-NEXT: store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 43890// CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 83891// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 43892// CHECK5-NEXT: store i32 [[TMP13]], ptr [[DOTCAPTURE_EXPR__CASTED3]], align 43893// CHECK5-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED3]], align 83894// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03895// CHECK5-NEXT: store i64 [[TMP10]], ptr [[TMP15]], align 83896// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03897// CHECK5-NEXT: store i64 [[TMP10]], ptr [[TMP16]], align 83898// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 03899// CHECK5-NEXT: store ptr null, ptr [[TMP17]], align 83900// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 13901// CHECK5-NEXT: store i64 [[TMP12]], ptr [[TMP18]], align 83902// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 13903// CHECK5-NEXT: store i64 [[TMP12]], ptr [[TMP19]], align 83904// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 13905// CHECK5-NEXT: store ptr null, ptr [[TMP20]], align 83906// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 23907// CHECK5-NEXT: store i64 [[TMP14]], ptr [[TMP21]], align 83908// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 23909// CHECK5-NEXT: store i64 [[TMP14]], ptr [[TMP22]], align 83910// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 23911// CHECK5-NEXT: store ptr null, ptr [[TMP23]], align 83912// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 03913// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 03914// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 03915// CHECK5-NEXT: [[TMP27:%.*]] = load i16, ptr [[AA]], align 23916// CHECK5-NEXT: store i16 [[TMP27]], ptr [[TMP26]], align 43917// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 13918// CHECK5-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 43919// CHECK5-NEXT: store i32 [[TMP29]], ptr [[TMP28]], align 43920// CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 23921// CHECK5-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 43922// CHECK5-NEXT: store i32 [[TMP31]], ptr [[TMP30]], align 43923// CHECK5-NEXT: [[TMP32:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, ptr @.omp_task_entry., i64 -1)3924// CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP32]], i32 0, i32 03925// CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP33]], i32 0, i32 03926// CHECK5-NEXT: [[TMP35:%.*]] = load ptr, ptr [[TMP34]], align 83927// CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP35]], ptr align 4 [[AGG_CAPTURED]], i64 12, i1 false)3928// CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP32]], i32 0, i32 13929// CHECK5-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP36]], i32 0, i32 03930// CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP37]], ptr align 8 [[TMP24]], i64 24, i1 false)3931// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 13932// CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP38]], ptr align 8 [[TMP25]], i64 24, i1 false)3933// CHECK5-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 23934// CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP39]], ptr align 8 @.offload_sizes, i64 24, i1 false)3935// CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 33936// CHECK5-NEXT: [[TMP41:%.*]] = load i16, ptr [[AA]], align 23937// CHECK5-NEXT: store i16 [[TMP41]], ptr [[TMP40]], align 83938// CHECK5-NEXT: [[TMP42:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP32]])3939// CHECK5-NEXT: [[TMP43:%.*]] = load i32, ptr [[A]], align 43940// CHECK5-NEXT: store i32 [[TMP43]], ptr [[A_CASTED]], align 43941// CHECK5-NEXT: [[TMP44:%.*]] = load i64, ptr [[A_CASTED]], align 83942// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102(i64 [[TMP44]]) #[[ATTR3:[0-9]+]]3943// CHECK5-NEXT: [[TMP45:%.*]] = load i16, ptr [[AA]], align 23944// CHECK5-NEXT: store i16 [[TMP45]], ptr [[AA_CASTED4]], align 23945// CHECK5-NEXT: [[TMP46:%.*]] = load i64, ptr [[AA_CASTED4]], align 83946// CHECK5-NEXT: [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 03947// CHECK5-NEXT: store i64 [[TMP46]], ptr [[TMP47]], align 83948// CHECK5-NEXT: [[TMP48:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 03949// CHECK5-NEXT: store i64 [[TMP46]], ptr [[TMP48]], align 83950// CHECK5-NEXT: [[TMP49:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 03951// CHECK5-NEXT: store ptr null, ptr [[TMP49]], align 83952// CHECK5-NEXT: [[TMP50:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 03953// CHECK5-NEXT: [[TMP51:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 03954// CHECK5-NEXT: [[TMP52:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 03955// CHECK5-NEXT: store i32 3, ptr [[TMP52]], align 43956// CHECK5-NEXT: [[TMP53:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 13957// CHECK5-NEXT: store i32 1, ptr [[TMP53]], align 43958// CHECK5-NEXT: [[TMP54:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 23959// CHECK5-NEXT: store ptr [[TMP50]], ptr [[TMP54]], align 83960// CHECK5-NEXT: [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 33961// CHECK5-NEXT: store ptr [[TMP51]], ptr [[TMP55]], align 83962// CHECK5-NEXT: [[TMP56:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 43963// CHECK5-NEXT: store ptr @.offload_sizes.1, ptr [[TMP56]], align 83964// CHECK5-NEXT: [[TMP57:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 53965// CHECK5-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP57]], align 83966// CHECK5-NEXT: [[TMP58:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 63967// CHECK5-NEXT: store ptr null, ptr [[TMP58]], align 83968// CHECK5-NEXT: [[TMP59:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 73969// CHECK5-NEXT: store ptr null, ptr [[TMP59]], align 83970// CHECK5-NEXT: [[TMP60:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 83971// CHECK5-NEXT: store i64 10, ptr [[TMP60]], align 83972// CHECK5-NEXT: [[TMP61:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 93973// CHECK5-NEXT: store i64 0, ptr [[TMP61]], align 83974// CHECK5-NEXT: [[TMP62:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 103975// CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP62]], align 43976// CHECK5-NEXT: [[TMP63:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 113977// CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP63]], align 43978// CHECK5-NEXT: [[TMP64:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 123979// CHECK5-NEXT: store i32 0, ptr [[TMP64]], align 43980// CHECK5-NEXT: [[TMP65:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, ptr [[KERNEL_ARGS]])3981// CHECK5-NEXT: [[TMP66:%.*]] = icmp ne i32 [[TMP65]], 03982// CHECK5-NEXT: br i1 [[TMP66]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]3983// CHECK5: omp_offload.failed:3984// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP46]]) #[[ATTR3]]3985// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]3986// CHECK5: omp_offload.cont:3987// CHECK5-NEXT: [[TMP67:%.*]] = load i32, ptr [[A]], align 43988// CHECK5-NEXT: store i32 [[TMP67]], ptr [[A_CASTED8]], align 43989// CHECK5-NEXT: [[TMP68:%.*]] = load i64, ptr [[A_CASTED8]], align 83990// CHECK5-NEXT: [[TMP69:%.*]] = load i16, ptr [[AA]], align 23991// CHECK5-NEXT: store i16 [[TMP69]], ptr [[AA_CASTED9]], align 23992// CHECK5-NEXT: [[TMP70:%.*]] = load i64, ptr [[AA_CASTED9]], align 83993// CHECK5-NEXT: [[TMP71:%.*]] = load i32, ptr [[N_ADDR]], align 43994// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP71]], 103995// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]3996// CHECK5: omp_if.then:3997// CHECK5-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 03998// CHECK5-NEXT: store i64 [[TMP68]], ptr [[TMP72]], align 83999// CHECK5-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 04000// CHECK5-NEXT: store i64 [[TMP68]], ptr [[TMP73]], align 84001// CHECK5-NEXT: [[TMP74:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 04002// CHECK5-NEXT: store ptr null, ptr [[TMP74]], align 84003// CHECK5-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 14004// CHECK5-NEXT: store i64 [[TMP70]], ptr [[TMP75]], align 84005// CHECK5-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 14006// CHECK5-NEXT: store i64 [[TMP70]], ptr [[TMP76]], align 84007// CHECK5-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 14008// CHECK5-NEXT: store ptr null, ptr [[TMP77]], align 84009// CHECK5-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 04010// CHECK5-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 04011// CHECK5-NEXT: [[TMP80:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 04012// CHECK5-NEXT: store i32 3, ptr [[TMP80]], align 44013// CHECK5-NEXT: [[TMP81:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 14014// CHECK5-NEXT: store i32 2, ptr [[TMP81]], align 44015// CHECK5-NEXT: [[TMP82:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 24016// CHECK5-NEXT: store ptr [[TMP78]], ptr [[TMP82]], align 84017// CHECK5-NEXT: [[TMP83:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 34018// CHECK5-NEXT: store ptr [[TMP79]], ptr [[TMP83]], align 84019// CHECK5-NEXT: [[TMP84:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 44020// CHECK5-NEXT: store ptr @.offload_sizes.3, ptr [[TMP84]], align 84021// CHECK5-NEXT: [[TMP85:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 54022// CHECK5-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP85]], align 84023// CHECK5-NEXT: [[TMP86:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 64024// CHECK5-NEXT: store ptr null, ptr [[TMP86]], align 84025// CHECK5-NEXT: [[TMP87:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 74026// CHECK5-NEXT: store ptr null, ptr [[TMP87]], align 84027// CHECK5-NEXT: [[TMP88:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 84028// CHECK5-NEXT: store i64 10, ptr [[TMP88]], align 84029// CHECK5-NEXT: [[TMP89:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 94030// CHECK5-NEXT: store i64 0, ptr [[TMP89]], align 84031// CHECK5-NEXT: [[TMP90:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 104032// CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP90]], align 44033// CHECK5-NEXT: [[TMP91:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 114034// CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP91]], align 44035// CHECK5-NEXT: [[TMP92:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 124036// CHECK5-NEXT: store i32 0, ptr [[TMP92]], align 44037// CHECK5-NEXT: [[TMP93:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, ptr [[KERNEL_ARGS14]])4038// CHECK5-NEXT: [[TMP94:%.*]] = icmp ne i32 [[TMP93]], 04039// CHECK5-NEXT: br i1 [[TMP94]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]4040// CHECK5: omp_offload.failed15:4041// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR3]]4042// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT16]]4043// CHECK5: omp_offload.cont16:4044// CHECK5-NEXT: br label [[OMP_IF_END:%.*]]4045// CHECK5: omp_if.else:4046// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR3]]4047// CHECK5-NEXT: br label [[OMP_IF_END]]4048// CHECK5: omp_if.end:4049// CHECK5-NEXT: [[TMP95:%.*]] = load i32, ptr [[A]], align 44050// CHECK5-NEXT: store i32 [[TMP95]], ptr [[A_CASTED17]], align 44051// CHECK5-NEXT: [[TMP96:%.*]] = load i64, ptr [[A_CASTED17]], align 84052// CHECK5-NEXT: [[TMP97:%.*]] = load i32, ptr [[N_ADDR]], align 44053// CHECK5-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP97]], 204054// CHECK5-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE27:%.*]]4055// CHECK5: omp_if.then19:4056// CHECK5-NEXT: [[TMP98:%.*]] = mul nuw i64 [[TMP2]], 44057// CHECK5-NEXT: [[TMP99:%.*]] = mul nuw i64 5, [[TMP5]]4058// CHECK5-NEXT: [[TMP100:%.*]] = mul nuw i64 [[TMP99]], 84059// CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.5, i64 72, i1 false)4060// CHECK5-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 04061// CHECK5-NEXT: store i64 [[TMP96]], ptr [[TMP101]], align 84062// CHECK5-NEXT: [[TMP102:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 04063// CHECK5-NEXT: store i64 [[TMP96]], ptr [[TMP102]], align 84064// CHECK5-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 04065// CHECK5-NEXT: store ptr null, ptr [[TMP103]], align 84066// CHECK5-NEXT: [[TMP104:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 14067// CHECK5-NEXT: store ptr [[B]], ptr [[TMP104]], align 84068// CHECK5-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 14069// CHECK5-NEXT: store ptr [[B]], ptr [[TMP105]], align 84070// CHECK5-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 14071// CHECK5-NEXT: store ptr null, ptr [[TMP106]], align 84072// CHECK5-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 24073// CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP107]], align 84074// CHECK5-NEXT: [[TMP108:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 24075// CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP108]], align 84076// CHECK5-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 24077// CHECK5-NEXT: store ptr null, ptr [[TMP109]], align 84078// CHECK5-NEXT: [[TMP110:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 34079// CHECK5-NEXT: store ptr [[VLA]], ptr [[TMP110]], align 84080// CHECK5-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 34081// CHECK5-NEXT: store ptr [[VLA]], ptr [[TMP111]], align 84082// CHECK5-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 34083// CHECK5-NEXT: store i64 [[TMP98]], ptr [[TMP112]], align 84084// CHECK5-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 34085// CHECK5-NEXT: store ptr null, ptr [[TMP113]], align 84086// CHECK5-NEXT: [[TMP114:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 44087// CHECK5-NEXT: store ptr [[C]], ptr [[TMP114]], align 84088// CHECK5-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 44089// CHECK5-NEXT: store ptr [[C]], ptr [[TMP115]], align 84090// CHECK5-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 44091// CHECK5-NEXT: store ptr null, ptr [[TMP116]], align 84092// CHECK5-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 54093// CHECK5-NEXT: store i64 5, ptr [[TMP117]], align 84094// CHECK5-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 54095// CHECK5-NEXT: store i64 5, ptr [[TMP118]], align 84096// CHECK5-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 54097// CHECK5-NEXT: store ptr null, ptr [[TMP119]], align 84098// CHECK5-NEXT: [[TMP120:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 64099// CHECK5-NEXT: store i64 [[TMP5]], ptr [[TMP120]], align 84100// CHECK5-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 64101// CHECK5-NEXT: store i64 [[TMP5]], ptr [[TMP121]], align 84102// CHECK5-NEXT: [[TMP122:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 64103// CHECK5-NEXT: store ptr null, ptr [[TMP122]], align 84104// CHECK5-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 74105// CHECK5-NEXT: store ptr [[VLA1]], ptr [[TMP123]], align 84106// CHECK5-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 74107// CHECK5-NEXT: store ptr [[VLA1]], ptr [[TMP124]], align 84108// CHECK5-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 74109// CHECK5-NEXT: store i64 [[TMP100]], ptr [[TMP125]], align 84110// CHECK5-NEXT: [[TMP126:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 74111// CHECK5-NEXT: store ptr null, ptr [[TMP126]], align 84112// CHECK5-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 84113// CHECK5-NEXT: store ptr [[D]], ptr [[TMP127]], align 84114// CHECK5-NEXT: [[TMP128:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 84115// CHECK5-NEXT: store ptr [[D]], ptr [[TMP128]], align 84116// CHECK5-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 84117// CHECK5-NEXT: store ptr null, ptr [[TMP129]], align 84118// CHECK5-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 04119// CHECK5-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 04120// CHECK5-NEXT: [[TMP132:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 04121// CHECK5-NEXT: [[TMP133:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 04122// CHECK5-NEXT: store i32 3, ptr [[TMP133]], align 44123// CHECK5-NEXT: [[TMP134:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 14124// CHECK5-NEXT: store i32 9, ptr [[TMP134]], align 44125// CHECK5-NEXT: [[TMP135:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 24126// CHECK5-NEXT: store ptr [[TMP130]], ptr [[TMP135]], align 84127// CHECK5-NEXT: [[TMP136:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 34128// CHECK5-NEXT: store ptr [[TMP131]], ptr [[TMP136]], align 84129// CHECK5-NEXT: [[TMP137:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 44130// CHECK5-NEXT: store ptr [[TMP132]], ptr [[TMP137]], align 84131// CHECK5-NEXT: [[TMP138:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 54132// CHECK5-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP138]], align 84133// CHECK5-NEXT: [[TMP139:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 64134// CHECK5-NEXT: store ptr null, ptr [[TMP139]], align 84135// CHECK5-NEXT: [[TMP140:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 74136// CHECK5-NEXT: store ptr null, ptr [[TMP140]], align 84137// CHECK5-NEXT: [[TMP141:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 84138// CHECK5-NEXT: store i64 10, ptr [[TMP141]], align 84139// CHECK5-NEXT: [[TMP142:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 94140// CHECK5-NEXT: store i64 0, ptr [[TMP142]], align 84141// CHECK5-NEXT: [[TMP143:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 104142// CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP143]], align 44143// CHECK5-NEXT: [[TMP144:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 114144// CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP144]], align 44145// CHECK5-NEXT: [[TMP145:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 124146// CHECK5-NEXT: store i32 0, ptr [[TMP145]], align 44147// CHECK5-NEXT: [[TMP146:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, ptr [[KERNEL_ARGS24]])4148// CHECK5-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 04149// CHECK5-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]]4150// CHECK5: omp_offload.failed25:4151// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP96]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]4152// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT26]]4153// CHECK5: omp_offload.cont26:4154// CHECK5-NEXT: br label [[OMP_IF_END28:%.*]]4155// CHECK5: omp_if.else27:4156// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP96]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]4157// CHECK5-NEXT: br label [[OMP_IF_END28]]4158// CHECK5: omp_if.end28:4159// CHECK5-NEXT: [[TMP148:%.*]] = load i32, ptr [[A]], align 44160// CHECK5-NEXT: [[TMP149:%.*]] = load ptr, ptr [[SAVED_STACK]], align 84161// CHECK5-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP149]])4162// CHECK5-NEXT: ret i32 [[TMP148]]4163//4164//4165// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l974166// CHECK5-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {4167// CHECK5-NEXT: entry:4168// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 84169// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 84170// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 84171// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 84172// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])4173// CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 84174// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 84175// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 84176// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 44177// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 44178// CHECK5-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])4179// CHECK5-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 24180// CHECK5-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 24181// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 84182// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i64 [[TMP4]])4183// CHECK5-NEXT: ret void4184//4185//4186// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined4187// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {4188// CHECK5-NEXT: entry:4189// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84190// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84191// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 84192// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44193// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 44194// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 44195// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 44196// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44197// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44198// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 44199// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84200// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84201// CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 84202// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 44203// CHECK5-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 44204// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 44205// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44206// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84207// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44208// CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)4209// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44210// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 94211// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4212// CHECK5: cond.true:4213// CHECK5-NEXT: br label [[COND_END:%.*]]4214// CHECK5: cond.false:4215// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44216// CHECK5-NEXT: br label [[COND_END]]4217// CHECK5: cond.end:4218// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]4219// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 44220// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44221// CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 44222// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4223// CHECK5: omp.inner.for.cond:4224// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]]4225// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]]4226// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]4227// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4228// CHECK5: omp.inner.for.body:4229// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]4230// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 14231// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]4232// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]4233// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4234// CHECK5: omp.body.continue:4235// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4236// CHECK5: omp.inner.for.inc:4237// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]4238// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 14239// CHECK5-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]4240// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]4241// CHECK5: omp.inner.for.end:4242// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]4243// CHECK5: omp.loop.exit:4244// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])4245// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 44246// CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 04247// CHECK5-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]4248// CHECK5: .omp.final.then:4249// CHECK5-NEXT: store i32 10, ptr [[I]], align 44250// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]4251// CHECK5: .omp.final.done:4252// CHECK5-NEXT: ret void4253//4254//4255// CHECK5-LABEL: define {{[^@]+}}@.omp_task_privates_map.4256// CHECK5-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {4257// CHECK5-NEXT: entry:4258// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 84259// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 84260// CHECK5-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 84261// CHECK5-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 84262// CHECK5-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 84263// CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 84264// CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 84265// CHECK5-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 84266// CHECK5-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 84267// CHECK5-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 84268// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 84269// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 04270// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 84271// CHECK5-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 84272// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 14273// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR3]], align 84274// CHECK5-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 84275// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 24276// CHECK5-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR4]], align 84277// CHECK5-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 84278// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 34279// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 84280// CHECK5-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 84281// CHECK5-NEXT: ret void4282//4283//4284// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry.4285// CHECK5-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {4286// CHECK5-NEXT: entry:4287// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 44288// CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 84289// CHECK5-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 84290// CHECK5-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 84291// CHECK5-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 84292// CHECK5-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 84293// CHECK5-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 84294// CHECK5-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 84295// CHECK5-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 84296// CHECK5-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 84297// CHECK5-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 84298// CHECK5-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 84299// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 84300// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i64, align 84301// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i32, align 44302// CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 84303// CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 44304// CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 84305// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 44306// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 84307// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 04308// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 24309// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 04310// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 84311// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 14312// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])4313// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])4314// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])4315// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])4316// CHECK5-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META26:![0-9]+]]4317// CHECK5-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META26]]4318// CHECK5-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META26]]4319// CHECK5-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META26]]4320// CHECK5-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META26]]4321// CHECK5-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META26]]4322// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META26]]4323// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META26]]4324// CHECK5-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META26]]4325// CHECK5-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]4326// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META26]]4327// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META26]]4328// CHECK5-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META26]]4329// CHECK5-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META26]]4330// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 14331// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 24332// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 44333// CHECK5-NEXT: [[TMP19:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP18]], 04334// CHECK5-NEXT: store i32 3, ptr [[KERNEL_ARGS_I]], align 4, !noalias [[META26]]4335// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 14336// CHECK5-NEXT: store i32 3, ptr [[TMP20]], align 4, !noalias [[META26]]4337// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 24338// CHECK5-NEXT: store ptr [[TMP13]], ptr [[TMP21]], align 8, !noalias [[META26]]4339// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 34340// CHECK5-NEXT: store ptr [[TMP14]], ptr [[TMP22]], align 8, !noalias [[META26]]4341// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 44342// CHECK5-NEXT: store ptr [[TMP15]], ptr [[TMP23]], align 8, !noalias [[META26]]4343// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 54344// CHECK5-NEXT: store ptr @.offload_maptypes, ptr [[TMP24]], align 8, !noalias [[META26]]4345// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 64346// CHECK5-NEXT: store ptr null, ptr [[TMP25]], align 8, !noalias [[META26]]4347// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 74348// CHECK5-NEXT: store ptr null, ptr [[TMP26]], align 8, !noalias [[META26]]4349// CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 84350// CHECK5-NEXT: store i64 10, ptr [[TMP27]], align 8, !noalias [[META26]]4351// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 94352// CHECK5-NEXT: store i64 1, ptr [[TMP28]], align 8, !noalias [[META26]]4353// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 104354// CHECK5-NEXT: store [3 x i32] [[TMP19]], ptr [[TMP29]], align 4, !noalias [[META26]]4355// CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 114356// CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP30]], align 4, !noalias [[META26]]4357// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 124358// CHECK5-NEXT: store i32 0, ptr [[TMP31]], align 4, !noalias [[META26]]4359// CHECK5-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 [[TMP18]], i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, ptr [[KERNEL_ARGS_I]])4360// CHECK5-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 04361// CHECK5-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]4362// CHECK5: omp_offload.failed.i:4363// CHECK5-NEXT: [[TMP34:%.*]] = load i16, ptr [[TMP12]], align 24364// CHECK5-NEXT: store i16 [[TMP34]], ptr [[AA_CASTED_I]], align 2, !noalias [[META26]]4365// CHECK5-NEXT: [[TMP35:%.*]] = load i64, ptr [[AA_CASTED_I]], align 8, !noalias [[META26]]4366// CHECK5-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP16]], align 44367// CHECK5-NEXT: store i32 [[TMP36]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias [[META26]]4368// CHECK5-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias [[META26]]4369// CHECK5-NEXT: [[TMP38:%.*]] = load i32, ptr [[TMP17]], align 44370// CHECK5-NEXT: store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias [[META26]]4371// CHECK5-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 8, !noalias [[META26]]4372// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i64 [[TMP35]], i64 [[TMP37]], i64 [[TMP39]]) #[[ATTR3]]4373// CHECK5-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]4374// CHECK5: .omp_outlined..exit:4375// CHECK5-NEXT: ret i32 04376//4377//4378// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1024379// CHECK5-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] {4380// CHECK5-NEXT: entry:4381// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 84382// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 84383// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 84384// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 44385// CHECK5-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 44386// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 84387// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102.omp_outlined, i64 [[TMP1]])4388// CHECK5-NEXT: ret void4389//4390//4391// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102.omp_outlined4392// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {4393// CHECK5-NEXT: entry:4394// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84395// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84396// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 84397// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44398// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 44399// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 44400// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 44401// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44402// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44403// CHECK5-NEXT: [[A1:%.*]] = alloca i32, align 44404// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84405// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84406// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 84407// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 44408// CHECK5-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 44409// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 44410// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44411// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84412// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44413// CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)4414// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44415// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 94416// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4417// CHECK5: cond.true:4418// CHECK5-NEXT: br label [[COND_END:%.*]]4419// CHECK5: cond.false:4420// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44421// CHECK5-NEXT: br label [[COND_END]]4422// CHECK5: cond.end:4423// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]4424// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 44425// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44426// CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 44427// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4428// CHECK5: omp.inner.for.cond:4429// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44430// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44431// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]4432// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4433// CHECK5: omp.inner.for.body:4434// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44435// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 14436// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]4437// CHECK5-NEXT: store i32 [[ADD]], ptr [[A1]], align 4, !nontemporal [[META27:![0-9]+]]4438// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 4, !nontemporal [[META27]]4439// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 14440// CHECK5-NEXT: store i32 [[ADD3]], ptr [[A1]], align 4, !nontemporal [[META27]]4441// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4442// CHECK5: omp.body.continue:4443// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4444// CHECK5: omp.inner.for.inc:4445// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 44446// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 14447// CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 44448// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]4449// CHECK5: omp.inner.for.end:4450// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]4451// CHECK5: omp.loop.exit:4452// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])4453// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 44454// CHECK5-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 04455// CHECK5-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]4456// CHECK5: .omp.final.then:4457// CHECK5-NEXT: store i32 10, ptr [[A_ADDR]], align 44458// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]4459// CHECK5: .omp.final.done:4460// CHECK5-NEXT: ret void4461//4462//4463// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1114464// CHECK5-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] {4465// CHECK5-NEXT: entry:4466// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 84467// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 84468// CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 84469// CHECK5-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 24470// CHECK5-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 24471// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 84472// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP1]])4473// CHECK5-NEXT: ret void4474//4475//4476// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined4477// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {4478// CHECK5-NEXT: entry:4479// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84480// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84481// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 84482// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44483// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 44484// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 44485// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 44486// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44487// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44488// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 44489// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84490// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84491// CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 84492// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 44493// CHECK5-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 44494// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 44495// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44496// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84497// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44498// CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)4499// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44500// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 94501// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4502// CHECK5: cond.true:4503// CHECK5-NEXT: br label [[COND_END:%.*]]4504// CHECK5: cond.false:4505// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44506// CHECK5-NEXT: br label [[COND_END]]4507// CHECK5: cond.end:4508// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]4509// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 44510// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44511// CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 44512// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4513// CHECK5: omp.inner.for.cond:4514// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30:![0-9]+]]4515// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP30]]4516// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]4517// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4518// CHECK5: omp.inner.for.body:4519// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]]4520// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 14521// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]4522// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP30]]4523// CHECK5-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]]4524// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i324525// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 14526// CHECK5-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i164527// CHECK5-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]]4528// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4529// CHECK5: omp.body.continue:4530// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4531// CHECK5: omp.inner.for.inc:4532// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]]4533// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 14534// CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]]4535// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]4536// CHECK5: omp.inner.for.end:4537// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]4538// CHECK5: omp.loop.exit:4539// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])4540// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 44541// CHECK5-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 04542// CHECK5-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]4543// CHECK5: .omp.final.then:4544// CHECK5-NEXT: store i32 10, ptr [[I]], align 44545// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]4546// CHECK5: .omp.final.done:4547// CHECK5-NEXT: ret void4548//4549//4550// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1184551// CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {4552// CHECK5-NEXT: entry:4553// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 84554// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 84555// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 84556// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 84557// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 84558// CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 84559// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 44560// CHECK5-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 44561// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 84562// CHECK5-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 24563// CHECK5-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 24564// CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 84565// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])4566// CHECK5-NEXT: ret void4567//4568//4569// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined4570// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {4571// CHECK5-NEXT: entry:4572// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84573// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84574// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 84575// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 84576// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44577// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 44578// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 44579// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 44580// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44581// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44582// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 44583// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84584// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84585// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 84586// CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 84587// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 44588// CHECK5-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 44589// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 44590// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44591// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84592// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 44593// CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)4594// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44595// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 94596// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4597// CHECK5: cond.true:4598// CHECK5-NEXT: br label [[COND_END:%.*]]4599// CHECK5: cond.false:4600// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44601// CHECK5-NEXT: br label [[COND_END]]4602// CHECK5: cond.end:4603// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]4604// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 44605// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44606// CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 44607// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4608// CHECK5: omp.inner.for.cond:4609// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]]4610// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]]4611// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]4612// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4613// CHECK5: omp.inner.for.body:4614// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]4615// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 14616// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]4617// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]]4618// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]]4619// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 14620// CHECK5-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]]4621// CHECK5-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]]4622// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i324623// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 14624// CHECK5-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i164625// CHECK5-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]]4626// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4627// CHECK5: omp.body.continue:4628// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4629// CHECK5: omp.inner.for.inc:4630// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]4631// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 14632// CHECK5-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]4633// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]4634// CHECK5: omp.inner.for.end:4635// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]4636// CHECK5: omp.loop.exit:4637// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])4638// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 44639// CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 04640// CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]4641// CHECK5: .omp.final.then:4642// CHECK5-NEXT: store i32 10, ptr [[I]], align 44643// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]4644// CHECK5: .omp.final.done:4645// CHECK5-NEXT: ret void4646//4647//4648// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1424649// CHECK5-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {4650// CHECK5-NEXT: entry:4651// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 84652// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 84653// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 84654// CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 84655// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 84656// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 84657// CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 84658// CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 84659// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 84660// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 84661// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 84662// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 84663// CHECK5-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 84664// CHECK5-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 84665// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 84666// CHECK5-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 84667// CHECK5-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 84668// CHECK5-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 84669// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 84670// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 84671// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 84672// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 84673// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 84674// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 84675// CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 84676// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 84677// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 84678// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 44679// CHECK5-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 44680// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 84681// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])4682// CHECK5-NEXT: ret void4683//4684//4685// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined4686// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {4687// CHECK5-NEXT: entry:4688// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 84689// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 84690// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 84691// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 84692// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 84693// CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 84694// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 84695// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 84696// CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 84697// CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 84698// CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 84699// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 44700// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 44701// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 44702// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 44703// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 44704// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 44705// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 44706// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 84707// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 84708// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 84709// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 84710// CHECK5-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 84711// CHECK5-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 84712// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 84713// CHECK5-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 84714// CHECK5-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 84715// CHECK5-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 84716// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 84717// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 84718// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 84719// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 84720// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 84721// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 84722// CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 84723// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 84724// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 84725// CHECK5-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 04726// CHECK5-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i64 16) ]4727// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 44728// CHECK5-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 44729// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 44730// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 44731// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 84732// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 44733// CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)4734// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44735// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 94736// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]4737// CHECK5: cond.true:4738// CHECK5-NEXT: br label [[COND_END:%.*]]4739// CHECK5: cond.false:4740// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 44741// CHECK5-NEXT: br label [[COND_END]]4742// CHECK5: cond.end:4743// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]4744// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 44745// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 44746// CHECK5-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 44747// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]4748// CHECK5: omp.inner.for.cond:4749// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]]4750// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP36]]4751// CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]4752// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]4753// CHECK5: omp.inner.for.body:4754// CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]4755// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 14756// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]4757// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP36]]4758// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]]4759// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 14760// CHECK5-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]]4761// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 24762// CHECK5-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]]4763// CHECK5-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double4764// CHECK5-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+004765// CHECK5-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float4766// CHECK5-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]]4767// CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 34768// CHECK5-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP36]]4769// CHECK5-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double4770// CHECK5-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+004771// CHECK5-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float4772// CHECK5-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP36]]4773// CHECK5-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 14774// CHECK5-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i64 0, i64 24775// CHECK5-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP36]]4776// CHECK5-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+004777// CHECK5-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP36]]4778// CHECK5-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]]4779// CHECK5-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP20]]4780// CHECK5-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i64 34781// CHECK5-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP36]]4782// CHECK5-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+004783// CHECK5-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP36]]4784// CHECK5-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 04785// CHECK5-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP36]]4786// CHECK5-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 14787// CHECK5-NEXT: store i64 [[ADD19]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP36]]4788// CHECK5-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 14789// CHECK5-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP36]]4790// CHECK5-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i324791// CHECK5-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 14792// CHECK5-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i84793// CHECK5-NEXT: store i8 [[CONV22]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP36]]4794// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]4795// CHECK5: omp.body.continue:4796// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]4797// CHECK5: omp.inner.for.inc:4798// CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]4799// CHECK5-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 14800// CHECK5-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]4801// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]4802// CHECK5: omp.inner.for.end:4803// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]4804// CHECK5: omp.loop.exit:4805// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP9]])4806// CHECK5-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 44807// CHECK5-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 04808// CHECK5-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]4809// CHECK5: .omp.final.then:4810// CHECK5-NEXT: store i32 10, ptr [[I]], align 44811// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]4812// CHECK5: .omp.final.done:4813// CHECK5-NEXT: ret void4814//4815//4816// CHECK5-LABEL: define {{[^@]+}}@_Z3bari4817// CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {4818// CHECK5-NEXT: entry:4819// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 44820// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 44821// CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 84822// CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 44823// CHECK5-NEXT: store i32 0, ptr [[A]], align 44824// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 44825// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])4826// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 44827// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]4828// CHECK5-NEXT: store i32 [[ADD]], ptr [[A]], align 44829// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 44830// CHECK5-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])4831// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 44832// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]4833// CHECK5-NEXT: store i32 [[ADD2]], ptr [[A]], align 44834// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 44835// CHECK5-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])4836// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 44837// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]4838// CHECK5-NEXT: store i32 [[ADD4]], ptr [[A]], align 44839// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 44840// CHECK5-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])4841// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 44842// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]4843// CHECK5-NEXT: store i32 [[ADD6]], ptr [[A]], align 44844// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 44845// CHECK5-NEXT: ret i32 [[TMP8]]4846//4847//4848// CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei4849// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {4850// CHECK5-NEXT: entry:4851// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 84852// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 44853// CHECK5-NEXT: [[B:%.*]] = alloca i32, align 44854// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 84855// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 84856// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 14857// CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 84858// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 84859// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x ptr], align 84860// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x ptr], align 84861// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x ptr], align 84862// CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 84863// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 44864// CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 84865// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 84866// CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 44867// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 84868// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 44869// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 14870// CHECK5-NEXT: store i32 [[ADD]], ptr [[B]], align 44871// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 44872// CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i644873// CHECK5-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()4874// CHECK5-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 84875// CHECK5-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]4876// CHECK5-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 24877// CHECK5-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 84878// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 44879// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 604880// CHECK5-NEXT: [[STOREDV:%.*]] = zext i1 [[CMP]] to i84881// CHECK5-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 14882// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[B]], align 44883// CHECK5-NEXT: store i32 [[TMP6]], ptr [[B_CASTED]], align 44884// CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[B_CASTED]], align 84885// CHECK5-NEXT: [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 14886// CHECK5-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP8]] to i14887// CHECK5-NEXT: [[STOREDV2:%.*]] = zext i1 [[LOADEDV]] to i84888// CHECK5-NEXT: store i8 [[STOREDV2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 14889// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 84890// CHECK5-NEXT: [[TMP10:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 14891// CHECK5-NEXT: [[LOADEDV3:%.*]] = trunc i8 [[TMP10]] to i14892// CHECK5-NEXT: br i1 [[LOADEDV3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]4893// CHECK5: omp_if.then:4894// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 04895// CHECK5-NEXT: [[TMP11:%.*]] = mul nuw i64 2, [[TMP2]]4896// CHECK5-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 24897// CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.7, i64 48, i1 false)4898// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04899// CHECK5-NEXT: store ptr [[THIS1]], ptr [[TMP13]], align 84900// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 04901// CHECK5-NEXT: store ptr [[A]], ptr [[TMP14]], align 84902// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 04903// CHECK5-NEXT: store ptr null, ptr [[TMP15]], align 84904// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 14905// CHECK5-NEXT: store i64 [[TMP7]], ptr [[TMP16]], align 84906// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 14907// CHECK5-NEXT: store i64 [[TMP7]], ptr [[TMP17]], align 84908// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 14909// CHECK5-NEXT: store ptr null, ptr [[TMP18]], align 84910// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 24911// CHECK5-NEXT: store i64 2, ptr [[TMP19]], align 84912// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 24913// CHECK5-NEXT: store i64 2, ptr [[TMP20]], align 84914// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 24915// CHECK5-NEXT: store ptr null, ptr [[TMP21]], align 84916// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 34917// CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP22]], align 84918// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 34919// CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP23]], align 84920// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 34921// CHECK5-NEXT: store ptr null, ptr [[TMP24]], align 84922// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 44923// CHECK5-NEXT: store ptr [[VLA]], ptr [[TMP25]], align 84924// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 44925// CHECK5-NEXT: store ptr [[VLA]], ptr [[TMP26]], align 84926// CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 44927// CHECK5-NEXT: store i64 [[TMP12]], ptr [[TMP27]], align 84928// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 44929// CHECK5-NEXT: store ptr null, ptr [[TMP28]], align 84930// CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 54931// CHECK5-NEXT: store i64 [[TMP9]], ptr [[TMP29]], align 84932// CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 54933// CHECK5-NEXT: store i64 [[TMP9]], ptr [[TMP30]], align 84934// CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 54935// CHECK5-NEXT: store ptr null, ptr [[TMP31]], align 84936// CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 04937// CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 04938// CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 04939// CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 04940// CHECK5-NEXT: store i32 3, ptr [[TMP35]], align 44941// CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 14942// CHECK5-NEXT: store i32 6, ptr [[TMP36]], align 44943// CHECK5-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 24944// CHECK5-NEXT: store ptr [[TMP32]], ptr [[TMP37]], align 84945// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 34946// CHECK5-NEXT: store ptr [[TMP33]], ptr [[TMP38]], align 84947// CHECK5-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 44948// CHECK5-NEXT: store ptr [[TMP34]], ptr [[TMP39]], align 84949// CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 54950// CHECK5-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP40]], align 84951// CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 64952// CHECK5-NEXT: store ptr null, ptr [[TMP41]], align 84953// CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 74954// CHECK5-NEXT: store ptr null, ptr [[TMP42]], align 84955// CHECK5-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 84956// CHECK5-NEXT: store i64 10, ptr [[TMP43]], align 84957// CHECK5-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 94958// CHECK5-NEXT: store i64 0, ptr [[TMP44]], align 84959// CHECK5-NEXT: [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 104960// CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP45]], align 44961// CHECK5-NEXT: [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 114962// CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP46]], align 44963// CHECK5-NEXT: [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 124964// CHECK5-NEXT: store i32 0, ptr [[TMP47]], align 44965// CHECK5-NEXT: [[TMP48:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.region_id, ptr [[KERNEL_ARGS]])4966// CHECK5-NEXT: [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 04967// CHECK5-NEXT: br i1 [[TMP49]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]4968// CHECK5: omp_offload.failed:4969// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], ptr [[VLA]], i64 [[TMP9]]) #[[ATTR3]]4970// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]4971// CHECK5: omp_offload.cont:4972// CHECK5-NEXT: br label [[OMP_IF_END:%.*]]4973// CHECK5: omp_if.else:4974// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], ptr [[VLA]], i64 [[TMP9]]) #[[ATTR3]]4975// CHECK5-NEXT: br label [[OMP_IF_END]]4976// CHECK5: omp_if.end:4977// CHECK5-NEXT: [[TMP50:%.*]] = mul nsw i64 1, [[TMP2]]4978// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP50]]4979// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 14980// CHECK5-NEXT: [[TMP51:%.*]] = load i16, ptr [[ARRAYIDX4]], align 24981// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP51]] to i324982// CHECK5-NEXT: [[TMP52:%.*]] = load i32, ptr [[B]], align 44983// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV]], [[TMP52]]4984// CHECK5-NEXT: [[TMP53:%.*]] = load ptr, ptr [[SAVED_STACK]], align 84985// CHECK5-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP53]])4986// CHECK5-NEXT: ret i32 [[ADD5]]4987//4988//4989// CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici4990// CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {4991// CHECK5-NEXT: entry:4992// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 44993// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 44994// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 24995// CHECK5-NEXT: [[AAA:%.*]] = alloca i8, align 14996// CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 44997// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 84998// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 84999// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 85000// CHECK5-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 85001// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 85002// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 85003// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 85004// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 45005// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 45006// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 45007// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 45008// CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 85009// CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 45010// CHECK5-NEXT: store i32 0, ptr [[A]], align 45011// CHECK5-NEXT: store i16 0, ptr [[AA]], align 25012// CHECK5-NEXT: store i8 0, ptr [[AAA]], align 15013// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 45014// CHECK5-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 45015// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 85016// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 45017// CHECK5-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 45018// CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[N_CASTED]], align 85019// CHECK5-NEXT: [[TMP4:%.*]] = load i16, ptr [[AA]], align 25020// CHECK5-NEXT: store i16 [[TMP4]], ptr [[AA_CASTED]], align 25021// CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[AA_CASTED]], align 85022// CHECK5-NEXT: [[TMP6:%.*]] = load i8, ptr [[AAA]], align 15023// CHECK5-NEXT: store i8 [[TMP6]], ptr [[AAA_CASTED]], align 15024// CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[AAA_CASTED]], align 85025// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[N_ADDR]], align 45026// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 505027// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]5028// CHECK5: omp_if.then:5029// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05030// CHECK5-NEXT: store i64 [[TMP1]], ptr [[TMP9]], align 85031// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 05032// CHECK5-NEXT: store i64 [[TMP1]], ptr [[TMP10]], align 85033// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 05034// CHECK5-NEXT: store ptr null, ptr [[TMP11]], align 85035// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 15036// CHECK5-NEXT: store i64 [[TMP3]], ptr [[TMP12]], align 85037// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 15038// CHECK5-NEXT: store i64 [[TMP3]], ptr [[TMP13]], align 85039// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 15040// CHECK5-NEXT: store ptr null, ptr [[TMP14]], align 85041// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 25042// CHECK5-NEXT: store i64 [[TMP5]], ptr [[TMP15]], align 85043// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 25044// CHECK5-NEXT: store i64 [[TMP5]], ptr [[TMP16]], align 85045// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 25046// CHECK5-NEXT: store ptr null, ptr [[TMP17]], align 85047// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 35048// CHECK5-NEXT: store i64 [[TMP7]], ptr [[TMP18]], align 85049// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 35050// CHECK5-NEXT: store i64 [[TMP7]], ptr [[TMP19]], align 85051// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 35052// CHECK5-NEXT: store ptr null, ptr [[TMP20]], align 85053// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 45054// CHECK5-NEXT: store ptr [[B]], ptr [[TMP21]], align 85055// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 45056// CHECK5-NEXT: store ptr [[B]], ptr [[TMP22]], align 85057// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 45058// CHECK5-NEXT: store ptr null, ptr [[TMP23]], align 85059// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05060// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 05061// CHECK5-NEXT: [[TMP26:%.*]] = load i32, ptr [[A]], align 45062// CHECK5-NEXT: store i32 [[TMP26]], ptr [[DOTCAPTURE_EXPR_]], align 45063// CHECK5-NEXT: [[TMP27:%.*]] = load i32, ptr [[N_ADDR]], align 45064// CHECK5-NEXT: store i32 [[TMP27]], ptr [[DOTCAPTURE_EXPR_1]], align 45065// CHECK5-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 45066// CHECK5-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 45067// CHECK5-NEXT: [[SUB:%.*]] = sub i32 [[TMP28]], [[TMP29]]5068// CHECK5-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 15069// CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 15070// CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 15071// CHECK5-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 15072// CHECK5-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 45073// CHECK5-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 45074// CHECK5-NEXT: [[ADD5:%.*]] = add i32 [[TMP30]], 15075// CHECK5-NEXT: [[TMP31:%.*]] = zext i32 [[ADD5]] to i645076// CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 05077// CHECK5-NEXT: store i32 3, ptr [[TMP32]], align 45078// CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 15079// CHECK5-NEXT: store i32 5, ptr [[TMP33]], align 45080// CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 25081// CHECK5-NEXT: store ptr [[TMP24]], ptr [[TMP34]], align 85082// CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 35083// CHECK5-NEXT: store ptr [[TMP25]], ptr [[TMP35]], align 85084// CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 45085// CHECK5-NEXT: store ptr @.offload_sizes.9, ptr [[TMP36]], align 85086// CHECK5-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 55087// CHECK5-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP37]], align 85088// CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 65089// CHECK5-NEXT: store ptr null, ptr [[TMP38]], align 85090// CHECK5-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 75091// CHECK5-NEXT: store ptr null, ptr [[TMP39]], align 85092// CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 85093// CHECK5-NEXT: store i64 [[TMP31]], ptr [[TMP40]], align 85094// CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 95095// CHECK5-NEXT: store i64 0, ptr [[TMP41]], align 85096// CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 105097// CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP42]], align 45098// CHECK5-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 115099// CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP43]], align 45100// CHECK5-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 125101// CHECK5-NEXT: store i32 0, ptr [[TMP44]], align 45102// CHECK5-NEXT: [[TMP45:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.region_id, ptr [[KERNEL_ARGS]])5103// CHECK5-NEXT: [[TMP46:%.*]] = icmp ne i32 [[TMP45]], 05104// CHECK5-NEXT: br i1 [[TMP46]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]5105// CHECK5: omp_offload.failed:5106// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], ptr [[B]]) #[[ATTR3]]5107// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]5108// CHECK5: omp_offload.cont:5109// CHECK5-NEXT: br label [[OMP_IF_END:%.*]]5110// CHECK5: omp_if.else:5111// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], ptr [[B]]) #[[ATTR3]]5112// CHECK5-NEXT: br label [[OMP_IF_END]]5113// CHECK5: omp_if.end:5114// CHECK5-NEXT: [[TMP47:%.*]] = load i32, ptr [[A]], align 45115// CHECK5-NEXT: ret i32 [[TMP47]]5116//5117//5118// CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i5119// CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {5120// CHECK5-NEXT: entry:5121// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 45122// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 45123// CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 25124// CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 45125// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 85126// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 85127// CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 85128// CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 85129// CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 85130// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 45131// CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 85132// CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 45133// CHECK5-NEXT: store i32 0, ptr [[A]], align 45134// CHECK5-NEXT: store i16 0, ptr [[AA]], align 25135// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 45136// CHECK5-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 45137// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 85138// CHECK5-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 25139// CHECK5-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 25140// CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 85141// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 45142// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 405143// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]5144// CHECK5: omp_if.then:5145// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05146// CHECK5-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 85147// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 05148// CHECK5-NEXT: store i64 [[TMP1]], ptr [[TMP6]], align 85149// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 05150// CHECK5-NEXT: store ptr null, ptr [[TMP7]], align 85151// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 15152// CHECK5-NEXT: store i64 [[TMP3]], ptr [[TMP8]], align 85153// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 15154// CHECK5-NEXT: store i64 [[TMP3]], ptr [[TMP9]], align 85155// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 15156// CHECK5-NEXT: store ptr null, ptr [[TMP10]], align 85157// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 25158// CHECK5-NEXT: store ptr [[B]], ptr [[TMP11]], align 85159// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 25160// CHECK5-NEXT: store ptr [[B]], ptr [[TMP12]], align 85161// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 25162// CHECK5-NEXT: store ptr null, ptr [[TMP13]], align 85163// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05164// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 05165// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 05166// CHECK5-NEXT: store i32 3, ptr [[TMP16]], align 45167// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 15168// CHECK5-NEXT: store i32 3, ptr [[TMP17]], align 45169// CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 25170// CHECK5-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 85171// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 35172// CHECK5-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 85173// CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 45174// CHECK5-NEXT: store ptr @.offload_sizes.11, ptr [[TMP20]], align 85175// CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 55176// CHECK5-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP21]], align 85177// CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 65178// CHECK5-NEXT: store ptr null, ptr [[TMP22]], align 85179// CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 75180// CHECK5-NEXT: store ptr null, ptr [[TMP23]], align 85181// CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 85182// CHECK5-NEXT: store i64 10, ptr [[TMP24]], align 85183// CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 95184// CHECK5-NEXT: store i64 0, ptr [[TMP25]], align 85185// CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 105186// CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 45187// CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 115188// CHECK5-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 45189// CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 125190// CHECK5-NEXT: store i32 0, ptr [[TMP28]], align 45191// CHECK5-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.region_id, ptr [[KERNEL_ARGS]])5192// CHECK5-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 05193// CHECK5-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]5194// CHECK5: omp_offload.failed:5195// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]5196// CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]5197// CHECK5: omp_offload.cont:5198// CHECK5-NEXT: br label [[OMP_IF_END:%.*]]5199// CHECK5: omp_if.else:5200// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]5201// CHECK5-NEXT: br label [[OMP_IF_END]]5202// CHECK5: omp_if.end:5203// CHECK5-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 45204// CHECK5-NEXT: ret i32 [[TMP31]]5205//5206//5207// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2155208// CHECK5-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {5209// CHECK5-NEXT: entry:5210// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 85211// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 85212// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 85213// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 85214// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 85215// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 85216// CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 85217// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 85218// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 85219// CHECK5-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 85220// CHECK5-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 85221// CHECK5-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 85222// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 85223// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 85224// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 85225// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 85226// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 85227// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 85228// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 45229// CHECK5-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 45230// CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 85231// CHECK5-NEXT: [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 15232// CHECK5-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP6]] to i15233// CHECK5-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i85234// CHECK5-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 15235// CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 85236// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]], i64 [[TMP7]])5237// CHECK5-NEXT: ret void5238//5239//5240// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined5241// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {5242// CHECK5-NEXT: entry:5243// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 85244// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 85245// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 85246// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 85247// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 85248// CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 85249// CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 85250// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 85251// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 45252// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 45253// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 45254// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 45255// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 45256// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 45257// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 45258// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 85259// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 85260// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 85261// CHECK5-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 85262// CHECK5-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 85263// CHECK5-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 85264// CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 85265// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 85266// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 85267// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 85268// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 85269// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 85270// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 45271// CHECK5-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 45272// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 45273// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 45274// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 85275// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 45276// CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)5277// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45278// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 95279// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]5280// CHECK5: cond.true:5281// CHECK5-NEXT: br label [[COND_END:%.*]]5282// CHECK5: cond.false:5283// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45284// CHECK5-NEXT: br label [[COND_END]]5285// CHECK5: cond.end:5286// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]5287// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 45288// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 45289// CHECK5-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 45290// CHECK5-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 15291// CHECK5-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP9]] to i15292// CHECK5-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]5293// CHECK5: omp_if.then:5294// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]5295// CHECK5: omp.inner.for.cond:5296// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39:![0-9]+]]5297// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]]5298// CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]5299// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]5300// CHECK5: omp.inner.for.body:5301// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]5302// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 15303// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]5304// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]]5305// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]]5306// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double5307// CHECK5-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+005308// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 05309// CHECK5-NEXT: store double [[ADD4]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP39]]5310// CHECK5-NEXT: [[A5:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 05311// CHECK5-NEXT: [[TMP14:%.*]] = load double, ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP39]]5312// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+005313// CHECK5-NEXT: store double [[INC]], ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP39]]5314// CHECK5-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i165315// CHECK5-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]]5316// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP15]]5317// CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 15318// CHECK5-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP39]]5319// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]5320// CHECK5: omp.body.continue:5321// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]5322// CHECK5: omp.inner.for.inc:5323// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]5324// CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], 15325// CHECK5-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]5326// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]5327// CHECK5: omp.inner.for.end:5328// CHECK5-NEXT: br label [[OMP_IF_END:%.*]]5329// CHECK5: omp_if.else:5330// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]5331// CHECK5: omp.inner.for.cond9:5332// CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45333// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45334// CHECK5-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]5335// CHECK5-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]]5336// CHECK5: omp.inner.for.body11:5337// CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45338// CHECK5-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP19]], 15339// CHECK5-NEXT: [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]5340// CHECK5-NEXT: store i32 [[ADD13]], ptr [[I]], align 45341// CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[B_ADDR]], align 45342// CHECK5-NEXT: [[CONV14:%.*]] = sitofp i32 [[TMP20]] to double5343// CHECK5-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+005344// CHECK5-NEXT: [[A16:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 05345// CHECK5-NEXT: store double [[ADD15]], ptr [[A16]], align 85346// CHECK5-NEXT: [[A17:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 05347// CHECK5-NEXT: [[TMP21:%.*]] = load double, ptr [[A17]], align 85348// CHECK5-NEXT: [[INC18:%.*]] = fadd double [[TMP21]], 1.000000e+005349// CHECK5-NEXT: store double [[INC18]], ptr [[A17]], align 85350// CHECK5-NEXT: [[CONV19:%.*]] = fptosi double [[INC18]] to i165351// CHECK5-NEXT: [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]5352// CHECK5-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP22]]5353// CHECK5-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX20]], i64 15354// CHECK5-NEXT: store i16 [[CONV19]], ptr [[ARRAYIDX21]], align 25355// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE22:%.*]]5356// CHECK5: omp.body.continue22:5357// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC23:%.*]]5358// CHECK5: omp.inner.for.inc23:5359// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 45360// CHECK5-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP23]], 15361// CHECK5-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 45362// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP42:![0-9]+]]5363// CHECK5: omp.inner.for.end25:5364// CHECK5-NEXT: br label [[OMP_IF_END]]5365// CHECK5: omp_if.end:5366// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]5367// CHECK5: omp.loop.exit:5368// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])5369// CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 45370// CHECK5-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 05371// CHECK5-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]5372// CHECK5: .omp.final.then:5373// CHECK5-NEXT: store i32 10, ptr [[I]], align 45374// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]5375// CHECK5: .omp.final.done:5376// CHECK5-NEXT: ret void5377//5378//5379// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1975380// CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {5381// CHECK5-NEXT: entry:5382// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 85383// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 85384// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 85385// CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 85386// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 85387// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 85388// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 85389// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 85390// CHECK5-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 85391// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 85392// CHECK5-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 85393// CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 85394// CHECK5-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 85395// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 85396// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 85397// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 45398// CHECK5-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 45399// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 85400// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 45401// CHECK5-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 45402// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 85403// CHECK5-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 25404// CHECK5-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 25405// CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[AA_CASTED]], align 85406// CHECK5-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 15407// CHECK5-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 15408// CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[AAA_CASTED]], align 85409// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], ptr [[TMP0]])5410// CHECK5-NEXT: ret void5411//5412//5413// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined5414// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {5415// CHECK5-NEXT: entry:5416// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 85417// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 85418// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 85419// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 85420// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 85421// CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 85422// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 85423// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 45424// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 45425// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 45426// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 45427// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 45428// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 45429// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 45430// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 45431// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 45432// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 45433// CHECK5-NEXT: [[I5:%.*]] = alloca i32, align 45434// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 85435// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 85436// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 85437// CHECK5-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 85438// CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 85439// CHECK5-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 85440// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 85441// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 85442// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 45443// CHECK5-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 45444// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 45445// CHECK5-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 45446// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 45447// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 45448// CHECK5-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]5449// CHECK5-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 15450// CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 15451// CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 15452// CHECK5-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 15453// CHECK5-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 45454// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 45455// CHECK5-NEXT: store i32 [[TMP5]], ptr [[I]], align 45456// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 45457// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 45458// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]5459// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]5460// CHECK5: omp.precond.then:5461// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 45462// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 45463// CHECK5-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 45464// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 45465// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 45466// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 85467// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 45468// CHECK5-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)5469// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45470// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 45471// CHECK5-NEXT: [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]5472// CHECK5-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]5473// CHECK5: cond.true:5474// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 45475// CHECK5-NEXT: br label [[COND_END:%.*]]5476// CHECK5: cond.false:5477// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45478// CHECK5-NEXT: br label [[COND_END]]5479// CHECK5: cond.end:5480// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]5481// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 45482// CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 45483// CHECK5-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 45484// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]5485// CHECK5: omp.inner.for.cond:5486// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44:![0-9]+]]5487// CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP44]]5488// CHECK5-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 15489// CHECK5-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]5490// CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]5491// CHECK5: omp.inner.for.body:5492// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP44]]5493// CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]5494// CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 15495// CHECK5-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]5496// CHECK5-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP44]]5497// CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]]5498// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 15499// CHECK5-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]]5500// CHECK5-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP44]]5501// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i325502// CHECK5-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 15503// CHECK5-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i165504// CHECK5-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP44]]5505// CHECK5-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP44]]5506// CHECK5-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i325507// CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 15508// CHECK5-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i85509// CHECK5-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP44]]5510// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 25511// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]]5512// CHECK5-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 15513// CHECK5-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]]5514// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]5515// CHECK5: omp.body.continue:5516// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]5517// CHECK5: omp.inner.for.inc:5518// CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]5519// CHECK5-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 15520// CHECK5-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]5521// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]]5522// CHECK5: omp.inner.for.end:5523// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]5524// CHECK5: omp.loop.exit:5525// CHECK5-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 85526// CHECK5-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 45527// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])5528// CHECK5-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 45529// CHECK5-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 05530// CHECK5-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]5531// CHECK5: .omp.final.then:5532// CHECK5-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 45533// CHECK5-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 45534// CHECK5-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 45535// CHECK5-NEXT: [[SUB18:%.*]] = sub i32 [[TMP30]], [[TMP31]]5536// CHECK5-NEXT: [[SUB19:%.*]] = sub i32 [[SUB18]], 15537// CHECK5-NEXT: [[ADD20:%.*]] = add i32 [[SUB19]], 15538// CHECK5-NEXT: [[DIV21:%.*]] = udiv i32 [[ADD20]], 15539// CHECK5-NEXT: [[MUL22:%.*]] = mul i32 [[DIV21]], 15540// CHECK5-NEXT: [[ADD23:%.*]] = add i32 [[TMP29]], [[MUL22]]5541// CHECK5-NEXT: store i32 [[ADD23]], ptr [[I5]], align 45542// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]5543// CHECK5: .omp.final.done:5544// CHECK5-NEXT: br label [[OMP_PRECOND_END]]5545// CHECK5: omp.precond.end:5546// CHECK5-NEXT: ret void5547//5548//5549// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1805550// CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {5551// CHECK5-NEXT: entry:5552// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 85553// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 85554// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 85555// CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 85556// CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 85557// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 85558// CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 85559// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 85560// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 85561// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 45562// CHECK5-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 45563// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 85564// CHECK5-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 25565// CHECK5-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 25566// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 85567// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])5568// CHECK5-NEXT: ret void5569//5570//5571// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined5572// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {5573// CHECK5-NEXT: entry:5574// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 85575// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 85576// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 85577// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 85578// CHECK5-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 85579// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 45580// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 45581// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 45582// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 45583// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 45584// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 45585// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 45586// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 85587// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 85588// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 85589// CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 85590// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 85591// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 85592// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 45593// CHECK5-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 45594// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 45595// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 45596// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 85597// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 45598// CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)5599// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45600// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 95601// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]5602// CHECK5: cond.true:5603// CHECK5-NEXT: br label [[COND_END:%.*]]5604// CHECK5: cond.false:5605// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 45606// CHECK5-NEXT: br label [[COND_END]]5607// CHECK5: cond.end:5608// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]5609// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 45610// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 45611// CHECK5-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 45612// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]5613// CHECK5: omp.inner.for.cond:5614// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP47:![0-9]+]]5615// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP47]]5616// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]5617// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]5618// CHECK5: omp.inner.for.body:5619// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP47]]5620// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 15621// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]5622// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP47]]5623// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP47]]5624// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 15625// CHECK5-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP47]]5626// CHECK5-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP47]]5627// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i325628// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 15629// CHECK5-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i165630// CHECK5-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP47]]5631// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 25632// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP47]]5633// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 15634// CHECK5-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP47]]5635// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]5636// CHECK5: omp.body.continue:5637// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]5638// CHECK5: omp.inner.for.inc:5639// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP47]]5640// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 15641// CHECK5-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP47]]5642// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP48:![0-9]+]]5643// CHECK5: omp.inner.for.end:5644// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]5645// CHECK5: omp.loop.exit:5646// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])5647// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 45648// CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 05649// CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]5650// CHECK5: .omp.final.then:5651// CHECK5-NEXT: store i32 10, ptr [[I]], align 45652// CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]5653// CHECK5: .omp.final.done:5654// CHECK5-NEXT: ret void5655//5656//5657// CHECK7-LABEL: define {{[^@]+}}@_Z3fooi5658// CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {5659// CHECK7-NEXT: entry:5660// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 45661// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 45662// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 25663// CHECK7-NEXT: [[B:%.*]] = alloca [10 x float], align 45664// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 45665// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 45666// CHECK7-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 85667// CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 45668// CHECK7-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 45669// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 45670// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 45671// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 45672// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 45673// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 45674// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 45675// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 45676// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 45677// CHECK7-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 45678// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 45679// CHECK7-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 45680// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x ptr], align 45681// CHECK7-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x ptr], align 45682// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x ptr], align 45683// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 45684// CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 85685// CHECK7-NEXT: [[A_CASTED8:%.*]] = alloca i32, align 45686// CHECK7-NEXT: [[AA_CASTED9:%.*]] = alloca i32, align 45687// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x ptr], align 45688// CHECK7-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x ptr], align 45689// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x ptr], align 45690// CHECK7-NEXT: [[_TMP13:%.*]] = alloca i32, align 45691// CHECK7-NEXT: [[KERNEL_ARGS14:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 85692// CHECK7-NEXT: [[A_CASTED17:%.*]] = alloca i32, align 45693// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x ptr], align 45694// CHECK7-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x ptr], align 45695// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x ptr], align 45696// CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 45697// CHECK7-NEXT: [[_TMP23:%.*]] = alloca i32, align 45698// CHECK7-NEXT: [[KERNEL_ARGS24:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 85699// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])5700// CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 45701// CHECK7-NEXT: store i32 0, ptr [[A]], align 45702// CHECK7-NEXT: store i16 0, ptr [[AA]], align 25703// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 45704// CHECK7-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()5705// CHECK7-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 45706// CHECK7-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 45707// CHECK7-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 45708// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 45709// CHECK7-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]5710// CHECK7-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 85711// CHECK7-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 45712// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 45713// CHECK7-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 45714// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 45715// CHECK7-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_2]], align 45716// CHECK7-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 25717// CHECK7-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 25718// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 45719// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 45720// CHECK7-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 45721// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 45722// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 45723// CHECK7-NEXT: store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED3]], align 45724// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED3]], align 45725// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05726// CHECK7-NEXT: store i32 [[TMP8]], ptr [[TMP13]], align 45727// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 05728// CHECK7-NEXT: store i32 [[TMP8]], ptr [[TMP14]], align 45729// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 05730// CHECK7-NEXT: store ptr null, ptr [[TMP15]], align 45731// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 15732// CHECK7-NEXT: store i32 [[TMP10]], ptr [[TMP16]], align 45733// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 15734// CHECK7-NEXT: store i32 [[TMP10]], ptr [[TMP17]], align 45735// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 15736// CHECK7-NEXT: store ptr null, ptr [[TMP18]], align 45737// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 25738// CHECK7-NEXT: store i32 [[TMP12]], ptr [[TMP19]], align 45739// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 25740// CHECK7-NEXT: store i32 [[TMP12]], ptr [[TMP20]], align 45741// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 25742// CHECK7-NEXT: store ptr null, ptr [[TMP21]], align 45743// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 05744// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 05745// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 05746// CHECK7-NEXT: [[TMP25:%.*]] = load i16, ptr [[AA]], align 25747// CHECK7-NEXT: store i16 [[TMP25]], ptr [[TMP24]], align 45748// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 15749// CHECK7-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 45750// CHECK7-NEXT: store i32 [[TMP27]], ptr [[TMP26]], align 45751// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 25752// CHECK7-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 45753// CHECK7-NEXT: store i32 [[TMP29]], ptr [[TMP28]], align 45754// CHECK7-NEXT: [[TMP30:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, ptr @.omp_task_entry., i64 -1)5755// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP30]], i32 0, i32 05756// CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP31]], i32 0, i32 05757// CHECK7-NEXT: [[TMP33:%.*]] = load ptr, ptr [[TMP32]], align 45758// CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP33]], ptr align 4 [[AGG_CAPTURED]], i32 12, i1 false)5759// CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP30]], i32 0, i32 15760// CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP34]], i32 0, i32 05761// CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP35]], ptr align 4 @.offload_sizes, i32 24, i1 false)5762// CHECK7-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 15763// CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP36]], ptr align 4 [[TMP22]], i32 12, i1 false)5764// CHECK7-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 25765// CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP37]], ptr align 4 [[TMP23]], i32 12, i1 false)5766// CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 35767// CHECK7-NEXT: [[TMP39:%.*]] = load i16, ptr [[AA]], align 25768// CHECK7-NEXT: store i16 [[TMP39]], ptr [[TMP38]], align 45769// CHECK7-NEXT: [[TMP40:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP30]])5770// CHECK7-NEXT: [[TMP41:%.*]] = load i32, ptr [[A]], align 45771// CHECK7-NEXT: store i32 [[TMP41]], ptr [[A_CASTED]], align 45772// CHECK7-NEXT: [[TMP42:%.*]] = load i32, ptr [[A_CASTED]], align 45773// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102(i32 [[TMP42]]) #[[ATTR3:[0-9]+]]5774// CHECK7-NEXT: [[TMP43:%.*]] = load i16, ptr [[AA]], align 25775// CHECK7-NEXT: store i16 [[TMP43]], ptr [[AA_CASTED4]], align 25776// CHECK7-NEXT: [[TMP44:%.*]] = load i32, ptr [[AA_CASTED4]], align 45777// CHECK7-NEXT: [[TMP45:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 05778// CHECK7-NEXT: store i32 [[TMP44]], ptr [[TMP45]], align 45779// CHECK7-NEXT: [[TMP46:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 05780// CHECK7-NEXT: store i32 [[TMP44]], ptr [[TMP46]], align 45781// CHECK7-NEXT: [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 05782// CHECK7-NEXT: store ptr null, ptr [[TMP47]], align 45783// CHECK7-NEXT: [[TMP48:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 05784// CHECK7-NEXT: [[TMP49:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 05785// CHECK7-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 05786// CHECK7-NEXT: store i32 3, ptr [[TMP50]], align 45787// CHECK7-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 15788// CHECK7-NEXT: store i32 1, ptr [[TMP51]], align 45789// CHECK7-NEXT: [[TMP52:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 25790// CHECK7-NEXT: store ptr [[TMP48]], ptr [[TMP52]], align 45791// CHECK7-NEXT: [[TMP53:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 35792// CHECK7-NEXT: store ptr [[TMP49]], ptr [[TMP53]], align 45793// CHECK7-NEXT: [[TMP54:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 45794// CHECK7-NEXT: store ptr @.offload_sizes.1, ptr [[TMP54]], align 45795// CHECK7-NEXT: [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 55796// CHECK7-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP55]], align 45797// CHECK7-NEXT: [[TMP56:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 65798// CHECK7-NEXT: store ptr null, ptr [[TMP56]], align 45799// CHECK7-NEXT: [[TMP57:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 75800// CHECK7-NEXT: store ptr null, ptr [[TMP57]], align 45801// CHECK7-NEXT: [[TMP58:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 85802// CHECK7-NEXT: store i64 10, ptr [[TMP58]], align 85803// CHECK7-NEXT: [[TMP59:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 95804// CHECK7-NEXT: store i64 0, ptr [[TMP59]], align 85805// CHECK7-NEXT: [[TMP60:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 105806// CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP60]], align 45807// CHECK7-NEXT: [[TMP61:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 115808// CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP61]], align 45809// CHECK7-NEXT: [[TMP62:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 125810// CHECK7-NEXT: store i32 0, ptr [[TMP62]], align 45811// CHECK7-NEXT: [[TMP63:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, ptr [[KERNEL_ARGS]])5812// CHECK7-NEXT: [[TMP64:%.*]] = icmp ne i32 [[TMP63]], 05813// CHECK7-NEXT: br i1 [[TMP64]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]5814// CHECK7: omp_offload.failed:5815// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP44]]) #[[ATTR3]]5816// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]5817// CHECK7: omp_offload.cont:5818// CHECK7-NEXT: [[TMP65:%.*]] = load i32, ptr [[A]], align 45819// CHECK7-NEXT: store i32 [[TMP65]], ptr [[A_CASTED8]], align 45820// CHECK7-NEXT: [[TMP66:%.*]] = load i32, ptr [[A_CASTED8]], align 45821// CHECK7-NEXT: [[TMP67:%.*]] = load i16, ptr [[AA]], align 25822// CHECK7-NEXT: store i16 [[TMP67]], ptr [[AA_CASTED9]], align 25823// CHECK7-NEXT: [[TMP68:%.*]] = load i32, ptr [[AA_CASTED9]], align 45824// CHECK7-NEXT: [[TMP69:%.*]] = load i32, ptr [[N_ADDR]], align 45825// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP69]], 105826// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]5827// CHECK7: omp_if.then:5828// CHECK7-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 05829// CHECK7-NEXT: store i32 [[TMP66]], ptr [[TMP70]], align 45830// CHECK7-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 05831// CHECK7-NEXT: store i32 [[TMP66]], ptr [[TMP71]], align 45832// CHECK7-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 05833// CHECK7-NEXT: store ptr null, ptr [[TMP72]], align 45834// CHECK7-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 15835// CHECK7-NEXT: store i32 [[TMP68]], ptr [[TMP73]], align 45836// CHECK7-NEXT: [[TMP74:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 15837// CHECK7-NEXT: store i32 [[TMP68]], ptr [[TMP74]], align 45838// CHECK7-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 15839// CHECK7-NEXT: store ptr null, ptr [[TMP75]], align 45840// CHECK7-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 05841// CHECK7-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 05842// CHECK7-NEXT: [[TMP78:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 05843// CHECK7-NEXT: store i32 3, ptr [[TMP78]], align 45844// CHECK7-NEXT: [[TMP79:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 15845// CHECK7-NEXT: store i32 2, ptr [[TMP79]], align 45846// CHECK7-NEXT: [[TMP80:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 25847// CHECK7-NEXT: store ptr [[TMP76]], ptr [[TMP80]], align 45848// CHECK7-NEXT: [[TMP81:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 35849// CHECK7-NEXT: store ptr [[TMP77]], ptr [[TMP81]], align 45850// CHECK7-NEXT: [[TMP82:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 45851// CHECK7-NEXT: store ptr @.offload_sizes.3, ptr [[TMP82]], align 45852// CHECK7-NEXT: [[TMP83:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 55853// CHECK7-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP83]], align 45854// CHECK7-NEXT: [[TMP84:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 65855// CHECK7-NEXT: store ptr null, ptr [[TMP84]], align 45856// CHECK7-NEXT: [[TMP85:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 75857// CHECK7-NEXT: store ptr null, ptr [[TMP85]], align 45858// CHECK7-NEXT: [[TMP86:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 85859// CHECK7-NEXT: store i64 10, ptr [[TMP86]], align 85860// CHECK7-NEXT: [[TMP87:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 95861// CHECK7-NEXT: store i64 0, ptr [[TMP87]], align 85862// CHECK7-NEXT: [[TMP88:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 105863// CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP88]], align 45864// CHECK7-NEXT: [[TMP89:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 115865// CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP89]], align 45866// CHECK7-NEXT: [[TMP90:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 125867// CHECK7-NEXT: store i32 0, ptr [[TMP90]], align 45868// CHECK7-NEXT: [[TMP91:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, ptr [[KERNEL_ARGS14]])5869// CHECK7-NEXT: [[TMP92:%.*]] = icmp ne i32 [[TMP91]], 05870// CHECK7-NEXT: br i1 [[TMP92]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]5871// CHECK7: omp_offload.failed15:5872// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR3]]5873// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT16]]5874// CHECK7: omp_offload.cont16:5875// CHECK7-NEXT: br label [[OMP_IF_END:%.*]]5876// CHECK7: omp_if.else:5877// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR3]]5878// CHECK7-NEXT: br label [[OMP_IF_END]]5879// CHECK7: omp_if.end:5880// CHECK7-NEXT: [[TMP93:%.*]] = load i32, ptr [[A]], align 45881// CHECK7-NEXT: store i32 [[TMP93]], ptr [[A_CASTED17]], align 45882// CHECK7-NEXT: [[TMP94:%.*]] = load i32, ptr [[A_CASTED17]], align 45883// CHECK7-NEXT: [[TMP95:%.*]] = load i32, ptr [[N_ADDR]], align 45884// CHECK7-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP95]], 205885// CHECK7-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE27:%.*]]5886// CHECK7: omp_if.then19:5887// CHECK7-NEXT: [[TMP96:%.*]] = mul nuw i32 [[TMP1]], 45888// CHECK7-NEXT: [[TMP97:%.*]] = sext i32 [[TMP96]] to i645889// CHECK7-NEXT: [[TMP98:%.*]] = mul nuw i32 5, [[TMP3]]5890// CHECK7-NEXT: [[TMP99:%.*]] = mul nuw i32 [[TMP98]], 85891// CHECK7-NEXT: [[TMP100:%.*]] = sext i32 [[TMP99]] to i645892// CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.5, i32 72, i1 false)5893// CHECK7-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 05894// CHECK7-NEXT: store i32 [[TMP94]], ptr [[TMP101]], align 45895// CHECK7-NEXT: [[TMP102:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 05896// CHECK7-NEXT: store i32 [[TMP94]], ptr [[TMP102]], align 45897// CHECK7-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 05898// CHECK7-NEXT: store ptr null, ptr [[TMP103]], align 45899// CHECK7-NEXT: [[TMP104:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 15900// CHECK7-NEXT: store ptr [[B]], ptr [[TMP104]], align 45901// CHECK7-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 15902// CHECK7-NEXT: store ptr [[B]], ptr [[TMP105]], align 45903// CHECK7-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 15904// CHECK7-NEXT: store ptr null, ptr [[TMP106]], align 45905// CHECK7-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 25906// CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP107]], align 45907// CHECK7-NEXT: [[TMP108:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 25908// CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP108]], align 45909// CHECK7-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 25910// CHECK7-NEXT: store ptr null, ptr [[TMP109]], align 45911// CHECK7-NEXT: [[TMP110:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 35912// CHECK7-NEXT: store ptr [[VLA]], ptr [[TMP110]], align 45913// CHECK7-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 35914// CHECK7-NEXT: store ptr [[VLA]], ptr [[TMP111]], align 45915// CHECK7-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 35916// CHECK7-NEXT: store i64 [[TMP97]], ptr [[TMP112]], align 45917// CHECK7-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 35918// CHECK7-NEXT: store ptr null, ptr [[TMP113]], align 45919// CHECK7-NEXT: [[TMP114:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 45920// CHECK7-NEXT: store ptr [[C]], ptr [[TMP114]], align 45921// CHECK7-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 45922// CHECK7-NEXT: store ptr [[C]], ptr [[TMP115]], align 45923// CHECK7-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 45924// CHECK7-NEXT: store ptr null, ptr [[TMP116]], align 45925// CHECK7-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 55926// CHECK7-NEXT: store i32 5, ptr [[TMP117]], align 45927// CHECK7-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 55928// CHECK7-NEXT: store i32 5, ptr [[TMP118]], align 45929// CHECK7-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 55930// CHECK7-NEXT: store ptr null, ptr [[TMP119]], align 45931// CHECK7-NEXT: [[TMP120:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 65932// CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP120]], align 45933// CHECK7-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 65934// CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP121]], align 45935// CHECK7-NEXT: [[TMP122:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 65936// CHECK7-NEXT: store ptr null, ptr [[TMP122]], align 45937// CHECK7-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 75938// CHECK7-NEXT: store ptr [[VLA1]], ptr [[TMP123]], align 45939// CHECK7-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 75940// CHECK7-NEXT: store ptr [[VLA1]], ptr [[TMP124]], align 45941// CHECK7-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 75942// CHECK7-NEXT: store i64 [[TMP100]], ptr [[TMP125]], align 45943// CHECK7-NEXT: [[TMP126:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 75944// CHECK7-NEXT: store ptr null, ptr [[TMP126]], align 45945// CHECK7-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 85946// CHECK7-NEXT: store ptr [[D]], ptr [[TMP127]], align 45947// CHECK7-NEXT: [[TMP128:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 85948// CHECK7-NEXT: store ptr [[D]], ptr [[TMP128]], align 45949// CHECK7-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 85950// CHECK7-NEXT: store ptr null, ptr [[TMP129]], align 45951// CHECK7-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 05952// CHECK7-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 05953// CHECK7-NEXT: [[TMP132:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 05954// CHECK7-NEXT: [[TMP133:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 05955// CHECK7-NEXT: store i32 3, ptr [[TMP133]], align 45956// CHECK7-NEXT: [[TMP134:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 15957// CHECK7-NEXT: store i32 9, ptr [[TMP134]], align 45958// CHECK7-NEXT: [[TMP135:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 25959// CHECK7-NEXT: store ptr [[TMP130]], ptr [[TMP135]], align 45960// CHECK7-NEXT: [[TMP136:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 35961// CHECK7-NEXT: store ptr [[TMP131]], ptr [[TMP136]], align 45962// CHECK7-NEXT: [[TMP137:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 45963// CHECK7-NEXT: store ptr [[TMP132]], ptr [[TMP137]], align 45964// CHECK7-NEXT: [[TMP138:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 55965// CHECK7-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP138]], align 45966// CHECK7-NEXT: [[TMP139:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 65967// CHECK7-NEXT: store ptr null, ptr [[TMP139]], align 45968// CHECK7-NEXT: [[TMP140:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 75969// CHECK7-NEXT: store ptr null, ptr [[TMP140]], align 45970// CHECK7-NEXT: [[TMP141:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 85971// CHECK7-NEXT: store i64 10, ptr [[TMP141]], align 85972// CHECK7-NEXT: [[TMP142:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 95973// CHECK7-NEXT: store i64 0, ptr [[TMP142]], align 85974// CHECK7-NEXT: [[TMP143:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 105975// CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP143]], align 45976// CHECK7-NEXT: [[TMP144:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 115977// CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP144]], align 45978// CHECK7-NEXT: [[TMP145:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 125979// CHECK7-NEXT: store i32 0, ptr [[TMP145]], align 45980// CHECK7-NEXT: [[TMP146:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, ptr [[KERNEL_ARGS24]])5981// CHECK7-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 05982// CHECK7-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]]5983// CHECK7: omp_offload.failed25:5984// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP94]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]5985// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT26]]5986// CHECK7: omp_offload.cont26:5987// CHECK7-NEXT: br label [[OMP_IF_END28:%.*]]5988// CHECK7: omp_if.else27:5989// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP94]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]5990// CHECK7-NEXT: br label [[OMP_IF_END28]]5991// CHECK7: omp_if.end28:5992// CHECK7-NEXT: [[TMP148:%.*]] = load i32, ptr [[A]], align 45993// CHECK7-NEXT: [[TMP149:%.*]] = load ptr, ptr [[SAVED_STACK]], align 45994// CHECK7-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP149]])5995// CHECK7-NEXT: ret i32 [[TMP148]]5996//5997//5998// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l975999// CHECK7-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {6000// CHECK7-NEXT: entry:6001// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 46002// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 46003// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 46004// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 46005// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])6006// CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 46007// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 46008// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 46009// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 46010// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 46011// CHECK7-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])6012// CHECK7-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 26013// CHECK7-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 26014// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 46015// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i32 [[TMP4]])6016// CHECK7-NEXT: ret void6017//6018//6019// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined6020// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {6021// CHECK7-NEXT: entry:6022// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 46023// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 46024// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 46025// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 46026// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 46027// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 46028// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 46029// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 46030// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 46031// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 46032// CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 46033// CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 46034// CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 46035// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 46036// CHECK7-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 46037// CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 46038// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 46039// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 46040// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 46041// CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)6042// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46043// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 96044// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]6045// CHECK7: cond.true:6046// CHECK7-NEXT: br label [[COND_END:%.*]]6047// CHECK7: cond.false:6048// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46049// CHECK7-NEXT: br label [[COND_END]]6050// CHECK7: cond.end:6051// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]6052// CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 46053// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 46054// CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 46055// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]6056// CHECK7: omp.inner.for.cond:6057// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]6058// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]]6059// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]6060// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]6061// CHECK7: omp.inner.for.body:6062// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]6063// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 16064// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]6065// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]6066// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]6067// CHECK7: omp.body.continue:6068// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]6069// CHECK7: omp.inner.for.inc:6070// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]6071// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 16072// CHECK7-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]6073// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]6074// CHECK7: omp.inner.for.end:6075// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]6076// CHECK7: omp.loop.exit:6077// CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])6078// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 46079// CHECK7-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 06080// CHECK7-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]6081// CHECK7: .omp.final.then:6082// CHECK7-NEXT: store i32 10, ptr [[I]], align 46083// CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]6084// CHECK7: .omp.final.done:6085// CHECK7-NEXT: ret void6086//6087//6088// CHECK7-LABEL: define {{[^@]+}}@.omp_task_privates_map.6089// CHECK7-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {6090// CHECK7-NEXT: entry:6091// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 46092// CHECK7-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 46093// CHECK7-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 46094// CHECK7-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 46095// CHECK7-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 46096// CHECK7-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 46097// CHECK7-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 46098// CHECK7-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 46099// CHECK7-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 46100// CHECK7-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 46101// CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 46102// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 06103// CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR4]], align 46104// CHECK7-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 46105// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 16106// CHECK7-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 46107// CHECK7-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 46108// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 26109// CHECK7-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 46110// CHECK7-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 46111// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 36112// CHECK7-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 46113// CHECK7-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 46114// CHECK7-NEXT: ret void6115//6116//6117// CHECK7-LABEL: define {{[^@]+}}@.omp_task_entry.6118// CHECK7-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {6119// CHECK7-NEXT: entry:6120// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 46121// CHECK7-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 46122// CHECK7-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 46123// CHECK7-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 46124// CHECK7-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 46125// CHECK7-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 46126// CHECK7-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 46127// CHECK7-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 46128// CHECK7-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 46129// CHECK7-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 46130// CHECK7-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 86131// CHECK7-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 46132// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 46133// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 46134// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i32, align 46135// CHECK7-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 46136// CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 46137// CHECK7-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 46138// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 46139// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 46140// CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 06141// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 26142// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 06143// CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 46144// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 16145// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])6146// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])6147// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])6148// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])6149// CHECK7-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META27:![0-9]+]]6150// CHECK7-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias [[META27]]6151// CHECK7-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META27]]6152// CHECK7-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META27]]6153// CHECK7-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias [[META27]]6154// CHECK7-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META27]]6155// CHECK7-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META27]]6156// CHECK7-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META27]]6157// CHECK7-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META27]]6158// CHECK7-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]6159// CHECK7-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias [[META27]]6160// CHECK7-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias [[META27]]6161// CHECK7-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias [[META27]]6162// CHECK7-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias [[META27]]6163// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 16164// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 26165// CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 46166// CHECK7-NEXT: [[TMP19:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP18]], 06167// CHECK7-NEXT: store i32 3, ptr [[KERNEL_ARGS_I]], align 4, !noalias [[META27]]6168// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 16169// CHECK7-NEXT: store i32 3, ptr [[TMP20]], align 4, !noalias [[META27]]6170// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 26171// CHECK7-NEXT: store ptr [[TMP13]], ptr [[TMP21]], align 4, !noalias [[META27]]6172// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 36173// CHECK7-NEXT: store ptr [[TMP14]], ptr [[TMP22]], align 4, !noalias [[META27]]6174// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 46175// CHECK7-NEXT: store ptr [[TMP15]], ptr [[TMP23]], align 4, !noalias [[META27]]6176// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 56177// CHECK7-NEXT: store ptr @.offload_maptypes, ptr [[TMP24]], align 4, !noalias [[META27]]6178// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 66179// CHECK7-NEXT: store ptr null, ptr [[TMP25]], align 4, !noalias [[META27]]6180// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 76181// CHECK7-NEXT: store ptr null, ptr [[TMP26]], align 4, !noalias [[META27]]6182// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 86183// CHECK7-NEXT: store i64 10, ptr [[TMP27]], align 8, !noalias [[META27]]6184// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 96185// CHECK7-NEXT: store i64 1, ptr [[TMP28]], align 8, !noalias [[META27]]6186// CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 106187// CHECK7-NEXT: store [3 x i32] [[TMP19]], ptr [[TMP29]], align 4, !noalias [[META27]]6188// CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 116189// CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP30]], align 4, !noalias [[META27]]6190// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 126191// CHECK7-NEXT: store i32 0, ptr [[TMP31]], align 4, !noalias [[META27]]6192// CHECK7-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 [[TMP18]], i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, ptr [[KERNEL_ARGS_I]])6193// CHECK7-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 06194// CHECK7-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]6195// CHECK7: omp_offload.failed.i:6196// CHECK7-NEXT: [[TMP34:%.*]] = load i16, ptr [[TMP12]], align 26197// CHECK7-NEXT: store i16 [[TMP34]], ptr [[AA_CASTED_I]], align 2, !noalias [[META27]]6198// CHECK7-NEXT: [[TMP35:%.*]] = load i32, ptr [[AA_CASTED_I]], align 4, !noalias [[META27]]6199// CHECK7-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP16]], align 46200// CHECK7-NEXT: store i32 [[TMP36]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias [[META27]]6201// CHECK7-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias [[META27]]6202// CHECK7-NEXT: [[TMP38:%.*]] = load i32, ptr [[TMP17]], align 46203// CHECK7-NEXT: store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias [[META27]]6204// CHECK7-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias [[META27]]6205// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i32 [[TMP35]], i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR3]]6206// CHECK7-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]6207// CHECK7: .omp_outlined..exit:6208// CHECK7-NEXT: ret i32 06209//6210//6211// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1026212// CHECK7-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] {6213// CHECK7-NEXT: entry:6214// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 46215// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 46216// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 46217// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 46218// CHECK7-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 46219// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 46220// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102.omp_outlined, i32 [[TMP1]])6221// CHECK7-NEXT: ret void6222//6223//6224// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102.omp_outlined6225// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {6226// CHECK7-NEXT: entry:6227// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 46228// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 46229// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 46230// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 46231// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 46232// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 46233// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 46234// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 46235// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 46236// CHECK7-NEXT: [[A1:%.*]] = alloca i32, align 46237// CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 46238// CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 46239// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 46240// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 46241// CHECK7-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 46242// CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 46243// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 46244// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 46245// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 46246// CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)6247// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46248// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 96249// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]6250// CHECK7: cond.true:6251// CHECK7-NEXT: br label [[COND_END:%.*]]6252// CHECK7: cond.false:6253// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46254// CHECK7-NEXT: br label [[COND_END]]6255// CHECK7: cond.end:6256// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]6257// CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 46258// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 46259// CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 46260// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]6261// CHECK7: omp.inner.for.cond:6262// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 46263// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46264// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]6265// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]6266// CHECK7: omp.inner.for.body:6267// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 46268// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 16269// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]6270// CHECK7-NEXT: store i32 [[ADD]], ptr [[A1]], align 4, !nontemporal [[META28:![0-9]+]]6271// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 4, !nontemporal [[META28]]6272// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 16273// CHECK7-NEXT: store i32 [[ADD3]], ptr [[A1]], align 4, !nontemporal [[META28]]6274// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]6275// CHECK7: omp.body.continue:6276// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]6277// CHECK7: omp.inner.for.inc:6278// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 46279// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 16280// CHECK7-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 46281// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]6282// CHECK7: omp.inner.for.end:6283// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]6284// CHECK7: omp.loop.exit:6285// CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])6286// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 46287// CHECK7-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 06288// CHECK7-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]6289// CHECK7: .omp.final.then:6290// CHECK7-NEXT: store i32 10, ptr [[A_ADDR]], align 46291// CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]6292// CHECK7: .omp.final.done:6293// CHECK7-NEXT: ret void6294//6295//6296// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1116297// CHECK7-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] {6298// CHECK7-NEXT: entry:6299// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 46300// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 46301// CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 46302// CHECK7-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 26303// CHECK7-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 26304// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 46305// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP1]])6306// CHECK7-NEXT: ret void6307//6308//6309// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined6310// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {6311// CHECK7-NEXT: entry:6312// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 46313// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 46314// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 46315// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 46316// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 46317// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 46318// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 46319// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 46320// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 46321// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 46322// CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 46323// CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 46324// CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 46325// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 46326// CHECK7-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 46327// CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 46328// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 46329// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 46330// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 46331// CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)6332// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46333// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 96334// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]6335// CHECK7: cond.true:6336// CHECK7-NEXT: br label [[COND_END:%.*]]6337// CHECK7: cond.false:6338// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46339// CHECK7-NEXT: br label [[COND_END]]6340// CHECK7: cond.end:6341// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]6342// CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 46343// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 46344// CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 46345// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]6346// CHECK7: omp.inner.for.cond:6347// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31:![0-9]+]]6348// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP31]]6349// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]6350// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]6351// CHECK7: omp.inner.for.body:6352// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]]6353// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 16354// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]6355// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP31]]6356// CHECK7-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP31]]6357// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i326358// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 16359// CHECK7-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i166360// CHECK7-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP31]]6361// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]6362// CHECK7: omp.body.continue:6363// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]6364// CHECK7: omp.inner.for.inc:6365// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]]6366// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 16367// CHECK7-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]]6368// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]6369// CHECK7: omp.inner.for.end:6370// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]6371// CHECK7: omp.loop.exit:6372// CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])6373// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 46374// CHECK7-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 06375// CHECK7-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]6376// CHECK7: .omp.final.then:6377// CHECK7-NEXT: store i32 10, ptr [[I]], align 46378// CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]6379// CHECK7: .omp.final.done:6380// CHECK7-NEXT: ret void6381//6382//6383// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1186384// CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {6385// CHECK7-NEXT: entry:6386// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 46387// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 46388// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 46389// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 46390// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 46391// CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 46392// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 46393// CHECK7-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 46394// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 46395// CHECK7-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 26396// CHECK7-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 26397// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 46398// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])6399// CHECK7-NEXT: ret void6400//6401//6402// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined6403// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {6404// CHECK7-NEXT: entry:6405// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 46406// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 46407// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 46408// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 46409// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 46410// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 46411// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 46412// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 46413// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 46414// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 46415// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 46416// CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 46417// CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 46418// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 46419// CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 46420// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 46421// CHECK7-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 46422// CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 46423// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 46424// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 46425// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 46426// CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)6427// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46428// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 96429// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]6430// CHECK7: cond.true:6431// CHECK7-NEXT: br label [[COND_END:%.*]]6432// CHECK7: cond.false:6433// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46434// CHECK7-NEXT: br label [[COND_END]]6435// CHECK7: cond.end:6436// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]6437// CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 46438// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 46439// CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 46440// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]6441// CHECK7: omp.inner.for.cond:6442// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34:![0-9]+]]6443// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP34]]6444// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]6445// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]6446// CHECK7: omp.inner.for.body:6447// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]]6448// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 16449// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]6450// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP34]]6451// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP34]]6452// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 16453// CHECK7-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP34]]6454// CHECK7-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP34]]6455// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i326456// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 16457// CHECK7-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i166458// CHECK7-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP34]]6459// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]6460// CHECK7: omp.body.continue:6461// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]6462// CHECK7: omp.inner.for.inc:6463// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]]6464// CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 16465// CHECK7-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]]6466// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]6467// CHECK7: omp.inner.for.end:6468// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]6469// CHECK7: omp.loop.exit:6470// CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])6471// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 46472// CHECK7-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 06473// CHECK7-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]6474// CHECK7: .omp.final.then:6475// CHECK7-NEXT: store i32 10, ptr [[I]], align 46476// CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]6477// CHECK7: .omp.final.done:6478// CHECK7-NEXT: ret void6479//6480//6481// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1426482// CHECK7-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {6483// CHECK7-NEXT: entry:6484// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 46485// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 46486// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 46487// CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 46488// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 46489// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 46490// CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 46491// CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 46492// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 46493// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 46494// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 46495// CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 46496// CHECK7-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 46497// CHECK7-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 46498// CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 46499// CHECK7-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 46500// CHECK7-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 46501// CHECK7-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 46502// CHECK7-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 46503// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 46504// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 46505// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 46506// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 46507// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 46508// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 46509// CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 46510// CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 46511// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 46512// CHECK7-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 46513// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 46514// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])6515// CHECK7-NEXT: ret void6516//6517//6518// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined6519// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {6520// CHECK7-NEXT: entry:6521// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 46522// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 46523// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 46524// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 46525// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 46526// CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 46527// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 46528// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 46529// CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 46530// CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 46531// CHECK7-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 46532// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 46533// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 46534// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 46535// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 46536// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 46537// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 46538// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 46539// CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 46540// CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 46541// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 46542// CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 46543// CHECK7-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 46544// CHECK7-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 46545// CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 46546// CHECK7-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 46547// CHECK7-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 46548// CHECK7-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 46549// CHECK7-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 46550// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 46551// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 46552// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 46553// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 46554// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 46555// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 46556// CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 46557// CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 46558// CHECK7-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 06559// CHECK7-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i32 16) ]6560// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 46561// CHECK7-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 46562// CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 46563// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 46564// CHECK7-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 46565// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 46566// CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)6567// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46568// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 96569// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]6570// CHECK7: cond.true:6571// CHECK7-NEXT: br label [[COND_END:%.*]]6572// CHECK7: cond.false:6573// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 46574// CHECK7-NEXT: br label [[COND_END]]6575// CHECK7: cond.end:6576// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]6577// CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 46578// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 46579// CHECK7-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 46580// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]6581// CHECK7: omp.inner.for.cond:6582// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37:![0-9]+]]6583// CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP37]]6584// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]6585// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]6586// CHECK7: omp.inner.for.body:6587// CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]]6588// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 16589// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]6590// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP37]]6591// CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP37]]6592// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 16593// CHECK7-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP37]]6594// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 26595// CHECK7-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP37]]6596// CHECK7-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double6597// CHECK7-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+006598// CHECK7-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float6599// CHECK7-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP37]]6600// CHECK7-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 36601// CHECK7-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP37]]6602// CHECK7-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double6603// CHECK7-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+006604// CHECK7-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float6605// CHECK7-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP37]]6606// CHECK7-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 16607// CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i32 0, i32 26608// CHECK7-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP37]]6609// CHECK7-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+006610// CHECK7-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP37]]6611// CHECK7-NEXT: [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]]6612// CHECK7-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP20]]6613// CHECK7-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i32 36614// CHECK7-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP37]]6615// CHECK7-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+006616// CHECK7-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP37]]6617// CHECK7-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 06618// CHECK7-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP37]]6619// CHECK7-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 16620// CHECK7-NEXT: store i64 [[ADD19]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP37]]6621// CHECK7-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 16622// CHECK7-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP37]]6623// CHECK7-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i326624// CHECK7-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 16625// CHECK7-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i86626// CHECK7-NEXT: store i8 [[CONV22]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP37]]6627// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]6628// CHECK7: omp.body.continue:6629// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]6630// CHECK7: omp.inner.for.inc:6631// CHECK7-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]]6632// CHECK7-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 16633// CHECK7-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]]6634// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]]6635// CHECK7: omp.inner.for.end:6636// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]6637// CHECK7: omp.loop.exit:6638// CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP9]])6639// CHECK7-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 46640// CHECK7-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 06641// CHECK7-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]6642// CHECK7: .omp.final.then:6643// CHECK7-NEXT: store i32 10, ptr [[I]], align 46644// CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]6645// CHECK7: .omp.final.done:6646// CHECK7-NEXT: ret void6647//6648//6649// CHECK7-LABEL: define {{[^@]+}}@_Z3bari6650// CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {6651// CHECK7-NEXT: entry:6652// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 46653// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 46654// CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 46655// CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 46656// CHECK7-NEXT: store i32 0, ptr [[A]], align 46657// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 46658// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])6659// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 46660// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]6661// CHECK7-NEXT: store i32 [[ADD]], ptr [[A]], align 46662// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 46663// CHECK7-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])6664// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 46665// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]6666// CHECK7-NEXT: store i32 [[ADD2]], ptr [[A]], align 46667// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 46668// CHECK7-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])6669// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 46670// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]6671// CHECK7-NEXT: store i32 [[ADD4]], ptr [[A]], align 46672// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 46673// CHECK7-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])6674// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 46675// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]6676// CHECK7-NEXT: store i32 [[ADD6]], ptr [[A]], align 46677// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 46678// CHECK7-NEXT: ret i32 [[TMP8]]6679//6680//6681// CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei6682// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {6683// CHECK7-NEXT: entry:6684// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 46685// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 46686// CHECK7-NEXT: [[B:%.*]] = alloca i32, align 46687// CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 46688// CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 46689// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 16690// CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 46691// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 46692// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x ptr], align 46693// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x ptr], align 46694// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x ptr], align 46695// CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 46696// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 46697// CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 86698// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 46699// CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 46700// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 46701// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 46702// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 16703// CHECK7-NEXT: store i32 [[ADD]], ptr [[B]], align 46704// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 46705// CHECK7-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()6706// CHECK7-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 46707// CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]6708// CHECK7-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 26709// CHECK7-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 46710// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 46711// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 606712// CHECK7-NEXT: [[STOREDV:%.*]] = zext i1 [[CMP]] to i86713// CHECK7-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 16714// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 46715// CHECK7-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 46716// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 46717// CHECK7-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 16718// CHECK7-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP7]] to i16719// CHECK7-NEXT: [[STOREDV2:%.*]] = zext i1 [[LOADEDV]] to i86720// CHECK7-NEXT: store i8 [[STOREDV2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 16721// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 46722// CHECK7-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 16723// CHECK7-NEXT: [[LOADEDV3:%.*]] = trunc i8 [[TMP9]] to i16724// CHECK7-NEXT: br i1 [[LOADEDV3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]6725// CHECK7: omp_if.then:6726// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 06727// CHECK7-NEXT: [[TMP10:%.*]] = mul nuw i32 2, [[TMP1]]6728// CHECK7-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 26729// CHECK7-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i646730// CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.7, i32 48, i1 false)6731// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06732// CHECK7-NEXT: store ptr [[THIS1]], ptr [[TMP13]], align 46733// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06734// CHECK7-NEXT: store ptr [[A]], ptr [[TMP14]], align 46735// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 06736// CHECK7-NEXT: store ptr null, ptr [[TMP15]], align 46737// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 16738// CHECK7-NEXT: store i32 [[TMP6]], ptr [[TMP16]], align 46739// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 16740// CHECK7-NEXT: store i32 [[TMP6]], ptr [[TMP17]], align 46741// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 16742// CHECK7-NEXT: store ptr null, ptr [[TMP18]], align 46743// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 26744// CHECK7-NEXT: store i32 2, ptr [[TMP19]], align 46745// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 26746// CHECK7-NEXT: store i32 2, ptr [[TMP20]], align 46747// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 26748// CHECK7-NEXT: store ptr null, ptr [[TMP21]], align 46749// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 36750// CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP22]], align 46751// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 36752// CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP23]], align 46753// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 36754// CHECK7-NEXT: store ptr null, ptr [[TMP24]], align 46755// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 46756// CHECK7-NEXT: store ptr [[VLA]], ptr [[TMP25]], align 46757// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 46758// CHECK7-NEXT: store ptr [[VLA]], ptr [[TMP26]], align 46759// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 46760// CHECK7-NEXT: store i64 [[TMP12]], ptr [[TMP27]], align 46761// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 46762// CHECK7-NEXT: store ptr null, ptr [[TMP28]], align 46763// CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 56764// CHECK7-NEXT: store i32 [[TMP8]], ptr [[TMP29]], align 46765// CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 56766// CHECK7-NEXT: store i32 [[TMP8]], ptr [[TMP30]], align 46767// CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 56768// CHECK7-NEXT: store ptr null, ptr [[TMP31]], align 46769// CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06770// CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06771// CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 06772// CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 06773// CHECK7-NEXT: store i32 3, ptr [[TMP35]], align 46774// CHECK7-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 16775// CHECK7-NEXT: store i32 6, ptr [[TMP36]], align 46776// CHECK7-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 26777// CHECK7-NEXT: store ptr [[TMP32]], ptr [[TMP37]], align 46778// CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 36779// CHECK7-NEXT: store ptr [[TMP33]], ptr [[TMP38]], align 46780// CHECK7-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 46781// CHECK7-NEXT: store ptr [[TMP34]], ptr [[TMP39]], align 46782// CHECK7-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 56783// CHECK7-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP40]], align 46784// CHECK7-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 66785// CHECK7-NEXT: store ptr null, ptr [[TMP41]], align 46786// CHECK7-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 76787// CHECK7-NEXT: store ptr null, ptr [[TMP42]], align 46788// CHECK7-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 86789// CHECK7-NEXT: store i64 10, ptr [[TMP43]], align 86790// CHECK7-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 96791// CHECK7-NEXT: store i64 0, ptr [[TMP44]], align 86792// CHECK7-NEXT: [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 106793// CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP45]], align 46794// CHECK7-NEXT: [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 116795// CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP46]], align 46796// CHECK7-NEXT: [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 126797// CHECK7-NEXT: store i32 0, ptr [[TMP47]], align 46798// CHECK7-NEXT: [[TMP48:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.region_id, ptr [[KERNEL_ARGS]])6799// CHECK7-NEXT: [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 06800// CHECK7-NEXT: br i1 [[TMP49]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]6801// CHECK7: omp_offload.failed:6802// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], ptr [[VLA]], i32 [[TMP8]]) #[[ATTR3]]6803// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]6804// CHECK7: omp_offload.cont:6805// CHECK7-NEXT: br label [[OMP_IF_END:%.*]]6806// CHECK7: omp_if.else:6807// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], ptr [[VLA]], i32 [[TMP8]]) #[[ATTR3]]6808// CHECK7-NEXT: br label [[OMP_IF_END]]6809// CHECK7: omp_if.end:6810// CHECK7-NEXT: [[TMP50:%.*]] = mul nsw i32 1, [[TMP1]]6811// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP50]]6812// CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 16813// CHECK7-NEXT: [[TMP51:%.*]] = load i16, ptr [[ARRAYIDX4]], align 26814// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP51]] to i326815// CHECK7-NEXT: [[TMP52:%.*]] = load i32, ptr [[B]], align 46816// CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV]], [[TMP52]]6817// CHECK7-NEXT: [[TMP53:%.*]] = load ptr, ptr [[SAVED_STACK]], align 46818// CHECK7-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP53]])6819// CHECK7-NEXT: ret i32 [[ADD5]]6820//6821//6822// CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici6823// CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {6824// CHECK7-NEXT: entry:6825// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 46826// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 46827// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 26828// CHECK7-NEXT: [[AAA:%.*]] = alloca i8, align 16829// CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 46830// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 46831// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 46832// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 46833// CHECK7-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 46834// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 46835// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 46836// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 46837// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 46838// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 46839// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 46840// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 46841// CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 86842// CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 46843// CHECK7-NEXT: store i32 0, ptr [[A]], align 46844// CHECK7-NEXT: store i16 0, ptr [[AA]], align 26845// CHECK7-NEXT: store i8 0, ptr [[AAA]], align 16846// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 46847// CHECK7-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 46848// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 46849// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 46850// CHECK7-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 46851// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 46852// CHECK7-NEXT: [[TMP4:%.*]] = load i16, ptr [[AA]], align 26853// CHECK7-NEXT: store i16 [[TMP4]], ptr [[AA_CASTED]], align 26854// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[AA_CASTED]], align 46855// CHECK7-NEXT: [[TMP6:%.*]] = load i8, ptr [[AAA]], align 16856// CHECK7-NEXT: store i8 [[TMP6]], ptr [[AAA_CASTED]], align 16857// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[AAA_CASTED]], align 46858// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[N_ADDR]], align 46859// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 506860// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]6861// CHECK7: omp_if.then:6862// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06863// CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP9]], align 46864// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06865// CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP10]], align 46866// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 06867// CHECK7-NEXT: store ptr null, ptr [[TMP11]], align 46868// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 16869// CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP12]], align 46870// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 16871// CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP13]], align 46872// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 16873// CHECK7-NEXT: store ptr null, ptr [[TMP14]], align 46874// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 26875// CHECK7-NEXT: store i32 [[TMP5]], ptr [[TMP15]], align 46876// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 26877// CHECK7-NEXT: store i32 [[TMP5]], ptr [[TMP16]], align 46878// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 26879// CHECK7-NEXT: store ptr null, ptr [[TMP17]], align 46880// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 36881// CHECK7-NEXT: store i32 [[TMP7]], ptr [[TMP18]], align 46882// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 36883// CHECK7-NEXT: store i32 [[TMP7]], ptr [[TMP19]], align 46884// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 36885// CHECK7-NEXT: store ptr null, ptr [[TMP20]], align 46886// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 46887// CHECK7-NEXT: store ptr [[B]], ptr [[TMP21]], align 46888// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 46889// CHECK7-NEXT: store ptr [[B]], ptr [[TMP22]], align 46890// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 46891// CHECK7-NEXT: store ptr null, ptr [[TMP23]], align 46892// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06893// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06894// CHECK7-NEXT: [[TMP26:%.*]] = load i32, ptr [[A]], align 46895// CHECK7-NEXT: store i32 [[TMP26]], ptr [[DOTCAPTURE_EXPR_]], align 46896// CHECK7-NEXT: [[TMP27:%.*]] = load i32, ptr [[N_ADDR]], align 46897// CHECK7-NEXT: store i32 [[TMP27]], ptr [[DOTCAPTURE_EXPR_1]], align 46898// CHECK7-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 46899// CHECK7-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 46900// CHECK7-NEXT: [[SUB:%.*]] = sub i32 [[TMP28]], [[TMP29]]6901// CHECK7-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 16902// CHECK7-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 16903// CHECK7-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 16904// CHECK7-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 16905// CHECK7-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 46906// CHECK7-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 46907// CHECK7-NEXT: [[ADD5:%.*]] = add i32 [[TMP30]], 16908// CHECK7-NEXT: [[TMP31:%.*]] = zext i32 [[ADD5]] to i646909// CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 06910// CHECK7-NEXT: store i32 3, ptr [[TMP32]], align 46911// CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 16912// CHECK7-NEXT: store i32 5, ptr [[TMP33]], align 46913// CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 26914// CHECK7-NEXT: store ptr [[TMP24]], ptr [[TMP34]], align 46915// CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 36916// CHECK7-NEXT: store ptr [[TMP25]], ptr [[TMP35]], align 46917// CHECK7-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 46918// CHECK7-NEXT: store ptr @.offload_sizes.9, ptr [[TMP36]], align 46919// CHECK7-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 56920// CHECK7-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP37]], align 46921// CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 66922// CHECK7-NEXT: store ptr null, ptr [[TMP38]], align 46923// CHECK7-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 76924// CHECK7-NEXT: store ptr null, ptr [[TMP39]], align 46925// CHECK7-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 86926// CHECK7-NEXT: store i64 [[TMP31]], ptr [[TMP40]], align 86927// CHECK7-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 96928// CHECK7-NEXT: store i64 0, ptr [[TMP41]], align 86929// CHECK7-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 106930// CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP42]], align 46931// CHECK7-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 116932// CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP43]], align 46933// CHECK7-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 126934// CHECK7-NEXT: store i32 0, ptr [[TMP44]], align 46935// CHECK7-NEXT: [[TMP45:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.region_id, ptr [[KERNEL_ARGS]])6936// CHECK7-NEXT: [[TMP46:%.*]] = icmp ne i32 [[TMP45]], 06937// CHECK7-NEXT: br i1 [[TMP46]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]6938// CHECK7: omp_offload.failed:6939// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], ptr [[B]]) #[[ATTR3]]6940// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]6941// CHECK7: omp_offload.cont:6942// CHECK7-NEXT: br label [[OMP_IF_END:%.*]]6943// CHECK7: omp_if.else:6944// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], ptr [[B]]) #[[ATTR3]]6945// CHECK7-NEXT: br label [[OMP_IF_END]]6946// CHECK7: omp_if.end:6947// CHECK7-NEXT: [[TMP47:%.*]] = load i32, ptr [[A]], align 46948// CHECK7-NEXT: ret i32 [[TMP47]]6949//6950//6951// CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i6952// CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {6953// CHECK7-NEXT: entry:6954// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 46955// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 46956// CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 26957// CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 46958// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 46959// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 46960// CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 46961// CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 46962// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 46963// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 46964// CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 86965// CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 46966// CHECK7-NEXT: store i32 0, ptr [[A]], align 46967// CHECK7-NEXT: store i16 0, ptr [[AA]], align 26968// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 46969// CHECK7-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 46970// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 46971// CHECK7-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 26972// CHECK7-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 26973// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 46974// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 46975// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 406976// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]6977// CHECK7: omp_if.then:6978// CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06979// CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 46980// CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06981// CHECK7-NEXT: store i32 [[TMP1]], ptr [[TMP6]], align 46982// CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 06983// CHECK7-NEXT: store ptr null, ptr [[TMP7]], align 46984// CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 16985// CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP8]], align 46986// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 16987// CHECK7-NEXT: store i32 [[TMP3]], ptr [[TMP9]], align 46988// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 16989// CHECK7-NEXT: store ptr null, ptr [[TMP10]], align 46990// CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 26991// CHECK7-NEXT: store ptr [[B]], ptr [[TMP11]], align 46992// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 26993// CHECK7-NEXT: store ptr [[B]], ptr [[TMP12]], align 46994// CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 26995// CHECK7-NEXT: store ptr null, ptr [[TMP13]], align 46996// CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 06997// CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 06998// CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 06999// CHECK7-NEXT: store i32 3, ptr [[TMP16]], align 47000// CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 17001// CHECK7-NEXT: store i32 3, ptr [[TMP17]], align 47002// CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 27003// CHECK7-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 47004// CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 37005// CHECK7-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 47006// CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 47007// CHECK7-NEXT: store ptr @.offload_sizes.11, ptr [[TMP20]], align 47008// CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 57009// CHECK7-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP21]], align 47010// CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 67011// CHECK7-NEXT: store ptr null, ptr [[TMP22]], align 47012// CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 77013// CHECK7-NEXT: store ptr null, ptr [[TMP23]], align 47014// CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 87015// CHECK7-NEXT: store i64 10, ptr [[TMP24]], align 87016// CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 97017// CHECK7-NEXT: store i64 0, ptr [[TMP25]], align 87018// CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 107019// CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 47020// CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 117021// CHECK7-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 47022// CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 127023// CHECK7-NEXT: store i32 0, ptr [[TMP28]], align 47024// CHECK7-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.region_id, ptr [[KERNEL_ARGS]])7025// CHECK7-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 07026// CHECK7-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]7027// CHECK7: omp_offload.failed:7028// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]7029// CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]7030// CHECK7: omp_offload.cont:7031// CHECK7-NEXT: br label [[OMP_IF_END:%.*]]7032// CHECK7: omp_if.else:7033// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]7034// CHECK7-NEXT: br label [[OMP_IF_END]]7035// CHECK7: omp_if.end:7036// CHECK7-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 47037// CHECK7-NEXT: ret i32 [[TMP31]]7038//7039//7040// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l2157041// CHECK7-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {7042// CHECK7-NEXT: entry:7043// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 47044// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 47045// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 47046// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 47047// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 47048// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 47049// CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 47050// CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 47051// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 47052// CHECK7-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 47053// CHECK7-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 47054// CHECK7-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 47055// CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 47056// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 47057// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 47058// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 47059// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 47060// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 47061// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 47062// CHECK7-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 47063// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 47064// CHECK7-NEXT: [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 17065// CHECK7-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP6]] to i17066// CHECK7-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i87067// CHECK7-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 17068// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 47069// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]], i32 [[TMP7]])7070// CHECK7-NEXT: ret void7071//7072//7073// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined7074// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {7075// CHECK7-NEXT: entry:7076// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 47077// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 47078// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 47079// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 47080// CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 47081// CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 47082// CHECK7-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 47083// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 47084// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 47085// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 47086// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 47087// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 47088// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 47089// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 47090// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 47091// CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 47092// CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 47093// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 47094// CHECK7-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 47095// CHECK7-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 47096// CHECK7-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 47097// CHECK7-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 47098// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 47099// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 47100// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 47101// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 47102// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 47103// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 47104// CHECK7-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 47105// CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 47106// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 47107// CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 47108// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 47109// CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)7110// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47111// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 97112// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]7113// CHECK7: cond.true:7114// CHECK7-NEXT: br label [[COND_END:%.*]]7115// CHECK7: cond.false:7116// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47117// CHECK7-NEXT: br label [[COND_END]]7118// CHECK7: cond.end:7119// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]7120// CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 47121// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 47122// CHECK7-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 47123// CHECK7-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 17124// CHECK7-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP9]] to i17125// CHECK7-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]7126// CHECK7: omp_if.then:7127// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]7128// CHECK7: omp.inner.for.cond:7129// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40:![0-9]+]]7130// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP40]]7131// CHECK7-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]7132// CHECK7-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]7133// CHECK7: omp.inner.for.body:7134// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]]7135// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 17136// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]7137// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP40]]7138// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP40]]7139// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double7140// CHECK7-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+007141// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 07142// CHECK7-NEXT: store double [[ADD4]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP40]]7143// CHECK7-NEXT: [[A5:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 07144// CHECK7-NEXT: [[TMP14:%.*]] = load double, ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP40]]7145// CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+007146// CHECK7-NEXT: store double [[INC]], ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP40]]7147// CHECK7-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i167148// CHECK7-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]]7149// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP15]]7150// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 17151// CHECK7-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP40]]7152// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]7153// CHECK7: omp.body.continue:7154// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]7155// CHECK7: omp.inner.for.inc:7156// CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]]7157// CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], 17158// CHECK7-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]]7159// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]]7160// CHECK7: omp.inner.for.end:7161// CHECK7-NEXT: br label [[OMP_IF_END:%.*]]7162// CHECK7: omp_if.else:7163// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]7164// CHECK7: omp.inner.for.cond9:7165// CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47166// CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47167// CHECK7-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]7168// CHECK7-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]]7169// CHECK7: omp.inner.for.body11:7170// CHECK7-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47171// CHECK7-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP19]], 17172// CHECK7-NEXT: [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]7173// CHECK7-NEXT: store i32 [[ADD13]], ptr [[I]], align 47174// CHECK7-NEXT: [[TMP20:%.*]] = load i32, ptr [[B_ADDR]], align 47175// CHECK7-NEXT: [[CONV14:%.*]] = sitofp i32 [[TMP20]] to double7176// CHECK7-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+007177// CHECK7-NEXT: [[A16:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 07178// CHECK7-NEXT: store double [[ADD15]], ptr [[A16]], align 47179// CHECK7-NEXT: [[A17:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 07180// CHECK7-NEXT: [[TMP21:%.*]] = load double, ptr [[A17]], align 47181// CHECK7-NEXT: [[INC18:%.*]] = fadd double [[TMP21]], 1.000000e+007182// CHECK7-NEXT: store double [[INC18]], ptr [[A17]], align 47183// CHECK7-NEXT: [[CONV19:%.*]] = fptosi double [[INC18]] to i167184// CHECK7-NEXT: [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]]7185// CHECK7-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP22]]7186// CHECK7-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX20]], i32 17187// CHECK7-NEXT: store i16 [[CONV19]], ptr [[ARRAYIDX21]], align 27188// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE22:%.*]]7189// CHECK7: omp.body.continue22:7190// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC23:%.*]]7191// CHECK7: omp.inner.for.inc23:7192// CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 47193// CHECK7-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP23]], 17194// CHECK7-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 47195// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP43:![0-9]+]]7196// CHECK7: omp.inner.for.end25:7197// CHECK7-NEXT: br label [[OMP_IF_END]]7198// CHECK7: omp_if.end:7199// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]7200// CHECK7: omp.loop.exit:7201// CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])7202// CHECK7-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 47203// CHECK7-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 07204// CHECK7-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]7205// CHECK7: .omp.final.then:7206// CHECK7-NEXT: store i32 10, ptr [[I]], align 47207// CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]7208// CHECK7: .omp.final.done:7209// CHECK7-NEXT: ret void7210//7211//7212// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l1977213// CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {7214// CHECK7-NEXT: entry:7215// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 47216// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 47217// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 47218// CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 47219// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 47220// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 47221// CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 47222// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 47223// CHECK7-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 47224// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 47225// CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 47226// CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 47227// CHECK7-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 47228// CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 47229// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 47230// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 47231// CHECK7-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 47232// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 47233// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 47234// CHECK7-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 47235// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 47236// CHECK7-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 27237// CHECK7-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 27238// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[AA_CASTED]], align 47239// CHECK7-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 17240// CHECK7-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 17241// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[AAA_CASTED]], align 47242// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], ptr [[TMP0]])7243// CHECK7-NEXT: ret void7244//7245//7246// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined7247// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {7248// CHECK7-NEXT: entry:7249// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 47250// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 47251// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 47252// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 47253// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 47254// CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 47255// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 47256// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 47257// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 47258// CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 47259// CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 47260// CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 47261// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 47262// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 47263// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 47264// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 47265// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 47266// CHECK7-NEXT: [[I5:%.*]] = alloca i32, align 47267// CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 47268// CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 47269// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 47270// CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 47271// CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 47272// CHECK7-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 47273// CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 47274// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 47275// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 47276// CHECK7-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 47277// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 47278// CHECK7-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 47279// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 47280// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 47281// CHECK7-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]7282// CHECK7-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 17283// CHECK7-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 17284// CHECK7-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 17285// CHECK7-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 17286// CHECK7-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 47287// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 47288// CHECK7-NEXT: store i32 [[TMP5]], ptr [[I]], align 47289// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 47290// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 47291// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]7292// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]7293// CHECK7: omp.precond.then:7294// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 47295// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 47296// CHECK7-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 47297// CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 47298// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 47299// CHECK7-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 47300// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 47301// CHECK7-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)7302// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47303// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 47304// CHECK7-NEXT: [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]7305// CHECK7-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]7306// CHECK7: cond.true:7307// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 47308// CHECK7-NEXT: br label [[COND_END:%.*]]7309// CHECK7: cond.false:7310// CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47311// CHECK7-NEXT: br label [[COND_END]]7312// CHECK7: cond.end:7313// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]7314// CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 47315// CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 47316// CHECK7-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 47317// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]7318// CHECK7: omp.inner.for.cond:7319// CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45:![0-9]+]]7320// CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]]7321// CHECK7-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 17322// CHECK7-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]7323// CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]7324// CHECK7: omp.inner.for.body:7325// CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP45]]7326// CHECK7-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]7327// CHECK7-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 17328// CHECK7-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]7329// CHECK7-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP45]]7330// CHECK7-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]7331// CHECK7-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 17332// CHECK7-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]7333// CHECK7-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP45]]7334// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i327335// CHECK7-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 17336// CHECK7-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i167337// CHECK7-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP45]]7338// CHECK7-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP45]]7339// CHECK7-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i327340// CHECK7-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 17341// CHECK7-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i87342// CHECK7-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP45]]7343// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 27344// CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]7345// CHECK7-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 17346// CHECK7-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]7347// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]7348// CHECK7: omp.body.continue:7349// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]7350// CHECK7: omp.inner.for.inc:7351// CHECK7-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]7352// CHECK7-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 17353// CHECK7-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]7354// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]7355// CHECK7: omp.inner.for.end:7356// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]7357// CHECK7: omp.loop.exit:7358// CHECK7-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 47359// CHECK7-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 47360// CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])7361// CHECK7-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 47362// CHECK7-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 07363// CHECK7-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]7364// CHECK7: .omp.final.then:7365// CHECK7-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 47366// CHECK7-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 47367// CHECK7-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 47368// CHECK7-NEXT: [[SUB18:%.*]] = sub i32 [[TMP30]], [[TMP31]]7369// CHECK7-NEXT: [[SUB19:%.*]] = sub i32 [[SUB18]], 17370// CHECK7-NEXT: [[ADD20:%.*]] = add i32 [[SUB19]], 17371// CHECK7-NEXT: [[DIV21:%.*]] = udiv i32 [[ADD20]], 17372// CHECK7-NEXT: [[MUL22:%.*]] = mul i32 [[DIV21]], 17373// CHECK7-NEXT: [[ADD23:%.*]] = add i32 [[TMP29]], [[MUL22]]7374// CHECK7-NEXT: store i32 [[ADD23]], ptr [[I5]], align 47375// CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]7376// CHECK7: .omp.final.done:7377// CHECK7-NEXT: br label [[OMP_PRECOND_END]]7378// CHECK7: omp.precond.end:7379// CHECK7-NEXT: ret void7380//7381//7382// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l1807383// CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {7384// CHECK7-NEXT: entry:7385// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 47386// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 47387// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 47388// CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 47389// CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 47390// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 47391// CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 47392// CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 47393// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 47394// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 47395// CHECK7-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 47396// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 47397// CHECK7-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 27398// CHECK7-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 27399// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 47400// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])7401// CHECK7-NEXT: ret void7402//7403//7404// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined7405// CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {7406// CHECK7-NEXT: entry:7407// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 47408// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 47409// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 47410// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 47411// CHECK7-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 47412// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 47413// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 47414// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 47415// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 47416// CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 47417// CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 47418// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 47419// CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 47420// CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 47421// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 47422// CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 47423// CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 47424// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 47425// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 47426// CHECK7-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 47427// CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 47428// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 47429// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 47430// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 47431// CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)7432// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47433// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 97434// CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]7435// CHECK7: cond.true:7436// CHECK7-NEXT: br label [[COND_END:%.*]]7437// CHECK7: cond.false:7438// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 47439// CHECK7-NEXT: br label [[COND_END]]7440// CHECK7: cond.end:7441// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]7442// CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 47443// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 47444// CHECK7-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 47445// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]7446// CHECK7: omp.inner.for.cond:7447// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48:![0-9]+]]7448// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP48]]7449// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]7450// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]7451// CHECK7: omp.inner.for.body:7452// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48]]7453// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 17454// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]7455// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP48]]7456// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP48]]7457// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 17458// CHECK7-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP48]]7459// CHECK7-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP48]]7460// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i327461// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 17462// CHECK7-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i167463// CHECK7-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP48]]7464// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 27465// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP48]]7466// CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 17467// CHECK7-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP48]]7468// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]7469// CHECK7: omp.body.continue:7470// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]7471// CHECK7: omp.inner.for.inc:7472// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48]]7473// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 17474// CHECK7-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48]]7475// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP49:![0-9]+]]7476// CHECK7: omp.inner.for.end:7477// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]7478// CHECK7: omp.loop.exit:7479// CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])7480// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 47481// CHECK7-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 07482// CHECK7-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]7483// CHECK7: .omp.final.then:7484// CHECK7-NEXT: store i32 10, ptr [[I]], align 47485// CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]7486// CHECK7: .omp.final.done:7487// CHECK7-NEXT: ret void7488//7489//7490// CHECK9-LABEL: define {{[^@]+}}@_Z3fooi7491// CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {7492// CHECK9-NEXT: entry:7493// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 47494// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 47495// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 27496// CHECK9-NEXT: [[B:%.*]] = alloca [10 x float], align 47497// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 87498// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 87499// CHECK9-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 87500// CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 87501// CHECK9-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 87502// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 47503// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 47504// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 47505// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 47506// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 47507// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 47508// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 47509// CHECK9-NEXT: [[_TMP4:%.*]] = alloca i32, align 47510// CHECK9-NEXT: [[DOTOMP_LB5:%.*]] = alloca i32, align 47511// CHECK9-NEXT: [[DOTOMP_UB6:%.*]] = alloca i32, align 47512// CHECK9-NEXT: [[DOTOMP_IV7:%.*]] = alloca i32, align 47513// CHECK9-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 47514// CHECK9-NEXT: [[A8:%.*]] = alloca i32, align 47515// CHECK9-NEXT: [[A9:%.*]] = alloca i32, align 47516// CHECK9-NEXT: [[_TMP20:%.*]] = alloca i32, align 47517// CHECK9-NEXT: [[DOTOMP_LB21:%.*]] = alloca i32, align 47518// CHECK9-NEXT: [[DOTOMP_UB22:%.*]] = alloca i32, align 47519// CHECK9-NEXT: [[DOTOMP_IV23:%.*]] = alloca i32, align 47520// CHECK9-NEXT: [[I24:%.*]] = alloca i32, align 47521// CHECK9-NEXT: [[_TMP36:%.*]] = alloca i32, align 47522// CHECK9-NEXT: [[DOTOMP_LB37:%.*]] = alloca i32, align 47523// CHECK9-NEXT: [[DOTOMP_UB38:%.*]] = alloca i32, align 47524// CHECK9-NEXT: [[DOTOMP_IV39:%.*]] = alloca i32, align 47525// CHECK9-NEXT: [[I40:%.*]] = alloca i32, align 47526// CHECK9-NEXT: [[_TMP54:%.*]] = alloca i32, align 47527// CHECK9-NEXT: [[DOTOMP_LB55:%.*]] = alloca i32, align 47528// CHECK9-NEXT: [[DOTOMP_UB56:%.*]] = alloca i32, align 47529// CHECK9-NEXT: [[DOTOMP_IV57:%.*]] = alloca i32, align 47530// CHECK9-NEXT: [[I58:%.*]] = alloca i32, align 47531// CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 47532// CHECK9-NEXT: store i32 0, ptr [[A]], align 47533// CHECK9-NEXT: store i16 0, ptr [[AA]], align 27534// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 47535// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i647536// CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()7537// CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 87538// CHECK9-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 47539// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 87540// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 47541// CHECK9-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i647542// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]7543// CHECK9-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 87544// CHECK9-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 87545// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 47546// CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 47547// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 47548// CHECK9-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_2]], align 47549// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 47550// CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 47551// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 47552// CHECK9-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 47553// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]7554// CHECK9: omp.inner.for.cond:7555// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]7556// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]7557// CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]7558// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]7559// CHECK9: omp.inner.for.body:7560// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]7561// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 17562// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]7563// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]7564// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]7565// CHECK9: omp.body.continue:7566// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]7567// CHECK9: omp.inner.for.inc:7568// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]7569// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 17570// CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]7571// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]7572// CHECK9: omp.inner.for.end:7573// CHECK9-NEXT: store i32 10, ptr [[I]], align 47574// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB5]], align 47575// CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB6]], align 47576// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB5]], align 47577// CHECK9-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV7]], align 47578// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 47579// CHECK9-NEXT: store i32 [[TMP14]], ptr [[DOTLINEAR_START]], align 47580// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND10:%.*]]7581// CHECK9: omp.inner.for.cond10:7582// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 47583// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB6]], align 47584// CHECK9-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]7585// CHECK9-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]7586// CHECK9: omp.inner.for.body12:7587// CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 47588// CHECK9-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 17589// CHECK9-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]7590// CHECK9-NEXT: store i32 [[ADD14]], ptr [[A8]], align 47591// CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[A8]], align 47592// CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 17593// CHECK9-NEXT: store i32 [[ADD15]], ptr [[A8]], align 47594// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]7595// CHECK9: omp.body.continue16:7596// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]7597// CHECK9: omp.inner.for.inc17:7598// CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 47599// CHECK9-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 17600// CHECK9-NEXT: store i32 [[ADD18]], ptr [[DOTOMP_IV7]], align 47601// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP7:![0-9]+]]7602// CHECK9: omp.inner.for.end19:7603// CHECK9-NEXT: store i32 10, ptr [[A]], align 47604// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB21]], align 47605// CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB22]], align 47606// CHECK9-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB21]], align 47607// CHECK9-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV23]], align 47608// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND25:%.*]]7609// CHECK9: omp.inner.for.cond25:7610// CHECK9-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]]7611// CHECK9-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB22]], align 4, !llvm.access.group [[ACC_GRP9]]7612// CHECK9-NEXT: [[CMP26:%.*]] = icmp sle i32 [[TMP21]], [[TMP22]]7613// CHECK9-NEXT: br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]7614// CHECK9: omp.inner.for.body27:7615// CHECK9-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP9]]7616// CHECK9-NEXT: [[MUL28:%.*]] = mul nsw i32 [[TMP23]], 17617// CHECK9-NEXT: [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]7618// CHECK9-NEXT: store i32 [[ADD29]], ptr [[I24]], align 4, !llvm.access.group [[ACC_GRP9]]7619// CHECK9-NEXT: [[TMP24:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP9]]7620// CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP24]] to i327621// CHECK9-NEXT: [[ADD30:%.*]] = add nsw i32 [[CONV]], 17622// CHECK9-NEXT: [[CONV31:%.*]] = trunc i32 [[ADD30]] to i167623// CHECK9-NEXT: store i16 [[CONV31]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP9]]7624// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE32:%.*]]7625// CHECK9: omp.body.continue32:7626// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC33:%.*]]7627// CHECK9: omp.inner.for.inc33:7628// CHECK9-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP9]]7629// CHECK9-NEXT: [[ADD34:%.*]] = add nsw i32 [[TMP25]], 17630// CHECK9-NEXT: store i32 [[ADD34]], ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP9]]7631// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP10:![0-9]+]]7632// CHECK9: omp.inner.for.end35:7633// CHECK9-NEXT: store i32 10, ptr [[I24]], align 47634// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB37]], align 47635// CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB38]], align 47636// CHECK9-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB37]], align 47637// CHECK9-NEXT: store i32 [[TMP26]], ptr [[DOTOMP_IV39]], align 47638// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND41:%.*]]7639// CHECK9: omp.inner.for.cond41:7640// CHECK9-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]7641// CHECK9-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB38]], align 4, !llvm.access.group [[ACC_GRP12]]7642// CHECK9-NEXT: [[CMP42:%.*]] = icmp sle i32 [[TMP27]], [[TMP28]]7643// CHECK9-NEXT: br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]7644// CHECK9: omp.inner.for.body43:7645// CHECK9-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP12]]7646// CHECK9-NEXT: [[MUL44:%.*]] = mul nsw i32 [[TMP29]], 17647// CHECK9-NEXT: [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]7648// CHECK9-NEXT: store i32 [[ADD45]], ptr [[I40]], align 4, !llvm.access.group [[ACC_GRP12]]7649// CHECK9-NEXT: [[TMP30:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP12]]7650// CHECK9-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP30]], 17651// CHECK9-NEXT: store i32 [[ADD46]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP12]]7652// CHECK9-NEXT: [[TMP31:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP12]]7653// CHECK9-NEXT: [[CONV47:%.*]] = sext i16 [[TMP31]] to i327654// CHECK9-NEXT: [[ADD48:%.*]] = add nsw i32 [[CONV47]], 17655// CHECK9-NEXT: [[CONV49:%.*]] = trunc i32 [[ADD48]] to i167656// CHECK9-NEXT: store i16 [[CONV49]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP12]]7657// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE50:%.*]]7658// CHECK9: omp.body.continue50:7659// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC51:%.*]]7660// CHECK9: omp.inner.for.inc51:7661// CHECK9-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP12]]7662// CHECK9-NEXT: [[ADD52:%.*]] = add nsw i32 [[TMP32]], 17663// CHECK9-NEXT: store i32 [[ADD52]], ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP12]]7664// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP13:![0-9]+]]7665// CHECK9: omp.inner.for.end53:7666// CHECK9-NEXT: store i32 10, ptr [[I40]], align 47667// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB55]], align 47668// CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB56]], align 47669// CHECK9-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_LB55]], align 47670// CHECK9-NEXT: store i32 [[TMP33]], ptr [[DOTOMP_IV57]], align 47671// CHECK9-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 07672// CHECK9-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i64 16) ]7673// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND59:%.*]]7674// CHECK9: omp.inner.for.cond59:7675// CHECK9-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]]7676// CHECK9-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_UB56]], align 4, !llvm.access.group [[ACC_GRP15]]7677// CHECK9-NEXT: [[CMP60:%.*]] = icmp sle i32 [[TMP34]], [[TMP35]]7678// CHECK9-NEXT: br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]7679// CHECK9: omp.inner.for.body61:7680// CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP15]]7681// CHECK9-NEXT: [[MUL62:%.*]] = mul nsw i32 [[TMP36]], 17682// CHECK9-NEXT: [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]7683// CHECK9-NEXT: store i32 [[ADD63]], ptr [[I58]], align 4, !llvm.access.group [[ACC_GRP15]]7684// CHECK9-NEXT: [[TMP37:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]]7685// CHECK9-NEXT: [[ADD64:%.*]] = add nsw i32 [[TMP37]], 17686// CHECK9-NEXT: store i32 [[ADD64]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]]7687// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 27688// CHECK9-NEXT: [[TMP38:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]]7689// CHECK9-NEXT: [[CONV65:%.*]] = fpext float [[TMP38]] to double7690// CHECK9-NEXT: [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+007691// CHECK9-NEXT: [[CONV67:%.*]] = fptrunc double [[ADD66]] to float7692// CHECK9-NEXT: store float [[CONV67]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]]7693// CHECK9-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds float, ptr [[VLA]], i64 37694// CHECK9-NEXT: [[TMP39:%.*]] = load float, ptr [[ARRAYIDX68]], align 4, !llvm.access.group [[ACC_GRP15]]7695// CHECK9-NEXT: [[CONV69:%.*]] = fpext float [[TMP39]] to double7696// CHECK9-NEXT: [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+007697// CHECK9-NEXT: [[CONV71:%.*]] = fptrunc double [[ADD70]] to float7698// CHECK9-NEXT: store float [[CONV71]], ptr [[ARRAYIDX68]], align 4, !llvm.access.group [[ACC_GRP15]]7699// CHECK9-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 17700// CHECK9-NEXT: [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX72]], i64 0, i64 27701// CHECK9-NEXT: [[TMP40:%.*]] = load double, ptr [[ARRAYIDX73]], align 8, !llvm.access.group [[ACC_GRP15]]7702// CHECK9-NEXT: [[ADD74:%.*]] = fadd double [[TMP40]], 1.000000e+007703// CHECK9-NEXT: store double [[ADD74]], ptr [[ARRAYIDX73]], align 8, !llvm.access.group [[ACC_GRP15]]7704// CHECK9-NEXT: [[TMP41:%.*]] = mul nsw i64 1, [[TMP4]]7705// CHECK9-NEXT: [[ARRAYIDX75:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i64 [[TMP41]]7706// CHECK9-NEXT: [[ARRAYIDX76:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX75]], i64 37707// CHECK9-NEXT: [[TMP42:%.*]] = load double, ptr [[ARRAYIDX76]], align 8, !llvm.access.group [[ACC_GRP15]]7708// CHECK9-NEXT: [[ADD77:%.*]] = fadd double [[TMP42]], 1.000000e+007709// CHECK9-NEXT: store double [[ADD77]], ptr [[ARRAYIDX76]], align 8, !llvm.access.group [[ACC_GRP15]]7710// CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 07711// CHECK9-NEXT: [[TMP43:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP15]]7712// CHECK9-NEXT: [[ADD78:%.*]] = add nsw i64 [[TMP43]], 17713// CHECK9-NEXT: store i64 [[ADD78]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP15]]7714// CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 17715// CHECK9-NEXT: [[TMP44:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP15]]7716// CHECK9-NEXT: [[CONV79:%.*]] = sext i8 [[TMP44]] to i327717// CHECK9-NEXT: [[ADD80:%.*]] = add nsw i32 [[CONV79]], 17718// CHECK9-NEXT: [[CONV81:%.*]] = trunc i32 [[ADD80]] to i87719// CHECK9-NEXT: store i8 [[CONV81]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP15]]7720// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE82:%.*]]7721// CHECK9: omp.body.continue82:7722// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC83:%.*]]7723// CHECK9: omp.inner.for.inc83:7724// CHECK9-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP15]]7725// CHECK9-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP45]], 17726// CHECK9-NEXT: store i32 [[ADD84]], ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP15]]7727// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP16:![0-9]+]]7728// CHECK9: omp.inner.for.end85:7729// CHECK9-NEXT: store i32 10, ptr [[I58]], align 47730// CHECK9-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 47731// CHECK9-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 87732// CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])7733// CHECK9-NEXT: ret i32 [[TMP46]]7734//7735//7736// CHECK9-LABEL: define {{[^@]+}}@_Z3bari7737// CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {7738// CHECK9-NEXT: entry:7739// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 47740// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 47741// CHECK9-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 87742// CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 47743// CHECK9-NEXT: store i32 0, ptr [[A]], align 47744// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 47745// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])7746// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 47747// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]7748// CHECK9-NEXT: store i32 [[ADD]], ptr [[A]], align 47749// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 47750// CHECK9-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])7751// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 47752// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]7753// CHECK9-NEXT: store i32 [[ADD2]], ptr [[A]], align 47754// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 47755// CHECK9-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])7756// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 47757// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]7758// CHECK9-NEXT: store i32 [[ADD4]], ptr [[A]], align 47759// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 47760// CHECK9-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])7761// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 47762// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]7763// CHECK9-NEXT: store i32 [[ADD6]], ptr [[A]], align 47764// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 47765// CHECK9-NEXT: ret i32 [[TMP8]]7766//7767//7768// CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei7769// CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {7770// CHECK9-NEXT: entry:7771// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 87772// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 47773// CHECK9-NEXT: [[B:%.*]] = alloca i32, align 47774// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 87775// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 87776// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 47777// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 47778// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 47779// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 47780// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 47781// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 87782// CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 47783// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 87784// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 47785// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 17786// CHECK9-NEXT: store i32 [[ADD]], ptr [[B]], align 47787// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 47788// CHECK9-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i647789// CHECK9-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()7790// CHECK9-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 87791// CHECK9-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]7792// CHECK9-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 27793// CHECK9-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 87794// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 47795// CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 47796// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 47797// CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 47798// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]7799// CHECK9: omp.inner.for.cond:7800// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]]7801// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]]7802// CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]7803// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]7804// CHECK9: omp.inner.for.body:7805// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]7806// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 17807// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 0, [[MUL]]7808// CHECK9-NEXT: store i32 [[ADD2]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]7809// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP18]]7810// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double7811// CHECK9-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+007812// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 07813// CHECK9-NEXT: store double [[ADD3]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP18]]7814// CHECK9-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 07815// CHECK9-NEXT: [[TMP10:%.*]] = load double, ptr [[A4]], align 8, !llvm.access.group [[ACC_GRP18]]7816// CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+007817// CHECK9-NEXT: store double [[INC]], ptr [[A4]], align 8, !llvm.access.group [[ACC_GRP18]]7818// CHECK9-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i167819// CHECK9-NEXT: [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]]7820// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP11]]7821// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 17822// CHECK9-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP18]]7823// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]7824// CHECK9: omp.body.continue:7825// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]7826// CHECK9: omp.inner.for.inc:7827// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]7828// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], 17829// CHECK9-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]7830// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]7831// CHECK9: omp.inner.for.end:7832// CHECK9-NEXT: store i32 10, ptr [[I]], align 47833// CHECK9-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]7834// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP13]]7835// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX8]], i64 17836// CHECK9-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX9]], align 27837// CHECK9-NEXT: [[CONV10:%.*]] = sext i16 [[TMP14]] to i327838// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 47839// CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV10]], [[TMP15]]7840// CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[SAVED_STACK]], align 87841// CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP16]])7842// CHECK9-NEXT: ret i32 [[ADD11]]7843//7844//7845// CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici7846// CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {7847// CHECK9-NEXT: entry:7848// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 47849// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 47850// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 27851// CHECK9-NEXT: [[AAA:%.*]] = alloca i8, align 17852// CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 47853// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 47854// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 47855// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 47856// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 47857// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 47858// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 47859// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 47860// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 47861// CHECK9-NEXT: [[I5:%.*]] = alloca i32, align 47862// CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 47863// CHECK9-NEXT: store i32 0, ptr [[A]], align 47864// CHECK9-NEXT: store i16 0, ptr [[AA]], align 27865// CHECK9-NEXT: store i8 0, ptr [[AAA]], align 17866// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 47867// CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 47868// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 47869// CHECK9-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_1]], align 47870// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 47871// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 47872// CHECK9-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]7873// CHECK9-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 17874// CHECK9-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 17875// CHECK9-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 17876// CHECK9-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 17877// CHECK9-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 47878// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 47879// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 47880// CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 47881// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 47882// CHECK9-NEXT: store i32 [[TMP5]], ptr [[I]], align 47883// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 47884// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 47885// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]7886// CHECK9-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]7887// CHECK9: simd.if.then:7888// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 47889// CHECK9-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 47890// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]7891// CHECK9: omp.inner.for.cond:7892// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]]7893// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]]7894// CHECK9-NEXT: [[ADD6:%.*]] = add i32 [[TMP10]], 17895// CHECK9-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]7896// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]7897// CHECK9: omp.inner.for.body:7898// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP21]]7899// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]7900// CHECK9-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 17901// CHECK9-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]7902// CHECK9-NEXT: store i32 [[ADD8]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP21]]7903// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP21]]7904// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 17905// CHECK9-NEXT: store i32 [[ADD9]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP21]]7906// CHECK9-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP21]]7907// CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i327908// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV]], 17909// CHECK9-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i167910// CHECK9-NEXT: store i16 [[CONV11]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP21]]7911// CHECK9-NEXT: [[TMP15:%.*]] = load i8, ptr [[AAA]], align 1, !llvm.access.group [[ACC_GRP21]]7912// CHECK9-NEXT: [[CONV12:%.*]] = sext i8 [[TMP15]] to i327913// CHECK9-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 17914// CHECK9-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i87915// CHECK9-NEXT: store i8 [[CONV14]], ptr [[AAA]], align 1, !llvm.access.group [[ACC_GRP21]]7916// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 27917// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]]7918// CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 17919// CHECK9-NEXT: store i32 [[ADD15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]]7920// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]7921// CHECK9: omp.body.continue:7922// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]7923// CHECK9: omp.inner.for.inc:7924// CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]7925// CHECK9-NEXT: [[ADD16:%.*]] = add i32 [[TMP17]], 17926// CHECK9-NEXT: store i32 [[ADD16]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]7927// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]7928// CHECK9: omp.inner.for.end:7929// CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 47930// CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 47931// CHECK9-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 47932// CHECK9-NEXT: [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]7933// CHECK9-NEXT: [[SUB18:%.*]] = sub i32 [[SUB17]], 17934// CHECK9-NEXT: [[ADD19:%.*]] = add i32 [[SUB18]], 17935// CHECK9-NEXT: [[DIV20:%.*]] = udiv i32 [[ADD19]], 17936// CHECK9-NEXT: [[MUL21:%.*]] = mul i32 [[DIV20]], 17937// CHECK9-NEXT: [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]7938// CHECK9-NEXT: store i32 [[ADD22]], ptr [[I5]], align 47939// CHECK9-NEXT: br label [[SIMD_IF_END]]7940// CHECK9: simd.if.end:7941// CHECK9-NEXT: [[TMP21:%.*]] = load i32, ptr [[A]], align 47942// CHECK9-NEXT: ret i32 [[TMP21]]7943//7944//7945// CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i7946// CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {7947// CHECK9-NEXT: entry:7948// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 47949// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 47950// CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 27951// CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 47952// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 47953// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 47954// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 47955// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 47956// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 47957// CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 47958// CHECK9-NEXT: store i32 0, ptr [[A]], align 47959// CHECK9-NEXT: store i16 0, ptr [[AA]], align 27960// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 47961// CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 47962// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 47963// CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 47964// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]7965// CHECK9: omp.inner.for.cond:7966// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]]7967// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]]7968// CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]7969// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]7970// CHECK9: omp.inner.for.body:7971// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]7972// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 17973// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]7974// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]]7975// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP24]]7976// CHECK9-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 17977// CHECK9-NEXT: store i32 [[ADD1]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP24]]7978// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP24]]7979// CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i327980// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 17981// CHECK9-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i167982// CHECK9-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP24]]7983// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 27984// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]]7985// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 17986// CHECK9-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]]7987// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]7988// CHECK9: omp.body.continue:7989// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]7990// CHECK9: omp.inner.for.inc:7991// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]7992// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP7]], 17993// CHECK9-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]7994// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]7995// CHECK9: omp.inner.for.end:7996// CHECK9-NEXT: store i32 10, ptr [[I]], align 47997// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 47998// CHECK9-NEXT: ret i32 [[TMP8]]7999//8000//8001// CHECK11-LABEL: define {{[^@]+}}@_Z3fooi8002// CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {8003// CHECK11-NEXT: entry:8004// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48005// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 48006// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 28007// CHECK11-NEXT: [[B:%.*]] = alloca [10 x float], align 48008// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 48009// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 48010// CHECK11-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 88011// CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 48012// CHECK11-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 48013// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 48014// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 48015// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 48016// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 48017// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 48018// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 48019// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 48020// CHECK11-NEXT: [[_TMP4:%.*]] = alloca i32, align 48021// CHECK11-NEXT: [[DOTOMP_LB5:%.*]] = alloca i32, align 48022// CHECK11-NEXT: [[DOTOMP_UB6:%.*]] = alloca i32, align 48023// CHECK11-NEXT: [[DOTOMP_IV7:%.*]] = alloca i32, align 48024// CHECK11-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 48025// CHECK11-NEXT: [[A8:%.*]] = alloca i32, align 48026// CHECK11-NEXT: [[A9:%.*]] = alloca i32, align 48027// CHECK11-NEXT: [[_TMP20:%.*]] = alloca i32, align 48028// CHECK11-NEXT: [[DOTOMP_LB21:%.*]] = alloca i32, align 48029// CHECK11-NEXT: [[DOTOMP_UB22:%.*]] = alloca i32, align 48030// CHECK11-NEXT: [[DOTOMP_IV23:%.*]] = alloca i32, align 48031// CHECK11-NEXT: [[I24:%.*]] = alloca i32, align 48032// CHECK11-NEXT: [[_TMP36:%.*]] = alloca i32, align 48033// CHECK11-NEXT: [[DOTOMP_LB37:%.*]] = alloca i32, align 48034// CHECK11-NEXT: [[DOTOMP_UB38:%.*]] = alloca i32, align 48035// CHECK11-NEXT: [[DOTOMP_IV39:%.*]] = alloca i32, align 48036// CHECK11-NEXT: [[I40:%.*]] = alloca i32, align 48037// CHECK11-NEXT: [[_TMP54:%.*]] = alloca i32, align 48038// CHECK11-NEXT: [[DOTOMP_LB55:%.*]] = alloca i32, align 48039// CHECK11-NEXT: [[DOTOMP_UB56:%.*]] = alloca i32, align 48040// CHECK11-NEXT: [[DOTOMP_IV57:%.*]] = alloca i32, align 48041// CHECK11-NEXT: [[I58:%.*]] = alloca i32, align 48042// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48043// CHECK11-NEXT: store i32 0, ptr [[A]], align 48044// CHECK11-NEXT: store i16 0, ptr [[AA]], align 28045// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 48046// CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()8047// CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 48048// CHECK11-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 48049// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 48050// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 48051// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]8052// CHECK11-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 88053// CHECK11-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 48054// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 48055// CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 48056// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 48057// CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_2]], align 48058// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 48059// CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 48060// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 48061// CHECK11-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 48062// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]8063// CHECK11: omp.inner.for.cond:8064// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]8065// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]]8066// CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]8067// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]8068// CHECK11: omp.inner.for.body:8069// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]8070// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 18071// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]8072// CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]8073// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]8074// CHECK11: omp.body.continue:8075// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]8076// CHECK11: omp.inner.for.inc:8077// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]8078// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 18079// CHECK11-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]8080// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]8081// CHECK11: omp.inner.for.end:8082// CHECK11-NEXT: store i32 10, ptr [[I]], align 48083// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB5]], align 48084// CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB6]], align 48085// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB5]], align 48086// CHECK11-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV7]], align 48087// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[A]], align 48088// CHECK11-NEXT: store i32 [[TMP12]], ptr [[DOTLINEAR_START]], align 48089// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND10:%.*]]8090// CHECK11: omp.inner.for.cond10:8091// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 48092// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB6]], align 48093// CHECK11-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]8094// CHECK11-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]8095// CHECK11: omp.inner.for.body12:8096// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 48097// CHECK11-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 18098// CHECK11-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]8099// CHECK11-NEXT: store i32 [[ADD14]], ptr [[A8]], align 48100// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[A8]], align 48101// CHECK11-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 18102// CHECK11-NEXT: store i32 [[ADD15]], ptr [[A8]], align 48103// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]8104// CHECK11: omp.body.continue16:8105// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]8106// CHECK11: omp.inner.for.inc17:8107// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 48108// CHECK11-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 18109// CHECK11-NEXT: store i32 [[ADD18]], ptr [[DOTOMP_IV7]], align 48110// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]]8111// CHECK11: omp.inner.for.end19:8112// CHECK11-NEXT: store i32 10, ptr [[A]], align 48113// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB21]], align 48114// CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB22]], align 48115// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_LB21]], align 48116// CHECK11-NEXT: store i32 [[TMP18]], ptr [[DOTOMP_IV23]], align 48117// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND25:%.*]]8118// CHECK11: omp.inner.for.cond25:8119// CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]]8120// CHECK11-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_UB22]], align 4, !llvm.access.group [[ACC_GRP10]]8121// CHECK11-NEXT: [[CMP26:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]8122// CHECK11-NEXT: br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]8123// CHECK11: omp.inner.for.body27:8124// CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP10]]8125// CHECK11-NEXT: [[MUL28:%.*]] = mul nsw i32 [[TMP21]], 18126// CHECK11-NEXT: [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]8127// CHECK11-NEXT: store i32 [[ADD29]], ptr [[I24]], align 4, !llvm.access.group [[ACC_GRP10]]8128// CHECK11-NEXT: [[TMP22:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP10]]8129// CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP22]] to i328130// CHECK11-NEXT: [[ADD30:%.*]] = add nsw i32 [[CONV]], 18131// CHECK11-NEXT: [[CONV31:%.*]] = trunc i32 [[ADD30]] to i168132// CHECK11-NEXT: store i16 [[CONV31]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP10]]8133// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE32:%.*]]8134// CHECK11: omp.body.continue32:8135// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC33:%.*]]8136// CHECK11: omp.inner.for.inc33:8137// CHECK11-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP10]]8138// CHECK11-NEXT: [[ADD34:%.*]] = add nsw i32 [[TMP23]], 18139// CHECK11-NEXT: store i32 [[ADD34]], ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP10]]8140// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP11:![0-9]+]]8141// CHECK11: omp.inner.for.end35:8142// CHECK11-NEXT: store i32 10, ptr [[I24]], align 48143// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB37]], align 48144// CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB38]], align 48145// CHECK11-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_LB37]], align 48146// CHECK11-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV39]], align 48147// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND41:%.*]]8148// CHECK11: omp.inner.for.cond41:8149// CHECK11-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]]8150// CHECK11-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_UB38]], align 4, !llvm.access.group [[ACC_GRP13]]8151// CHECK11-NEXT: [[CMP42:%.*]] = icmp sle i32 [[TMP25]], [[TMP26]]8152// CHECK11-NEXT: br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]8153// CHECK11: omp.inner.for.body43:8154// CHECK11-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP13]]8155// CHECK11-NEXT: [[MUL44:%.*]] = mul nsw i32 [[TMP27]], 18156// CHECK11-NEXT: [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]8157// CHECK11-NEXT: store i32 [[ADD45]], ptr [[I40]], align 4, !llvm.access.group [[ACC_GRP13]]8158// CHECK11-NEXT: [[TMP28:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP13]]8159// CHECK11-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP28]], 18160// CHECK11-NEXT: store i32 [[ADD46]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP13]]8161// CHECK11-NEXT: [[TMP29:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP13]]8162// CHECK11-NEXT: [[CONV47:%.*]] = sext i16 [[TMP29]] to i328163// CHECK11-NEXT: [[ADD48:%.*]] = add nsw i32 [[CONV47]], 18164// CHECK11-NEXT: [[CONV49:%.*]] = trunc i32 [[ADD48]] to i168165// CHECK11-NEXT: store i16 [[CONV49]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP13]]8166// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE50:%.*]]8167// CHECK11: omp.body.continue50:8168// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC51:%.*]]8169// CHECK11: omp.inner.for.inc51:8170// CHECK11-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP13]]8171// CHECK11-NEXT: [[ADD52:%.*]] = add nsw i32 [[TMP30]], 18172// CHECK11-NEXT: store i32 [[ADD52]], ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP13]]8173// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP14:![0-9]+]]8174// CHECK11: omp.inner.for.end53:8175// CHECK11-NEXT: store i32 10, ptr [[I40]], align 48176// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB55]], align 48177// CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB56]], align 48178// CHECK11-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_LB55]], align 48179// CHECK11-NEXT: store i32 [[TMP31]], ptr [[DOTOMP_IV57]], align 48180// CHECK11-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 08181// CHECK11-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i32 16) ]8182// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND59:%.*]]8183// CHECK11: omp.inner.for.cond59:8184// CHECK11-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]]8185// CHECK11-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_UB56]], align 4, !llvm.access.group [[ACC_GRP16]]8186// CHECK11-NEXT: [[CMP60:%.*]] = icmp sle i32 [[TMP32]], [[TMP33]]8187// CHECK11-NEXT: br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]8188// CHECK11: omp.inner.for.body61:8189// CHECK11-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP16]]8190// CHECK11-NEXT: [[MUL62:%.*]] = mul nsw i32 [[TMP34]], 18191// CHECK11-NEXT: [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]8192// CHECK11-NEXT: store i32 [[ADD63]], ptr [[I58]], align 4, !llvm.access.group [[ACC_GRP16]]8193// CHECK11-NEXT: [[TMP35:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]]8194// CHECK11-NEXT: [[ADD64:%.*]] = add nsw i32 [[TMP35]], 18195// CHECK11-NEXT: store i32 [[ADD64]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]]8196// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 28197// CHECK11-NEXT: [[TMP36:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]]8198// CHECK11-NEXT: [[CONV65:%.*]] = fpext float [[TMP36]] to double8199// CHECK11-NEXT: [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+008200// CHECK11-NEXT: [[CONV67:%.*]] = fptrunc double [[ADD66]] to float8201// CHECK11-NEXT: store float [[CONV67]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]]8202// CHECK11-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds float, ptr [[VLA]], i32 38203// CHECK11-NEXT: [[TMP37:%.*]] = load float, ptr [[ARRAYIDX68]], align 4, !llvm.access.group [[ACC_GRP16]]8204// CHECK11-NEXT: [[CONV69:%.*]] = fpext float [[TMP37]] to double8205// CHECK11-NEXT: [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+008206// CHECK11-NEXT: [[CONV71:%.*]] = fptrunc double [[ADD70]] to float8207// CHECK11-NEXT: store float [[CONV71]], ptr [[ARRAYIDX68]], align 4, !llvm.access.group [[ACC_GRP16]]8208// CHECK11-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 18209// CHECK11-NEXT: [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX72]], i32 0, i32 28210// CHECK11-NEXT: [[TMP38:%.*]] = load double, ptr [[ARRAYIDX73]], align 8, !llvm.access.group [[ACC_GRP16]]8211// CHECK11-NEXT: [[ADD74:%.*]] = fadd double [[TMP38]], 1.000000e+008212// CHECK11-NEXT: store double [[ADD74]], ptr [[ARRAYIDX73]], align 8, !llvm.access.group [[ACC_GRP16]]8213// CHECK11-NEXT: [[TMP39:%.*]] = mul nsw i32 1, [[TMP2]]8214// CHECK11-NEXT: [[ARRAYIDX75:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i32 [[TMP39]]8215// CHECK11-NEXT: [[ARRAYIDX76:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX75]], i32 38216// CHECK11-NEXT: [[TMP40:%.*]] = load double, ptr [[ARRAYIDX76]], align 8, !llvm.access.group [[ACC_GRP16]]8217// CHECK11-NEXT: [[ADD77:%.*]] = fadd double [[TMP40]], 1.000000e+008218// CHECK11-NEXT: store double [[ADD77]], ptr [[ARRAYIDX76]], align 8, !llvm.access.group [[ACC_GRP16]]8219// CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 08220// CHECK11-NEXT: [[TMP41:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP16]]8221// CHECK11-NEXT: [[ADD78:%.*]] = add nsw i64 [[TMP41]], 18222// CHECK11-NEXT: store i64 [[ADD78]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP16]]8223// CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 18224// CHECK11-NEXT: [[TMP42:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP16]]8225// CHECK11-NEXT: [[CONV79:%.*]] = sext i8 [[TMP42]] to i328226// CHECK11-NEXT: [[ADD80:%.*]] = add nsw i32 [[CONV79]], 18227// CHECK11-NEXT: [[CONV81:%.*]] = trunc i32 [[ADD80]] to i88228// CHECK11-NEXT: store i8 [[CONV81]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP16]]8229// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE82:%.*]]8230// CHECK11: omp.body.continue82:8231// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC83:%.*]]8232// CHECK11: omp.inner.for.inc83:8233// CHECK11-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP16]]8234// CHECK11-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP43]], 18235// CHECK11-NEXT: store i32 [[ADD84]], ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP16]]8236// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP17:![0-9]+]]8237// CHECK11: omp.inner.for.end85:8238// CHECK11-NEXT: store i32 10, ptr [[I58]], align 48239// CHECK11-NEXT: [[TMP44:%.*]] = load i32, ptr [[A]], align 48240// CHECK11-NEXT: [[TMP45:%.*]] = load ptr, ptr [[SAVED_STACK]], align 48241// CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP45]])8242// CHECK11-NEXT: ret i32 [[TMP44]]8243//8244//8245// CHECK11-LABEL: define {{[^@]+}}@_Z3bari8246// CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {8247// CHECK11-NEXT: entry:8248// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48249// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 48250// CHECK11-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 48251// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48252// CHECK11-NEXT: store i32 0, ptr [[A]], align 48253// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 48254// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])8255// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 48256// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]8257// CHECK11-NEXT: store i32 [[ADD]], ptr [[A]], align 48258// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 48259// CHECK11-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])8260// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 48261// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]8262// CHECK11-NEXT: store i32 [[ADD2]], ptr [[A]], align 48263// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 48264// CHECK11-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])8265// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 48266// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]8267// CHECK11-NEXT: store i32 [[ADD4]], ptr [[A]], align 48268// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 48269// CHECK11-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])8270// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 48271// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]8272// CHECK11-NEXT: store i32 [[ADD6]], ptr [[A]], align 48273// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 48274// CHECK11-NEXT: ret i32 [[TMP8]]8275//8276//8277// CHECK11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei8278// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {8279// CHECK11-NEXT: entry:8280// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 48281// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48282// CHECK11-NEXT: [[B:%.*]] = alloca i32, align 48283// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 48284// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 48285// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 48286// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 48287// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 48288// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 48289// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 48290// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 48291// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48292// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 48293// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 48294// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 18295// CHECK11-NEXT: store i32 [[ADD]], ptr [[B]], align 48296// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 48297// CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()8298// CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 48299// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]8300// CHECK11-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 28301// CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 48302// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 48303// CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 48304// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 48305// CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 48306// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]8307// CHECK11: omp.inner.for.cond:8308// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]]8309// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]]8310// CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]8311// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]8312// CHECK11: omp.inner.for.body:8313// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]8314// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 18315// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 0, [[MUL]]8316// CHECK11-NEXT: store i32 [[ADD2]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]]8317// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP19]]8318// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double8319// CHECK11-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+008320// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 08321// CHECK11-NEXT: store double [[ADD3]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP19]]8322// CHECK11-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 08323// CHECK11-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 4, !llvm.access.group [[ACC_GRP19]]8324// CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+008325// CHECK11-NEXT: store double [[INC]], ptr [[A4]], align 4, !llvm.access.group [[ACC_GRP19]]8326// CHECK11-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i168327// CHECK11-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]]8328// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP10]]8329// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 18330// CHECK11-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP19]]8331// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]8332// CHECK11: omp.body.continue:8333// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]8334// CHECK11: omp.inner.for.inc:8335// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]8336// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 18337// CHECK11-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]8338// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]8339// CHECK11: omp.inner.for.end:8340// CHECK11-NEXT: store i32 10, ptr [[I]], align 48341// CHECK11-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]8342// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP12]]8343// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX8]], i32 18344// CHECK11-NEXT: [[TMP13:%.*]] = load i16, ptr [[ARRAYIDX9]], align 28345// CHECK11-NEXT: [[CONV10:%.*]] = sext i16 [[TMP13]] to i328346// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[B]], align 48347// CHECK11-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV10]], [[TMP14]]8348// CHECK11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 48349// CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])8350// CHECK11-NEXT: ret i32 [[ADD11]]8351//8352//8353// CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici8354// CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {8355// CHECK11-NEXT: entry:8356// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48357// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 48358// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 28359// CHECK11-NEXT: [[AAA:%.*]] = alloca i8, align 18360// CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 48361// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 48362// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 48363// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 48364// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 48365// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 48366// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 48367// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 48368// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 48369// CHECK11-NEXT: [[I5:%.*]] = alloca i32, align 48370// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48371// CHECK11-NEXT: store i32 0, ptr [[A]], align 48372// CHECK11-NEXT: store i16 0, ptr [[AA]], align 28373// CHECK11-NEXT: store i8 0, ptr [[AAA]], align 18374// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 48375// CHECK11-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 48376// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 48377// CHECK11-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_1]], align 48378// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 48379// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 48380// CHECK11-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]8381// CHECK11-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 18382// CHECK11-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 18383// CHECK11-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 18384// CHECK11-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 18385// CHECK11-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 48386// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 48387// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 48388// CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 48389// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 48390// CHECK11-NEXT: store i32 [[TMP5]], ptr [[I]], align 48391// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 48392// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 48393// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]8394// CHECK11-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]8395// CHECK11: simd.if.then:8396// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 48397// CHECK11-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 48398// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]8399// CHECK11: omp.inner.for.cond:8400// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]]8401// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]]8402// CHECK11-NEXT: [[ADD6:%.*]] = add i32 [[TMP10]], 18403// CHECK11-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]8404// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]8405// CHECK11: omp.inner.for.body:8406// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP22]]8407// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]8408// CHECK11-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 18409// CHECK11-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]8410// CHECK11-NEXT: store i32 [[ADD8]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP22]]8411// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP22]]8412// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 18413// CHECK11-NEXT: store i32 [[ADD9]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP22]]8414// CHECK11-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP22]]8415// CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i328416// CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV]], 18417// CHECK11-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i168418// CHECK11-NEXT: store i16 [[CONV11]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP22]]8419// CHECK11-NEXT: [[TMP15:%.*]] = load i8, ptr [[AAA]], align 1, !llvm.access.group [[ACC_GRP22]]8420// CHECK11-NEXT: [[CONV12:%.*]] = sext i8 [[TMP15]] to i328421// CHECK11-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 18422// CHECK11-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i88423// CHECK11-NEXT: store i8 [[CONV14]], ptr [[AAA]], align 1, !llvm.access.group [[ACC_GRP22]]8424// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 28425// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]]8426// CHECK11-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 18427// CHECK11-NEXT: store i32 [[ADD15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]]8428// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]8429// CHECK11: omp.body.continue:8430// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]8431// CHECK11: omp.inner.for.inc:8432// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]8433// CHECK11-NEXT: [[ADD16:%.*]] = add i32 [[TMP17]], 18434// CHECK11-NEXT: store i32 [[ADD16]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]8435// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]8436// CHECK11: omp.inner.for.end:8437// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 48438// CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 48439// CHECK11-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 48440// CHECK11-NEXT: [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]8441// CHECK11-NEXT: [[SUB18:%.*]] = sub i32 [[SUB17]], 18442// CHECK11-NEXT: [[ADD19:%.*]] = add i32 [[SUB18]], 18443// CHECK11-NEXT: [[DIV20:%.*]] = udiv i32 [[ADD19]], 18444// CHECK11-NEXT: [[MUL21:%.*]] = mul i32 [[DIV20]], 18445// CHECK11-NEXT: [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]8446// CHECK11-NEXT: store i32 [[ADD22]], ptr [[I5]], align 48447// CHECK11-NEXT: br label [[SIMD_IF_END]]8448// CHECK11: simd.if.end:8449// CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[A]], align 48450// CHECK11-NEXT: ret i32 [[TMP21]]8451//8452//8453// CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i8454// CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {8455// CHECK11-NEXT: entry:8456// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48457// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 48458// CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 28459// CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 48460// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 48461// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 48462// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 48463// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 48464// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 48465// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48466// CHECK11-NEXT: store i32 0, ptr [[A]], align 48467// CHECK11-NEXT: store i16 0, ptr [[AA]], align 28468// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 48469// CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 48470// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 48471// CHECK11-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 48472// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]8473// CHECK11: omp.inner.for.cond:8474// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]]8475// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP25]]8476// CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]8477// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]8478// CHECK11: omp.inner.for.body:8479// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]8480// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 18481// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]8482// CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]]8483// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP25]]8484// CHECK11-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 18485// CHECK11-NEXT: store i32 [[ADD1]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP25]]8486// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP25]]8487// CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i328488// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 18489// CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i168490// CHECK11-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP25]]8491// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 28492// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]8493// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 18494// CHECK11-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]8495// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]8496// CHECK11: omp.body.continue:8497// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]8498// CHECK11: omp.inner.for.inc:8499// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]8500// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP7]], 18501// CHECK11-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]8502// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]8503// CHECK11: omp.inner.for.end:8504// CHECK11-NEXT: store i32 10, ptr [[I]], align 48505// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 48506// CHECK11-NEXT: ret i32 [[TMP8]]8507//8508//8509// CHECK13-LABEL: define {{[^@]+}}@_Z3fooi8510// CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {8511// CHECK13-NEXT: entry:8512// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48513// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 48514// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 28515// CHECK13-NEXT: [[B:%.*]] = alloca [10 x float], align 48516// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 88517// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 88518// CHECK13-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 88519// CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 88520// CHECK13-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 88521// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 48522// CHECK13-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 48523// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 48524// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 48525// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 48526// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 48527// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 48528// CHECK13-NEXT: [[_TMP4:%.*]] = alloca i32, align 48529// CHECK13-NEXT: [[DOTOMP_LB5:%.*]] = alloca i32, align 48530// CHECK13-NEXT: [[DOTOMP_UB6:%.*]] = alloca i32, align 48531// CHECK13-NEXT: [[DOTOMP_IV7:%.*]] = alloca i32, align 48532// CHECK13-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 48533// CHECK13-NEXT: [[A8:%.*]] = alloca i32, align 48534// CHECK13-NEXT: [[A9:%.*]] = alloca i32, align 48535// CHECK13-NEXT: [[_TMP20:%.*]] = alloca i32, align 48536// CHECK13-NEXT: [[DOTOMP_LB21:%.*]] = alloca i32, align 48537// CHECK13-NEXT: [[DOTOMP_UB22:%.*]] = alloca i32, align 48538// CHECK13-NEXT: [[DOTOMP_IV23:%.*]] = alloca i32, align 48539// CHECK13-NEXT: [[I24:%.*]] = alloca i32, align 48540// CHECK13-NEXT: [[_TMP36:%.*]] = alloca i32, align 48541// CHECK13-NEXT: [[DOTOMP_LB37:%.*]] = alloca i32, align 48542// CHECK13-NEXT: [[DOTOMP_UB38:%.*]] = alloca i32, align 48543// CHECK13-NEXT: [[DOTOMP_IV39:%.*]] = alloca i32, align 48544// CHECK13-NEXT: [[I40:%.*]] = alloca i32, align 48545// CHECK13-NEXT: [[_TMP54:%.*]] = alloca i32, align 48546// CHECK13-NEXT: [[DOTOMP_LB55:%.*]] = alloca i32, align 48547// CHECK13-NEXT: [[DOTOMP_UB56:%.*]] = alloca i32, align 48548// CHECK13-NEXT: [[DOTOMP_IV57:%.*]] = alloca i32, align 48549// CHECK13-NEXT: [[I58:%.*]] = alloca i32, align 48550// CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48551// CHECK13-NEXT: store i32 0, ptr [[A]], align 48552// CHECK13-NEXT: store i16 0, ptr [[AA]], align 28553// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 48554// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i648555// CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()8556// CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 88557// CHECK13-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 48558// CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 88559// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 48560// CHECK13-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i648561// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]8562// CHECK13-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 88563// CHECK13-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 88564// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 48565// CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 48566// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 48567// CHECK13-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_2]], align 48568// CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 48569// CHECK13-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 48570// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 48571// CHECK13-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 48572// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]8573// CHECK13: omp.inner.for.cond:8574// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]8575// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]8576// CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]8577// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]8578// CHECK13: omp.inner.for.body:8579// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]8580// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 18581// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]8582// CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]8583// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]8584// CHECK13: omp.body.continue:8585// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]8586// CHECK13: omp.inner.for.inc:8587// CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]8588// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 18589// CHECK13-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]8590// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]8591// CHECK13: omp.inner.for.end:8592// CHECK13-NEXT: store i32 10, ptr [[I]], align 48593// CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB5]], align 48594// CHECK13-NEXT: store i32 9, ptr [[DOTOMP_UB6]], align 48595// CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB5]], align 48596// CHECK13-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV7]], align 48597// CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 48598// CHECK13-NEXT: store i32 [[TMP14]], ptr [[DOTLINEAR_START]], align 48599// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND10:%.*]]8600// CHECK13: omp.inner.for.cond10:8601// CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 48602// CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB6]], align 48603// CHECK13-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]8604// CHECK13-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]8605// CHECK13: omp.inner.for.body12:8606// CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 48607// CHECK13-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 18608// CHECK13-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]8609// CHECK13-NEXT: store i32 [[ADD14]], ptr [[A8]], align 4, !nontemporal [[META7:![0-9]+]]8610// CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[A8]], align 4, !nontemporal [[META7]]8611// CHECK13-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 18612// CHECK13-NEXT: store i32 [[ADD15]], ptr [[A8]], align 4, !nontemporal [[META7]]8613// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]8614// CHECK13: omp.body.continue16:8615// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]8616// CHECK13: omp.inner.for.inc17:8617// CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 48618// CHECK13-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 18619// CHECK13-NEXT: store i32 [[ADD18]], ptr [[DOTOMP_IV7]], align 48620// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]]8621// CHECK13: omp.inner.for.end19:8622// CHECK13-NEXT: store i32 10, ptr [[A]], align 48623// CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB21]], align 48624// CHECK13-NEXT: store i32 9, ptr [[DOTOMP_UB22]], align 48625// CHECK13-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB21]], align 48626// CHECK13-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV23]], align 48627// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND25:%.*]]8628// CHECK13: omp.inner.for.cond25:8629// CHECK13-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]]8630// CHECK13-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB22]], align 4, !llvm.access.group [[ACC_GRP10]]8631// CHECK13-NEXT: [[CMP26:%.*]] = icmp sle i32 [[TMP21]], [[TMP22]]8632// CHECK13-NEXT: br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]8633// CHECK13: omp.inner.for.body27:8634// CHECK13-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP10]]8635// CHECK13-NEXT: [[MUL28:%.*]] = mul nsw i32 [[TMP23]], 18636// CHECK13-NEXT: [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]8637// CHECK13-NEXT: store i32 [[ADD29]], ptr [[I24]], align 4, !llvm.access.group [[ACC_GRP10]]8638// CHECK13-NEXT: [[TMP24:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP10]]8639// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP24]] to i328640// CHECK13-NEXT: [[ADD30:%.*]] = add nsw i32 [[CONV]], 18641// CHECK13-NEXT: [[CONV31:%.*]] = trunc i32 [[ADD30]] to i168642// CHECK13-NEXT: store i16 [[CONV31]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP10]]8643// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE32:%.*]]8644// CHECK13: omp.body.continue32:8645// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC33:%.*]]8646// CHECK13: omp.inner.for.inc33:8647// CHECK13-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP10]]8648// CHECK13-NEXT: [[ADD34:%.*]] = add nsw i32 [[TMP25]], 18649// CHECK13-NEXT: store i32 [[ADD34]], ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP10]]8650// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP11:![0-9]+]]8651// CHECK13: omp.inner.for.end35:8652// CHECK13-NEXT: store i32 10, ptr [[I24]], align 48653// CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB37]], align 48654// CHECK13-NEXT: store i32 9, ptr [[DOTOMP_UB38]], align 48655// CHECK13-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB37]], align 48656// CHECK13-NEXT: store i32 [[TMP26]], ptr [[DOTOMP_IV39]], align 48657// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND41:%.*]]8658// CHECK13: omp.inner.for.cond41:8659// CHECK13-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]]8660// CHECK13-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB38]], align 4, !llvm.access.group [[ACC_GRP13]]8661// CHECK13-NEXT: [[CMP42:%.*]] = icmp sle i32 [[TMP27]], [[TMP28]]8662// CHECK13-NEXT: br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]8663// CHECK13: omp.inner.for.body43:8664// CHECK13-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP13]]8665// CHECK13-NEXT: [[MUL44:%.*]] = mul nsw i32 [[TMP29]], 18666// CHECK13-NEXT: [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]8667// CHECK13-NEXT: store i32 [[ADD45]], ptr [[I40]], align 4, !llvm.access.group [[ACC_GRP13]]8668// CHECK13-NEXT: [[TMP30:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP13]]8669// CHECK13-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP30]], 18670// CHECK13-NEXT: store i32 [[ADD46]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP13]]8671// CHECK13-NEXT: [[TMP31:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP13]]8672// CHECK13-NEXT: [[CONV47:%.*]] = sext i16 [[TMP31]] to i328673// CHECK13-NEXT: [[ADD48:%.*]] = add nsw i32 [[CONV47]], 18674// CHECK13-NEXT: [[CONV49:%.*]] = trunc i32 [[ADD48]] to i168675// CHECK13-NEXT: store i16 [[CONV49]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP13]]8676// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE50:%.*]]8677// CHECK13: omp.body.continue50:8678// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC51:%.*]]8679// CHECK13: omp.inner.for.inc51:8680// CHECK13-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP13]]8681// CHECK13-NEXT: [[ADD52:%.*]] = add nsw i32 [[TMP32]], 18682// CHECK13-NEXT: store i32 [[ADD52]], ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP13]]8683// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP14:![0-9]+]]8684// CHECK13: omp.inner.for.end53:8685// CHECK13-NEXT: store i32 10, ptr [[I40]], align 48686// CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB55]], align 48687// CHECK13-NEXT: store i32 9, ptr [[DOTOMP_UB56]], align 48688// CHECK13-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_LB55]], align 48689// CHECK13-NEXT: store i32 [[TMP33]], ptr [[DOTOMP_IV57]], align 48690// CHECK13-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 08691// CHECK13-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i64 16) ]8692// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND59:%.*]]8693// CHECK13: omp.inner.for.cond59:8694// CHECK13-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]]8695// CHECK13-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_UB56]], align 4, !llvm.access.group [[ACC_GRP16]]8696// CHECK13-NEXT: [[CMP60:%.*]] = icmp sle i32 [[TMP34]], [[TMP35]]8697// CHECK13-NEXT: br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]8698// CHECK13: omp.inner.for.body61:8699// CHECK13-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP16]]8700// CHECK13-NEXT: [[MUL62:%.*]] = mul nsw i32 [[TMP36]], 18701// CHECK13-NEXT: [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]8702// CHECK13-NEXT: store i32 [[ADD63]], ptr [[I58]], align 4, !llvm.access.group [[ACC_GRP16]]8703// CHECK13-NEXT: [[TMP37:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]]8704// CHECK13-NEXT: [[ADD64:%.*]] = add nsw i32 [[TMP37]], 18705// CHECK13-NEXT: store i32 [[ADD64]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]]8706// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 28707// CHECK13-NEXT: [[TMP38:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]]8708// CHECK13-NEXT: [[CONV65:%.*]] = fpext float [[TMP38]] to double8709// CHECK13-NEXT: [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+008710// CHECK13-NEXT: [[CONV67:%.*]] = fptrunc double [[ADD66]] to float8711// CHECK13-NEXT: store float [[CONV67]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]]8712// CHECK13-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds float, ptr [[VLA]], i64 38713// CHECK13-NEXT: [[TMP39:%.*]] = load float, ptr [[ARRAYIDX68]], align 4, !llvm.access.group [[ACC_GRP16]]8714// CHECK13-NEXT: [[CONV69:%.*]] = fpext float [[TMP39]] to double8715// CHECK13-NEXT: [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+008716// CHECK13-NEXT: [[CONV71:%.*]] = fptrunc double [[ADD70]] to float8717// CHECK13-NEXT: store float [[CONV71]], ptr [[ARRAYIDX68]], align 4, !llvm.access.group [[ACC_GRP16]]8718// CHECK13-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 18719// CHECK13-NEXT: [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX72]], i64 0, i64 28720// CHECK13-NEXT: [[TMP40:%.*]] = load double, ptr [[ARRAYIDX73]], align 8, !llvm.access.group [[ACC_GRP16]]8721// CHECK13-NEXT: [[ADD74:%.*]] = fadd double [[TMP40]], 1.000000e+008722// CHECK13-NEXT: store double [[ADD74]], ptr [[ARRAYIDX73]], align 8, !llvm.access.group [[ACC_GRP16]]8723// CHECK13-NEXT: [[TMP41:%.*]] = mul nsw i64 1, [[TMP4]]8724// CHECK13-NEXT: [[ARRAYIDX75:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i64 [[TMP41]]8725// CHECK13-NEXT: [[ARRAYIDX76:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX75]], i64 38726// CHECK13-NEXT: [[TMP42:%.*]] = load double, ptr [[ARRAYIDX76]], align 8, !llvm.access.group [[ACC_GRP16]]8727// CHECK13-NEXT: [[ADD77:%.*]] = fadd double [[TMP42]], 1.000000e+008728// CHECK13-NEXT: store double [[ADD77]], ptr [[ARRAYIDX76]], align 8, !llvm.access.group [[ACC_GRP16]]8729// CHECK13-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 08730// CHECK13-NEXT: [[TMP43:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP16]]8731// CHECK13-NEXT: [[ADD78:%.*]] = add nsw i64 [[TMP43]], 18732// CHECK13-NEXT: store i64 [[ADD78]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP16]]8733// CHECK13-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 18734// CHECK13-NEXT: [[TMP44:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP16]]8735// CHECK13-NEXT: [[CONV79:%.*]] = sext i8 [[TMP44]] to i328736// CHECK13-NEXT: [[ADD80:%.*]] = add nsw i32 [[CONV79]], 18737// CHECK13-NEXT: [[CONV81:%.*]] = trunc i32 [[ADD80]] to i88738// CHECK13-NEXT: store i8 [[CONV81]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP16]]8739// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE82:%.*]]8740// CHECK13: omp.body.continue82:8741// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC83:%.*]]8742// CHECK13: omp.inner.for.inc83:8743// CHECK13-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP16]]8744// CHECK13-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP45]], 18745// CHECK13-NEXT: store i32 [[ADD84]], ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP16]]8746// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP17:![0-9]+]]8747// CHECK13: omp.inner.for.end85:8748// CHECK13-NEXT: store i32 10, ptr [[I58]], align 48749// CHECK13-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 48750// CHECK13-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 88751// CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])8752// CHECK13-NEXT: ret i32 [[TMP46]]8753//8754//8755// CHECK13-LABEL: define {{[^@]+}}@_Z3bari8756// CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {8757// CHECK13-NEXT: entry:8758// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48759// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 48760// CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 88761// CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48762// CHECK13-NEXT: store i32 0, ptr [[A]], align 48763// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 48764// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])8765// CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 48766// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]8767// CHECK13-NEXT: store i32 [[ADD]], ptr [[A]], align 48768// CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 48769// CHECK13-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])8770// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 48771// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]8772// CHECK13-NEXT: store i32 [[ADD2]], ptr [[A]], align 48773// CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 48774// CHECK13-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])8775// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 48776// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]8777// CHECK13-NEXT: store i32 [[ADD4]], ptr [[A]], align 48778// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 48779// CHECK13-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])8780// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 48781// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]8782// CHECK13-NEXT: store i32 [[ADD6]], ptr [[A]], align 48783// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 48784// CHECK13-NEXT: ret i32 [[TMP8]]8785//8786//8787// CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei8788// CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {8789// CHECK13-NEXT: entry:8790// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 88791// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48792// CHECK13-NEXT: [[B:%.*]] = alloca i32, align 48793// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 88794// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 88795// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 18796// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 48797// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 48798// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 48799// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 48800// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 48801// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 88802// CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48803// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 88804// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 48805// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 18806// CHECK13-NEXT: store i32 [[ADD]], ptr [[B]], align 48807// CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 48808// CHECK13-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i648809// CHECK13-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()8810// CHECK13-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 88811// CHECK13-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]8812// CHECK13-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 28813// CHECK13-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 88814// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 48815// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 608816// CHECK13-NEXT: [[STOREDV:%.*]] = zext i1 [[CMP]] to i88817// CHECK13-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 18818// CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 48819// CHECK13-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 48820// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 48821// CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 48822// CHECK13-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 18823// CHECK13-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP7]] to i18824// CHECK13-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]8825// CHECK13: omp_if.then:8826// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]8827// CHECK13: omp.inner.for.cond:8828// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]]8829// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]]8830// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]8831// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]8832// CHECK13: omp.inner.for.body:8833// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]8834// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 18835// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]]8836// CHECK13-NEXT: store i32 [[ADD3]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]]8837// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP19]]8838// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP11]] to double8839// CHECK13-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+008840// CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 08841// CHECK13-NEXT: store double [[ADD4]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP19]]8842// CHECK13-NEXT: [[A5:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 08843// CHECK13-NEXT: [[TMP12:%.*]] = load double, ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP19]]8844// CHECK13-NEXT: [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+008845// CHECK13-NEXT: store double [[INC]], ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP19]]8846// CHECK13-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i168847// CHECK13-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]8848// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP13]]8849// CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 18850// CHECK13-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP19]]8851// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]8852// CHECK13: omp.body.continue:8853// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]8854// CHECK13: omp.inner.for.inc:8855// CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]8856// CHECK13-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP14]], 18857// CHECK13-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]8858// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]8859// CHECK13: omp.inner.for.end:8860// CHECK13-NEXT: br label [[OMP_IF_END:%.*]]8861// CHECK13: omp_if.else:8862// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]8863// CHECK13: omp.inner.for.cond9:8864// CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 48865// CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 48866// CHECK13-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]8867// CHECK13-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]]8868// CHECK13: omp.inner.for.body11:8869// CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 48870// CHECK13-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP17]], 18871// CHECK13-NEXT: [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]8872// CHECK13-NEXT: store i32 [[ADD13]], ptr [[I]], align 48873// CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[B]], align 48874// CHECK13-NEXT: [[CONV14:%.*]] = sitofp i32 [[TMP18]] to double8875// CHECK13-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+008876// CHECK13-NEXT: [[A16:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 08877// CHECK13-NEXT: store double [[ADD15]], ptr [[A16]], align 88878// CHECK13-NEXT: [[A17:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 08879// CHECK13-NEXT: [[TMP19:%.*]] = load double, ptr [[A17]], align 88880// CHECK13-NEXT: [[INC18:%.*]] = fadd double [[TMP19]], 1.000000e+008881// CHECK13-NEXT: store double [[INC18]], ptr [[A17]], align 88882// CHECK13-NEXT: [[CONV19:%.*]] = fptosi double [[INC18]] to i168883// CHECK13-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]]8884// CHECK13-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP20]]8885// CHECK13-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX20]], i64 18886// CHECK13-NEXT: store i16 [[CONV19]], ptr [[ARRAYIDX21]], align 28887// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE22:%.*]]8888// CHECK13: omp.body.continue22:8889// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC23:%.*]]8890// CHECK13: omp.inner.for.inc23:8891// CHECK13-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV]], align 48892// CHECK13-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP21]], 18893// CHECK13-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 48894// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP22:![0-9]+]]8895// CHECK13: omp.inner.for.end25:8896// CHECK13-NEXT: br label [[OMP_IF_END]]8897// CHECK13: omp_if.end:8898// CHECK13-NEXT: store i32 10, ptr [[I]], align 48899// CHECK13-NEXT: [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]8900// CHECK13-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP22]]8901// CHECK13-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX26]], i64 18902// CHECK13-NEXT: [[TMP23:%.*]] = load i16, ptr [[ARRAYIDX27]], align 28903// CHECK13-NEXT: [[CONV28:%.*]] = sext i16 [[TMP23]] to i328904// CHECK13-NEXT: [[TMP24:%.*]] = load i32, ptr [[B]], align 48905// CHECK13-NEXT: [[ADD29:%.*]] = add nsw i32 [[CONV28]], [[TMP24]]8906// CHECK13-NEXT: [[TMP25:%.*]] = load ptr, ptr [[SAVED_STACK]], align 88907// CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP25]])8908// CHECK13-NEXT: ret i32 [[ADD29]]8909//8910//8911// CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici8912// CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {8913// CHECK13-NEXT: entry:8914// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 48915// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 48916// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 28917// CHECK13-NEXT: [[AAA:%.*]] = alloca i8, align 18918// CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 48919// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 48920// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 48921// CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 48922// CHECK13-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 48923// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 48924// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 48925// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 48926// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 48927// CHECK13-NEXT: [[I5:%.*]] = alloca i32, align 48928// CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 48929// CHECK13-NEXT: store i32 0, ptr [[A]], align 48930// CHECK13-NEXT: store i16 0, ptr [[AA]], align 28931// CHECK13-NEXT: store i8 0, ptr [[AAA]], align 18932// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 48933// CHECK13-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 48934// CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 48935// CHECK13-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_1]], align 48936// CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 48937// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 48938// CHECK13-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]8939// CHECK13-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 18940// CHECK13-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 18941// CHECK13-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 18942// CHECK13-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 18943// CHECK13-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 48944// CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 48945// CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 48946// CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 48947// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 48948// CHECK13-NEXT: store i32 [[TMP5]], ptr [[I]], align 48949// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 48950// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 48951// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]8952// CHECK13-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]8953// CHECK13: simd.if.then:8954// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 48955// CHECK13-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 48956// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]8957// CHECK13: omp.inner.for.cond:8958// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]]8959// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]]8960// CHECK13-NEXT: [[ADD6:%.*]] = add i32 [[TMP10]], 18961// CHECK13-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]8962// CHECK13-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]8963// CHECK13: omp.inner.for.body:8964// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP24]]8965// CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]8966// CHECK13-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 18967// CHECK13-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]8968// CHECK13-NEXT: store i32 [[ADD8]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP24]]8969// CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP24]]8970// CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 18971// CHECK13-NEXT: store i32 [[ADD9]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP24]]8972// CHECK13-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP24]]8973// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i328974// CHECK13-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV]], 18975// CHECK13-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i168976// CHECK13-NEXT: store i16 [[CONV11]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP24]]8977// CHECK13-NEXT: [[TMP15:%.*]] = load i8, ptr [[AAA]], align 1, !llvm.access.group [[ACC_GRP24]]8978// CHECK13-NEXT: [[CONV12:%.*]] = sext i8 [[TMP15]] to i328979// CHECK13-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 18980// CHECK13-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i88981// CHECK13-NEXT: store i8 [[CONV14]], ptr [[AAA]], align 1, !llvm.access.group [[ACC_GRP24]]8982// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 28983// CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]]8984// CHECK13-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 18985// CHECK13-NEXT: store i32 [[ADD15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]]8986// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]8987// CHECK13: omp.body.continue:8988// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]8989// CHECK13: omp.inner.for.inc:8990// CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]8991// CHECK13-NEXT: [[ADD16:%.*]] = add i32 [[TMP17]], 18992// CHECK13-NEXT: store i32 [[ADD16]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]8993// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]8994// CHECK13: omp.inner.for.end:8995// CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 48996// CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 48997// CHECK13-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 48998// CHECK13-NEXT: [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]8999// CHECK13-NEXT: [[SUB18:%.*]] = sub i32 [[SUB17]], 19000// CHECK13-NEXT: [[ADD19:%.*]] = add i32 [[SUB18]], 19001// CHECK13-NEXT: [[DIV20:%.*]] = udiv i32 [[ADD19]], 19002// CHECK13-NEXT: [[MUL21:%.*]] = mul i32 [[DIV20]], 19003// CHECK13-NEXT: [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]9004// CHECK13-NEXT: store i32 [[ADD22]], ptr [[I5]], align 49005// CHECK13-NEXT: br label [[SIMD_IF_END]]9006// CHECK13: simd.if.end:9007// CHECK13-NEXT: [[TMP21:%.*]] = load i32, ptr [[A]], align 49008// CHECK13-NEXT: ret i32 [[TMP21]]9009//9010//9011// CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i9012// CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {9013// CHECK13-NEXT: entry:9014// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49015// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 49016// CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 29017// CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 49018// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 49019// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 49020// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 49021// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 49022// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 49023// CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49024// CHECK13-NEXT: store i32 0, ptr [[A]], align 49025// CHECK13-NEXT: store i16 0, ptr [[AA]], align 29026// CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 49027// CHECK13-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 49028// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 49029// CHECK13-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 49030// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]9031// CHECK13: omp.inner.for.cond:9032// CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]]9033// CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]]9034// CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]9035// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]9036// CHECK13: omp.inner.for.body:9037// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]9038// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 19039// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]9040// CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]]9041// CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP27]]9042// CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 19043// CHECK13-NEXT: store i32 [[ADD1]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP27]]9044// CHECK13-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP27]]9045// CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i329046// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 19047// CHECK13-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i169048// CHECK13-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP27]]9049// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 29050// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]]9051// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 19052// CHECK13-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]]9053// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]9054// CHECK13: omp.body.continue:9055// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]9056// CHECK13: omp.inner.for.inc:9057// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]9058// CHECK13-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP7]], 19059// CHECK13-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]9060// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]9061// CHECK13: omp.inner.for.end:9062// CHECK13-NEXT: store i32 10, ptr [[I]], align 49063// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 49064// CHECK13-NEXT: ret i32 [[TMP8]]9065//9066//9067// CHECK15-LABEL: define {{[^@]+}}@_Z3fooi9068// CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {9069// CHECK15-NEXT: entry:9070// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49071// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 49072// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 29073// CHECK15-NEXT: [[B:%.*]] = alloca [10 x float], align 49074// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 49075// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 49076// CHECK15-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 89077// CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 49078// CHECK15-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 49079// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 49080// CHECK15-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 49081// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 49082// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 49083// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 49084// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 49085// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 49086// CHECK15-NEXT: [[_TMP4:%.*]] = alloca i32, align 49087// CHECK15-NEXT: [[DOTOMP_LB5:%.*]] = alloca i32, align 49088// CHECK15-NEXT: [[DOTOMP_UB6:%.*]] = alloca i32, align 49089// CHECK15-NEXT: [[DOTOMP_IV7:%.*]] = alloca i32, align 49090// CHECK15-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 49091// CHECK15-NEXT: [[A8:%.*]] = alloca i32, align 49092// CHECK15-NEXT: [[A9:%.*]] = alloca i32, align 49093// CHECK15-NEXT: [[_TMP20:%.*]] = alloca i32, align 49094// CHECK15-NEXT: [[DOTOMP_LB21:%.*]] = alloca i32, align 49095// CHECK15-NEXT: [[DOTOMP_UB22:%.*]] = alloca i32, align 49096// CHECK15-NEXT: [[DOTOMP_IV23:%.*]] = alloca i32, align 49097// CHECK15-NEXT: [[I24:%.*]] = alloca i32, align 49098// CHECK15-NEXT: [[_TMP36:%.*]] = alloca i32, align 49099// CHECK15-NEXT: [[DOTOMP_LB37:%.*]] = alloca i32, align 49100// CHECK15-NEXT: [[DOTOMP_UB38:%.*]] = alloca i32, align 49101// CHECK15-NEXT: [[DOTOMP_IV39:%.*]] = alloca i32, align 49102// CHECK15-NEXT: [[I40:%.*]] = alloca i32, align 49103// CHECK15-NEXT: [[_TMP54:%.*]] = alloca i32, align 49104// CHECK15-NEXT: [[DOTOMP_LB55:%.*]] = alloca i32, align 49105// CHECK15-NEXT: [[DOTOMP_UB56:%.*]] = alloca i32, align 49106// CHECK15-NEXT: [[DOTOMP_IV57:%.*]] = alloca i32, align 49107// CHECK15-NEXT: [[I58:%.*]] = alloca i32, align 49108// CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49109// CHECK15-NEXT: store i32 0, ptr [[A]], align 49110// CHECK15-NEXT: store i16 0, ptr [[AA]], align 29111// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 49112// CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()9113// CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 49114// CHECK15-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 49115// CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 49116// CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 49117// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]9118// CHECK15-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 89119// CHECK15-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 49120// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 49121// CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 49122// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 49123// CHECK15-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_2]], align 49124// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 49125// CHECK15-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 49126// CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 49127// CHECK15-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 49128// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]9129// CHECK15: omp.inner.for.cond:9130// CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]9131// CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]]9132// CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]9133// CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]9134// CHECK15: omp.inner.for.body:9135// CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]9136// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 19137// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]9138// CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]9139// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]9140// CHECK15: omp.body.continue:9141// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]9142// CHECK15: omp.inner.for.inc:9143// CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]9144// CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 19145// CHECK15-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]9146// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]9147// CHECK15: omp.inner.for.end:9148// CHECK15-NEXT: store i32 10, ptr [[I]], align 49149// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB5]], align 49150// CHECK15-NEXT: store i32 9, ptr [[DOTOMP_UB6]], align 49151// CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB5]], align 49152// CHECK15-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV7]], align 49153// CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[A]], align 49154// CHECK15-NEXT: store i32 [[TMP12]], ptr [[DOTLINEAR_START]], align 49155// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND10:%.*]]9156// CHECK15: omp.inner.for.cond10:9157// CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 49158// CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB6]], align 49159// CHECK15-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]9160// CHECK15-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]9161// CHECK15: omp.inner.for.body12:9162// CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 49163// CHECK15-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 19164// CHECK15-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]9165// CHECK15-NEXT: store i32 [[ADD14]], ptr [[A8]], align 4, !nontemporal [[META8:![0-9]+]]9166// CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[A8]], align 4, !nontemporal [[META8]]9167// CHECK15-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 19168// CHECK15-NEXT: store i32 [[ADD15]], ptr [[A8]], align 4, !nontemporal [[META8]]9169// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]]9170// CHECK15: omp.body.continue16:9171// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]]9172// CHECK15: omp.inner.for.inc17:9173// CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 49174// CHECK15-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 19175// CHECK15-NEXT: store i32 [[ADD18]], ptr [[DOTOMP_IV7]], align 49176// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]]9177// CHECK15: omp.inner.for.end19:9178// CHECK15-NEXT: store i32 10, ptr [[A]], align 49179// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB21]], align 49180// CHECK15-NEXT: store i32 9, ptr [[DOTOMP_UB22]], align 49181// CHECK15-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_LB21]], align 49182// CHECK15-NEXT: store i32 [[TMP18]], ptr [[DOTOMP_IV23]], align 49183// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND25:%.*]]9184// CHECK15: omp.inner.for.cond25:9185// CHECK15-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]9186// CHECK15-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_UB22]], align 4, !llvm.access.group [[ACC_GRP11]]9187// CHECK15-NEXT: [[CMP26:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]9188// CHECK15-NEXT: br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]9189// CHECK15: omp.inner.for.body27:9190// CHECK15-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP11]]9191// CHECK15-NEXT: [[MUL28:%.*]] = mul nsw i32 [[TMP21]], 19192// CHECK15-NEXT: [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]9193// CHECK15-NEXT: store i32 [[ADD29]], ptr [[I24]], align 4, !llvm.access.group [[ACC_GRP11]]9194// CHECK15-NEXT: [[TMP22:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP11]]9195// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP22]] to i329196// CHECK15-NEXT: [[ADD30:%.*]] = add nsw i32 [[CONV]], 19197// CHECK15-NEXT: [[CONV31:%.*]] = trunc i32 [[ADD30]] to i169198// CHECK15-NEXT: store i16 [[CONV31]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP11]]9199// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE32:%.*]]9200// CHECK15: omp.body.continue32:9201// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC33:%.*]]9202// CHECK15: omp.inner.for.inc33:9203// CHECK15-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP11]]9204// CHECK15-NEXT: [[ADD34:%.*]] = add nsw i32 [[TMP23]], 19205// CHECK15-NEXT: store i32 [[ADD34]], ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP11]]9206// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP12:![0-9]+]]9207// CHECK15: omp.inner.for.end35:9208// CHECK15-NEXT: store i32 10, ptr [[I24]], align 49209// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB37]], align 49210// CHECK15-NEXT: store i32 9, ptr [[DOTOMP_UB38]], align 49211// CHECK15-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_LB37]], align 49212// CHECK15-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV39]], align 49213// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND41:%.*]]9214// CHECK15: omp.inner.for.cond41:9215// CHECK15-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]]9216// CHECK15-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_UB38]], align 4, !llvm.access.group [[ACC_GRP14]]9217// CHECK15-NEXT: [[CMP42:%.*]] = icmp sle i32 [[TMP25]], [[TMP26]]9218// CHECK15-NEXT: br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]9219// CHECK15: omp.inner.for.body43:9220// CHECK15-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP14]]9221// CHECK15-NEXT: [[MUL44:%.*]] = mul nsw i32 [[TMP27]], 19222// CHECK15-NEXT: [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]9223// CHECK15-NEXT: store i32 [[ADD45]], ptr [[I40]], align 4, !llvm.access.group [[ACC_GRP14]]9224// CHECK15-NEXT: [[TMP28:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP14]]9225// CHECK15-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP28]], 19226// CHECK15-NEXT: store i32 [[ADD46]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP14]]9227// CHECK15-NEXT: [[TMP29:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP14]]9228// CHECK15-NEXT: [[CONV47:%.*]] = sext i16 [[TMP29]] to i329229// CHECK15-NEXT: [[ADD48:%.*]] = add nsw i32 [[CONV47]], 19230// CHECK15-NEXT: [[CONV49:%.*]] = trunc i32 [[ADD48]] to i169231// CHECK15-NEXT: store i16 [[CONV49]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP14]]9232// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE50:%.*]]9233// CHECK15: omp.body.continue50:9234// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC51:%.*]]9235// CHECK15: omp.inner.for.inc51:9236// CHECK15-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP14]]9237// CHECK15-NEXT: [[ADD52:%.*]] = add nsw i32 [[TMP30]], 19238// CHECK15-NEXT: store i32 [[ADD52]], ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP14]]9239// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP15:![0-9]+]]9240// CHECK15: omp.inner.for.end53:9241// CHECK15-NEXT: store i32 10, ptr [[I40]], align 49242// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB55]], align 49243// CHECK15-NEXT: store i32 9, ptr [[DOTOMP_UB56]], align 49244// CHECK15-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_LB55]], align 49245// CHECK15-NEXT: store i32 [[TMP31]], ptr [[DOTOMP_IV57]], align 49246// CHECK15-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 09247// CHECK15-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i32 16) ]9248// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND59:%.*]]9249// CHECK15: omp.inner.for.cond59:9250// CHECK15-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]]9251// CHECK15-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_UB56]], align 4, !llvm.access.group [[ACC_GRP17]]9252// CHECK15-NEXT: [[CMP60:%.*]] = icmp sle i32 [[TMP32]], [[TMP33]]9253// CHECK15-NEXT: br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]9254// CHECK15: omp.inner.for.body61:9255// CHECK15-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP17]]9256// CHECK15-NEXT: [[MUL62:%.*]] = mul nsw i32 [[TMP34]], 19257// CHECK15-NEXT: [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]9258// CHECK15-NEXT: store i32 [[ADD63]], ptr [[I58]], align 4, !llvm.access.group [[ACC_GRP17]]9259// CHECK15-NEXT: [[TMP35:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP17]]9260// CHECK15-NEXT: [[ADD64:%.*]] = add nsw i32 [[TMP35]], 19261// CHECK15-NEXT: store i32 [[ADD64]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP17]]9262// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 29263// CHECK15-NEXT: [[TMP36:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]]9264// CHECK15-NEXT: [[CONV65:%.*]] = fpext float [[TMP36]] to double9265// CHECK15-NEXT: [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+009266// CHECK15-NEXT: [[CONV67:%.*]] = fptrunc double [[ADD66]] to float9267// CHECK15-NEXT: store float [[CONV67]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]]9268// CHECK15-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds float, ptr [[VLA]], i32 39269// CHECK15-NEXT: [[TMP37:%.*]] = load float, ptr [[ARRAYIDX68]], align 4, !llvm.access.group [[ACC_GRP17]]9270// CHECK15-NEXT: [[CONV69:%.*]] = fpext float [[TMP37]] to double9271// CHECK15-NEXT: [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+009272// CHECK15-NEXT: [[CONV71:%.*]] = fptrunc double [[ADD70]] to float9273// CHECK15-NEXT: store float [[CONV71]], ptr [[ARRAYIDX68]], align 4, !llvm.access.group [[ACC_GRP17]]9274// CHECK15-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 19275// CHECK15-NEXT: [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX72]], i32 0, i32 29276// CHECK15-NEXT: [[TMP38:%.*]] = load double, ptr [[ARRAYIDX73]], align 8, !llvm.access.group [[ACC_GRP17]]9277// CHECK15-NEXT: [[ADD74:%.*]] = fadd double [[TMP38]], 1.000000e+009278// CHECK15-NEXT: store double [[ADD74]], ptr [[ARRAYIDX73]], align 8, !llvm.access.group [[ACC_GRP17]]9279// CHECK15-NEXT: [[TMP39:%.*]] = mul nsw i32 1, [[TMP2]]9280// CHECK15-NEXT: [[ARRAYIDX75:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i32 [[TMP39]]9281// CHECK15-NEXT: [[ARRAYIDX76:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX75]], i32 39282// CHECK15-NEXT: [[TMP40:%.*]] = load double, ptr [[ARRAYIDX76]], align 8, !llvm.access.group [[ACC_GRP17]]9283// CHECK15-NEXT: [[ADD77:%.*]] = fadd double [[TMP40]], 1.000000e+009284// CHECK15-NEXT: store double [[ADD77]], ptr [[ARRAYIDX76]], align 8, !llvm.access.group [[ACC_GRP17]]9285// CHECK15-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 09286// CHECK15-NEXT: [[TMP41:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP17]]9287// CHECK15-NEXT: [[ADD78:%.*]] = add nsw i64 [[TMP41]], 19288// CHECK15-NEXT: store i64 [[ADD78]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP17]]9289// CHECK15-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D]], i32 0, i32 19290// CHECK15-NEXT: [[TMP42:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP17]]9291// CHECK15-NEXT: [[CONV79:%.*]] = sext i8 [[TMP42]] to i329292// CHECK15-NEXT: [[ADD80:%.*]] = add nsw i32 [[CONV79]], 19293// CHECK15-NEXT: [[CONV81:%.*]] = trunc i32 [[ADD80]] to i89294// CHECK15-NEXT: store i8 [[CONV81]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP17]]9295// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE82:%.*]]9296// CHECK15: omp.body.continue82:9297// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC83:%.*]]9298// CHECK15: omp.inner.for.inc83:9299// CHECK15-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP17]]9300// CHECK15-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP43]], 19301// CHECK15-NEXT: store i32 [[ADD84]], ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP17]]9302// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP18:![0-9]+]]9303// CHECK15: omp.inner.for.end85:9304// CHECK15-NEXT: store i32 10, ptr [[I58]], align 49305// CHECK15-NEXT: [[TMP44:%.*]] = load i32, ptr [[A]], align 49306// CHECK15-NEXT: [[TMP45:%.*]] = load ptr, ptr [[SAVED_STACK]], align 49307// CHECK15-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP45]])9308// CHECK15-NEXT: ret i32 [[TMP44]]9309//9310//9311// CHECK15-LABEL: define {{[^@]+}}@_Z3bari9312// CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {9313// CHECK15-NEXT: entry:9314// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49315// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 49316// CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 49317// CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49318// CHECK15-NEXT: store i32 0, ptr [[A]], align 49319// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 49320// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])9321// CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 49322// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]9323// CHECK15-NEXT: store i32 [[ADD]], ptr [[A]], align 49324// CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 49325// CHECK15-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])9326// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 49327// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]9328// CHECK15-NEXT: store i32 [[ADD2]], ptr [[A]], align 49329// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 49330// CHECK15-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])9331// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 49332// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]9333// CHECK15-NEXT: store i32 [[ADD4]], ptr [[A]], align 49334// CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 49335// CHECK15-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])9336// CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 49337// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]9338// CHECK15-NEXT: store i32 [[ADD6]], ptr [[A]], align 49339// CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 49340// CHECK15-NEXT: ret i32 [[TMP8]]9341//9342//9343// CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei9344// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {9345// CHECK15-NEXT: entry:9346// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 49347// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49348// CHECK15-NEXT: [[B:%.*]] = alloca i32, align 49349// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 49350// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 49351// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 19352// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 49353// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 49354// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 49355// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 49356// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 49357// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 49358// CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49359// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 49360// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 49361// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 19362// CHECK15-NEXT: store i32 [[ADD]], ptr [[B]], align 49363// CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 49364// CHECK15-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()9365// CHECK15-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 49366// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]9367// CHECK15-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 29368// CHECK15-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 49369// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 49370// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 609371// CHECK15-NEXT: [[STOREDV:%.*]] = zext i1 [[CMP]] to i89372// CHECK15-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 19373// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 49374// CHECK15-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 49375// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 49376// CHECK15-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 49377// CHECK15-NEXT: [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 19378// CHECK15-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP6]] to i19379// CHECK15-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]9380// CHECK15: omp_if.then:9381// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]9382// CHECK15: omp.inner.for.cond:9383// CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]]9384// CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]]9385// CHECK15-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]9386// CHECK15-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]9387// CHECK15: omp.inner.for.body:9388// CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]9389// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 19390// CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]]9391// CHECK15-NEXT: store i32 [[ADD3]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]]9392// CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP20]]9393// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double9394// CHECK15-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+009395// CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 09396// CHECK15-NEXT: store double [[ADD4]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP20]]9397// CHECK15-NEXT: [[A5:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 09398// CHECK15-NEXT: [[TMP11:%.*]] = load double, ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP20]]9399// CHECK15-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+009400// CHECK15-NEXT: store double [[INC]], ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP20]]9401// CHECK15-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i169402// CHECK15-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]9403// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP12]]9404// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 19405// CHECK15-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP20]]9406// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]9407// CHECK15: omp.body.continue:9408// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]9409// CHECK15: omp.inner.for.inc:9410// CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]9411// CHECK15-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 19412// CHECK15-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]9413// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]9414// CHECK15: omp.inner.for.end:9415// CHECK15-NEXT: br label [[OMP_IF_END:%.*]]9416// CHECK15: omp_if.else:9417// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]9418// CHECK15: omp.inner.for.cond9:9419// CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 49420// CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 49421// CHECK15-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]9422// CHECK15-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]]9423// CHECK15: omp.inner.for.body11:9424// CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 49425// CHECK15-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP16]], 19426// CHECK15-NEXT: [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]9427// CHECK15-NEXT: store i32 [[ADD13]], ptr [[I]], align 49428// CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[B]], align 49429// CHECK15-NEXT: [[CONV14:%.*]] = sitofp i32 [[TMP17]] to double9430// CHECK15-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+009431// CHECK15-NEXT: [[A16:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 09432// CHECK15-NEXT: store double [[ADD15]], ptr [[A16]], align 49433// CHECK15-NEXT: [[A17:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 09434// CHECK15-NEXT: [[TMP18:%.*]] = load double, ptr [[A17]], align 49435// CHECK15-NEXT: [[INC18:%.*]] = fadd double [[TMP18]], 1.000000e+009436// CHECK15-NEXT: store double [[INC18]], ptr [[A17]], align 49437// CHECK15-NEXT: [[CONV19:%.*]] = fptosi double [[INC18]] to i169438// CHECK15-NEXT: [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]]9439// CHECK15-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP19]]9440// CHECK15-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX20]], i32 19441// CHECK15-NEXT: store i16 [[CONV19]], ptr [[ARRAYIDX21]], align 29442// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE22:%.*]]9443// CHECK15: omp.body.continue22:9444// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC23:%.*]]9445// CHECK15: omp.inner.for.inc23:9446// CHECK15-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 49447// CHECK15-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP20]], 19448// CHECK15-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 49449// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP23:![0-9]+]]9450// CHECK15: omp.inner.for.end25:9451// CHECK15-NEXT: br label [[OMP_IF_END]]9452// CHECK15: omp_if.end:9453// CHECK15-NEXT: store i32 10, ptr [[I]], align 49454// CHECK15-NEXT: [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]]9455// CHECK15-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP21]]9456// CHECK15-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX26]], i32 19457// CHECK15-NEXT: [[TMP22:%.*]] = load i16, ptr [[ARRAYIDX27]], align 29458// CHECK15-NEXT: [[CONV28:%.*]] = sext i16 [[TMP22]] to i329459// CHECK15-NEXT: [[TMP23:%.*]] = load i32, ptr [[B]], align 49460// CHECK15-NEXT: [[ADD29:%.*]] = add nsw i32 [[CONV28]], [[TMP23]]9461// CHECK15-NEXT: [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 49462// CHECK15-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP24]])9463// CHECK15-NEXT: ret i32 [[ADD29]]9464//9465//9466// CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici9467// CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {9468// CHECK15-NEXT: entry:9469// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49470// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 49471// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 29472// CHECK15-NEXT: [[AAA:%.*]] = alloca i8, align 19473// CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 49474// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 49475// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 49476// CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 49477// CHECK15-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 49478// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 49479// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 49480// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 49481// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 49482// CHECK15-NEXT: [[I5:%.*]] = alloca i32, align 49483// CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49484// CHECK15-NEXT: store i32 0, ptr [[A]], align 49485// CHECK15-NEXT: store i16 0, ptr [[AA]], align 29486// CHECK15-NEXT: store i8 0, ptr [[AAA]], align 19487// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 49488// CHECK15-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 49489// CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 49490// CHECK15-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_1]], align 49491// CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 49492// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 49493// CHECK15-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]9494// CHECK15-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 19495// CHECK15-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 19496// CHECK15-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 19497// CHECK15-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 19498// CHECK15-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 49499// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 49500// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 49501// CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 49502// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 49503// CHECK15-NEXT: store i32 [[TMP5]], ptr [[I]], align 49504// CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 49505// CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 49506// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]9507// CHECK15-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]9508// CHECK15: simd.if.then:9509// CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 49510// CHECK15-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 49511// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]9512// CHECK15: omp.inner.for.cond:9513// CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]]9514// CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP25]]9515// CHECK15-NEXT: [[ADD6:%.*]] = add i32 [[TMP10]], 19516// CHECK15-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]9517// CHECK15-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]9518// CHECK15: omp.inner.for.body:9519// CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP25]]9520// CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]9521// CHECK15-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 19522// CHECK15-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]9523// CHECK15-NEXT: store i32 [[ADD8]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP25]]9524// CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP25]]9525// CHECK15-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 19526// CHECK15-NEXT: store i32 [[ADD9]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP25]]9527// CHECK15-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP25]]9528// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i329529// CHECK15-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV]], 19530// CHECK15-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i169531// CHECK15-NEXT: store i16 [[CONV11]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP25]]9532// CHECK15-NEXT: [[TMP15:%.*]] = load i8, ptr [[AAA]], align 1, !llvm.access.group [[ACC_GRP25]]9533// CHECK15-NEXT: [[CONV12:%.*]] = sext i8 [[TMP15]] to i329534// CHECK15-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 19535// CHECK15-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i89536// CHECK15-NEXT: store i8 [[CONV14]], ptr [[AAA]], align 1, !llvm.access.group [[ACC_GRP25]]9537// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 29538// CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]9539// CHECK15-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 19540// CHECK15-NEXT: store i32 [[ADD15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]9541// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]9542// CHECK15: omp.body.continue:9543// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]9544// CHECK15: omp.inner.for.inc:9545// CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]9546// CHECK15-NEXT: [[ADD16:%.*]] = add i32 [[TMP17]], 19547// CHECK15-NEXT: store i32 [[ADD16]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]9548// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]9549// CHECK15: omp.inner.for.end:9550// CHECK15-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 49551// CHECK15-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 49552// CHECK15-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 49553// CHECK15-NEXT: [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]9554// CHECK15-NEXT: [[SUB18:%.*]] = sub i32 [[SUB17]], 19555// CHECK15-NEXT: [[ADD19:%.*]] = add i32 [[SUB18]], 19556// CHECK15-NEXT: [[DIV20:%.*]] = udiv i32 [[ADD19]], 19557// CHECK15-NEXT: [[MUL21:%.*]] = mul i32 [[DIV20]], 19558// CHECK15-NEXT: [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]9559// CHECK15-NEXT: store i32 [[ADD22]], ptr [[I5]], align 49560// CHECK15-NEXT: br label [[SIMD_IF_END]]9561// CHECK15: simd.if.end:9562// CHECK15-NEXT: [[TMP21:%.*]] = load i32, ptr [[A]], align 49563// CHECK15-NEXT: ret i32 [[TMP21]]9564//9565//9566// CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i9567// CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {9568// CHECK15-NEXT: entry:9569// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 49570// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 49571// CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 29572// CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 49573// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 49574// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 49575// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 49576// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 49577// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 49578// CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 49579// CHECK15-NEXT: store i32 0, ptr [[A]], align 49580// CHECK15-NEXT: store i16 0, ptr [[AA]], align 29581// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 49582// CHECK15-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 49583// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 49584// CHECK15-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 49585// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]9586// CHECK15: omp.inner.for.cond:9587// CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]]9588// CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP28]]9589// CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]9590// CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]9591// CHECK15: omp.inner.for.body:9592// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]9593// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 19594// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]9595// CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]]9596// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP28]]9597// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 19598// CHECK15-NEXT: store i32 [[ADD1]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP28]]9599// CHECK15-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP28]]9600// CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i329601// CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 19602// CHECK15-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i169603// CHECK15-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP28]]9604// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 29605// CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]]9606// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 19607// CHECK15-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]]9608// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]9609// CHECK15: omp.body.continue:9610// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]9611// CHECK15: omp.inner.for.inc:9612// CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]9613// CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP7]], 19614// CHECK15-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]9615// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]9616// CHECK15: omp.inner.for.end:9617// CHECK15-NEXT: store i32 10, ptr [[I]], align 49618// CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 49619// CHECK15-NEXT: ret i32 [[TMP8]]9620//9621//9622// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l979623// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {9624// CHECK17-NEXT: entry:9625// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 89626// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 89627// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 89628// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 89629// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 89630// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])9631// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 89632// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 89633// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 89634// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 89635// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 49636// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 49637// CHECK17-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])9638// CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 29639// CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 29640// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 89641// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i64 [[TMP4]])9642// CHECK17-NEXT: ret void9643//9644//9645// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined9646// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {9647// CHECK17-NEXT: entry:9648// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 89649// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 89650// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 89651// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 49652// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 49653// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 49654// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 49655// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 49656// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 49657// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 49658// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 89659// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 89660// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 89661// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 49662// CHECK17-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 49663// CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 49664// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 49665// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 89666// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 49667// CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)9668// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 49669// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99670// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]9671// CHECK17: cond.true:9672// CHECK17-NEXT: br label [[COND_END:%.*]]9673// CHECK17: cond.false:9674// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 49675// CHECK17-NEXT: br label [[COND_END]]9676// CHECK17: cond.end:9677// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]9678// CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 49679// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 49680// CHECK17-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 49681// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]9682// CHECK17: omp.inner.for.cond:9683// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]9684// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]]9685// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]9686// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]9687// CHECK17: omp.inner.for.body:9688// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]9689// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 19690// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]9691// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]9692// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]9693// CHECK17: omp.body.continue:9694// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]9695// CHECK17: omp.inner.for.inc:9696// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]9697// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 19698// CHECK17-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]9699// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]9700// CHECK17: omp.inner.for.end:9701// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]9702// CHECK17: omp.loop.exit:9703// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])9704// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 49705// CHECK17-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 09706// CHECK17-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]9707// CHECK17: .omp.final.then:9708// CHECK17-NEXT: store i32 10, ptr [[I]], align 49709// CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]9710// CHECK17: .omp.final.done:9711// CHECK17-NEXT: ret void9712//9713//9714// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1119715// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {9716// CHECK17-NEXT: entry:9717// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 89718// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 89719// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 89720// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 89721// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 89722// CHECK17-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 29723// CHECK17-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 29724// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 89725// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP1]])9726// CHECK17-NEXT: ret void9727//9728//9729// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined9730// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {9731// CHECK17-NEXT: entry:9732// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 89733// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 89734// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 89735// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 49736// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 49737// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 49738// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 49739// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 49740// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 49741// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 49742// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 89743// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 89744// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 89745// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 49746// CHECK17-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 49747// CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 49748// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 49749// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 89750// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 49751// CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)9752// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 49753// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99754// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]9755// CHECK17: cond.true:9756// CHECK17-NEXT: br label [[COND_END:%.*]]9757// CHECK17: cond.false:9758// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 49759// CHECK17-NEXT: br label [[COND_END]]9760// CHECK17: cond.end:9761// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]9762// CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 49763// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 49764// CHECK17-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 49765// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]9766// CHECK17: omp.inner.for.cond:9767// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]]9768// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]]9769// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]9770// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]9771// CHECK17: omp.inner.for.body:9772// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]9773// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 19774// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]9775// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]9776// CHECK17-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]]9777// CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i329778// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 19779// CHECK17-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i169780// CHECK17-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]]9781// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]9782// CHECK17: omp.body.continue:9783// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]9784// CHECK17: omp.inner.for.inc:9785// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]9786// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 19787// CHECK17-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]9788// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]9789// CHECK17: omp.inner.for.end:9790// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]9791// CHECK17: omp.loop.exit:9792// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])9793// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 49794// CHECK17-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 09795// CHECK17-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]9796// CHECK17: .omp.final.then:9797// CHECK17-NEXT: store i32 10, ptr [[I]], align 49798// CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]9799// CHECK17: .omp.final.done:9800// CHECK17-NEXT: ret void9801//9802//9803// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1189804// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {9805// CHECK17-NEXT: entry:9806// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 89807// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 89808// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 89809// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 89810// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 89811// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 89812// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 89813// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 89814// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 49815// CHECK17-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 49816// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 89817// CHECK17-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 29818// CHECK17-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 29819// CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 89820// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])9821// CHECK17-NEXT: ret void9822//9823//9824// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined9825// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {9826// CHECK17-NEXT: entry:9827// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 89828// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 89829// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 89830// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 89831// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 49832// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 49833// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 49834// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 49835// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 49836// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 49837// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 49838// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 89839// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 89840// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 89841// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 89842// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 49843// CHECK17-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 49844// CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 49845// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 49846// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 89847// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 49848// CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)9849// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 49850// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 99851// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]9852// CHECK17: cond.true:9853// CHECK17-NEXT: br label [[COND_END:%.*]]9854// CHECK17: cond.false:9855// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 49856// CHECK17-NEXT: br label [[COND_END]]9857// CHECK17: cond.end:9858// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]9859// CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 49860// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 49861// CHECK17-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 49862// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]9863// CHECK17: omp.inner.for.cond:9864// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]]9865// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]]9866// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]9867// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]9868// CHECK17: omp.inner.for.body:9869// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]9870// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 19871// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]9872// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]]9873// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]]9874// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 19875// CHECK17-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]]9876// CHECK17-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]]9877// CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i329878// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 19879// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i169880// CHECK17-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]]9881// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]9882// CHECK17: omp.body.continue:9883// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]9884// CHECK17: omp.inner.for.inc:9885// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]9886// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 19887// CHECK17-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]9888// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]9889// CHECK17: omp.inner.for.end:9890// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]9891// CHECK17: omp.loop.exit:9892// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])9893// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 49894// CHECK17-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 09895// CHECK17-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]9896// CHECK17: .omp.final.then:9897// CHECK17-NEXT: store i32 10, ptr [[I]], align 49898// CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]9899// CHECK17: .omp.final.done:9900// CHECK17-NEXT: ret void9901//9902//9903// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l1429904// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {9905// CHECK17-NEXT: entry:9906// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 89907// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 89908// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 89909// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 89910// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 89911// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 89912// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 89913// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 89914// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 89915// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 89916// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 89917// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 89918// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 89919// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 89920// CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 89921// CHECK17-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 89922// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 89923// CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 89924// CHECK17-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 89925// CHECK17-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 89926// CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 89927// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 89928// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 89929// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 89930// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 89931// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 89932// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 89933// CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 89934// CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 89935// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 49936// CHECK17-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 49937// CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 89938// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])9939// CHECK17-NEXT: ret void9940//9941//9942// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined9943// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {9944// CHECK17-NEXT: entry:9945// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 89946// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 89947// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 89948// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 89949// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 89950// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 89951// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 89952// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 89953// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 89954// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 89955// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 89956// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 49957// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 49958// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 49959// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 49960// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 49961// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 49962// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 49963// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 89964// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 89965// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 89966// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 89967// CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 89968// CHECK17-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 89969// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 89970// CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 89971// CHECK17-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 89972// CHECK17-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 89973// CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 89974// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 89975// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 89976// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 89977// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 89978// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 89979// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 89980// CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 89981// CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 89982// CHECK17-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 09983// CHECK17-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i64 16) ]9984// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 49985// CHECK17-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 49986// CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 49987// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 49988// CHECK17-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 89989// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 49990// CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)9991// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 49992// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 99993// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]9994// CHECK17: cond.true:9995// CHECK17-NEXT: br label [[COND_END:%.*]]9996// CHECK17: cond.false:9997// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 49998// CHECK17-NEXT: br label [[COND_END]]9999// CHECK17: cond.end:10000// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]10001// CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 410002// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 410003// CHECK17-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 410004// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]10005// CHECK17: omp.inner.for.cond:10006// CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]]10007// CHECK17-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]]10008// CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]10009// CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]10010// CHECK17: omp.inner.for.body:10011// CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]10012// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 110013// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]10014// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]]10015// CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]]10016// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 110017// CHECK17-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]]10018// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 210019// CHECK17-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]]10020// CHECK17-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double10021// CHECK17-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+0010022// CHECK17-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float10023// CHECK17-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]]10024// CHECK17-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 310025// CHECK17-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP24]]10026// CHECK17-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double10027// CHECK17-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+0010028// CHECK17-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float10029// CHECK17-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP24]]10030// CHECK17-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 110031// CHECK17-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i64 0, i64 210032// CHECK17-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP24]]10033// CHECK17-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+0010034// CHECK17-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP24]]10035// CHECK17-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]]10036// CHECK17-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP20]]10037// CHECK17-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i64 310038// CHECK17-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP24]]10039// CHECK17-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+0010040// CHECK17-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP24]]10041// CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 010042// CHECK17-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP24]]10043// CHECK17-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 110044// CHECK17-NEXT: store i64 [[ADD19]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP24]]10045// CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 110046// CHECK17-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP24]]10047// CHECK17-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i3210048// CHECK17-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 110049// CHECK17-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i810050// CHECK17-NEXT: store i8 [[CONV22]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP24]]10051// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]10052// CHECK17: omp.body.continue:10053// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]10054// CHECK17: omp.inner.for.inc:10055// CHECK17-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]10056// CHECK17-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 110057// CHECK17-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]10058// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]10059// CHECK17: omp.inner.for.end:10060// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]10061// CHECK17: omp.loop.exit:10062// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP9]])10063// CHECK17-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 410064// CHECK17-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 010065// CHECK17-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]10066// CHECK17: .omp.final.then:10067// CHECK17-NEXT: store i32 10, ptr [[I]], align 410068// CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]10069// CHECK17: .omp.final.done:10070// CHECK17-NEXT: ret void10071//10072//10073// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l19710074// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {10075// CHECK17-NEXT: entry:10076// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 810077// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 810078// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 810079// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 810080// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 810081// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 810082// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 810083// CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 810084// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 810085// CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 810086// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 810087// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 810088// CHECK17-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 810089// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 810090// CHECK17-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 810091// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 810092// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 810093// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 410094// CHECK17-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 410095// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 810096// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 410097// CHECK17-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 410098// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 810099// CHECK17-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 210100// CHECK17-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 210101// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[AA_CASTED]], align 810102// CHECK17-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 110103// CHECK17-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 110104// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[AAA_CASTED]], align 810105// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], ptr [[TMP0]])10106// CHECK17-NEXT: ret void10107//10108//10109// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined10110// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {10111// CHECK17-NEXT: entry:10112// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 810113// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 810114// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 810115// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 810116// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 810117// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 810118// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 810119// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 410120// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 410121// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 410122// CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 410123// CHECK17-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 410124// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 410125// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 410126// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 410127// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 410128// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 410129// CHECK17-NEXT: [[I5:%.*]] = alloca i32, align 410130// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 810131// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 810132// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 810133// CHECK17-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 810134// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 810135// CHECK17-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 810136// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 810137// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 810138// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 410139// CHECK17-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 410140// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 410141// CHECK17-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 410142// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 410143// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 410144// CHECK17-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]10145// CHECK17-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 110146// CHECK17-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 110147// CHECK17-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 110148// CHECK17-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 110149// CHECK17-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 410150// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 410151// CHECK17-NEXT: store i32 [[TMP5]], ptr [[I]], align 410152// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 410153// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 410154// CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]10155// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]10156// CHECK17: omp.precond.then:10157// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 410158// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 410159// CHECK17-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 410160// CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 410161// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 410162// CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 810163// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 410164// CHECK17-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)10165// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 410166// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 410167// CHECK17-NEXT: [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]10168// CHECK17-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]10169// CHECK17: cond.true:10170// CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 410171// CHECK17-NEXT: br label [[COND_END:%.*]]10172// CHECK17: cond.false:10173// CHECK17-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 410174// CHECK17-NEXT: br label [[COND_END]]10175// CHECK17: cond.end:10176// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]10177// CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 410178// CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 410179// CHECK17-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 410180// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]10181// CHECK17: omp.inner.for.cond:10182// CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]]10183// CHECK17-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]]10184// CHECK17-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 110185// CHECK17-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]10186// CHECK17-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]10187// CHECK17: omp.inner.for.body:10188// CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP27]]10189// CHECK17-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]10190// CHECK17-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 110191// CHECK17-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]10192// CHECK17-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP27]]10193// CHECK17-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]]10194// CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 110195// CHECK17-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]]10196// CHECK17-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP27]]10197// CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i3210198// CHECK17-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 110199// CHECK17-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i1610200// CHECK17-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP27]]10201// CHECK17-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP27]]10202// CHECK17-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i3210203// CHECK17-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 110204// CHECK17-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i810205// CHECK17-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP27]]10206// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 210207// CHECK17-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]]10208// CHECK17-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 110209// CHECK17-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]]10210// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]10211// CHECK17: omp.body.continue:10212// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]10213// CHECK17: omp.inner.for.inc:10214// CHECK17-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]10215// CHECK17-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 110216// CHECK17-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]10217// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]10218// CHECK17: omp.inner.for.end:10219// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]10220// CHECK17: omp.loop.exit:10221// CHECK17-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 810222// CHECK17-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 410223// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])10224// CHECK17-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 410225// CHECK17-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 010226// CHECK17-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]10227// CHECK17: .omp.final.then:10228// CHECK17-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 410229// CHECK17-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 410230// CHECK17-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 410231// CHECK17-NEXT: [[SUB18:%.*]] = sub i32 [[TMP30]], [[TMP31]]10232// CHECK17-NEXT: [[SUB19:%.*]] = sub i32 [[SUB18]], 110233// CHECK17-NEXT: [[ADD20:%.*]] = add i32 [[SUB19]], 110234// CHECK17-NEXT: [[DIV21:%.*]] = udiv i32 [[ADD20]], 110235// CHECK17-NEXT: [[MUL22:%.*]] = mul i32 [[DIV21]], 110236// CHECK17-NEXT: [[ADD23:%.*]] = add i32 [[TMP29]], [[MUL22]]10237// CHECK17-NEXT: store i32 [[ADD23]], ptr [[I5]], align 410238// CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]10239// CHECK17: .omp.final.done:10240// CHECK17-NEXT: br label [[OMP_PRECOND_END]]10241// CHECK17: omp.precond.end:10242// CHECK17-NEXT: ret void10243//10244//10245// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l21510246// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {10247// CHECK17-NEXT: entry:10248// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 810249// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 810250// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 810251// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 810252// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 810253// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 810254// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 810255// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 810256// CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 810257// CHECK17-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 810258// CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 810259// CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 810260// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 810261// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 810262// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 810263// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 810264// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 810265// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 410266// CHECK17-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 410267// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 810268// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])10269// CHECK17-NEXT: ret void10270//10271//10272// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined10273// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {10274// CHECK17-NEXT: entry:10275// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 810276// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 810277// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 810278// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 810279// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 810280// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 810281// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 810282// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 410283// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 410284// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 410285// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 410286// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 410287// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 410288// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 410289// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 810290// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 810291// CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 810292// CHECK17-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 810293// CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 810294// CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 810295// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 810296// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 810297// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 810298// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 810299// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 810300// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 410301// CHECK17-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 410302// CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 410303// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 410304// CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 810305// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 410306// CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)10307// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 410308// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 910309// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]10310// CHECK17: cond.true:10311// CHECK17-NEXT: br label [[COND_END:%.*]]10312// CHECK17: cond.false:10313// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 410314// CHECK17-NEXT: br label [[COND_END]]10315// CHECK17: cond.end:10316// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]10317// CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 410318// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 410319// CHECK17-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 410320// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]10321// CHECK17: omp.inner.for.cond:10322// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30:![0-9]+]]10323// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP30]]10324// CHECK17-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]10325// CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]10326// CHECK17: omp.inner.for.body:10327// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]]10328// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 110329// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]10330// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP30]]10331// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP30]]10332// CHECK17-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double10333// CHECK17-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+0010334// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 010335// CHECK17-NEXT: store double [[ADD4]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP30]]10336// CHECK17-NEXT: [[A5:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 010337// CHECK17-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP30]]10338// CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+0010339// CHECK17-NEXT: store double [[INC]], ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP30]]10340// CHECK17-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i1610341// CHECK17-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]10342// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]]10343// CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 110344// CHECK17-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP30]]10345// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]10346// CHECK17: omp.body.continue:10347// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]10348// CHECK17: omp.inner.for.inc:10349// CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]]10350// CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 110351// CHECK17-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]]10352// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]10353// CHECK17: omp.inner.for.end:10354// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]10355// CHECK17: omp.loop.exit:10356// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])10357// CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 410358// CHECK17-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 010359// CHECK17-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]10360// CHECK17: .omp.final.then:10361// CHECK17-NEXT: store i32 10, ptr [[I]], align 410362// CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]10363// CHECK17: .omp.final.done:10364// CHECK17-NEXT: ret void10365//10366//10367// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l18010368// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {10369// CHECK17-NEXT: entry:10370// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 810371// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 810372// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 810373// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 810374// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 810375// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 810376// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 810377// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 810378// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 810379// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 810380// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 810381// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 410382// CHECK17-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 410383// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 810384// CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 210385// CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 210386// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 810387// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])10388// CHECK17-NEXT: ret void10389//10390//10391// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined10392// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {10393// CHECK17-NEXT: entry:10394// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 810395// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 810396// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 810397// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 810398// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 810399// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 410400// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 410401// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 410402// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 410403// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 410404// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 410405// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 410406// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 810407// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 810408// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 810409// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 810410// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 810411// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 810412// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 410413// CHECK17-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 410414// CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 410415// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 410416// CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 810417// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 410418// CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)10419// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 410420// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 910421// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]10422// CHECK17: cond.true:10423// CHECK17-NEXT: br label [[COND_END:%.*]]10424// CHECK17: cond.false:10425// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 410426// CHECK17-NEXT: br label [[COND_END]]10427// CHECK17: cond.end:10428// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]10429// CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 410430// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 410431// CHECK17-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 410432// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]10433// CHECK17: omp.inner.for.cond:10434// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]]10435// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]]10436// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]10437// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]10438// CHECK17: omp.inner.for.body:10439// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]10440// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 110441// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]10442// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]]10443// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]]10444// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 110445// CHECK17-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]]10446// CHECK17-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]]10447// CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i3210448// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 110449// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i1610450// CHECK17-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]]10451// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 210452// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]]10453// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 110454// CHECK17-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]]10455// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]10456// CHECK17: omp.body.continue:10457// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]10458// CHECK17: omp.inner.for.inc:10459// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]10460// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 110461// CHECK17-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]10462// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]10463// CHECK17: omp.inner.for.end:10464// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]10465// CHECK17: omp.loop.exit:10466// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])10467// CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 410468// CHECK17-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 010469// CHECK17-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]10470// CHECK17: .omp.final.then:10471// CHECK17-NEXT: store i32 10, ptr [[I]], align 410472// CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]10473// CHECK17: .omp.final.done:10474// CHECK17-NEXT: ret void10475//10476//10477// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l9710478// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {10479// CHECK19-NEXT: entry:10480// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 410481// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 410482// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 410483// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 410484// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 410485// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])10486// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 410487// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 410488// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 410489// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 410490// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 410491// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 410492// CHECK19-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])10493// CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 210494// CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 210495// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 410496// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i32 [[TMP4]])10497// CHECK19-NEXT: ret void10498//10499//10500// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined10501// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {10502// CHECK19-NEXT: entry:10503// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 410504// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 410505// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 410506// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 410507// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 410508// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 410509// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 410510// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 410511// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 410512// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 410513// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 410514// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 410515// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 410516// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 410517// CHECK19-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 410518// CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 410519// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 410520// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 410521// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 410522// CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)10523// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 410524// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 910525// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]10526// CHECK19: cond.true:10527// CHECK19-NEXT: br label [[COND_END:%.*]]10528// CHECK19: cond.false:10529// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 410530// CHECK19-NEXT: br label [[COND_END]]10531// CHECK19: cond.end:10532// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]10533// CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 410534// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 410535// CHECK19-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 410536// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]10537// CHECK19: omp.inner.for.cond:10538// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]10539// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]10540// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]10541// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]10542// CHECK19: omp.inner.for.body:10543// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]10544// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 110545// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]10546// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]10547// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]10548// CHECK19: omp.body.continue:10549// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]10550// CHECK19: omp.inner.for.inc:10551// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]10552// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 110553// CHECK19-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]10554// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]10555// CHECK19: omp.inner.for.end:10556// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]10557// CHECK19: omp.loop.exit:10558// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])10559// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 410560// CHECK19-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 010561// CHECK19-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]10562// CHECK19: .omp.final.then:10563// CHECK19-NEXT: store i32 10, ptr [[I]], align 410564// CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]10565// CHECK19: .omp.final.done:10566// CHECK19-NEXT: ret void10567//10568//10569// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l11110570// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {10571// CHECK19-NEXT: entry:10572// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 410573// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 410574// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 410575// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 410576// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 410577// CHECK19-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 210578// CHECK19-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 210579// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 410580// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP1]])10581// CHECK19-NEXT: ret void10582//10583//10584// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined10585// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {10586// CHECK19-NEXT: entry:10587// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 410588// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 410589// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 410590// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 410591// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 410592// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 410593// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 410594// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 410595// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 410596// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 410597// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 410598// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 410599// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 410600// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 410601// CHECK19-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 410602// CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 410603// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 410604// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 410605// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 410606// CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)10607// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 410608// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 910609// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]10610// CHECK19: cond.true:10611// CHECK19-NEXT: br label [[COND_END:%.*]]10612// CHECK19: cond.false:10613// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 410614// CHECK19-NEXT: br label [[COND_END]]10615// CHECK19: cond.end:10616// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]10617// CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 410618// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 410619// CHECK19-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 410620// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]10621// CHECK19: omp.inner.for.cond:10622// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]]10623// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]]10624// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]10625// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]10626// CHECK19: omp.inner.for.body:10627// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]10628// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 110629// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]10630// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]]10631// CHECK19-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP19]]10632// CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i3210633// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 110634// CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i1610635// CHECK19-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP19]]10636// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]10637// CHECK19: omp.body.continue:10638// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]10639// CHECK19: omp.inner.for.inc:10640// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]10641// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 110642// CHECK19-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]10643// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]10644// CHECK19: omp.inner.for.end:10645// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]10646// CHECK19: omp.loop.exit:10647// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])10648// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 410649// CHECK19-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 010650// CHECK19-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]10651// CHECK19: .omp.final.then:10652// CHECK19-NEXT: store i32 10, ptr [[I]], align 410653// CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]10654// CHECK19: .omp.final.done:10655// CHECK19-NEXT: ret void10656//10657//10658// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l11810659// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {10660// CHECK19-NEXT: entry:10661// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 410662// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 410663// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 410664// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 410665// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 410666// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 410667// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 410668// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 410669// CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 410670// CHECK19-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 410671// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 410672// CHECK19-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 210673// CHECK19-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 210674// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 410675// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])10676// CHECK19-NEXT: ret void10677//10678//10679// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined10680// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {10681// CHECK19-NEXT: entry:10682// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 410683// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 410684// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 410685// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 410686// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 410687// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 410688// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 410689// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 410690// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 410691// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 410692// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 410693// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 410694// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 410695// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 410696// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 410697// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 410698// CHECK19-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 410699// CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 410700// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 410701// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 410702// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 410703// CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)10704// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 410705// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 910706// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]10707// CHECK19: cond.true:10708// CHECK19-NEXT: br label [[COND_END:%.*]]10709// CHECK19: cond.false:10710// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 410711// CHECK19-NEXT: br label [[COND_END]]10712// CHECK19: cond.end:10713// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]10714// CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 410715// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 410716// CHECK19-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 410717// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]10718// CHECK19: omp.inner.for.cond:10719// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]]10720// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]]10721// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]10722// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]10723// CHECK19: omp.inner.for.body:10724// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]10725// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 110726// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]10727// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]]10728// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]]10729// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 110730// CHECK19-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]]10731// CHECK19-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP22]]10732// CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i3210733// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 110734// CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i1610735// CHECK19-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP22]]10736// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]10737// CHECK19: omp.body.continue:10738// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]10739// CHECK19: omp.inner.for.inc:10740// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]10741// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 110742// CHECK19-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]10743// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]10744// CHECK19: omp.inner.for.end:10745// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]10746// CHECK19: omp.loop.exit:10747// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])10748// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 410749// CHECK19-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 010750// CHECK19-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]10751// CHECK19: .omp.final.then:10752// CHECK19-NEXT: store i32 10, ptr [[I]], align 410753// CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]10754// CHECK19: .omp.final.done:10755// CHECK19-NEXT: ret void10756//10757//10758// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l14210759// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {10760// CHECK19-NEXT: entry:10761// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 410762// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 410763// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 410764// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 410765// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 410766// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 410767// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 410768// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 410769// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 410770// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 410771// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 410772// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 410773// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 410774// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 410775// CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 410776// CHECK19-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 410777// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 410778// CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 410779// CHECK19-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 410780// CHECK19-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 410781// CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 410782// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 410783// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 410784// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 410785// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 410786// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 410787// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 410788// CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 410789// CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 410790// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 410791// CHECK19-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 410792// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 410793// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])10794// CHECK19-NEXT: ret void10795//10796//10797// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined10798// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {10799// CHECK19-NEXT: entry:10800// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 410801// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 410802// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 410803// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 410804// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 410805// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 410806// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 410807// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 410808// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 410809// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 410810// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 410811// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 410812// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 410813// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 410814// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 410815// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 410816// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 410817// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 410818// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 410819// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 410820// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 410821// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 410822// CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 410823// CHECK19-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 410824// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 410825// CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 410826// CHECK19-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 410827// CHECK19-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 410828// CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 410829// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 410830// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 410831// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 410832// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 410833// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 410834// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 410835// CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 410836// CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 410837// CHECK19-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 010838// CHECK19-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i32 16) ]10839// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 410840// CHECK19-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 410841// CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 410842// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 410843// CHECK19-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 410844// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 410845// CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)10846// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 410847// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 910848// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]10849// CHECK19: cond.true:10850// CHECK19-NEXT: br label [[COND_END:%.*]]10851// CHECK19: cond.false:10852// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 410853// CHECK19-NEXT: br label [[COND_END]]10854// CHECK19: cond.end:10855// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]10856// CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 410857// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 410858// CHECK19-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 410859// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]10860// CHECK19: omp.inner.for.cond:10861// CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]]10862// CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP25]]10863// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]10864// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]10865// CHECK19: omp.inner.for.body:10866// CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]10867// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 110868// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]10869// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]]10870// CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP25]]10871// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 110872// CHECK19-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP25]]10873// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 210874// CHECK19-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]10875// CHECK19-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double10876// CHECK19-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+0010877// CHECK19-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float10878// CHECK19-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]10879// CHECK19-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 310880// CHECK19-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP25]]10881// CHECK19-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double10882// CHECK19-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+0010883// CHECK19-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float10884// CHECK19-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP25]]10885// CHECK19-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 110886// CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i32 0, i32 210887// CHECK19-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP25]]10888// CHECK19-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+0010889// CHECK19-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP25]]10890// CHECK19-NEXT: [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]]10891// CHECK19-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP20]]10892// CHECK19-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i32 310893// CHECK19-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP25]]10894// CHECK19-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+0010895// CHECK19-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP25]]10896// CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 010897// CHECK19-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP25]]10898// CHECK19-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 110899// CHECK19-NEXT: store i64 [[ADD19]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP25]]10900// CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 110901// CHECK19-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP25]]10902// CHECK19-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i3210903// CHECK19-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 110904// CHECK19-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i810905// CHECK19-NEXT: store i8 [[CONV22]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP25]]10906// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]10907// CHECK19: omp.body.continue:10908// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]10909// CHECK19: omp.inner.for.inc:10910// CHECK19-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]10911// CHECK19-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 110912// CHECK19-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]10913// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]10914// CHECK19: omp.inner.for.end:10915// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]10916// CHECK19: omp.loop.exit:10917// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP9]])10918// CHECK19-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 410919// CHECK19-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 010920// CHECK19-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]10921// CHECK19: .omp.final.then:10922// CHECK19-NEXT: store i32 10, ptr [[I]], align 410923// CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]10924// CHECK19: .omp.final.done:10925// CHECK19-NEXT: ret void10926//10927//10928// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l19710929// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {10930// CHECK19-NEXT: entry:10931// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 410932// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 410933// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 410934// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 410935// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 410936// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 410937// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 410938// CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 410939// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 410940// CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 410941// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 410942// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 410943// CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 410944// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 410945// CHECK19-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 410946// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 410947// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 410948// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 410949// CHECK19-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 410950// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 410951// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 410952// CHECK19-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 410953// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 410954// CHECK19-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 210955// CHECK19-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 210956// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[AA_CASTED]], align 410957// CHECK19-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 110958// CHECK19-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 110959// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[AAA_CASTED]], align 410960// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], ptr [[TMP0]])10961// CHECK19-NEXT: ret void10962//10963//10964// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined10965// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {10966// CHECK19-NEXT: entry:10967// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 410968// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 410969// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 410970// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 410971// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 410972// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 410973// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 410974// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 410975// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 410976// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 410977// CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 410978// CHECK19-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 410979// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 410980// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 410981// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 410982// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 410983// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 410984// CHECK19-NEXT: [[I5:%.*]] = alloca i32, align 410985// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 410986// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 410987// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 410988// CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 410989// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 410990// CHECK19-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 410991// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 410992// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 410993// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 410994// CHECK19-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 410995// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 410996// CHECK19-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 410997// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 410998// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 410999// CHECK19-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]11000// CHECK19-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 111001// CHECK19-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 111002// CHECK19-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 111003// CHECK19-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 111004// CHECK19-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 411005// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 411006// CHECK19-NEXT: store i32 [[TMP5]], ptr [[I]], align 411007// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 411008// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 411009// CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]11010// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]11011// CHECK19: omp.precond.then:11012// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 411013// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 411014// CHECK19-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 411015// CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 411016// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 411017// CHECK19-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 411018// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 411019// CHECK19-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)11020// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411021// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 411022// CHECK19-NEXT: [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]11023// CHECK19-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]11024// CHECK19: cond.true:11025// CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 411026// CHECK19-NEXT: br label [[COND_END:%.*]]11027// CHECK19: cond.false:11028// CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411029// CHECK19-NEXT: br label [[COND_END]]11030// CHECK19: cond.end:11031// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]11032// CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 411033// CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 411034// CHECK19-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 411035// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]11036// CHECK19: omp.inner.for.cond:11037// CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]]11038// CHECK19-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP28]]11039// CHECK19-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 111040// CHECK19-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]11041// CHECK19-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]11042// CHECK19: omp.inner.for.body:11043// CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP28]]11044// CHECK19-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]11045// CHECK19-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 111046// CHECK19-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]11047// CHECK19-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP28]]11048// CHECK19-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP28]]11049// CHECK19-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 111050// CHECK19-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP28]]11051// CHECK19-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP28]]11052// CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i3211053// CHECK19-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 111054// CHECK19-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i1611055// CHECK19-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP28]]11056// CHECK19-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP28]]11057// CHECK19-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i3211058// CHECK19-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 111059// CHECK19-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i811060// CHECK19-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP28]]11061// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 211062// CHECK19-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]]11063// CHECK19-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 111064// CHECK19-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]]11065// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]11066// CHECK19: omp.body.continue:11067// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]11068// CHECK19: omp.inner.for.inc:11069// CHECK19-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]11070// CHECK19-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 111071// CHECK19-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]11072// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]11073// CHECK19: omp.inner.for.end:11074// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]11075// CHECK19: omp.loop.exit:11076// CHECK19-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 411077// CHECK19-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 411078// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])11079// CHECK19-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 411080// CHECK19-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 011081// CHECK19-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]11082// CHECK19: .omp.final.then:11083// CHECK19-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 411084// CHECK19-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 411085// CHECK19-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 411086// CHECK19-NEXT: [[SUB18:%.*]] = sub i32 [[TMP30]], [[TMP31]]11087// CHECK19-NEXT: [[SUB19:%.*]] = sub i32 [[SUB18]], 111088// CHECK19-NEXT: [[ADD20:%.*]] = add i32 [[SUB19]], 111089// CHECK19-NEXT: [[DIV21:%.*]] = udiv i32 [[ADD20]], 111090// CHECK19-NEXT: [[MUL22:%.*]] = mul i32 [[DIV21]], 111091// CHECK19-NEXT: [[ADD23:%.*]] = add i32 [[TMP29]], [[MUL22]]11092// CHECK19-NEXT: store i32 [[ADD23]], ptr [[I5]], align 411093// CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]11094// CHECK19: .omp.final.done:11095// CHECK19-NEXT: br label [[OMP_PRECOND_END]]11096// CHECK19: omp.precond.end:11097// CHECK19-NEXT: ret void11098//11099//11100// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l21511101// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {11102// CHECK19-NEXT: entry:11103// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 411104// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 411105// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 411106// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 411107// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 411108// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 411109// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 411110// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 411111// CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 411112// CHECK19-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 411113// CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 411114// CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 411115// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 411116// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 411117// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 411118// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 411119// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 411120// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 411121// CHECK19-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 411122// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 411123// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])11124// CHECK19-NEXT: ret void11125//11126//11127// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined11128// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {11129// CHECK19-NEXT: entry:11130// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 411131// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 411132// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 411133// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 411134// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 411135// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 411136// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 411137// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 411138// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 411139// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 411140// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 411141// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 411142// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 411143// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 411144// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 411145// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 411146// CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 411147// CHECK19-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 411148// CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 411149// CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 411150// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 411151// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 411152// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 411153// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 411154// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 411155// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 411156// CHECK19-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 411157// CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 411158// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 411159// CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 411160// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 411161// CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)11162// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411163// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 911164// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]11165// CHECK19: cond.true:11166// CHECK19-NEXT: br label [[COND_END:%.*]]11167// CHECK19: cond.false:11168// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411169// CHECK19-NEXT: br label [[COND_END]]11170// CHECK19: cond.end:11171// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]11172// CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 411173// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 411174// CHECK19-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 411175// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]11176// CHECK19: omp.inner.for.cond:11177// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31:![0-9]+]]11178// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP31]]11179// CHECK19-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]11180// CHECK19-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]11181// CHECK19: omp.inner.for.body:11182// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]]11183// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 111184// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]11185// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP31]]11186// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP31]]11187// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double11188// CHECK19-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+0011189// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 011190// CHECK19-NEXT: store double [[ADD4]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP31]]11191// CHECK19-NEXT: [[A5:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 011192// CHECK19-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP31]]11193// CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+0011194// CHECK19-NEXT: store double [[INC]], ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP31]]11195// CHECK19-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i1611196// CHECK19-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]11197// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]]11198// CHECK19-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 111199// CHECK19-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP31]]11200// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]11201// CHECK19: omp.body.continue:11202// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]11203// CHECK19: omp.inner.for.inc:11204// CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]]11205// CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 111206// CHECK19-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]]11207// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]11208// CHECK19: omp.inner.for.end:11209// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]11210// CHECK19: omp.loop.exit:11211// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])11212// CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 411213// CHECK19-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 011214// CHECK19-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]11215// CHECK19: .omp.final.then:11216// CHECK19-NEXT: store i32 10, ptr [[I]], align 411217// CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]11218// CHECK19: .omp.final.done:11219// CHECK19-NEXT: ret void11220//11221//11222// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l18011223// CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {11224// CHECK19-NEXT: entry:11225// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 411226// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 411227// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 411228// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 411229// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 411230// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 411231// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 411232// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 411233// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 411234// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 411235// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 411236// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 411237// CHECK19-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 411238// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 411239// CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 211240// CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 211241// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 411242// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])11243// CHECK19-NEXT: ret void11244//11245//11246// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined11247// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {11248// CHECK19-NEXT: entry:11249// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 411250// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 411251// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 411252// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 411253// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 411254// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 411255// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 411256// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 411257// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 411258// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 411259// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 411260// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 411261// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 411262// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 411263// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 411264// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 411265// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 411266// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 411267// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 411268// CHECK19-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 411269// CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 411270// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 411271// CHECK19-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 411272// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 411273// CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)11274// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411275// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 911276// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]11277// CHECK19: cond.true:11278// CHECK19-NEXT: br label [[COND_END:%.*]]11279// CHECK19: cond.false:11280// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411281// CHECK19-NEXT: br label [[COND_END]]11282// CHECK19: cond.end:11283// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]11284// CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 411285// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 411286// CHECK19-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 411287// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]11288// CHECK19: omp.inner.for.cond:11289// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34:![0-9]+]]11290// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP34]]11291// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]11292// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]11293// CHECK19: omp.inner.for.body:11294// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]]11295// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 111296// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]11297// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP34]]11298// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP34]]11299// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 111300// CHECK19-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP34]]11301// CHECK19-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP34]]11302// CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i3211303// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 111304// CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i1611305// CHECK19-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP34]]11306// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 211307// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP34]]11308// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 111309// CHECK19-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP34]]11310// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]11311// CHECK19: omp.body.continue:11312// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]11313// CHECK19: omp.inner.for.inc:11314// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]]11315// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 111316// CHECK19-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]]11317// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]11318// CHECK19: omp.inner.for.end:11319// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]11320// CHECK19: omp.loop.exit:11321// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])11322// CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 411323// CHECK19-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 011324// CHECK19-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]11325// CHECK19: .omp.final.then:11326// CHECK19-NEXT: store i32 10, ptr [[I]], align 411327// CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]11328// CHECK19: .omp.final.done:11329// CHECK19-NEXT: ret void11330//11331//11332// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l9711333// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {11334// CHECK21-NEXT: entry:11335// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 811336// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 811337// CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 811338// CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 811339// CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 811340// CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])11341// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 811342// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 811343// CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 811344// CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 811345// CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 411346// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 411347// CHECK21-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])11348// CHECK21-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 211349// CHECK21-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 211350// CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 811351// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i64 [[TMP4]])11352// CHECK21-NEXT: ret void11353//11354//11355// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined11356// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {11357// CHECK21-NEXT: entry:11358// CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 811359// CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 811360// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 811361// CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 411362// CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 411363// CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 411364// CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 411365// CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 411366// CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 411367// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 411368// CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 811369// CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 811370// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 811371// CHECK21-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 411372// CHECK21-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 411373// CHECK21-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 411374// CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 411375// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 811376// CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 411377// CHECK21-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)11378// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411379// CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 911380// CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]11381// CHECK21: cond.true:11382// CHECK21-NEXT: br label [[COND_END:%.*]]11383// CHECK21: cond.false:11384// CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411385// CHECK21-NEXT: br label [[COND_END]]11386// CHECK21: cond.end:11387// CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]11388// CHECK21-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 411389// CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 411390// CHECK21-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 411391// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]11392// CHECK21: omp.inner.for.cond:11393// CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]11394// CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]]11395// CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]11396// CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]11397// CHECK21: omp.inner.for.body:11398// CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]11399// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 111400// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]11401// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]11402// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]11403// CHECK21: omp.body.continue:11404// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]11405// CHECK21: omp.inner.for.inc:11406// CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]11407// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 111408// CHECK21-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]11409// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]11410// CHECK21: omp.inner.for.end:11411// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]11412// CHECK21: omp.loop.exit:11413// CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])11414// CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 411415// CHECK21-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 011416// CHECK21-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]11417// CHECK21: .omp.final.then:11418// CHECK21-NEXT: store i32 10, ptr [[I]], align 411419// CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]11420// CHECK21: .omp.final.done:11421// CHECK21-NEXT: ret void11422//11423//11424// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l11111425// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {11426// CHECK21-NEXT: entry:11427// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 811428// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 811429// CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 811430// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 811431// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 811432// CHECK21-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 211433// CHECK21-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 211434// CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 811435// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP1]])11436// CHECK21-NEXT: ret void11437//11438//11439// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined11440// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {11441// CHECK21-NEXT: entry:11442// CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 811443// CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 811444// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 811445// CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 411446// CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 411447// CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 411448// CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 411449// CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 411450// CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 411451// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 411452// CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 811453// CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 811454// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 811455// CHECK21-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 411456// CHECK21-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 411457// CHECK21-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 411458// CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 411459// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 811460// CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 411461// CHECK21-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)11462// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411463// CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 911464// CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]11465// CHECK21: cond.true:11466// CHECK21-NEXT: br label [[COND_END:%.*]]11467// CHECK21: cond.false:11468// CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411469// CHECK21-NEXT: br label [[COND_END]]11470// CHECK21: cond.end:11471// CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]11472// CHECK21-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 411473// CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 411474// CHECK21-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 411475// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]11476// CHECK21: omp.inner.for.cond:11477// CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]]11478// CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]]11479// CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]11480// CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]11481// CHECK21: omp.inner.for.body:11482// CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]11483// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 111484// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]11485// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]11486// CHECK21-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]]11487// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i3211488// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 111489// CHECK21-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i1611490// CHECK21-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]]11491// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]11492// CHECK21: omp.body.continue:11493// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]11494// CHECK21: omp.inner.for.inc:11495// CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]11496// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 111497// CHECK21-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]11498// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]11499// CHECK21: omp.inner.for.end:11500// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]11501// CHECK21: omp.loop.exit:11502// CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])11503// CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 411504// CHECK21-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 011505// CHECK21-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]11506// CHECK21: .omp.final.then:11507// CHECK21-NEXT: store i32 10, ptr [[I]], align 411508// CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]11509// CHECK21: .omp.final.done:11510// CHECK21-NEXT: ret void11511//11512//11513// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l11811514// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {11515// CHECK21-NEXT: entry:11516// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 811517// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 811518// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 811519// CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 811520// CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 811521// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 811522// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 811523// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 811524// CHECK21-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 411525// CHECK21-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 411526// CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 811527// CHECK21-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 211528// CHECK21-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 211529// CHECK21-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 811530// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])11531// CHECK21-NEXT: ret void11532//11533//11534// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined11535// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {11536// CHECK21-NEXT: entry:11537// CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 811538// CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 811539// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 811540// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 811541// CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 411542// CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 411543// CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 411544// CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 411545// CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 411546// CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 411547// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 411548// CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 811549// CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 811550// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 811551// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 811552// CHECK21-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 411553// CHECK21-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 411554// CHECK21-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 411555// CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 411556// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 811557// CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 411558// CHECK21-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)11559// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411560// CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 911561// CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]11562// CHECK21: cond.true:11563// CHECK21-NEXT: br label [[COND_END:%.*]]11564// CHECK21: cond.false:11565// CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411566// CHECK21-NEXT: br label [[COND_END]]11567// CHECK21: cond.end:11568// CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]11569// CHECK21-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 411570// CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 411571// CHECK21-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 411572// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]11573// CHECK21: omp.inner.for.cond:11574// CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]]11575// CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]]11576// CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]11577// CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]11578// CHECK21: omp.inner.for.body:11579// CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]11580// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 111581// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]11582// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]]11583// CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]]11584// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 111585// CHECK21-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]]11586// CHECK21-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]]11587// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i3211588// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 111589// CHECK21-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i1611590// CHECK21-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]]11591// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]11592// CHECK21: omp.body.continue:11593// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]11594// CHECK21: omp.inner.for.inc:11595// CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]11596// CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 111597// CHECK21-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]11598// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]11599// CHECK21: omp.inner.for.end:11600// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]11601// CHECK21: omp.loop.exit:11602// CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])11603// CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 411604// CHECK21-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 011605// CHECK21-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]11606// CHECK21: .omp.final.then:11607// CHECK21-NEXT: store i32 10, ptr [[I]], align 411608// CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]11609// CHECK21: .omp.final.done:11610// CHECK21-NEXT: ret void11611//11612//11613// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l14211614// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {11615// CHECK21-NEXT: entry:11616// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 811617// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 811618// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 811619// CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 811620// CHECK21-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 811621// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 811622// CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 811623// CHECK21-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 811624// CHECK21-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 811625// CHECK21-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 811626// CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 811627// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 811628// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 811629// CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 811630// CHECK21-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 811631// CHECK21-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 811632// CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 811633// CHECK21-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 811634// CHECK21-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 811635// CHECK21-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 811636// CHECK21-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 811637// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 811638// CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 811639// CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 811640// CHECK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 811641// CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 811642// CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 811643// CHECK21-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 811644// CHECK21-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 811645// CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 411646// CHECK21-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 411647// CHECK21-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 811648// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])11649// CHECK21-NEXT: ret void11650//11651//11652// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined11653// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {11654// CHECK21-NEXT: entry:11655// CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 811656// CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 811657// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 811658// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 811659// CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 811660// CHECK21-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 811661// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 811662// CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 811663// CHECK21-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 811664// CHECK21-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 811665// CHECK21-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 811666// CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 411667// CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 411668// CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 411669// CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 411670// CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 411671// CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 411672// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 411673// CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 811674// CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 811675// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 811676// CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 811677// CHECK21-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 811678// CHECK21-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 811679// CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 811680// CHECK21-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 811681// CHECK21-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 811682// CHECK21-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 811683// CHECK21-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 811684// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 811685// CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 811686// CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 811687// CHECK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 811688// CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 811689// CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 811690// CHECK21-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 811691// CHECK21-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 811692// CHECK21-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 011693// CHECK21-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i64 16) ]11694// CHECK21-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 411695// CHECK21-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 411696// CHECK21-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 411697// CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 411698// CHECK21-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 811699// CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 411700// CHECK21-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)11701// CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411702// CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 911703// CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]11704// CHECK21: cond.true:11705// CHECK21-NEXT: br label [[COND_END:%.*]]11706// CHECK21: cond.false:11707// CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411708// CHECK21-NEXT: br label [[COND_END]]11709// CHECK21: cond.end:11710// CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]11711// CHECK21-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 411712// CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 411713// CHECK21-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 411714// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]11715// CHECK21: omp.inner.for.cond:11716// CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]]11717// CHECK21-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]]11718// CHECK21-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]11719// CHECK21-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]11720// CHECK21: omp.inner.for.body:11721// CHECK21-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]11722// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 111723// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]11724// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]]11725// CHECK21-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]]11726// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 111727// CHECK21-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]]11728// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 211729// CHECK21-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]]11730// CHECK21-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double11731// CHECK21-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+0011732// CHECK21-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float11733// CHECK21-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]]11734// CHECK21-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 311735// CHECK21-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP24]]11736// CHECK21-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double11737// CHECK21-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+0011738// CHECK21-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float11739// CHECK21-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP24]]11740// CHECK21-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 111741// CHECK21-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i64 0, i64 211742// CHECK21-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP24]]11743// CHECK21-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+0011744// CHECK21-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP24]]11745// CHECK21-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]]11746// CHECK21-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP20]]11747// CHECK21-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i64 311748// CHECK21-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP24]]11749// CHECK21-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+0011750// CHECK21-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP24]]11751// CHECK21-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 011752// CHECK21-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP24]]11753// CHECK21-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 111754// CHECK21-NEXT: store i64 [[ADD19]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP24]]11755// CHECK21-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 111756// CHECK21-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP24]]11757// CHECK21-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i3211758// CHECK21-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 111759// CHECK21-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i811760// CHECK21-NEXT: store i8 [[CONV22]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP24]]11761// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]11762// CHECK21: omp.body.continue:11763// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]11764// CHECK21: omp.inner.for.inc:11765// CHECK21-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]11766// CHECK21-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 111767// CHECK21-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]11768// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]11769// CHECK21: omp.inner.for.end:11770// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]11771// CHECK21: omp.loop.exit:11772// CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP9]])11773// CHECK21-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 411774// CHECK21-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 011775// CHECK21-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]11776// CHECK21: .omp.final.then:11777// CHECK21-NEXT: store i32 10, ptr [[I]], align 411778// CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]11779// CHECK21: .omp.final.done:11780// CHECK21-NEXT: ret void11781//11782//11783// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l19711784// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {11785// CHECK21-NEXT: entry:11786// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 811787// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 811788// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i64, align 811789// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 811790// CHECK21-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 811791// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 811792// CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 811793// CHECK21-NEXT: [[N_CASTED:%.*]] = alloca i64, align 811794// CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 811795// CHECK21-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 811796// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 811797// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 811798// CHECK21-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 811799// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 811800// CHECK21-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 811801// CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 811802// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 811803// CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 411804// CHECK21-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 411805// CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 811806// CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 411807// CHECK21-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 411808// CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 811809// CHECK21-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 211810// CHECK21-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 211811// CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[AA_CASTED]], align 811812// CHECK21-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 111813// CHECK21-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 111814// CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[AAA_CASTED]], align 811815// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], ptr [[TMP0]])11816// CHECK21-NEXT: ret void11817//11818//11819// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined11820// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {11821// CHECK21-NEXT: entry:11822// CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 811823// CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 811824// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 811825// CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i64, align 811826// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 811827// CHECK21-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 811828// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 811829// CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 411830// CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 411831// CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 411832// CHECK21-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 411833// CHECK21-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 411834// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 411835// CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 411836// CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 411837// CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 411838// CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 411839// CHECK21-NEXT: [[I5:%.*]] = alloca i32, align 411840// CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 811841// CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 811842// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 811843// CHECK21-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 811844// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 811845// CHECK21-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 811846// CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 811847// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 811848// CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 411849// CHECK21-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 411850// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 411851// CHECK21-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 411852// CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 411853// CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 411854// CHECK21-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]11855// CHECK21-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 111856// CHECK21-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 111857// CHECK21-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 111858// CHECK21-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 111859// CHECK21-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 411860// CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 411861// CHECK21-NEXT: store i32 [[TMP5]], ptr [[I]], align 411862// CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 411863// CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 411864// CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]11865// CHECK21-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]11866// CHECK21: omp.precond.then:11867// CHECK21-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 411868// CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 411869// CHECK21-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 411870// CHECK21-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 411871// CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 411872// CHECK21-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 811873// CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 411874// CHECK21-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)11875// CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411876// CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 411877// CHECK21-NEXT: [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]11878// CHECK21-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]11879// CHECK21: cond.true:11880// CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 411881// CHECK21-NEXT: br label [[COND_END:%.*]]11882// CHECK21: cond.false:11883// CHECK21-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 411884// CHECK21-NEXT: br label [[COND_END]]11885// CHECK21: cond.end:11886// CHECK21-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]11887// CHECK21-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 411888// CHECK21-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 411889// CHECK21-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 411890// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]11891// CHECK21: omp.inner.for.cond:11892// CHECK21-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]]11893// CHECK21-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]]11894// CHECK21-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 111895// CHECK21-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]11896// CHECK21-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]11897// CHECK21: omp.inner.for.body:11898// CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP27]]11899// CHECK21-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]11900// CHECK21-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 111901// CHECK21-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]11902// CHECK21-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP27]]11903// CHECK21-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]]11904// CHECK21-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 111905// CHECK21-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]]11906// CHECK21-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP27]]11907// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i3211908// CHECK21-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 111909// CHECK21-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i1611910// CHECK21-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP27]]11911// CHECK21-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP27]]11912// CHECK21-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i3211913// CHECK21-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 111914// CHECK21-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i811915// CHECK21-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP27]]11916// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 211917// CHECK21-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]]11918// CHECK21-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 111919// CHECK21-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]]11920// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]11921// CHECK21: omp.body.continue:11922// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]11923// CHECK21: omp.inner.for.inc:11924// CHECK21-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]11925// CHECK21-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 111926// CHECK21-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]11927// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]11928// CHECK21: omp.inner.for.end:11929// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]11930// CHECK21: omp.loop.exit:11931// CHECK21-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 811932// CHECK21-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 411933// CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])11934// CHECK21-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 411935// CHECK21-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 011936// CHECK21-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]11937// CHECK21: .omp.final.then:11938// CHECK21-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 411939// CHECK21-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 411940// CHECK21-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 411941// CHECK21-NEXT: [[SUB18:%.*]] = sub i32 [[TMP30]], [[TMP31]]11942// CHECK21-NEXT: [[SUB19:%.*]] = sub i32 [[SUB18]], 111943// CHECK21-NEXT: [[ADD20:%.*]] = add i32 [[SUB19]], 111944// CHECK21-NEXT: [[DIV21:%.*]] = udiv i32 [[ADD20]], 111945// CHECK21-NEXT: [[MUL22:%.*]] = mul i32 [[DIV21]], 111946// CHECK21-NEXT: [[ADD23:%.*]] = add i32 [[TMP29]], [[MUL22]]11947// CHECK21-NEXT: store i32 [[ADD23]], ptr [[I5]], align 411948// CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]11949// CHECK21: .omp.final.done:11950// CHECK21-NEXT: br label [[OMP_PRECOND_END]]11951// CHECK21: omp.precond.end:11952// CHECK21-NEXT: ret void11953//11954//11955// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l21511956// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {11957// CHECK21-NEXT: entry:11958// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 811959// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 811960// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 811961// CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 811962// CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 811963// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 811964// CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 811965// CHECK21-NEXT: [[B_CASTED:%.*]] = alloca i64, align 811966// CHECK21-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 811967// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 811968// CHECK21-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 811969// CHECK21-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 811970// CHECK21-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 811971// CHECK21-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 811972// CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 811973// CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 811974// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 811975// CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 811976// CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 811977// CHECK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 811978// CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 411979// CHECK21-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 411980// CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 811981// CHECK21-NEXT: [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 111982// CHECK21-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP6]] to i111983// CHECK21-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i811984// CHECK21-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 111985// CHECK21-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 811986// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]], i64 [[TMP7]])11987// CHECK21-NEXT: ret void11988//11989//11990// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined11991// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {11992// CHECK21-NEXT: entry:11993// CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 811994// CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 811995// CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 811996// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 811997// CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 811998// CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 811999// CHECK21-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 812000// CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 812001// CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 412002// CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 412003// CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 412004// CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 412005// CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 412006// CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 412007// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 412008// CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 812009// CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 812010// CHECK21-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 812011// CHECK21-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 812012// CHECK21-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 812013// CHECK21-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 812014// CHECK21-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 812015// CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 812016// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 812017// CHECK21-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 812018// CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 812019// CHECK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 812020// CHECK21-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 412021// CHECK21-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 412022// CHECK21-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 412023// CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 412024// CHECK21-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 812025// CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 412026// CHECK21-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)12027// CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 412028// CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 912029// CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]12030// CHECK21: cond.true:12031// CHECK21-NEXT: br label [[COND_END:%.*]]12032// CHECK21: cond.false:12033// CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 412034// CHECK21-NEXT: br label [[COND_END]]12035// CHECK21: cond.end:12036// CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]12037// CHECK21-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 412038// CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 412039// CHECK21-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 412040// CHECK21-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 112041// CHECK21-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP9]] to i112042// CHECK21-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]12043// CHECK21: omp_if.then:12044// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]12045// CHECK21: omp.inner.for.cond:12046// CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30:![0-9]+]]12047// CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP30]]12048// CHECK21-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]12049// CHECK21-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]12050// CHECK21: omp.inner.for.body:12051// CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]]12052// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 112053// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]12054// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP30]]12055// CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP30]]12056// CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double12057// CHECK21-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+0012058// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 012059// CHECK21-NEXT: store double [[ADD4]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP30]]12060// CHECK21-NEXT: [[A5:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 012061// CHECK21-NEXT: [[TMP14:%.*]] = load double, ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP30]]12062// CHECK21-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+0012063// CHECK21-NEXT: store double [[INC]], ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP30]]12064// CHECK21-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i1612065// CHECK21-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]]12066// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP15]]12067// CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 112068// CHECK21-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP30]]12069// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]12070// CHECK21: omp.body.continue:12071// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]12072// CHECK21: omp.inner.for.inc:12073// CHECK21-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]]12074// CHECK21-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], 112075// CHECK21-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]]12076// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]12077// CHECK21: omp.inner.for.end:12078// CHECK21-NEXT: br label [[OMP_IF_END:%.*]]12079// CHECK21: omp_if.else:12080// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]12081// CHECK21: omp.inner.for.cond9:12082// CHECK21-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 412083// CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_UB]], align 412084// CHECK21-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]12085// CHECK21-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]]12086// CHECK21: omp.inner.for.body11:12087// CHECK21-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 412088// CHECK21-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP19]], 112089// CHECK21-NEXT: [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]12090// CHECK21-NEXT: store i32 [[ADD13]], ptr [[I]], align 412091// CHECK21-NEXT: [[TMP20:%.*]] = load i32, ptr [[B_ADDR]], align 412092// CHECK21-NEXT: [[CONV14:%.*]] = sitofp i32 [[TMP20]] to double12093// CHECK21-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+0012094// CHECK21-NEXT: [[A16:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 012095// CHECK21-NEXT: store double [[ADD15]], ptr [[A16]], align 812096// CHECK21-NEXT: [[A17:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 012097// CHECK21-NEXT: [[TMP21:%.*]] = load double, ptr [[A17]], align 812098// CHECK21-NEXT: [[INC18:%.*]] = fadd double [[TMP21]], 1.000000e+0012099// CHECK21-NEXT: store double [[INC18]], ptr [[A17]], align 812100// CHECK21-NEXT: [[CONV19:%.*]] = fptosi double [[INC18]] to i1612101// CHECK21-NEXT: [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]12102// CHECK21-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP22]]12103// CHECK21-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX20]], i64 112104// CHECK21-NEXT: store i16 [[CONV19]], ptr [[ARRAYIDX21]], align 212105// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE22:%.*]]12106// CHECK21: omp.body.continue22:12107// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC23:%.*]]12108// CHECK21: omp.inner.for.inc23:12109// CHECK21-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 412110// CHECK21-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP23]], 112111// CHECK21-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 412112// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP33:![0-9]+]]12113// CHECK21: omp.inner.for.end25:12114// CHECK21-NEXT: br label [[OMP_IF_END]]12115// CHECK21: omp_if.end:12116// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]12117// CHECK21: omp.loop.exit:12118// CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])12119// CHECK21-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 412120// CHECK21-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 012121// CHECK21-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]12122// CHECK21: .omp.final.then:12123// CHECK21-NEXT: store i32 10, ptr [[I]], align 412124// CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]12125// CHECK21: .omp.final.done:12126// CHECK21-NEXT: ret void12127//12128//12129// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l18012130// CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {12131// CHECK21-NEXT: entry:12132// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 812133// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 812134// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 812135// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 812136// CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 812137// CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 812138// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 812139// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 812140// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 812141// CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 812142// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 812143// CHECK21-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 412144// CHECK21-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 412145// CHECK21-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 812146// CHECK21-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 212147// CHECK21-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 212148// CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 812149// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])12150// CHECK21-NEXT: ret void12151//12152//12153// CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined12154// CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {12155// CHECK21-NEXT: entry:12156// CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 812157// CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 812158// CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 812159// CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 812160// CHECK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 812161// CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 412162// CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 412163// CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 412164// CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 412165// CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 412166// CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 412167// CHECK21-NEXT: [[I:%.*]] = alloca i32, align 412168// CHECK21-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 812169// CHECK21-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 812170// CHECK21-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 812171// CHECK21-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 812172// CHECK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 812173// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 812174// CHECK21-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 412175// CHECK21-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 412176// CHECK21-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 412177// CHECK21-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 412178// CHECK21-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 812179// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 412180// CHECK21-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)12181// CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 412182// CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 912183// CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]12184// CHECK21: cond.true:12185// CHECK21-NEXT: br label [[COND_END:%.*]]12186// CHECK21: cond.false:12187// CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 412188// CHECK21-NEXT: br label [[COND_END]]12189// CHECK21: cond.end:12190// CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]12191// CHECK21-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 412192// CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 412193// CHECK21-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 412194// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]12195// CHECK21: omp.inner.for.cond:12196// CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35:![0-9]+]]12197// CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP35]]12198// CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]12199// CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]12200// CHECK21: omp.inner.for.body:12201// CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]12202// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 112203// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]12204// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP35]]12205// CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]]12206// CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 112207// CHECK21-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]]12208// CHECK21-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP35]]12209// CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i3212210// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 112211// CHECK21-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i1612212// CHECK21-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP35]]12213// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 212214// CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]]12215// CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 112216// CHECK21-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]]12217// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]12218// CHECK21: omp.body.continue:12219// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]12220// CHECK21: omp.inner.for.inc:12221// CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]12222// CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 112223// CHECK21-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]12224// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]12225// CHECK21: omp.inner.for.end:12226// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]12227// CHECK21: omp.loop.exit:12228// CHECK21-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])12229// CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 412230// CHECK21-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 012231// CHECK21-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]12232// CHECK21: .omp.final.then:12233// CHECK21-NEXT: store i32 10, ptr [[I]], align 412234// CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]12235// CHECK21: .omp.final.done:12236// CHECK21-NEXT: ret void12237//12238//12239// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l9712240// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {12241// CHECK23-NEXT: entry:12242// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 412243// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 412244// CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 412245// CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 412246// CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 412247// CHECK23-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])12248// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 412249// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 412250// CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 412251// CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 412252// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 412253// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 412254// CHECK23-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])12255// CHECK23-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 212256// CHECK23-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 212257// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 412258// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i32 [[TMP4]])12259// CHECK23-NEXT: ret void12260//12261//12262// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined12263// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {12264// CHECK23-NEXT: entry:12265// CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 412266// CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 412267// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 412268// CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 412269// CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 412270// CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 412271// CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 412272// CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 412273// CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 412274// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 412275// CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 412276// CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 412277// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 412278// CHECK23-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 412279// CHECK23-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 412280// CHECK23-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 412281// CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 412282// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 412283// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 412284// CHECK23-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)12285// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 412286// CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 912287// CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]12288// CHECK23: cond.true:12289// CHECK23-NEXT: br label [[COND_END:%.*]]12290// CHECK23: cond.false:12291// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 412292// CHECK23-NEXT: br label [[COND_END]]12293// CHECK23: cond.end:12294// CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]12295// CHECK23-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 412296// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 412297// CHECK23-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 412298// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]12299// CHECK23: omp.inner.for.cond:12300// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]12301// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]12302// CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]12303// CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]12304// CHECK23: omp.inner.for.body:12305// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]12306// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 112307// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]12308// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]12309// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]12310// CHECK23: omp.body.continue:12311// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]12312// CHECK23: omp.inner.for.inc:12313// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]12314// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 112315// CHECK23-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]12316// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]12317// CHECK23: omp.inner.for.end:12318// CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]12319// CHECK23: omp.loop.exit:12320// CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])12321// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 412322// CHECK23-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 012323// CHECK23-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]12324// CHECK23: .omp.final.then:12325// CHECK23-NEXT: store i32 10, ptr [[I]], align 412326// CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]12327// CHECK23: .omp.final.done:12328// CHECK23-NEXT: ret void12329//12330//12331// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l11112332// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {12333// CHECK23-NEXT: entry:12334// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 412335// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 412336// CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 412337// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 412338// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 412339// CHECK23-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 212340// CHECK23-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 212341// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 412342// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP1]])12343// CHECK23-NEXT: ret void12344//12345//12346// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined12347// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {12348// CHECK23-NEXT: entry:12349// CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 412350// CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 412351// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 412352// CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 412353// CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 412354// CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 412355// CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 412356// CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 412357// CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 412358// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 412359// CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 412360// CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 412361// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 412362// CHECK23-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 412363// CHECK23-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 412364// CHECK23-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 412365// CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 412366// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 412367// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 412368// CHECK23-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)12369// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 412370// CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 912371// CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]12372// CHECK23: cond.true:12373// CHECK23-NEXT: br label [[COND_END:%.*]]12374// CHECK23: cond.false:12375// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 412376// CHECK23-NEXT: br label [[COND_END]]12377// CHECK23: cond.end:12378// CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]12379// CHECK23-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 412380// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 412381// CHECK23-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 412382// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]12383// CHECK23: omp.inner.for.cond:12384// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]]12385// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]]12386// CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]12387// CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]12388// CHECK23: omp.inner.for.body:12389// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]12390// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 112391// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]12392// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]]12393// CHECK23-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP19]]12394// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i3212395// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 112396// CHECK23-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i1612397// CHECK23-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP19]]12398// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]12399// CHECK23: omp.body.continue:12400// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]12401// CHECK23: omp.inner.for.inc:12402// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]12403// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 112404// CHECK23-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]12405// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]12406// CHECK23: omp.inner.for.end:12407// CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]12408// CHECK23: omp.loop.exit:12409// CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])12410// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 412411// CHECK23-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 012412// CHECK23-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]12413// CHECK23: .omp.final.then:12414// CHECK23-NEXT: store i32 10, ptr [[I]], align 412415// CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]12416// CHECK23: .omp.final.done:12417// CHECK23-NEXT: ret void12418//12419//12420// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l11812421// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {12422// CHECK23-NEXT: entry:12423// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 412424// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 412425// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 412426// CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 412427// CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 412428// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 412429// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 412430// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 412431// CHECK23-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 412432// CHECK23-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 412433// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 412434// CHECK23-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 212435// CHECK23-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 212436// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 412437// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])12438// CHECK23-NEXT: ret void12439//12440//12441// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined12442// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {12443// CHECK23-NEXT: entry:12444// CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 412445// CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 412446// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 412447// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 412448// CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 412449// CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 412450// CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 412451// CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 412452// CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 412453// CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 412454// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 412455// CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 412456// CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 412457// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 412458// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 412459// CHECK23-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 412460// CHECK23-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 412461// CHECK23-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 412462// CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 412463// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 412464// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 412465// CHECK23-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)12466// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 412467// CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 912468// CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]12469// CHECK23: cond.true:12470// CHECK23-NEXT: br label [[COND_END:%.*]]12471// CHECK23: cond.false:12472// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 412473// CHECK23-NEXT: br label [[COND_END]]12474// CHECK23: cond.end:12475// CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]12476// CHECK23-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 412477// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 412478// CHECK23-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 412479// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]12480// CHECK23: omp.inner.for.cond:12481// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]]12482// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]]12483// CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]12484// CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]12485// CHECK23: omp.inner.for.body:12486// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]12487// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 112488// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]12489// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]]12490// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]]12491// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 112492// CHECK23-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]]12493// CHECK23-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP22]]12494// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i3212495// CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 112496// CHECK23-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i1612497// CHECK23-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP22]]12498// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]12499// CHECK23: omp.body.continue:12500// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]12501// CHECK23: omp.inner.for.inc:12502// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]12503// CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 112504// CHECK23-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]12505// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]12506// CHECK23: omp.inner.for.end:12507// CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]12508// CHECK23: omp.loop.exit:12509// CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])12510// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 412511// CHECK23-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 012512// CHECK23-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]12513// CHECK23: .omp.final.then:12514// CHECK23-NEXT: store i32 10, ptr [[I]], align 412515// CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]12516// CHECK23: .omp.final.done:12517// CHECK23-NEXT: ret void12518//12519//12520// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l14212521// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {12522// CHECK23-NEXT: entry:12523// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 412524// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 412525// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 412526// CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 412527// CHECK23-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 412528// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 412529// CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 412530// CHECK23-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 412531// CHECK23-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 412532// CHECK23-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 412533// CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 412534// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 412535// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 412536// CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 412537// CHECK23-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 412538// CHECK23-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 412539// CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 412540// CHECK23-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 412541// CHECK23-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 412542// CHECK23-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 412543// CHECK23-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 412544// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 412545// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 412546// CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 412547// CHECK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 412548// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 412549// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 412550// CHECK23-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 412551// CHECK23-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 412552// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 412553// CHECK23-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 412554// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 412555// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])12556// CHECK23-NEXT: ret void12557//12558//12559// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined12560// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {12561// CHECK23-NEXT: entry:12562// CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 412563// CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 412564// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 412565// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 412566// CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 412567// CHECK23-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 412568// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 412569// CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 412570// CHECK23-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 412571// CHECK23-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 412572// CHECK23-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 412573// CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 412574// CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 412575// CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 412576// CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 412577// CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 412578// CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 412579// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 412580// CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 412581// CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 412582// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 412583// CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 412584// CHECK23-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 412585// CHECK23-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 412586// CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 412587// CHECK23-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 412588// CHECK23-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 412589// CHECK23-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 412590// CHECK23-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 412591// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 412592// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 412593// CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 412594// CHECK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 412595// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 412596// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 412597// CHECK23-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 412598// CHECK23-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 412599// CHECK23-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 012600// CHECK23-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i32 16) ]12601// CHECK23-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 412602// CHECK23-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 412603// CHECK23-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 412604// CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 412605// CHECK23-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 412606// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 412607// CHECK23-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)12608// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 412609// CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 912610// CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]12611// CHECK23: cond.true:12612// CHECK23-NEXT: br label [[COND_END:%.*]]12613// CHECK23: cond.false:12614// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 412615// CHECK23-NEXT: br label [[COND_END]]12616// CHECK23: cond.end:12617// CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]12618// CHECK23-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 412619// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 412620// CHECK23-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 412621// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]12622// CHECK23: omp.inner.for.cond:12623// CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]]12624// CHECK23-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP25]]12625// CHECK23-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]12626// CHECK23-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]12627// CHECK23: omp.inner.for.body:12628// CHECK23-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]12629// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 112630// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]12631// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]]12632// CHECK23-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP25]]12633// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 112634// CHECK23-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP25]]12635// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 212636// CHECK23-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]12637// CHECK23-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double12638// CHECK23-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+0012639// CHECK23-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float12640// CHECK23-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]12641// CHECK23-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 312642// CHECK23-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP25]]12643// CHECK23-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double12644// CHECK23-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+0012645// CHECK23-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float12646// CHECK23-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP25]]12647// CHECK23-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 112648// CHECK23-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i32 0, i32 212649// CHECK23-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP25]]12650// CHECK23-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+0012651// CHECK23-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP25]]12652// CHECK23-NEXT: [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]]12653// CHECK23-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP20]]12654// CHECK23-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i32 312655// CHECK23-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP25]]12656// CHECK23-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+0012657// CHECK23-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP25]]12658// CHECK23-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 012659// CHECK23-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP25]]12660// CHECK23-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 112661// CHECK23-NEXT: store i64 [[ADD19]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP25]]12662// CHECK23-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 112663// CHECK23-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP25]]12664// CHECK23-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i3212665// CHECK23-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 112666// CHECK23-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i812667// CHECK23-NEXT: store i8 [[CONV22]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP25]]12668// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]12669// CHECK23: omp.body.continue:12670// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]12671// CHECK23: omp.inner.for.inc:12672// CHECK23-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]12673// CHECK23-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 112674// CHECK23-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]12675// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]12676// CHECK23: omp.inner.for.end:12677// CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]12678// CHECK23: omp.loop.exit:12679// CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP9]])12680// CHECK23-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 412681// CHECK23-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 012682// CHECK23-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]12683// CHECK23: .omp.final.then:12684// CHECK23-NEXT: store i32 10, ptr [[I]], align 412685// CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]12686// CHECK23: .omp.final.done:12687// CHECK23-NEXT: ret void12688//12689//12690// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l19712691// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {12692// CHECK23-NEXT: entry:12693// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 412694// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 412695// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 412696// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 412697// CHECK23-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 412698// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 412699// CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 412700// CHECK23-NEXT: [[N_CASTED:%.*]] = alloca i32, align 412701// CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 412702// CHECK23-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 412703// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 412704// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 412705// CHECK23-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 412706// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 412707// CHECK23-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 412708// CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 412709// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 412710// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 412711// CHECK23-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 412712// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 412713// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 412714// CHECK23-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 412715// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 412716// CHECK23-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 212717// CHECK23-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 212718// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[AA_CASTED]], align 412719// CHECK23-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 112720// CHECK23-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 112721// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[AAA_CASTED]], align 412722// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], ptr [[TMP0]])12723// CHECK23-NEXT: ret void12724//12725//12726// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined12727// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {12728// CHECK23-NEXT: entry:12729// CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 412730// CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 412731// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 412732// CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 412733// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 412734// CHECK23-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 412735// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 412736// CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 412737// CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 412738// CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 412739// CHECK23-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 412740// CHECK23-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 412741// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 412742// CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 412743// CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 412744// CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 412745// CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 412746// CHECK23-NEXT: [[I5:%.*]] = alloca i32, align 412747// CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 412748// CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 412749// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 412750// CHECK23-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 412751// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 412752// CHECK23-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 412753// CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 412754// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 412755// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 412756// CHECK23-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 412757// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 412758// CHECK23-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 412759// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 412760// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 412761// CHECK23-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]12762// CHECK23-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 112763// CHECK23-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 112764// CHECK23-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 112765// CHECK23-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 112766// CHECK23-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 412767// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 412768// CHECK23-NEXT: store i32 [[TMP5]], ptr [[I]], align 412769// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 412770// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 412771// CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]12772// CHECK23-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]12773// CHECK23: omp.precond.then:12774// CHECK23-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 412775// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 412776// CHECK23-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 412777// CHECK23-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 412778// CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 412779// CHECK23-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 412780// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 412781// CHECK23-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)12782// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 412783// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 412784// CHECK23-NEXT: [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]12785// CHECK23-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]12786// CHECK23: cond.true:12787// CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 412788// CHECK23-NEXT: br label [[COND_END:%.*]]12789// CHECK23: cond.false:12790// CHECK23-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 412791// CHECK23-NEXT: br label [[COND_END]]12792// CHECK23: cond.end:12793// CHECK23-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]12794// CHECK23-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 412795// CHECK23-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 412796// CHECK23-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 412797// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]12798// CHECK23: omp.inner.for.cond:12799// CHECK23-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]]12800// CHECK23-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP28]]12801// CHECK23-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 112802// CHECK23-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]12803// CHECK23-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]12804// CHECK23: omp.inner.for.body:12805// CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP28]]12806// CHECK23-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]12807// CHECK23-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 112808// CHECK23-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]12809// CHECK23-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP28]]12810// CHECK23-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP28]]12811// CHECK23-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 112812// CHECK23-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP28]]12813// CHECK23-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP28]]12814// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i3212815// CHECK23-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 112816// CHECK23-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i1612817// CHECK23-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP28]]12818// CHECK23-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP28]]12819// CHECK23-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i3212820// CHECK23-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 112821// CHECK23-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i812822// CHECK23-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP28]]12823// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 212824// CHECK23-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]]12825// CHECK23-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 112826// CHECK23-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]]12827// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]12828// CHECK23: omp.body.continue:12829// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]12830// CHECK23: omp.inner.for.inc:12831// CHECK23-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]12832// CHECK23-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 112833// CHECK23-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]12834// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]12835// CHECK23: omp.inner.for.end:12836// CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]12837// CHECK23: omp.loop.exit:12838// CHECK23-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 412839// CHECK23-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 412840// CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])12841// CHECK23-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 412842// CHECK23-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 012843// CHECK23-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]12844// CHECK23: .omp.final.then:12845// CHECK23-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 412846// CHECK23-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 412847// CHECK23-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 412848// CHECK23-NEXT: [[SUB18:%.*]] = sub i32 [[TMP30]], [[TMP31]]12849// CHECK23-NEXT: [[SUB19:%.*]] = sub i32 [[SUB18]], 112850// CHECK23-NEXT: [[ADD20:%.*]] = add i32 [[SUB19]], 112851// CHECK23-NEXT: [[DIV21:%.*]] = udiv i32 [[ADD20]], 112852// CHECK23-NEXT: [[MUL22:%.*]] = mul i32 [[DIV21]], 112853// CHECK23-NEXT: [[ADD23:%.*]] = add i32 [[TMP29]], [[MUL22]]12854// CHECK23-NEXT: store i32 [[ADD23]], ptr [[I5]], align 412855// CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]12856// CHECK23: .omp.final.done:12857// CHECK23-NEXT: br label [[OMP_PRECOND_END]]12858// CHECK23: omp.precond.end:12859// CHECK23-NEXT: ret void12860//12861//12862// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l21512863// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {12864// CHECK23-NEXT: entry:12865// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 412866// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 412867// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 412868// CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 412869// CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 412870// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 412871// CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 412872// CHECK23-NEXT: [[B_CASTED:%.*]] = alloca i32, align 412873// CHECK23-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 412874// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 412875// CHECK23-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 412876// CHECK23-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 412877// CHECK23-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 412878// CHECK23-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 412879// CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 412880// CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 412881// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 412882// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 412883// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 412884// CHECK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 412885// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 412886// CHECK23-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 412887// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 412888// CHECK23-NEXT: [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 112889// CHECK23-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP6]] to i112890// CHECK23-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i812891// CHECK23-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 112892// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 412893// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]], i32 [[TMP7]])12894// CHECK23-NEXT: ret void12895//12896//12897// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined12898// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {12899// CHECK23-NEXT: entry:12900// CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 412901// CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 412902// CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 412903// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 412904// CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 412905// CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 412906// CHECK23-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 412907// CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 412908// CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 412909// CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 412910// CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 412911// CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 412912// CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 412913// CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 412914// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 412915// CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 412916// CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 412917// CHECK23-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 412918// CHECK23-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 412919// CHECK23-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 412920// CHECK23-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 412921// CHECK23-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 412922// CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 412923// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 412924// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 412925// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 412926// CHECK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 412927// CHECK23-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 412928// CHECK23-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 412929// CHECK23-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 412930// CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 412931// CHECK23-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 412932// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 412933// CHECK23-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)12934// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 412935// CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 912936// CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]12937// CHECK23: cond.true:12938// CHECK23-NEXT: br label [[COND_END:%.*]]12939// CHECK23: cond.false:12940// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 412941// CHECK23-NEXT: br label [[COND_END]]12942// CHECK23: cond.end:12943// CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]12944// CHECK23-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 412945// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 412946// CHECK23-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 412947// CHECK23-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 112948// CHECK23-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP9]] to i112949// CHECK23-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]12950// CHECK23: omp_if.then:12951// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]12952// CHECK23: omp.inner.for.cond:12953// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31:![0-9]+]]12954// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP31]]12955// CHECK23-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]12956// CHECK23-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]12957// CHECK23: omp.inner.for.body:12958// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]]12959// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 112960// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]12961// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP31]]12962// CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP31]]12963// CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double12964// CHECK23-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+0012965// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 012966// CHECK23-NEXT: store double [[ADD4]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP31]]12967// CHECK23-NEXT: [[A5:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 012968// CHECK23-NEXT: [[TMP14:%.*]] = load double, ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP31]]12969// CHECK23-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+0012970// CHECK23-NEXT: store double [[INC]], ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP31]]12971// CHECK23-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i1612972// CHECK23-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]]12973// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP15]]12974// CHECK23-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 112975// CHECK23-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP31]]12976// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]12977// CHECK23: omp.body.continue:12978// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]12979// CHECK23: omp.inner.for.inc:12980// CHECK23-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]]12981// CHECK23-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], 112982// CHECK23-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]]12983// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]12984// CHECK23: omp.inner.for.end:12985// CHECK23-NEXT: br label [[OMP_IF_END:%.*]]12986// CHECK23: omp_if.else:12987// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]]12988// CHECK23: omp.inner.for.cond9:12989// CHECK23-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 412990// CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_UB]], align 412991// CHECK23-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]12992// CHECK23-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]]12993// CHECK23: omp.inner.for.body11:12994// CHECK23-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 412995// CHECK23-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP19]], 112996// CHECK23-NEXT: [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]12997// CHECK23-NEXT: store i32 [[ADD13]], ptr [[I]], align 412998// CHECK23-NEXT: [[TMP20:%.*]] = load i32, ptr [[B_ADDR]], align 412999// CHECK23-NEXT: [[CONV14:%.*]] = sitofp i32 [[TMP20]] to double13000// CHECK23-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+0013001// CHECK23-NEXT: [[A16:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 013002// CHECK23-NEXT: store double [[ADD15]], ptr [[A16]], align 413003// CHECK23-NEXT: [[A17:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 013004// CHECK23-NEXT: [[TMP21:%.*]] = load double, ptr [[A17]], align 413005// CHECK23-NEXT: [[INC18:%.*]] = fadd double [[TMP21]], 1.000000e+0013006// CHECK23-NEXT: store double [[INC18]], ptr [[A17]], align 413007// CHECK23-NEXT: [[CONV19:%.*]] = fptosi double [[INC18]] to i1613008// CHECK23-NEXT: [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]]13009// CHECK23-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP22]]13010// CHECK23-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX20]], i32 113011// CHECK23-NEXT: store i16 [[CONV19]], ptr [[ARRAYIDX21]], align 213012// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE22:%.*]]13013// CHECK23: omp.body.continue22:13014// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC23:%.*]]13015// CHECK23: omp.inner.for.inc23:13016// CHECK23-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 413017// CHECK23-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP23]], 113018// CHECK23-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 413019// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP34:![0-9]+]]13020// CHECK23: omp.inner.for.end25:13021// CHECK23-NEXT: br label [[OMP_IF_END]]13022// CHECK23: omp_if.end:13023// CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]13024// CHECK23: omp.loop.exit:13025// CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])13026// CHECK23-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 413027// CHECK23-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 013028// CHECK23-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]13029// CHECK23: .omp.final.then:13030// CHECK23-NEXT: store i32 10, ptr [[I]], align 413031// CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]13032// CHECK23: .omp.final.done:13033// CHECK23-NEXT: ret void13034//13035//13036// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l18013037// CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {13038// CHECK23-NEXT: entry:13039// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 413040// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 413041// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 413042// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 413043// CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 413044// CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 413045// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 413046// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 413047// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 413048// CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 413049// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 413050// CHECK23-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 413051// CHECK23-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 413052// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 413053// CHECK23-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 213054// CHECK23-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 213055// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 413056// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])13057// CHECK23-NEXT: ret void13058//13059//13060// CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined13061// CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {13062// CHECK23-NEXT: entry:13063// CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 413064// CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 413065// CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 413066// CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 413067// CHECK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 413068// CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 413069// CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 413070// CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 413071// CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 413072// CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 413073// CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 413074// CHECK23-NEXT: [[I:%.*]] = alloca i32, align 413075// CHECK23-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 413076// CHECK23-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 413077// CHECK23-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 413078// CHECK23-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 413079// CHECK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 413080// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 413081// CHECK23-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 413082// CHECK23-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 413083// CHECK23-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 413084// CHECK23-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 413085// CHECK23-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 413086// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 413087// CHECK23-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)13088// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 413089// CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 913090// CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]13091// CHECK23: cond.true:13092// CHECK23-NEXT: br label [[COND_END:%.*]]13093// CHECK23: cond.false:13094// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 413095// CHECK23-NEXT: br label [[COND_END]]13096// CHECK23: cond.end:13097// CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]13098// CHECK23-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 413099// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 413100// CHECK23-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 413101// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]13102// CHECK23: omp.inner.for.cond:13103// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]]13104// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP36]]13105// CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]13106// CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]13107// CHECK23: omp.inner.for.body:13108// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]13109// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 113110// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]13111// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP36]]13112// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]]13113// CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 113114// CHECK23-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]]13115// CHECK23-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP36]]13116// CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i3213117// CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 113118// CHECK23-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i1613119// CHECK23-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP36]]13120// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 213121// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]]13122// CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 113123// CHECK23-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]]13124// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]13125// CHECK23: omp.body.continue:13126// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]13127// CHECK23: omp.inner.for.inc:13128// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]13129// CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 113130// CHECK23-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]13131// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]13132// CHECK23: omp.inner.for.end:13133// CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]13134// CHECK23: omp.loop.exit:13135// CHECK23-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])13136// CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 413137// CHECK23-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 013138// CHECK23-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]13139// CHECK23: .omp.final.then:13140// CHECK23-NEXT: store i32 10, ptr [[I]], align 413141// CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]13142// CHECK23: .omp.final.done:13143// CHECK23-NEXT: ret void13144//13145