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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// expected-no-diagnostics3#ifndef HEADER4#define HEADER5 6// Test host codegen.7// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK18// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s9// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK110// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK311// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s12// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK313 14// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK515// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s16// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK517// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK718// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s19// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK720#ifdef CK121 22template <typename T, int X, long long Y>23struct SS{24  T a[X][Y];25 26  int foo(void) {27 28    #pragma omp target teams distribute simd collapse(2)29    for(int i = 0; i < X; i++) {30      for(int j = 0; j < Y; j++) {31        a[i][j] = (T)0;32      }33    }34 35    // discard loop variables not needed here36 37    return a[0][0];38  }39};40 41int teams_template_struct(void) {42  SS<int, 123, 456> V;43  return V.foo();44 45}46#endif // CK147 48// Test host codegen.49// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK950// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s51// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK952// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1153// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s54// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1155 56// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1357// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s58// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1359// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1560// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s61// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1562#ifdef CK263 64template <typename T, int n, int m>65int tmain(T argc) {66  T a[n][m];67  #pragma omp target teams distribute simd collapse(2)68  for(int i = 0; i < n; i++) {69    for(int j = 0; j < m; j++) {70      a[i][j] = (T)0;71    }72  }73  return 0;74}75 76int main (int argc, char **argv) {77  int n = 100;78  int m = 2;79  int a[n][m];80  #pragma omp target teams distribute simd collapse(2)81  for(int i = 0; i < n; i++) {82    for(int j = 0; j < m; j++) {83      a[i][j] = 0;84    }85  }86  return tmain<int, 10, 2>(argc);87}88 89 90 91 92 93// discard loop variables not needed here94 95#endif // CK296#endif // #ifndef HEADER97// CHECK1-LABEL: define {{[^@]+}}@_Z21teams_template_structv98// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {99// CHECK1-NEXT:  entry:100// CHECK1-NEXT:    [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4101// CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])102// CHECK1-NEXT:    ret i32 [[CALL]]103//104//105// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv106// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat {107// CHECK1-NEXT:  entry:108// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8109// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8110// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8111// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8112// CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4113// CHECK1-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4114// CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8115// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8116// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8117// CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0118// CHECK1-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0119// CHECK1-NEXT:    store ptr [[THIS1]], ptr [[TMP0]], align 8120// CHECK1-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0121// CHECK1-NEXT:    store ptr [[A]], ptr [[TMP1]], align 8122// CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0123// CHECK1-NEXT:    store ptr null, ptr [[TMP2]], align 8124// CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0125// CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0126// CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0127// CHECK1-NEXT:    store i32 3, ptr [[TMP5]], align 4128// CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1129// CHECK1-NEXT:    store i32 1, ptr [[TMP6]], align 4130// CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2131// CHECK1-NEXT:    store ptr [[TMP3]], ptr [[TMP7]], align 8132// CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3133// CHECK1-NEXT:    store ptr [[TMP4]], ptr [[TMP8]], align 8134// CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4135// CHECK1-NEXT:    store ptr @.offload_sizes, ptr [[TMP9]], align 8136// CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5137// CHECK1-NEXT:    store ptr @.offload_maptypes, ptr [[TMP10]], align 8138// CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6139// CHECK1-NEXT:    store ptr null, ptr [[TMP11]], align 8140// CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7141// CHECK1-NEXT:    store ptr null, ptr [[TMP12]], align 8142// CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8143// CHECK1-NEXT:    store i64 56088, ptr [[TMP13]], align 8144// CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9145// CHECK1-NEXT:    store i64 0, ptr [[TMP14]], align 8146// CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10147// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4148// CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11149// CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP16]], align 4150// CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12151// CHECK1-NEXT:    store i32 0, ptr [[TMP17]], align 4152// CHECK1-NEXT:    [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, ptr [[KERNEL_ARGS]])153// CHECK1-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0154// CHECK1-NEXT:    br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]155// CHECK1:       omp_offload.failed:156// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(ptr [[THIS1]]) #[[ATTR2:[0-9]+]]157// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]158// CHECK1:       omp_offload.cont:159// CHECK1-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0160// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i64 0, i64 0161// CHECK1-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 0162// CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4163// CHECK1-NEXT:    ret i32 [[TMP20]]164//165//166// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28167// CHECK1-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] {168// CHECK1-NEXT:  entry:169// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8170// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8171// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8172// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined, ptr [[TMP0]])173// CHECK1-NEXT:    ret void174//175//176// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined177// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR1]] {178// CHECK1-NEXT:  entry:179// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8180// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8181// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8182// CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4183// CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4184// CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4185// CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4186// CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4187// CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4188// CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4189// CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4190// CHECK1-NEXT:    [[J:%.*]] = alloca i32, align 4191// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8192// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8193// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8194// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8195// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4196// CHECK1-NEXT:    store i32 56087, ptr [[DOTOMP_UB]], align 4197// CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4198// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4199// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8200// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4201// CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)202// CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4203// CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087204// CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]205// CHECK1:       cond.true:206// CHECK1-NEXT:    br label [[COND_END:%.*]]207// CHECK1:       cond.false:208// CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4209// CHECK1-NEXT:    br label [[COND_END]]210// CHECK1:       cond.end:211// CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]212// CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4213// CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4214// CHECK1-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4215// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]216// CHECK1:       omp.inner.for.cond:217// CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]]218// CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP4]]219// CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]220// CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]221// CHECK1:       omp.inner.for.body:222// CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]223// CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP8]], 456224// CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1225// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]226// CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]]227// CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]228// CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]229// CHECK1-NEXT:    [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456230// CHECK1-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456231// CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]232// CHECK1-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1233// CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]234// CHECK1-NEXT:    store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP4]]235// CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0236// CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]]237// CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64238// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]]239// CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP4]]240// CHECK1-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64241// CHECK1-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]242// CHECK1-NEXT:    store i32 0, ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP4]]243// CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]244// CHECK1:       omp.body.continue:245// CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]246// CHECK1:       omp.inner.for.inc:247// CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]248// CHECK1-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1249// CHECK1-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]250// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]251// CHECK1:       omp.inner.for.end:252// CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]253// CHECK1:       omp.loop.exit:254// CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])255// CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4256// CHECK1-NEXT:    [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0257// CHECK1-NEXT:    br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]258// CHECK1:       .omp.final.then:259// CHECK1-NEXT:    store i32 123, ptr [[I]], align 4260// CHECK1-NEXT:    store i32 456, ptr [[J]], align 4261// CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]262// CHECK1:       .omp.final.done:263// CHECK1-NEXT:    ret void264//265//266// CHECK3-LABEL: define {{[^@]+}}@_Z21teams_template_structv267// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {268// CHECK3-NEXT:  entry:269// CHECK3-NEXT:    [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4270// CHECK3-NEXT:    [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])271// CHECK3-NEXT:    ret i32 [[CALL]]272//273//274// CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv275// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {276// CHECK3-NEXT:  entry:277// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4278// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4279// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4280// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4281// CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4282// CHECK3-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4283// CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8284// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4285// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4286// CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0287// CHECK3-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0288// CHECK3-NEXT:    store ptr [[THIS1]], ptr [[TMP0]], align 4289// CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0290// CHECK3-NEXT:    store ptr [[A]], ptr [[TMP1]], align 4291// CHECK3-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0292// CHECK3-NEXT:    store ptr null, ptr [[TMP2]], align 4293// CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0294// CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0295// CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0296// CHECK3-NEXT:    store i32 3, ptr [[TMP5]], align 4297// CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1298// CHECK3-NEXT:    store i32 1, ptr [[TMP6]], align 4299// CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2300// CHECK3-NEXT:    store ptr [[TMP3]], ptr [[TMP7]], align 4301// CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3302// CHECK3-NEXT:    store ptr [[TMP4]], ptr [[TMP8]], align 4303// CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4304// CHECK3-NEXT:    store ptr @.offload_sizes, ptr [[TMP9]], align 4305// CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5306// CHECK3-NEXT:    store ptr @.offload_maptypes, ptr [[TMP10]], align 4307// CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6308// CHECK3-NEXT:    store ptr null, ptr [[TMP11]], align 4309// CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7310// CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 4311// CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8312// CHECK3-NEXT:    store i64 56088, ptr [[TMP13]], align 8313// CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9314// CHECK3-NEXT:    store i64 0, ptr [[TMP14]], align 8315// CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10316// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4317// CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11318// CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP16]], align 4319// CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12320// CHECK3-NEXT:    store i32 0, ptr [[TMP17]], align 4321// CHECK3-NEXT:    [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, ptr [[KERNEL_ARGS]])322// CHECK3-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0323// CHECK3-NEXT:    br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]324// CHECK3:       omp_offload.failed:325// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(ptr [[THIS1]]) #[[ATTR2:[0-9]+]]326// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]327// CHECK3:       omp_offload.cont:328// CHECK3-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0329// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i32 0, i32 0330// CHECK3-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 0331// CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4332// CHECK3-NEXT:    ret i32 [[TMP20]]333//334//335// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28336// CHECK3-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] {337// CHECK3-NEXT:  entry:338// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4339// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4340// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4341// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined, ptr [[TMP0]])342// CHECK3-NEXT:    ret void343//344//345// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined346// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR1]] {347// CHECK3-NEXT:  entry:348// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4349// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4350// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4351// CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4352// CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4353// CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4354// CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4355// CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4356// CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4357// CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4358// CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4359// CHECK3-NEXT:    [[J:%.*]] = alloca i32, align 4360// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4361// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4362// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4363// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4364// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4365// CHECK3-NEXT:    store i32 56087, ptr [[DOTOMP_UB]], align 4366// CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4367// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4368// CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4369// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4370// CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)371// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4372// CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087373// CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]374// CHECK3:       cond.true:375// CHECK3-NEXT:    br label [[COND_END:%.*]]376// CHECK3:       cond.false:377// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4378// CHECK3-NEXT:    br label [[COND_END]]379// CHECK3:       cond.end:380// CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]381// CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4382// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4383// CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4384// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]385// CHECK3:       omp.inner.for.cond:386// CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]387// CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]]388// CHECK3-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]389// CHECK3-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]390// CHECK3:       omp.inner.for.body:391// CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]392// CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP8]], 456393// CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1394// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]395// CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]396// CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]397// CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]398// CHECK3-NEXT:    [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456399// CHECK3-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456400// CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]401// CHECK3-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1402// CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]403// CHECK3-NEXT:    store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP5]]404// CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0405// CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]406// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i32 0, i32 [[TMP11]]407// CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP5]]408// CHECK3-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP12]]409// CHECK3-NEXT:    store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP5]]410// CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]411// CHECK3:       omp.body.continue:412// CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]413// CHECK3:       omp.inner.for.inc:414// CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]415// CHECK3-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1416// CHECK3-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]417// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]418// CHECK3:       omp.inner.for.end:419// CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]420// CHECK3:       omp.loop.exit:421// CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])422// CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4423// CHECK3-NEXT:    [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0424// CHECK3-NEXT:    br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]425// CHECK3:       .omp.final.then:426// CHECK3-NEXT:    store i32 123, ptr [[I]], align 4427// CHECK3-NEXT:    store i32 456, ptr [[J]], align 4428// CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]429// CHECK3:       .omp.final.done:430// CHECK3-NEXT:    ret void431//432//433// CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv434// CHECK5-SAME: () #[[ATTR0:[0-9]+]] {435// CHECK5-NEXT:  entry:436// CHECK5-NEXT:    [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4437// CHECK5-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])438// CHECK5-NEXT:    ret i32 [[CALL]]439//440//441// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv442// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat {443// CHECK5-NEXT:  entry:444// CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8445// CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4446// CHECK5-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4447// CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4448// CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4449// CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4450// CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4451// CHECK5-NEXT:    [[J:%.*]] = alloca i32, align 4452// CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8453// CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8454// CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4455// CHECK5-NEXT:    store i32 56087, ptr [[DOTOMP_UB]], align 4456// CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4457// CHECK5-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4458// CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]459// CHECK5:       omp.inner.for.cond:460// CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]461// CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]462// CHECK5-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]463// CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]464// CHECK5:       omp.inner.for.body:465// CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]466// CHECK5-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP3]], 456467// CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1468// CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]469// CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]470// CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]471// CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]472// CHECK5-NEXT:    [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456473// CHECK5-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456474// CHECK5-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]]475// CHECK5-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1476// CHECK5-NEXT:    [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]477// CHECK5-NEXT:    store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP2]]478// CHECK5-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0479// CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]480// CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64481// CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]]482// CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP2]]483// CHECK5-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64484// CHECK5-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]485// CHECK5-NEXT:    store i32 0, ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP2]]486// CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]487// CHECK5:       omp.body.continue:488// CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]489// CHECK5:       omp.inner.for.inc:490// CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]491// CHECK5-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP8]], 1492// CHECK5-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]493// CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]494// CHECK5:       omp.inner.for.end:495// CHECK5-NEXT:    store i32 123, ptr [[I]], align 4496// CHECK5-NEXT:    store i32 456, ptr [[J]], align 4497// CHECK5-NEXT:    [[A10:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0498// CHECK5-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A10]], i64 0, i64 0499// CHECK5-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX11]], i64 0, i64 0500// CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX12]], align 4501// CHECK5-NEXT:    ret i32 [[TMP9]]502//503//504// CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv505// CHECK7-SAME: () #[[ATTR0:[0-9]+]] {506// CHECK7-NEXT:  entry:507// CHECK7-NEXT:    [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4508// CHECK7-NEXT:    [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])509// CHECK7-NEXT:    ret i32 [[CALL]]510//511//512// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv513// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {514// CHECK7-NEXT:  entry:515// CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4516// CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4517// CHECK7-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4518// CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4519// CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4520// CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4521// CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4522// CHECK7-NEXT:    [[J:%.*]] = alloca i32, align 4523// CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4524// CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4525// CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4526// CHECK7-NEXT:    store i32 56087, ptr [[DOTOMP_UB]], align 4527// CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4528// CHECK7-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4529// CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]530// CHECK7:       omp.inner.for.cond:531// CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]532// CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]]533// CHECK7-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]534// CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]535// CHECK7:       omp.inner.for.body:536// CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]537// CHECK7-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP3]], 456538// CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1539// CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]540// CHECK7-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]541// CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]542// CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]543// CHECK7-NEXT:    [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456544// CHECK7-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456545// CHECK7-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]]546// CHECK7-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1547// CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]548// CHECK7-NEXT:    store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP3]]549// CHECK7-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0550// CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]551// CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i32 0, i32 [[TMP6]]552// CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP3]]553// CHECK7-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP7]]554// CHECK7-NEXT:    store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP3]]555// CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]556// CHECK7:       omp.body.continue:557// CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]558// CHECK7:       omp.inner.for.inc:559// CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]560// CHECK7-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1561// CHECK7-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]562// CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]563// CHECK7:       omp.inner.for.end:564// CHECK7-NEXT:    store i32 123, ptr [[I]], align 4565// CHECK7-NEXT:    store i32 456, ptr [[J]], align 4566// CHECK7-NEXT:    [[A9:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0567// CHECK7-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A9]], i32 0, i32 0568// CHECK7-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX10]], i32 0, i32 0569// CHECK7-NEXT:    [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX11]], align 4570// CHECK7-NEXT:    ret i32 [[TMP9]]571//572//573// CHECK9-LABEL: define {{[^@]+}}@main574// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {575// CHECK9-NEXT:  entry:576// CHECK9-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4577// CHECK9-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 4578// CHECK9-NEXT:    [[ARGV_ADDR:%.*]] = alloca ptr, align 8579// CHECK9-NEXT:    [[N:%.*]] = alloca i32, align 4580// CHECK9-NEXT:    [[M:%.*]] = alloca i32, align 4581// CHECK9-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8582// CHECK9-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8583// CHECK9-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8584// CHECK9-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8585// CHECK9-NEXT:    [[M_CASTED:%.*]] = alloca i64, align 8586// CHECK9-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8587// CHECK9-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8588// CHECK9-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8589// CHECK9-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8590// CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4591// CHECK9-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4592// CHECK9-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4593// CHECK9-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4594// CHECK9-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8595// CHECK9-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8596// CHECK9-NEXT:    store i32 0, ptr [[RETVAL]], align 4597// CHECK9-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4598// CHECK9-NEXT:    store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8599// CHECK9-NEXT:    store i32 100, ptr [[N]], align 4600// CHECK9-NEXT:    store i32 2, ptr [[M]], align 4601// CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N]], align 4602// CHECK9-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64603// CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[M]], align 4604// CHECK9-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64605// CHECK9-NEXT:    [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()606// CHECK9-NEXT:    store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8607// CHECK9-NEXT:    [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]608// CHECK9-NEXT:    [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4609// CHECK9-NEXT:    store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8610// CHECK9-NEXT:    store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8611// CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N]], align 4612// CHECK9-NEXT:    store i32 [[TMP6]], ptr [[N_CASTED]], align 4613// CHECK9-NEXT:    [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8614// CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[M]], align 4615// CHECK9-NEXT:    store i32 [[TMP8]], ptr [[M_CASTED]], align 4616// CHECK9-NEXT:    [[TMP9:%.*]] = load i64, ptr [[M_CASTED]], align 8617// CHECK9-NEXT:    [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]618// CHECK9-NEXT:    [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4619// CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 40, i1 false)620// CHECK9-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0621// CHECK9-NEXT:    store i64 [[TMP7]], ptr [[TMP12]], align 8622// CHECK9-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0623// CHECK9-NEXT:    store i64 [[TMP7]], ptr [[TMP13]], align 8624// CHECK9-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0625// CHECK9-NEXT:    store ptr null, ptr [[TMP14]], align 8626// CHECK9-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1627// CHECK9-NEXT:    store i64 [[TMP9]], ptr [[TMP15]], align 8628// CHECK9-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1629// CHECK9-NEXT:    store i64 [[TMP9]], ptr [[TMP16]], align 8630// CHECK9-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1631// CHECK9-NEXT:    store ptr null, ptr [[TMP17]], align 8632// CHECK9-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2633// CHECK9-NEXT:    store i64 [[TMP1]], ptr [[TMP18]], align 8634// CHECK9-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2635// CHECK9-NEXT:    store i64 [[TMP1]], ptr [[TMP19]], align 8636// CHECK9-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2637// CHECK9-NEXT:    store ptr null, ptr [[TMP20]], align 8638// CHECK9-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3639// CHECK9-NEXT:    store i64 [[TMP3]], ptr [[TMP21]], align 8640// CHECK9-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3641// CHECK9-NEXT:    store i64 [[TMP3]], ptr [[TMP22]], align 8642// CHECK9-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3643// CHECK9-NEXT:    store ptr null, ptr [[TMP23]], align 8644// CHECK9-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4645// CHECK9-NEXT:    store ptr [[VLA]], ptr [[TMP24]], align 8646// CHECK9-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4647// CHECK9-NEXT:    store ptr [[VLA]], ptr [[TMP25]], align 8648// CHECK9-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4649// CHECK9-NEXT:    store i64 [[TMP11]], ptr [[TMP26]], align 8650// CHECK9-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4651// CHECK9-NEXT:    store ptr null, ptr [[TMP27]], align 8652// CHECK9-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0653// CHECK9-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0654// CHECK9-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0655// CHECK9-NEXT:    [[TMP31:%.*]] = load i32, ptr [[N]], align 4656// CHECK9-NEXT:    store i32 [[TMP31]], ptr [[DOTCAPTURE_EXPR_]], align 4657// CHECK9-NEXT:    [[TMP32:%.*]] = load i32, ptr [[M]], align 4658// CHECK9-NEXT:    store i32 [[TMP32]], ptr [[DOTCAPTURE_EXPR_2]], align 4659// CHECK9-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4660// CHECK9-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP33]], 0661// CHECK9-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1662// CHECK9-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i64663// CHECK9-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4664// CHECK9-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP34]], 0665// CHECK9-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1666// CHECK9-NEXT:    [[CONV6:%.*]] = sext i32 [[DIV5]] to i64667// CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]668// CHECK9-NEXT:    [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1669// CHECK9-NEXT:    store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 8670// CHECK9-NEXT:    [[TMP35:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8671// CHECK9-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP35]], 1672// CHECK9-NEXT:    [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0673// CHECK9-NEXT:    store i32 3, ptr [[TMP36]], align 4674// CHECK9-NEXT:    [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1675// CHECK9-NEXT:    store i32 5, ptr [[TMP37]], align 4676// CHECK9-NEXT:    [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2677// CHECK9-NEXT:    store ptr [[TMP28]], ptr [[TMP38]], align 8678// CHECK9-NEXT:    [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3679// CHECK9-NEXT:    store ptr [[TMP29]], ptr [[TMP39]], align 8680// CHECK9-NEXT:    [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4681// CHECK9-NEXT:    store ptr [[TMP30]], ptr [[TMP40]], align 8682// CHECK9-NEXT:    [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5683// CHECK9-NEXT:    store ptr @.offload_maptypes, ptr [[TMP41]], align 8684// CHECK9-NEXT:    [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6685// CHECK9-NEXT:    store ptr null, ptr [[TMP42]], align 8686// CHECK9-NEXT:    [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7687// CHECK9-NEXT:    store ptr null, ptr [[TMP43]], align 8688// CHECK9-NEXT:    [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8689// CHECK9-NEXT:    store i64 [[ADD]], ptr [[TMP44]], align 8690// CHECK9-NEXT:    [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9691// CHECK9-NEXT:    store i64 0, ptr [[TMP45]], align 8692// CHECK9-NEXT:    [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10693// CHECK9-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP46]], align 4694// CHECK9-NEXT:    [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11695// CHECK9-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP47]], align 4696// CHECK9-NEXT:    [[TMP48:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12697// CHECK9-NEXT:    store i32 0, ptr [[TMP48]], align 4698// CHECK9-NEXT:    [[TMP49:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.region_id, ptr [[KERNEL_ARGS]])699// CHECK9-NEXT:    [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0700// CHECK9-NEXT:    br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]701// CHECK9:       omp_offload.failed:702// CHECK9-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]703// CHECK9-NEXT:    br label [[OMP_OFFLOAD_CONT]]704// CHECK9:       omp_offload.cont:705// CHECK9-NEXT:    [[TMP51:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4706// CHECK9-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP51]])707// CHECK9-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 4708// CHECK9-NEXT:    [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8709// CHECK9-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP52]])710// CHECK9-NEXT:    [[TMP53:%.*]] = load i32, ptr [[RETVAL]], align 4711// CHECK9-NEXT:    ret i32 [[TMP53]]712//713//714// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80715// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {716// CHECK9-NEXT:  entry:717// CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8718// CHECK9-NEXT:    [[M_ADDR:%.*]] = alloca i64, align 8719// CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8720// CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8721// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8722// CHECK9-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8723// CHECK9-NEXT:    [[M_CASTED:%.*]] = alloca i64, align 8724// CHECK9-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8725// CHECK9-NEXT:    store i64 [[M]], ptr [[M_ADDR]], align 8726// CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8727// CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8728// CHECK9-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8729// CHECK9-NEXT:    [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8730// CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8731// CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8732// CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4733// CHECK9-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4734// CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8735// CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[M_ADDR]], align 4736// CHECK9-NEXT:    store i32 [[TMP5]], ptr [[M_CASTED]], align 4737// CHECK9-NEXT:    [[TMP6:%.*]] = load i64, ptr [[M_CASTED]], align 8738// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.omp_outlined, i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], ptr [[TMP2]])739// CHECK9-NEXT:    ret void740//741//742// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.omp_outlined743// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {744// CHECK9-NEXT:  entry:745// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8746// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8747// CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8748// CHECK9-NEXT:    [[M_ADDR:%.*]] = alloca i64, align 8749// CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8750// CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8751// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8752// CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8753// CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4754// CHECK9-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4755// CHECK9-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4756// CHECK9-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4757// CHECK9-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8758// CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4759// CHECK9-NEXT:    [[J:%.*]] = alloca i32, align 4760// CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8761// CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8762// CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8763// CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4764// CHECK9-NEXT:    [[I11:%.*]] = alloca i32, align 4765// CHECK9-NEXT:    [[J12:%.*]] = alloca i32, align 4766// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8767// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8768// CHECK9-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8769// CHECK9-NEXT:    store i64 [[M]], ptr [[M_ADDR]], align 8770// CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8771// CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8772// CHECK9-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8773// CHECK9-NEXT:    [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8774// CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8775// CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8776// CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4777// CHECK9-NEXT:    store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4778// CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[M_ADDR]], align 4779// CHECK9-NEXT:    store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_4]], align 4780// CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4781// CHECK9-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0782// CHECK9-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1783// CHECK9-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i64784// CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4785// CHECK9-NEXT:    [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 0786// CHECK9-NEXT:    [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1787// CHECK9-NEXT:    [[CONV8:%.*]] = sext i32 [[DIV7]] to i64788// CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]]789// CHECK9-NEXT:    [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1790// CHECK9-NEXT:    store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 8791// CHECK9-NEXT:    store i32 0, ptr [[I]], align 4792// CHECK9-NEXT:    store i32 0, ptr [[J]], align 4793// CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4794// CHECK9-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP7]]795// CHECK9-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]796// CHECK9:       land.lhs.true:797// CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4798// CHECK9-NEXT:    [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]]799// CHECK9-NEXT:    br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]800// CHECK9:       omp.precond.then:801// CHECK9-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8802// CHECK9-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8803// CHECK9-NEXT:    store i64 [[TMP9]], ptr [[DOTOMP_UB]], align 8804// CHECK9-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8805// CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4806// CHECK9-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8807// CHECK9-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4808// CHECK9-NEXT:    call void @__kmpc_for_static_init_8(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)809// CHECK9-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8810// CHECK9-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8811// CHECK9-NEXT:    [[CMP13:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]]812// CHECK9-NEXT:    br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]813// CHECK9:       cond.true:814// CHECK9-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8815// CHECK9-NEXT:    br label [[COND_END:%.*]]816// CHECK9:       cond.false:817// CHECK9-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8818// CHECK9-NEXT:    br label [[COND_END]]819// CHECK9:       cond.end:820// CHECK9-NEXT:    [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ]821// CHECK9-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8822// CHECK9-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8823// CHECK9-NEXT:    store i64 [[TMP16]], ptr [[DOTOMP_IV]], align 8824// CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]825// CHECK9:       omp.inner.for.cond:826// CHECK9-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5:![0-9]+]]827// CHECK9-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP5]]828// CHECK9-NEXT:    [[CMP14:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]829// CHECK9-NEXT:    br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]830// CHECK9:       omp.inner.for.body:831// CHECK9-NEXT:    [[TMP19:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]832// CHECK9-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP5]]833// CHECK9-NEXT:    [[SUB15:%.*]] = sub nsw i32 [[TMP20]], 0834// CHECK9-NEXT:    [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1835// CHECK9-NEXT:    [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]836// CHECK9-NEXT:    [[CONV18:%.*]] = sext i32 [[MUL17]] to i64837// CHECK9-NEXT:    [[DIV19:%.*]] = sdiv i64 [[TMP19]], [[CONV18]]838// CHECK9-NEXT:    [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1839// CHECK9-NEXT:    [[ADD:%.*]] = add nsw i64 0, [[MUL20]]840// CHECK9-NEXT:    [[CONV21:%.*]] = trunc i64 [[ADD]] to i32841// CHECK9-NEXT:    store i32 [[CONV21]], ptr [[I11]], align 4, !llvm.access.group [[ACC_GRP5]]842// CHECK9-NEXT:    [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]843// CHECK9-NEXT:    [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]844// CHECK9-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP5]]845// CHECK9-NEXT:    [[SUB22:%.*]] = sub nsw i32 [[TMP23]], 0846// CHECK9-NEXT:    [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1847// CHECK9-NEXT:    [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]848// CHECK9-NEXT:    [[CONV25:%.*]] = sext i32 [[MUL24]] to i64849// CHECK9-NEXT:    [[DIV26:%.*]] = sdiv i64 [[TMP22]], [[CONV25]]850// CHECK9-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP5]]851// CHECK9-NEXT:    [[SUB27:%.*]] = sub nsw i32 [[TMP24]], 0852// CHECK9-NEXT:    [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1853// CHECK9-NEXT:    [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]854// CHECK9-NEXT:    [[CONV30:%.*]] = sext i32 [[MUL29]] to i64855// CHECK9-NEXT:    [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]856// CHECK9-NEXT:    [[SUB32:%.*]] = sub nsw i64 [[TMP21]], [[MUL31]]857// CHECK9-NEXT:    [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1858// CHECK9-NEXT:    [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]859// CHECK9-NEXT:    [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32860// CHECK9-NEXT:    store i32 [[CONV35]], ptr [[J12]], align 4, !llvm.access.group [[ACC_GRP5]]861// CHECK9-NEXT:    [[TMP25:%.*]] = load i32, ptr [[I11]], align 4, !llvm.access.group [[ACC_GRP5]]862// CHECK9-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64863// CHECK9-NEXT:    [[TMP26:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP1]]864// CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 [[TMP26]]865// CHECK9-NEXT:    [[TMP27:%.*]] = load i32, ptr [[J12]], align 4, !llvm.access.group [[ACC_GRP5]]866// CHECK9-NEXT:    [[IDXPROM36:%.*]] = sext i32 [[TMP27]] to i64867// CHECK9-NEXT:    [[ARRAYIDX37:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i64 [[IDXPROM36]]868// CHECK9-NEXT:    store i32 0, ptr [[ARRAYIDX37]], align 4, !llvm.access.group [[ACC_GRP5]]869// CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]870// CHECK9:       omp.body.continue:871// CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]872// CHECK9:       omp.inner.for.inc:873// CHECK9-NEXT:    [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]874// CHECK9-NEXT:    [[ADD38:%.*]] = add nsw i64 [[TMP28]], 1875// CHECK9-NEXT:    store i64 [[ADD38]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]876// CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]877// CHECK9:       omp.inner.for.end:878// CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]879// CHECK9:       omp.loop.exit:880// CHECK9-NEXT:    [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8881// CHECK9-NEXT:    [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4882// CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP30]])883// CHECK9-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4884// CHECK9-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0885// CHECK9-NEXT:    br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]886// CHECK9:       .omp.final.then:887// CHECK9-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4888// CHECK9-NEXT:    [[SUB39:%.*]] = sub nsw i32 [[TMP33]], 0889// CHECK9-NEXT:    [[DIV40:%.*]] = sdiv i32 [[SUB39]], 1890// CHECK9-NEXT:    [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 1891// CHECK9-NEXT:    [[ADD42:%.*]] = add nsw i32 0, [[MUL41]]892// CHECK9-NEXT:    store i32 [[ADD42]], ptr [[I11]], align 4893// CHECK9-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4894// CHECK9-NEXT:    [[SUB43:%.*]] = sub nsw i32 [[TMP34]], 0895// CHECK9-NEXT:    [[DIV44:%.*]] = sdiv i32 [[SUB43]], 1896// CHECK9-NEXT:    [[MUL45:%.*]] = mul nsw i32 [[DIV44]], 1897// CHECK9-NEXT:    [[ADD46:%.*]] = add nsw i32 0, [[MUL45]]898// CHECK9-NEXT:    store i32 [[ADD46]], ptr [[J12]], align 4899// CHECK9-NEXT:    br label [[DOTOMP_FINAL_DONE]]900// CHECK9:       .omp.final.done:901// CHECK9-NEXT:    br label [[OMP_PRECOND_END]]902// CHECK9:       omp.precond.end:903// CHECK9-NEXT:    ret void904//905//906// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_907// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat {908// CHECK9-NEXT:  entry:909// CHECK9-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 4910// CHECK9-NEXT:    [[A:%.*]] = alloca [10 x [2 x i32]], align 4911// CHECK9-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8912// CHECK9-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8913// CHECK9-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8914// CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4915// CHECK9-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4916// CHECK9-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8917// CHECK9-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4918// CHECK9-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0919// CHECK9-NEXT:    store ptr [[A]], ptr [[TMP0]], align 8920// CHECK9-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0921// CHECK9-NEXT:    store ptr [[A]], ptr [[TMP1]], align 8922// CHECK9-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0923// CHECK9-NEXT:    store ptr null, ptr [[TMP2]], align 8924// CHECK9-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0925// CHECK9-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0926// CHECK9-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0927// CHECK9-NEXT:    store i32 3, ptr [[TMP5]], align 4928// CHECK9-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1929// CHECK9-NEXT:    store i32 1, ptr [[TMP6]], align 4930// CHECK9-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2931// CHECK9-NEXT:    store ptr [[TMP3]], ptr [[TMP7]], align 8932// CHECK9-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3933// CHECK9-NEXT:    store ptr [[TMP4]], ptr [[TMP8]], align 8934// CHECK9-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4935// CHECK9-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP9]], align 8936// CHECK9-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5937// CHECK9-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP10]], align 8938// CHECK9-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6939// CHECK9-NEXT:    store ptr null, ptr [[TMP11]], align 8940// CHECK9-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7941// CHECK9-NEXT:    store ptr null, ptr [[TMP12]], align 8942// CHECK9-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8943// CHECK9-NEXT:    store i64 20, ptr [[TMP13]], align 8944// CHECK9-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9945// CHECK9-NEXT:    store i64 0, ptr [[TMP14]], align 8946// CHECK9-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10947// CHECK9-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4948// CHECK9-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11949// CHECK9-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP16]], align 4950// CHECK9-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12951// CHECK9-NEXT:    store i32 0, ptr [[TMP17]], align 4952// CHECK9-NEXT:    [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.region_id, ptr [[KERNEL_ARGS]])953// CHECK9-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0954// CHECK9-NEXT:    br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]955// CHECK9:       omp_offload.failed:956// CHECK9-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67(ptr [[A]]) #[[ATTR3]]957// CHECK9-NEXT:    br label [[OMP_OFFLOAD_CONT]]958// CHECK9:       omp_offload.cont:959// CHECK9-NEXT:    ret i32 0960//961//962// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67963// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {964// CHECK9-NEXT:  entry:965// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8966// CHECK9-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8967// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8968// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.omp_outlined, ptr [[TMP0]])969// CHECK9-NEXT:    ret void970//971//972// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.omp_outlined973// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {974// CHECK9-NEXT:  entry:975// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8976// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8977// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8978// CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4979// CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4980// CHECK9-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4981// CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4982// CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4983// CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4984// CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4985// CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4986// CHECK9-NEXT:    [[J:%.*]] = alloca i32, align 4987// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8988// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8989// CHECK9-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8990// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8991// CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4992// CHECK9-NEXT:    store i32 19, ptr [[DOTOMP_UB]], align 4993// CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4994// CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4995// CHECK9-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8996// CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4997// CHECK9-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)998// CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4999// CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 191000// CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1001// CHECK9:       cond.true:1002// CHECK9-NEXT:    br label [[COND_END:%.*]]1003// CHECK9:       cond.false:1004// CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41005// CHECK9-NEXT:    br label [[COND_END]]1006// CHECK9:       cond.end:1007// CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]1008// CHECK9-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 41009// CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41010// CHECK9-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 41011// CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1012// CHECK9:       omp.inner.for.cond:1013// CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]1014// CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]]1015// CHECK9-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]1016// CHECK9-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1017// CHECK9:       omp.inner.for.body:1018// CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]1019// CHECK9-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP8]], 21020// CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 11021// CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1022// CHECK9-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]1023// CHECK9-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]1024// CHECK9-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]1025// CHECK9-NEXT:    [[DIV3:%.*]] = sdiv i32 [[TMP10]], 21026// CHECK9-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 21027// CHECK9-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]1028// CHECK9-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[SUB]], 11029// CHECK9-NEXT:    [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]1030// CHECK9-NEXT:    store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP11]]1031// CHECK9-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]1032// CHECK9-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i641033// CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]1034// CHECK9-NEXT:    [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP11]]1035// CHECK9-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i641036// CHECK9-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]1037// CHECK9-NEXT:    store i32 0, ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP11]]1038// CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1039// CHECK9:       omp.body.continue:1040// CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1041// CHECK9:       omp.inner.for.inc:1042// CHECK9-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]1043// CHECK9-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 11044// CHECK9-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]1045// CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]1046// CHECK9:       omp.inner.for.end:1047// CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]1048// CHECK9:       omp.loop.exit:1049// CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])1050// CHECK9-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41051// CHECK9-NEXT:    [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 01052// CHECK9-NEXT:    br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1053// CHECK9:       .omp.final.then:1054// CHECK9-NEXT:    store i32 10, ptr [[I]], align 41055// CHECK9-NEXT:    store i32 2, ptr [[J]], align 41056// CHECK9-NEXT:    br label [[DOTOMP_FINAL_DONE]]1057// CHECK9:       .omp.final.done:1058// CHECK9-NEXT:    ret void1059//1060//1061// CHECK11-LABEL: define {{[^@]+}}@main1062// CHECK11-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {1063// CHECK11-NEXT:  entry:1064// CHECK11-NEXT:    [[RETVAL:%.*]] = alloca i32, align 41065// CHECK11-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 41066// CHECK11-NEXT:    [[ARGV_ADDR:%.*]] = alloca ptr, align 41067// CHECK11-NEXT:    [[N:%.*]] = alloca i32, align 41068// CHECK11-NEXT:    [[M:%.*]] = alloca i32, align 41069// CHECK11-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 41070// CHECK11-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 41071// CHECK11-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 41072// CHECK11-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 41073// CHECK11-NEXT:    [[M_CASTED:%.*]] = alloca i32, align 41074// CHECK11-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 41075// CHECK11-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 41076// CHECK11-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 41077// CHECK11-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 41078// CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 41079// CHECK11-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41080// CHECK11-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 41081// CHECK11-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 41082// CHECK11-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 81083// CHECK11-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81084// CHECK11-NEXT:    store i32 0, ptr [[RETVAL]], align 41085// CHECK11-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 41086// CHECK11-NEXT:    store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 41087// CHECK11-NEXT:    store i32 100, ptr [[N]], align 41088// CHECK11-NEXT:    store i32 2, ptr [[M]], align 41089// CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N]], align 41090// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[M]], align 41091// CHECK11-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()1092// CHECK11-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 41093// CHECK11-NEXT:    [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]1094// CHECK11-NEXT:    [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 41095// CHECK11-NEXT:    store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 41096// CHECK11-NEXT:    store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 41097// CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N]], align 41098// CHECK11-NEXT:    store i32 [[TMP4]], ptr [[N_CASTED]], align 41099// CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 41100// CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[M]], align 41101// CHECK11-NEXT:    store i32 [[TMP6]], ptr [[M_CASTED]], align 41102// CHECK11-NEXT:    [[TMP7:%.*]] = load i32, ptr [[M_CASTED]], align 41103// CHECK11-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]1104// CHECK11-NEXT:    [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 41105// CHECK11-NEXT:    [[TMP10:%.*]] = sext i32 [[TMP9]] to i641106// CHECK11-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes, i32 40, i1 false)1107// CHECK11-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01108// CHECK11-NEXT:    store i32 [[TMP5]], ptr [[TMP11]], align 41109// CHECK11-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01110// CHECK11-NEXT:    store i32 [[TMP5]], ptr [[TMP12]], align 41111// CHECK11-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 01112// CHECK11-NEXT:    store ptr null, ptr [[TMP13]], align 41113// CHECK11-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11114// CHECK11-NEXT:    store i32 [[TMP7]], ptr [[TMP14]], align 41115// CHECK11-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11116// CHECK11-NEXT:    store i32 [[TMP7]], ptr [[TMP15]], align 41117// CHECK11-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 11118// CHECK11-NEXT:    store ptr null, ptr [[TMP16]], align 41119// CHECK11-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21120// CHECK11-NEXT:    store i32 [[TMP0]], ptr [[TMP17]], align 41121// CHECK11-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21122// CHECK11-NEXT:    store i32 [[TMP0]], ptr [[TMP18]], align 41123// CHECK11-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 21124// CHECK11-NEXT:    store ptr null, ptr [[TMP19]], align 41125// CHECK11-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31126// CHECK11-NEXT:    store i32 [[TMP1]], ptr [[TMP20]], align 41127// CHECK11-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31128// CHECK11-NEXT:    store i32 [[TMP1]], ptr [[TMP21]], align 41129// CHECK11-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 31130// CHECK11-NEXT:    store ptr null, ptr [[TMP22]], align 41131// CHECK11-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 41132// CHECK11-NEXT:    store ptr [[VLA]], ptr [[TMP23]], align 41133// CHECK11-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 41134// CHECK11-NEXT:    store ptr [[VLA]], ptr [[TMP24]], align 41135// CHECK11-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 41136// CHECK11-NEXT:    store i64 [[TMP10]], ptr [[TMP25]], align 41137// CHECK11-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 41138// CHECK11-NEXT:    store ptr null, ptr [[TMP26]], align 41139// CHECK11-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01140// CHECK11-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01141// CHECK11-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 01142// CHECK11-NEXT:    [[TMP30:%.*]] = load i32, ptr [[N]], align 41143// CHECK11-NEXT:    store i32 [[TMP30]], ptr [[DOTCAPTURE_EXPR_]], align 41144// CHECK11-NEXT:    [[TMP31:%.*]] = load i32, ptr [[M]], align 41145// CHECK11-NEXT:    store i32 [[TMP31]], ptr [[DOTCAPTURE_EXPR_2]], align 41146// CHECK11-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41147// CHECK11-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP32]], 01148// CHECK11-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 11149// CHECK11-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i641150// CHECK11-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41151// CHECK11-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP33]], 01152// CHECK11-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 11153// CHECK11-NEXT:    [[CONV6:%.*]] = sext i32 [[DIV5]] to i641154// CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]1155// CHECK11-NEXT:    [[SUB7:%.*]] = sub nsw i64 [[MUL]], 11156// CHECK11-NEXT:    store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 81157// CHECK11-NEXT:    [[TMP34:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 81158// CHECK11-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP34]], 11159// CHECK11-NEXT:    [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01160// CHECK11-NEXT:    store i32 3, ptr [[TMP35]], align 41161// CHECK11-NEXT:    [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11162// CHECK11-NEXT:    store i32 5, ptr [[TMP36]], align 41163// CHECK11-NEXT:    [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21164// CHECK11-NEXT:    store ptr [[TMP27]], ptr [[TMP37]], align 41165// CHECK11-NEXT:    [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31166// CHECK11-NEXT:    store ptr [[TMP28]], ptr [[TMP38]], align 41167// CHECK11-NEXT:    [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41168// CHECK11-NEXT:    store ptr [[TMP29]], ptr [[TMP39]], align 41169// CHECK11-NEXT:    [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51170// CHECK11-NEXT:    store ptr @.offload_maptypes, ptr [[TMP40]], align 41171// CHECK11-NEXT:    [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61172// CHECK11-NEXT:    store ptr null, ptr [[TMP41]], align 41173// CHECK11-NEXT:    [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71174// CHECK11-NEXT:    store ptr null, ptr [[TMP42]], align 41175// CHECK11-NEXT:    [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81176// CHECK11-NEXT:    store i64 [[ADD]], ptr [[TMP43]], align 81177// CHECK11-NEXT:    [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91178// CHECK11-NEXT:    store i64 0, ptr [[TMP44]], align 81179// CHECK11-NEXT:    [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101180// CHECK11-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP45]], align 41181// CHECK11-NEXT:    [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111182// CHECK11-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP46]], align 41183// CHECK11-NEXT:    [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121184// CHECK11-NEXT:    store i32 0, ptr [[TMP47]], align 41185// CHECK11-NEXT:    [[TMP48:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.region_id, ptr [[KERNEL_ARGS]])1186// CHECK11-NEXT:    [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 01187// CHECK11-NEXT:    br i1 [[TMP49]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1188// CHECK11:       omp_offload.failed:1189// CHECK11-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]1190// CHECK11-NEXT:    br label [[OMP_OFFLOAD_CONT]]1191// CHECK11:       omp_offload.cont:1192// CHECK11-NEXT:    [[TMP50:%.*]] = load i32, ptr [[ARGC_ADDR]], align 41193// CHECK11-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP50]])1194// CHECK11-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 41195// CHECK11-NEXT:    [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 41196// CHECK11-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP51]])1197// CHECK11-NEXT:    [[TMP52:%.*]] = load i32, ptr [[RETVAL]], align 41198// CHECK11-NEXT:    ret i32 [[TMP52]]1199//1200//1201// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l801202// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {1203// CHECK11-NEXT:  entry:1204// CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 41205// CHECK11-NEXT:    [[M_ADDR:%.*]] = alloca i32, align 41206// CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 41207// CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 41208// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 41209// CHECK11-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 41210// CHECK11-NEXT:    [[M_CASTED:%.*]] = alloca i32, align 41211// CHECK11-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 41212// CHECK11-NEXT:    store i32 [[M]], ptr [[M_ADDR]], align 41213// CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 41214// CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 41215// CHECK11-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 41216// CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 41217// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR2]], align 41218// CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 41219// CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 41220// CHECK11-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 41221// CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 41222// CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[M_ADDR]], align 41223// CHECK11-NEXT:    store i32 [[TMP5]], ptr [[M_CASTED]], align 41224// CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[M_CASTED]], align 41225// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.omp_outlined, i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP0]], i32 [[TMP1]], ptr [[TMP2]])1226// CHECK11-NEXT:    ret void1227//1228//1229// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.omp_outlined1230// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {1231// CHECK11-NEXT:  entry:1232// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41233// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41234// CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 41235// CHECK11-NEXT:    [[M_ADDR:%.*]] = alloca i32, align 41236// CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 41237// CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 41238// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 41239// CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 81240// CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 41241// CHECK11-NEXT:    [[_TMP3:%.*]] = alloca i32, align 41242// CHECK11-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 41243// CHECK11-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 41244// CHECK11-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 81245// CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 41246// CHECK11-NEXT:    [[J:%.*]] = alloca i32, align 41247// CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 81248// CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 81249// CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 81250// CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41251// CHECK11-NEXT:    [[I11:%.*]] = alloca i32, align 41252// CHECK11-NEXT:    [[J12:%.*]] = alloca i32, align 41253// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41254// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41255// CHECK11-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 41256// CHECK11-NEXT:    store i32 [[M]], ptr [[M_ADDR]], align 41257// CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 41258// CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 41259// CHECK11-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 41260// CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 41261// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR2]], align 41262// CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 41263// CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 41264// CHECK11-NEXT:    store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 41265// CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[M_ADDR]], align 41266// CHECK11-NEXT:    store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_4]], align 41267// CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41268// CHECK11-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP5]], 01269// CHECK11-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 11270// CHECK11-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i641271// CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 41272// CHECK11-NEXT:    [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 01273// CHECK11-NEXT:    [[DIV7:%.*]] = sdiv i32 [[SUB6]], 11274// CHECK11-NEXT:    [[CONV8:%.*]] = sext i32 [[DIV7]] to i641275// CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]]1276// CHECK11-NEXT:    [[SUB9:%.*]] = sub nsw i64 [[MUL]], 11277// CHECK11-NEXT:    store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 81278// CHECK11-NEXT:    store i32 0, ptr [[I]], align 41279// CHECK11-NEXT:    store i32 0, ptr [[J]], align 41280// CHECK11-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41281// CHECK11-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP7]]1282// CHECK11-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]1283// CHECK11:       land.lhs.true:1284// CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 41285// CHECK11-NEXT:    [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]]1286// CHECK11-NEXT:    br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]1287// CHECK11:       omp.precond.then:1288// CHECK11-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 81289// CHECK11-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 81290// CHECK11-NEXT:    store i64 [[TMP9]], ptr [[DOTOMP_UB]], align 81291// CHECK11-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 81292// CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41293// CHECK11-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41294// CHECK11-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 41295// CHECK11-NEXT:    call void @__kmpc_for_static_init_8(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)1296// CHECK11-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_UB]], align 81297// CHECK11-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 81298// CHECK11-NEXT:    [[CMP13:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]]1299// CHECK11-NEXT:    br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1300// CHECK11:       cond.true:1301// CHECK11-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 81302// CHECK11-NEXT:    br label [[COND_END:%.*]]1303// CHECK11:       cond.false:1304// CHECK11-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 81305// CHECK11-NEXT:    br label [[COND_END]]1306// CHECK11:       cond.end:1307// CHECK11-NEXT:    [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ]1308// CHECK11-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 81309// CHECK11-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTOMP_LB]], align 81310// CHECK11-NEXT:    store i64 [[TMP16]], ptr [[DOTOMP_IV]], align 81311// CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1312// CHECK11:       omp.inner.for.cond:1313// CHECK11-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6:![0-9]+]]1314// CHECK11-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP6]]1315// CHECK11-NEXT:    [[CMP14:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]1316// CHECK11-NEXT:    br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1317// CHECK11:       omp.inner.for.body:1318// CHECK11-NEXT:    [[TMP19:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6]]1319// CHECK11-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP6]]1320// CHECK11-NEXT:    [[SUB15:%.*]] = sub nsw i32 [[TMP20]], 01321// CHECK11-NEXT:    [[DIV16:%.*]] = sdiv i32 [[SUB15]], 11322// CHECK11-NEXT:    [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]1323// CHECK11-NEXT:    [[CONV18:%.*]] = sext i32 [[MUL17]] to i641324// CHECK11-NEXT:    [[DIV19:%.*]] = sdiv i64 [[TMP19]], [[CONV18]]1325// CHECK11-NEXT:    [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 11326// CHECK11-NEXT:    [[ADD:%.*]] = add nsw i64 0, [[MUL20]]1327// CHECK11-NEXT:    [[CONV21:%.*]] = trunc i64 [[ADD]] to i321328// CHECK11-NEXT:    store i32 [[CONV21]], ptr [[I11]], align 4, !llvm.access.group [[ACC_GRP6]]1329// CHECK11-NEXT:    [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6]]1330// CHECK11-NEXT:    [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6]]1331// CHECK11-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP6]]1332// CHECK11-NEXT:    [[SUB22:%.*]] = sub nsw i32 [[TMP23]], 01333// CHECK11-NEXT:    [[DIV23:%.*]] = sdiv i32 [[SUB22]], 11334// CHECK11-NEXT:    [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]1335// CHECK11-NEXT:    [[CONV25:%.*]] = sext i32 [[MUL24]] to i641336// CHECK11-NEXT:    [[DIV26:%.*]] = sdiv i64 [[TMP22]], [[CONV25]]1337// CHECK11-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP6]]1338// CHECK11-NEXT:    [[SUB27:%.*]] = sub nsw i32 [[TMP24]], 01339// CHECK11-NEXT:    [[DIV28:%.*]] = sdiv i32 [[SUB27]], 11340// CHECK11-NEXT:    [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]1341// CHECK11-NEXT:    [[CONV30:%.*]] = sext i32 [[MUL29]] to i641342// CHECK11-NEXT:    [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]1343// CHECK11-NEXT:    [[SUB32:%.*]] = sub nsw i64 [[TMP21]], [[MUL31]]1344// CHECK11-NEXT:    [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 11345// CHECK11-NEXT:    [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]1346// CHECK11-NEXT:    [[CONV35:%.*]] = trunc i64 [[ADD34]] to i321347// CHECK11-NEXT:    store i32 [[CONV35]], ptr [[J12]], align 4, !llvm.access.group [[ACC_GRP6]]1348// CHECK11-NEXT:    [[TMP25:%.*]] = load i32, ptr [[I11]], align 4, !llvm.access.group [[ACC_GRP6]]1349// CHECK11-NEXT:    [[TMP26:%.*]] = mul nsw i32 [[TMP25]], [[TMP1]]1350// CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i32 [[TMP26]]1351// CHECK11-NEXT:    [[TMP27:%.*]] = load i32, ptr [[J12]], align 4, !llvm.access.group [[ACC_GRP6]]1352// CHECK11-NEXT:    [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i32 [[TMP27]]1353// CHECK11-NEXT:    store i32 0, ptr [[ARRAYIDX36]], align 4, !llvm.access.group [[ACC_GRP6]]1354// CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1355// CHECK11:       omp.body.continue:1356// CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1357// CHECK11:       omp.inner.for.inc:1358// CHECK11-NEXT:    [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6]]1359// CHECK11-NEXT:    [[ADD37:%.*]] = add nsw i64 [[TMP28]], 11360// CHECK11-NEXT:    store i64 [[ADD37]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6]]1361// CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]1362// CHECK11:       omp.inner.for.end:1363// CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]1364// CHECK11:       omp.loop.exit:1365// CHECK11-NEXT:    [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41366// CHECK11-NEXT:    [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 41367// CHECK11-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP30]])1368// CHECK11-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41369// CHECK11-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 01370// CHECK11-NEXT:    br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1371// CHECK11:       .omp.final.then:1372// CHECK11-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41373// CHECK11-NEXT:    [[SUB38:%.*]] = sub nsw i32 [[TMP33]], 01374// CHECK11-NEXT:    [[DIV39:%.*]] = sdiv i32 [[SUB38]], 11375// CHECK11-NEXT:    [[MUL40:%.*]] = mul nsw i32 [[DIV39]], 11376// CHECK11-NEXT:    [[ADD41:%.*]] = add nsw i32 0, [[MUL40]]1377// CHECK11-NEXT:    store i32 [[ADD41]], ptr [[I11]], align 41378// CHECK11-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 41379// CHECK11-NEXT:    [[SUB42:%.*]] = sub nsw i32 [[TMP34]], 01380// CHECK11-NEXT:    [[DIV43:%.*]] = sdiv i32 [[SUB42]], 11381// CHECK11-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[DIV43]], 11382// CHECK11-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]1383// CHECK11-NEXT:    store i32 [[ADD45]], ptr [[J12]], align 41384// CHECK11-NEXT:    br label [[DOTOMP_FINAL_DONE]]1385// CHECK11:       .omp.final.done:1386// CHECK11-NEXT:    br label [[OMP_PRECOND_END]]1387// CHECK11:       omp.precond.end:1388// CHECK11-NEXT:    ret void1389//1390//1391// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_1392// CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat {1393// CHECK11-NEXT:  entry:1394// CHECK11-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 41395// CHECK11-NEXT:    [[A:%.*]] = alloca [10 x [2 x i32]], align 41396// CHECK11-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 41397// CHECK11-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 41398// CHECK11-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 41399// CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 41400// CHECK11-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41401// CHECK11-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81402// CHECK11-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 41403// CHECK11-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01404// CHECK11-NEXT:    store ptr [[A]], ptr [[TMP0]], align 41405// CHECK11-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01406// CHECK11-NEXT:    store ptr [[A]], ptr [[TMP1]], align 41407// CHECK11-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 01408// CHECK11-NEXT:    store ptr null, ptr [[TMP2]], align 41409// CHECK11-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01410// CHECK11-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01411// CHECK11-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01412// CHECK11-NEXT:    store i32 3, ptr [[TMP5]], align 41413// CHECK11-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11414// CHECK11-NEXT:    store i32 1, ptr [[TMP6]], align 41415// CHECK11-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21416// CHECK11-NEXT:    store ptr [[TMP3]], ptr [[TMP7]], align 41417// CHECK11-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31418// CHECK11-NEXT:    store ptr [[TMP4]], ptr [[TMP8]], align 41419// CHECK11-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41420// CHECK11-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP9]], align 41421// CHECK11-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51422// CHECK11-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP10]], align 41423// CHECK11-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61424// CHECK11-NEXT:    store ptr null, ptr [[TMP11]], align 41425// CHECK11-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71426// CHECK11-NEXT:    store ptr null, ptr [[TMP12]], align 41427// CHECK11-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81428// CHECK11-NEXT:    store i64 20, ptr [[TMP13]], align 81429// CHECK11-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91430// CHECK11-NEXT:    store i64 0, ptr [[TMP14]], align 81431// CHECK11-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101432// CHECK11-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP15]], align 41433// CHECK11-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111434// CHECK11-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP16]], align 41435// CHECK11-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121436// CHECK11-NEXT:    store i32 0, ptr [[TMP17]], align 41437// CHECK11-NEXT:    [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.region_id, ptr [[KERNEL_ARGS]])1438// CHECK11-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 01439// CHECK11-NEXT:    br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1440// CHECK11:       omp_offload.failed:1441// CHECK11-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67(ptr [[A]]) #[[ATTR3]]1442// CHECK11-NEXT:    br label [[OMP_OFFLOAD_CONT]]1443// CHECK11:       omp_offload.cont:1444// CHECK11-NEXT:    ret i32 01445//1446//1447// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l671448// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {1449// CHECK11-NEXT:  entry:1450// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 41451// CHECK11-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 41452// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 41453// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.omp_outlined, ptr [[TMP0]])1454// CHECK11-NEXT:    ret void1455//1456//1457// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.omp_outlined1458// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {1459// CHECK11-NEXT:  entry:1460// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41461// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41462// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 41463// CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41464// CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 41465// CHECK11-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41466// CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41467// CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41468// CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41469// CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41470// CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 41471// CHECK11-NEXT:    [[J:%.*]] = alloca i32, align 41472// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41473// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41474// CHECK11-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 41475// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 41476// CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41477// CHECK11-NEXT:    store i32 19, ptr [[DOTOMP_UB]], align 41478// CHECK11-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41479// CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41480// CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41481// CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 41482// CHECK11-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1483// CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41484// CHECK11-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 191485// CHECK11-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1486// CHECK11:       cond.true:1487// CHECK11-NEXT:    br label [[COND_END:%.*]]1488// CHECK11:       cond.false:1489// CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41490// CHECK11-NEXT:    br label [[COND_END]]1491// CHECK11:       cond.end:1492// CHECK11-NEXT:    [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]1493// CHECK11-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 41494// CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41495// CHECK11-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 41496// CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1497// CHECK11:       omp.inner.for.cond:1498// CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]1499// CHECK11-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]1500// CHECK11-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]1501// CHECK11-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1502// CHECK11:       omp.inner.for.body:1503// CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]1504// CHECK11-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP8]], 21505// CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 11506// CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1507// CHECK11-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]1508// CHECK11-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]1509// CHECK11-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]1510// CHECK11-NEXT:    [[DIV3:%.*]] = sdiv i32 [[TMP10]], 21511// CHECK11-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 21512// CHECK11-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]1513// CHECK11-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[SUB]], 11514// CHECK11-NEXT:    [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]1515// CHECK11-NEXT:    store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP12]]1516// CHECK11-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]1517// CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP11]]1518// CHECK11-NEXT:    [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP12]]1519// CHECK11-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP12]]1520// CHECK11-NEXT:    store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP12]]1521// CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1522// CHECK11:       omp.body.continue:1523// CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1524// CHECK11:       omp.inner.for.inc:1525// CHECK11-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]1526// CHECK11-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP13]], 11527// CHECK11-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]1528// CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]1529// CHECK11:       omp.inner.for.end:1530// CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]1531// CHECK11:       omp.loop.exit:1532// CHECK11-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])1533// CHECK11-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41534// CHECK11-NEXT:    [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 01535// CHECK11-NEXT:    br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1536// CHECK11:       .omp.final.then:1537// CHECK11-NEXT:    store i32 10, ptr [[I]], align 41538// CHECK11-NEXT:    store i32 2, ptr [[J]], align 41539// CHECK11-NEXT:    br label [[DOTOMP_FINAL_DONE]]1540// CHECK11:       .omp.final.done:1541// CHECK11-NEXT:    ret void1542//1543//1544// CHECK13-LABEL: define {{[^@]+}}@main1545// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {1546// CHECK13-NEXT:  entry:1547// CHECK13-NEXT:    [[RETVAL:%.*]] = alloca i32, align 41548// CHECK13-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 41549// CHECK13-NEXT:    [[ARGV_ADDR:%.*]] = alloca ptr, align 81550// CHECK13-NEXT:    [[N:%.*]] = alloca i32, align 41551// CHECK13-NEXT:    [[M:%.*]] = alloca i32, align 41552// CHECK13-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 81553// CHECK13-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 81554// CHECK13-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 81555// CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 41556// CHECK13-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41557// CHECK13-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 41558// CHECK13-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 41559// CHECK13-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 81560// CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 81561// CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 81562// CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 41563// CHECK13-NEXT:    [[J:%.*]] = alloca i32, align 41564// CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 81565// CHECK13-NEXT:    [[I9:%.*]] = alloca i32, align 41566// CHECK13-NEXT:    [[J10:%.*]] = alloca i32, align 41567// CHECK13-NEXT:    store i32 0, ptr [[RETVAL]], align 41568// CHECK13-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 41569// CHECK13-NEXT:    store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 81570// CHECK13-NEXT:    store i32 100, ptr [[N]], align 41571// CHECK13-NEXT:    store i32 2, ptr [[M]], align 41572// CHECK13-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N]], align 41573// CHECK13-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i641574// CHECK13-NEXT:    [[TMP2:%.*]] = load i32, ptr [[M]], align 41575// CHECK13-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i641576// CHECK13-NEXT:    [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()1577// CHECK13-NEXT:    store ptr [[TMP4]], ptr [[SAVED_STACK]], align 81578// CHECK13-NEXT:    [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]1579// CHECK13-NEXT:    [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 41580// CHECK13-NEXT:    store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 81581// CHECK13-NEXT:    store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 81582// CHECK13-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N]], align 41583// CHECK13-NEXT:    store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 41584// CHECK13-NEXT:    [[TMP7:%.*]] = load i32, ptr [[M]], align 41585// CHECK13-NEXT:    store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_2]], align 41586// CHECK13-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41587// CHECK13-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP8]], 01588// CHECK13-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 11589// CHECK13-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i641590// CHECK13-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41591// CHECK13-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP9]], 01592// CHECK13-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 11593// CHECK13-NEXT:    [[CONV6:%.*]] = sext i32 [[DIV5]] to i641594// CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]1595// CHECK13-NEXT:    [[SUB7:%.*]] = sub nsw i64 [[MUL]], 11596// CHECK13-NEXT:    store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 81597// CHECK13-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 81598// CHECK13-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 81599// CHECK13-NEXT:    store i64 [[TMP10]], ptr [[DOTOMP_UB]], align 81600// CHECK13-NEXT:    store i32 0, ptr [[I]], align 41601// CHECK13-NEXT:    store i32 0, ptr [[J]], align 41602// CHECK13-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41603// CHECK13-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP11]]1604// CHECK13-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]]1605// CHECK13:       land.lhs.true:1606// CHECK13-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41607// CHECK13-NEXT:    [[CMP8:%.*]] = icmp slt i32 0, [[TMP12]]1608// CHECK13-NEXT:    br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]]1609// CHECK13:       simd.if.then:1610// CHECK13-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_LB]], align 81611// CHECK13-NEXT:    store i64 [[TMP13]], ptr [[DOTOMP_IV]], align 81612// CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1613// CHECK13:       omp.inner.for.cond:1614// CHECK13-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2:![0-9]+]]1615// CHECK13-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]]1616// CHECK13-NEXT:    [[CMP11:%.*]] = icmp sle i64 [[TMP14]], [[TMP15]]1617// CHECK13-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1618// CHECK13:       omp.inner.for.body:1619// CHECK13-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2]]1620// CHECK13-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP2]]1621// CHECK13-NEXT:    [[SUB12:%.*]] = sub nsw i32 [[TMP17]], 01622// CHECK13-NEXT:    [[DIV13:%.*]] = sdiv i32 [[SUB12]], 11623// CHECK13-NEXT:    [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]]1624// CHECK13-NEXT:    [[CONV15:%.*]] = sext i32 [[MUL14]] to i641625// CHECK13-NEXT:    [[DIV16:%.*]] = sdiv i64 [[TMP16]], [[CONV15]]1626// CHECK13-NEXT:    [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 11627// CHECK13-NEXT:    [[ADD:%.*]] = add nsw i64 0, [[MUL17]]1628// CHECK13-NEXT:    [[CONV18:%.*]] = trunc i64 [[ADD]] to i321629// CHECK13-NEXT:    store i32 [[CONV18]], ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP2]]1630// CHECK13-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2]]1631// CHECK13-NEXT:    [[TMP19:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2]]1632// CHECK13-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP2]]1633// CHECK13-NEXT:    [[SUB19:%.*]] = sub nsw i32 [[TMP20]], 01634// CHECK13-NEXT:    [[DIV20:%.*]] = sdiv i32 [[SUB19]], 11635// CHECK13-NEXT:    [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]]1636// CHECK13-NEXT:    [[CONV22:%.*]] = sext i32 [[MUL21]] to i641637// CHECK13-NEXT:    [[DIV23:%.*]] = sdiv i64 [[TMP19]], [[CONV22]]1638// CHECK13-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP2]]1639// CHECK13-NEXT:    [[SUB24:%.*]] = sub nsw i32 [[TMP21]], 01640// CHECK13-NEXT:    [[DIV25:%.*]] = sdiv i32 [[SUB24]], 11641// CHECK13-NEXT:    [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]]1642// CHECK13-NEXT:    [[CONV27:%.*]] = sext i32 [[MUL26]] to i641643// CHECK13-NEXT:    [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]]1644// CHECK13-NEXT:    [[SUB29:%.*]] = sub nsw i64 [[TMP18]], [[MUL28]]1645// CHECK13-NEXT:    [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 11646// CHECK13-NEXT:    [[ADD31:%.*]] = add nsw i64 0, [[MUL30]]1647// CHECK13-NEXT:    [[CONV32:%.*]] = trunc i64 [[ADD31]] to i321648// CHECK13-NEXT:    store i32 [[CONV32]], ptr [[J10]], align 4, !llvm.access.group [[ACC_GRP2]]1649// CHECK13-NEXT:    [[TMP22:%.*]] = load i32, ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP2]]1650// CHECK13-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i641651// CHECK13-NEXT:    [[TMP23:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]]1652// CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i64 [[TMP23]]1653// CHECK13-NEXT:    [[TMP24:%.*]] = load i32, ptr [[J10]], align 4, !llvm.access.group [[ACC_GRP2]]1654// CHECK13-NEXT:    [[IDXPROM33:%.*]] = sext i32 [[TMP24]] to i641655// CHECK13-NEXT:    [[ARRAYIDX34:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i64 [[IDXPROM33]]1656// CHECK13-NEXT:    store i32 0, ptr [[ARRAYIDX34]], align 4, !llvm.access.group [[ACC_GRP2]]1657// CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1658// CHECK13:       omp.body.continue:1659// CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1660// CHECK13:       omp.inner.for.inc:1661// CHECK13-NEXT:    [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2]]1662// CHECK13-NEXT:    [[ADD35:%.*]] = add nsw i64 [[TMP25]], 11663// CHECK13-NEXT:    store i64 [[ADD35]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2]]1664// CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]1665// CHECK13:       omp.inner.for.end:1666// CHECK13-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41667// CHECK13-NEXT:    [[SUB36:%.*]] = sub nsw i32 [[TMP26]], 01668// CHECK13-NEXT:    [[DIV37:%.*]] = sdiv i32 [[SUB36]], 11669// CHECK13-NEXT:    [[MUL38:%.*]] = mul nsw i32 [[DIV37]], 11670// CHECK13-NEXT:    [[ADD39:%.*]] = add nsw i32 0, [[MUL38]]1671// CHECK13-NEXT:    store i32 [[ADD39]], ptr [[I9]], align 41672// CHECK13-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41673// CHECK13-NEXT:    [[SUB40:%.*]] = sub nsw i32 [[TMP27]], 01674// CHECK13-NEXT:    [[DIV41:%.*]] = sdiv i32 [[SUB40]], 11675// CHECK13-NEXT:    [[MUL42:%.*]] = mul nsw i32 [[DIV41]], 11676// CHECK13-NEXT:    [[ADD43:%.*]] = add nsw i32 0, [[MUL42]]1677// CHECK13-NEXT:    store i32 [[ADD43]], ptr [[J10]], align 41678// CHECK13-NEXT:    br label [[SIMD_IF_END]]1679// CHECK13:       simd.if.end:1680// CHECK13-NEXT:    [[TMP28:%.*]] = load i32, ptr [[ARGC_ADDR]], align 41681// CHECK13-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]])1682// CHECK13-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 41683// CHECK13-NEXT:    [[TMP29:%.*]] = load ptr, ptr [[SAVED_STACK]], align 81684// CHECK13-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP29]])1685// CHECK13-NEXT:    [[TMP30:%.*]] = load i32, ptr [[RETVAL]], align 41686// CHECK13-NEXT:    ret i32 [[TMP30]]1687//1688//1689// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_1690// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {1691// CHECK13-NEXT:  entry:1692// CHECK13-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 41693// CHECK13-NEXT:    [[A:%.*]] = alloca [10 x [2 x i32]], align 41694// CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 41695// CHECK13-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41696// CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41697// CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41698// CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41699// CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 41700// CHECK13-NEXT:    [[J:%.*]] = alloca i32, align 41701// CHECK13-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 41702// CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41703// CHECK13-NEXT:    store i32 19, ptr [[DOTOMP_UB]], align 41704// CHECK13-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41705// CHECK13-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 41706// CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1707// CHECK13:       omp.inner.for.cond:1708// CHECK13-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]1709// CHECK13-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]]1710// CHECK13-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]1711// CHECK13-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1712// CHECK13:       omp.inner.for.body:1713// CHECK13-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]1714// CHECK13-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP3]], 21715// CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 11716// CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1717// CHECK13-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]1718// CHECK13-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]1719// CHECK13-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]1720// CHECK13-NEXT:    [[DIV2:%.*]] = sdiv i32 [[TMP5]], 21721// CHECK13-NEXT:    [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 21722// CHECK13-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]]1723// CHECK13-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[SUB]], 11724// CHECK13-NEXT:    [[ADD5:%.*]] = add nsw i32 0, [[MUL4]]1725// CHECK13-NEXT:    store i32 [[ADD5]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP6]]1726// CHECK13-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]1727// CHECK13-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i641728// CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]]1729// CHECK13-NEXT:    [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP6]]1730// CHECK13-NEXT:    [[IDXPROM6:%.*]] = sext i32 [[TMP7]] to i641731// CHECK13-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM6]]1732// CHECK13-NEXT:    store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP6]]1733// CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1734// CHECK13:       omp.body.continue:1735// CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1736// CHECK13:       omp.inner.for.inc:1737// CHECK13-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]1738// CHECK13-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP8]], 11739// CHECK13-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]1740// CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]1741// CHECK13:       omp.inner.for.end:1742// CHECK13-NEXT:    store i32 10, ptr [[I]], align 41743// CHECK13-NEXT:    store i32 2, ptr [[J]], align 41744// CHECK13-NEXT:    ret i32 01745//1746//1747// CHECK15-LABEL: define {{[^@]+}}@main1748// CHECK15-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {1749// CHECK15-NEXT:  entry:1750// CHECK15-NEXT:    [[RETVAL:%.*]] = alloca i32, align 41751// CHECK15-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 41752// CHECK15-NEXT:    [[ARGV_ADDR:%.*]] = alloca ptr, align 41753// CHECK15-NEXT:    [[N:%.*]] = alloca i32, align 41754// CHECK15-NEXT:    [[M:%.*]] = alloca i32, align 41755// CHECK15-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 41756// CHECK15-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 41757// CHECK15-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 41758// CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 41759// CHECK15-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41760// CHECK15-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 41761// CHECK15-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 41762// CHECK15-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 81763// CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 81764// CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 81765// CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 41766// CHECK15-NEXT:    [[J:%.*]] = alloca i32, align 41767// CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 81768// CHECK15-NEXT:    [[I9:%.*]] = alloca i32, align 41769// CHECK15-NEXT:    [[J10:%.*]] = alloca i32, align 41770// CHECK15-NEXT:    store i32 0, ptr [[RETVAL]], align 41771// CHECK15-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 41772// CHECK15-NEXT:    store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 41773// CHECK15-NEXT:    store i32 100, ptr [[N]], align 41774// CHECK15-NEXT:    store i32 2, ptr [[M]], align 41775// CHECK15-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N]], align 41776// CHECK15-NEXT:    [[TMP1:%.*]] = load i32, ptr [[M]], align 41777// CHECK15-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()1778// CHECK15-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 41779// CHECK15-NEXT:    [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]1780// CHECK15-NEXT:    [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 41781// CHECK15-NEXT:    store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 41782// CHECK15-NEXT:    store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 41783// CHECK15-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N]], align 41784// CHECK15-NEXT:    store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 41785// CHECK15-NEXT:    [[TMP5:%.*]] = load i32, ptr [[M]], align 41786// CHECK15-NEXT:    store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_2]], align 41787// CHECK15-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41788// CHECK15-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP6]], 01789// CHECK15-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 11790// CHECK15-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i641791// CHECK15-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41792// CHECK15-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP7]], 01793// CHECK15-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 11794// CHECK15-NEXT:    [[CONV6:%.*]] = sext i32 [[DIV5]] to i641795// CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]1796// CHECK15-NEXT:    [[SUB7:%.*]] = sub nsw i64 [[MUL]], 11797// CHECK15-NEXT:    store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 81798// CHECK15-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 81799// CHECK15-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 81800// CHECK15-NEXT:    store i64 [[TMP8]], ptr [[DOTOMP_UB]], align 81801// CHECK15-NEXT:    store i32 0, ptr [[I]], align 41802// CHECK15-NEXT:    store i32 0, ptr [[J]], align 41803// CHECK15-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41804// CHECK15-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP9]]1805// CHECK15-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]]1806// CHECK15:       land.lhs.true:1807// CHECK15-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41808// CHECK15-NEXT:    [[CMP8:%.*]] = icmp slt i32 0, [[TMP10]]1809// CHECK15-NEXT:    br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]]1810// CHECK15:       simd.if.then:1811// CHECK15-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_LB]], align 81812// CHECK15-NEXT:    store i64 [[TMP11]], ptr [[DOTOMP_IV]], align 81813// CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1814// CHECK15:       omp.inner.for.cond:1815// CHECK15-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3:![0-9]+]]1816// CHECK15-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP3]]1817// CHECK15-NEXT:    [[CMP11:%.*]] = icmp sle i64 [[TMP12]], [[TMP13]]1818// CHECK15-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1819// CHECK15:       omp.inner.for.body:1820// CHECK15-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]1821// CHECK15-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]1822// CHECK15-NEXT:    [[SUB12:%.*]] = sub nsw i32 [[TMP15]], 01823// CHECK15-NEXT:    [[DIV13:%.*]] = sdiv i32 [[SUB12]], 11824// CHECK15-NEXT:    [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]]1825// CHECK15-NEXT:    [[CONV15:%.*]] = sext i32 [[MUL14]] to i641826// CHECK15-NEXT:    [[DIV16:%.*]] = sdiv i64 [[TMP14]], [[CONV15]]1827// CHECK15-NEXT:    [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 11828// CHECK15-NEXT:    [[ADD:%.*]] = add nsw i64 0, [[MUL17]]1829// CHECK15-NEXT:    [[CONV18:%.*]] = trunc i64 [[ADD]] to i321830// CHECK15-NEXT:    store i32 [[CONV18]], ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP3]]1831// CHECK15-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]1832// CHECK15-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]1833// CHECK15-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]1834// CHECK15-NEXT:    [[SUB19:%.*]] = sub nsw i32 [[TMP18]], 01835// CHECK15-NEXT:    [[DIV20:%.*]] = sdiv i32 [[SUB19]], 11836// CHECK15-NEXT:    [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]]1837// CHECK15-NEXT:    [[CONV22:%.*]] = sext i32 [[MUL21]] to i641838// CHECK15-NEXT:    [[DIV23:%.*]] = sdiv i64 [[TMP17]], [[CONV22]]1839// CHECK15-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]1840// CHECK15-NEXT:    [[SUB24:%.*]] = sub nsw i32 [[TMP19]], 01841// CHECK15-NEXT:    [[DIV25:%.*]] = sdiv i32 [[SUB24]], 11842// CHECK15-NEXT:    [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]]1843// CHECK15-NEXT:    [[CONV27:%.*]] = sext i32 [[MUL26]] to i641844// CHECK15-NEXT:    [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]]1845// CHECK15-NEXT:    [[SUB29:%.*]] = sub nsw i64 [[TMP16]], [[MUL28]]1846// CHECK15-NEXT:    [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 11847// CHECK15-NEXT:    [[ADD31:%.*]] = add nsw i64 0, [[MUL30]]1848// CHECK15-NEXT:    [[CONV32:%.*]] = trunc i64 [[ADD31]] to i321849// CHECK15-NEXT:    store i32 [[CONV32]], ptr [[J10]], align 4, !llvm.access.group [[ACC_GRP3]]1850// CHECK15-NEXT:    [[TMP20:%.*]] = load i32, ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP3]]1851// CHECK15-NEXT:    [[TMP21:%.*]] = mul nsw i32 [[TMP20]], [[TMP1]]1852// CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i32 [[TMP21]]1853// CHECK15-NEXT:    [[TMP22:%.*]] = load i32, ptr [[J10]], align 4, !llvm.access.group [[ACC_GRP3]]1854// CHECK15-NEXT:    [[ARRAYIDX33:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i32 [[TMP22]]1855// CHECK15-NEXT:    store i32 0, ptr [[ARRAYIDX33]], align 4, !llvm.access.group [[ACC_GRP3]]1856// CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1857// CHECK15:       omp.body.continue:1858// CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1859// CHECK15:       omp.inner.for.inc:1860// CHECK15-NEXT:    [[TMP23:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]1861// CHECK15-NEXT:    [[ADD34:%.*]] = add nsw i64 [[TMP23]], 11862// CHECK15-NEXT:    store i64 [[ADD34]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]1863// CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]1864// CHECK15:       omp.inner.for.end:1865// CHECK15-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41866// CHECK15-NEXT:    [[SUB35:%.*]] = sub nsw i32 [[TMP24]], 01867// CHECK15-NEXT:    [[DIV36:%.*]] = sdiv i32 [[SUB35]], 11868// CHECK15-NEXT:    [[MUL37:%.*]] = mul nsw i32 [[DIV36]], 11869// CHECK15-NEXT:    [[ADD38:%.*]] = add nsw i32 0, [[MUL37]]1870// CHECK15-NEXT:    store i32 [[ADD38]], ptr [[I9]], align 41871// CHECK15-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41872// CHECK15-NEXT:    [[SUB39:%.*]] = sub nsw i32 [[TMP25]], 01873// CHECK15-NEXT:    [[DIV40:%.*]] = sdiv i32 [[SUB39]], 11874// CHECK15-NEXT:    [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 11875// CHECK15-NEXT:    [[ADD42:%.*]] = add nsw i32 0, [[MUL41]]1876// CHECK15-NEXT:    store i32 [[ADD42]], ptr [[J10]], align 41877// CHECK15-NEXT:    br label [[SIMD_IF_END]]1878// CHECK15:       simd.if.end:1879// CHECK15-NEXT:    [[TMP26:%.*]] = load i32, ptr [[ARGC_ADDR]], align 41880// CHECK15-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]])1881// CHECK15-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 41882// CHECK15-NEXT:    [[TMP27:%.*]] = load ptr, ptr [[SAVED_STACK]], align 41883// CHECK15-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP27]])1884// CHECK15-NEXT:    [[TMP28:%.*]] = load i32, ptr [[RETVAL]], align 41885// CHECK15-NEXT:    ret i32 [[TMP28]]1886//1887//1888// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_1889// CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {1890// CHECK15-NEXT:  entry:1891// CHECK15-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 41892// CHECK15-NEXT:    [[A:%.*]] = alloca [10 x [2 x i32]], align 41893// CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 41894// CHECK15-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41895// CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41896// CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41897// CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41898// CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 41899// CHECK15-NEXT:    [[J:%.*]] = alloca i32, align 41900// CHECK15-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 41901// CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41902// CHECK15-NEXT:    store i32 19, ptr [[DOTOMP_UB]], align 41903// CHECK15-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41904// CHECK15-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 41905// CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1906// CHECK15:       omp.inner.for.cond:1907// CHECK15-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]1908// CHECK15-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]]1909// CHECK15-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]1910// CHECK15-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1911// CHECK15:       omp.inner.for.body:1912// CHECK15-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]1913// CHECK15-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP3]], 21914// CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 11915// CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1916// CHECK15-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]1917// CHECK15-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]1918// CHECK15-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]1919// CHECK15-NEXT:    [[DIV2:%.*]] = sdiv i32 [[TMP5]], 21920// CHECK15-NEXT:    [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 21921// CHECK15-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]]1922// CHECK15-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[SUB]], 11923// CHECK15-NEXT:    [[ADD5:%.*]] = add nsw i32 0, [[MUL4]]1924// CHECK15-NEXT:    store i32 [[ADD5]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP7]]1925// CHECK15-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]1926// CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], i32 0, i32 [[TMP6]]1927// CHECK15-NEXT:    [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP7]]1928// CHECK15-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP7]]1929// CHECK15-NEXT:    store i32 0, ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP7]]1930// CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1931// CHECK15:       omp.body.continue:1932// CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1933// CHECK15:       omp.inner.for.inc:1934// CHECK15-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]1935// CHECK15-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP8]], 11936// CHECK15-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]1937// CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]1938// CHECK15:       omp.inner.for.end:1939// CHECK15-NEXT:    store i32 10, ptr [[I]], align 41940// CHECK15-NEXT:    store i32 2, ptr [[J]], align 41941// CHECK15-NEXT:    ret i32 01942//1943