2785 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s4// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK36// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s7// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK38 9// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK510// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s11// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK512// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK713// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s14// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK715 16// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK917// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s18// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK919 20// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1121// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s22// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1123 24// expected-no-diagnostics25#ifndef HEADER26#define HEADER27 28struct St {29 int a, b;30 St() : a(0), b(0) {}31 St(const St &st) : a(st.a + st.b), b(0) {}32 ~St() {}33};34 35volatile int g = 1212;36volatile int &g1 = g;37 38template <class T>39struct S {40 T f;41 S(T a) : f(a + g) {}42 S() : f(g) {}43 S(const S &s, St t = St()) : f(s.f + t.a) {}44 operator T() { return T(); }45 ~S() {}46};47 48 49template <typename T>50T tmain() {51 S<T> test;52 T t_var = T();53 T vec[] = {1, 2};54 S<T> s_arr[] = {1, 2};55 S<T> &var = test;56#pragma omp target teams distribute simd firstprivate(t_var, vec, s_arr, var)57 for (int i = 0; i < 2; ++i) {58 vec[i] = t_var;59 s_arr[i] = var;60 }61 return T();62}63 64S<float> test;65int t_var = 333;66int vec[] = {1, 2};67S<float> s_arr[] = {1, 2};68S<float> var(3);69 70int main() {71 static int sivar;72#ifdef LAMBDA73 [&]() {74#pragma omp target teams distribute simd firstprivate(g, g1, sivar)75 for (int i = 0; i < 2; ++i) {76 77 // Skip global and bound tid vars78 // skip loop vars79 g = 1;80 g1 = 1;81 sivar = 2;82 [&]() {83 g = 2;84 g1 = 2;85 sivar = 4;86 87 }();88 }89 }();90 return 0;91#else92#pragma omp target teams distribute simd firstprivate(t_var, vec, s_arr, var, sivar)93 for (int i = 0; i < 2; ++i) {94 vec[i] = t_var;95 s_arr[i] = var;96 sivar += i;97 }98 return tmain<int>();99#endif100}101 102 103 104 105 106// Skip global and bound tid vars107// Skip temp vars for loop108 109// param copy110 111// T_VAR and SIVAR112 113// preparation vars114 115// firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2116 117// firstprivate(s_arr)118 119// firstprivate(var)120 121 122 123 124 125 126// Skip global and bound tid vars127// Skip temp vars for loop128 129// param copy130 131 132// T_VAR and preparation variables133 134// firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2135 136// firstprivate(s_arr)137 138// firstprivate(var)139 140 141#endif142// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init143// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {144// CHECK1-NEXT: entry:145// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)146// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]147// CHECK1-NEXT: ret void148//149//150// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev151// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {152// CHECK1-NEXT: entry:153// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8154// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8155// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8156// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])157// CHECK1-NEXT: ret void158//159//160// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev161// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {162// CHECK1-NEXT: entry:163// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8164// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8165// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8166// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]167// CHECK1-NEXT: ret void168//169//170// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev171// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {172// CHECK1-NEXT: entry:173// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8174// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8175// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8176// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0177// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4178// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float179// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4180// CHECK1-NEXT: ret void181//182//183// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev184// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {185// CHECK1-NEXT: entry:186// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8187// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8188// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8189// CHECK1-NEXT: ret void190//191//192// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1193// CHECK1-SAME: () #[[ATTR0]] {194// CHECK1-NEXT: entry:195// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)196// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)197// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]198// CHECK1-NEXT: ret void199//200//201// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef202// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {203// CHECK1-NEXT: entry:204// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8205// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4206// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8207// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4208// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8209// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4210// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])211// CHECK1-NEXT: ret void212//213//214// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor215// CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {216// CHECK1-NEXT: entry:217// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8218// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8219// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]220// CHECK1: arraydestroy.body:221// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]222// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1223// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]224// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr225// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]226// CHECK1: arraydestroy.done1:227// CHECK1-NEXT: ret void228//229//230// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef231// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {232// CHECK1-NEXT: entry:233// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8234// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4235// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8236// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4237// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8238// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0239// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4240// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4241// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float242// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]243// CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4244// CHECK1-NEXT: ret void245//246//247// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2248// CHECK1-SAME: () #[[ATTR0]] {249// CHECK1-NEXT: entry:250// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)251// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]252// CHECK1-NEXT: ret void253//254//255// CHECK1-LABEL: define {{[^@]+}}@main256// CHECK1-SAME: () #[[ATTR3:[0-9]+]] {257// CHECK1-NEXT: entry:258// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4259// CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8260// CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8261// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8262// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8263// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8264// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4265// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8266// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4267// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr @t_var, align 4268// CHECK1-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4269// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8270// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4271// CHECK1-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4272// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8273// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0274// CHECK1-NEXT: store ptr @vec, ptr [[TMP4]], align 8275// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0276// CHECK1-NEXT: store ptr @vec, ptr [[TMP5]], align 8277// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0278// CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8279// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1280// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP7]], align 8281// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1282// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP8]], align 8283// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1284// CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8285// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2286// CHECK1-NEXT: store ptr @s_arr, ptr [[TMP10]], align 8287// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2288// CHECK1-NEXT: store ptr @s_arr, ptr [[TMP11]], align 8289// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2290// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8291// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3292// CHECK1-NEXT: store ptr @var, ptr [[TMP13]], align 8293// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3294// CHECK1-NEXT: store ptr @var, ptr [[TMP14]], align 8295// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3296// CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8297// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4298// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP16]], align 8299// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4300// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP17]], align 8301// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4302// CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8303// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0304// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0305// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0306// CHECK1-NEXT: store i32 3, ptr [[TMP21]], align 4307// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1308// CHECK1-NEXT: store i32 5, ptr [[TMP22]], align 4309// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2310// CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8311// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3312// CHECK1-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 8313// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4314// CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP25]], align 8315// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5316// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 8317// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6318// CHECK1-NEXT: store ptr null, ptr [[TMP27]], align 8319// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7320// CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8321// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8322// CHECK1-NEXT: store i64 2, ptr [[TMP29]], align 8323// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9324// CHECK1-NEXT: store i64 0, ptr [[TMP30]], align 8325// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10326// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4327// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11328// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP32]], align 4329// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12330// CHECK1-NEXT: store i32 0, ptr [[TMP33]], align 4331// CHECK1-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.region_id, ptr [[KERNEL_ARGS]])332// CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0333// CHECK1-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]334// CHECK1: omp_offload.failed:335// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92(ptr @vec, i64 [[TMP1]], ptr @s_arr, ptr @var, i64 [[TMP3]]) #[[ATTR2]]336// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]337// CHECK1: omp_offload.cont:338// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()339// CHECK1-NEXT: ret i32 [[CALL]]340//341//342// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92343// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {344// CHECK1-NEXT: entry:345// CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8346// CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8347// CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8348// CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8349// CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8350// CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8351// CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8352// CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8353// CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8354// CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8355// CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8356// CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8357// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]]358// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]359// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]360// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4361// CHECK1-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4362// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8363// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4364// CHECK1-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4365// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8366// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i64 [[TMP6]])367// CHECK1-NEXT: ret void368//369//370// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.omp_outlined371// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] {372// CHECK1-NEXT: entry:373// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8374// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8375// CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8376// CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8377// CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8378// CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8379// CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8380// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4381// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4382// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4383// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4384// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4385// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4386// CHECK1-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4387// CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4388// CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4389// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4390// CHECK1-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4391// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4392// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8393// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8394// CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8395// CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8396// CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8397// CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8398// CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8399// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]400// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]401// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]402// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4403// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4404// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4405// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4406// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false)407// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0408// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2409// CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]410// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]411// CHECK1: omp.arraycpy.body:412// CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]413// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]414// CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])415// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])416// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]417// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1418// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1419// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]420// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]421// CHECK1: omp.arraycpy.done3:422// CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]])423// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]])424// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]425// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8426// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4427// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)428// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4429// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1430// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]431// CHECK1: cond.true:432// CHECK1-NEXT: br label [[COND_END:%.*]]433// CHECK1: cond.false:434// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4435// CHECK1-NEXT: br label [[COND_END]]436// CHECK1: cond.end:437// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]438// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4439// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4440// CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4441// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]442// CHECK1: omp.inner.for.cond:443// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]]444// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]]445// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]446// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]447// CHECK1: omp.inner.for.cond.cleanup:448// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]449// CHECK1: omp.inner.for.body:450// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]451// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1452// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]453// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]454// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP9]]455// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]456// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64457// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 [[IDXPROM]]458// CHECK1-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]]459// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]460// CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64461// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i64 0, i64 [[IDXPROM7]]462// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[VAR4]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]]463// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]464// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP9]]465// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]466// CHECK1-NEXT: store i32 [[ADD9]], ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP9]]467// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]468// CHECK1: omp.body.continue:469// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]470// CHECK1: omp.inner.for.inc:471// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]472// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP17]], 1473// CHECK1-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]474// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]475// CHECK1: omp.inner.for.end:476// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]477// CHECK1: omp.loop.exit:478// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8479// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4480// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]])481// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4482// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0483// CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]484// CHECK1: .omp.final.then:485// CHECK1-NEXT: store i32 2, ptr [[I]], align 4486// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]487// CHECK1: .omp.final.done:488// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]489// CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0490// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2491// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]492// CHECK1: arraydestroy.body:493// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]494// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1495// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]496// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]497// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]498// CHECK1: arraydestroy.done12:499// CHECK1-NEXT: ret void500//501//502// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev503// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {504// CHECK1-NEXT: entry:505// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8506// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8507// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8508// CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])509// CHECK1-NEXT: ret void510//511//512// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St513// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {514// CHECK1-NEXT: entry:515// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8516// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8517// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8518// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8519// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8520// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8521// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8522// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8523// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])524// CHECK1-NEXT: ret void525//526//527// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev528// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {529// CHECK1-NEXT: entry:530// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8531// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8532// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8533// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]534// CHECK1-NEXT: ret void535//536//537// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v538// CHECK1-SAME: () #[[ATTR1]] comdat {539// CHECK1-NEXT: entry:540// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4541// CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4542// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4543// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4544// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4545// CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8546// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8547// CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8548// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8549// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8550// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8551// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4552// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8553// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])554// CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4555// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)556// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1)557// CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1558// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)559// CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8560// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META7]], !align [[META8]]561// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8562// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4563// CHECK1-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4564// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8565// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]566// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0567// CHECK1-NEXT: store ptr [[VEC]], ptr [[TMP4]], align 8568// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0569// CHECK1-NEXT: store ptr [[VEC]], ptr [[TMP5]], align 8570// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0571// CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8572// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1573// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP7]], align 8574// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1575// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP8]], align 8576// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1577// CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8578// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2579// CHECK1-NEXT: store ptr [[S_ARR]], ptr [[TMP10]], align 8580// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2581// CHECK1-NEXT: store ptr [[S_ARR]], ptr [[TMP11]], align 8582// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2583// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8584// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3585// CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 8586// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3587// CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 8588// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3589// CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8590// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0591// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0592// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0593// CHECK1-NEXT: store i32 3, ptr [[TMP18]], align 4594// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1595// CHECK1-NEXT: store i32 4, ptr [[TMP19]], align 4596// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2597// CHECK1-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 8598// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3599// CHECK1-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 8600// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4601// CHECK1-NEXT: store ptr @.offload_sizes.3, ptr [[TMP22]], align 8602// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5603// CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP23]], align 8604// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6605// CHECK1-NEXT: store ptr null, ptr [[TMP24]], align 8606// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7607// CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8608// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8609// CHECK1-NEXT: store i64 2, ptr [[TMP26]], align 8610// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9611// CHECK1-NEXT: store i64 0, ptr [[TMP27]], align 8612// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10613// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4614// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11615// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4616// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12617// CHECK1-NEXT: store i32 0, ptr [[TMP30]], align 4618// CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])619// CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0620// CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]621// CHECK1: omp_offload.failed:622// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(ptr [[VEC]], i64 [[TMP2]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]]623// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]624// CHECK1: omp_offload.cont:625// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4626// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0627// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2628// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]629// CHECK1: arraydestroy.body:630// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]631// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1632// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]633// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]634// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]635// CHECK1: arraydestroy.done2:636// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]637// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4638// CHECK1-NEXT: ret i32 [[TMP34]]639//640//641// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev642// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {643// CHECK1-NEXT: entry:644// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8645// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8646// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8647// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0648// CHECK1-NEXT: store i32 0, ptr [[A]], align 4649// CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1650// CHECK1-NEXT: store i32 0, ptr [[B]], align 4651// CHECK1-NEXT: ret void652//653//654// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St655// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {656// CHECK1-NEXT: entry:657// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8658// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8659// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8660// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8661// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8662// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8663// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8664// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0665// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]666// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0667// CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4668// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0669// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4670// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float671// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]672// CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4673// CHECK1-NEXT: ret void674//675//676// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev677// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {678// CHECK1-NEXT: entry:679// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8680// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8681// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8682// CHECK1-NEXT: ret void683//684//685// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev686// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {687// CHECK1-NEXT: entry:688// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8689// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8690// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8691// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])692// CHECK1-NEXT: ret void693//694//695// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei696// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {697// CHECK1-NEXT: entry:698// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8699// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4700// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8701// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4702// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8703// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4704// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])705// CHECK1-NEXT: ret void706//707//708// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56709// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {710// CHECK1-NEXT: entry:711// CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8712// CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8713// CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8714// CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8715// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8716// CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8717// CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8718// CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8719// CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8720// CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8721// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]722// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]723// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]724// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8725// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4726// CHECK1-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4727// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8728// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]729// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]])730// CHECK1-NEXT: ret void731//732//733// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined734// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {735// CHECK1-NEXT: entry:736// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8737// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8738// CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8739// CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8740// CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8741// CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8742// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8743// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4744// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4745// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4746// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4747// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4748// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4749// CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4750// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4751// CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4752// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4753// CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4754// CHECK1-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8755// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4756// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8757// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8758// CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8759// CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8760// CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8761// CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8762// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]763// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]764// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]765// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8766// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4767// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4768// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4769// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4770// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false)771// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0772// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2773// CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]774// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]775// CHECK1: omp.arraycpy.body:776// CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]777// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]778// CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])779// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])780// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]781// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1782// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1783// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]784// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]785// CHECK1: omp.arraycpy.done4:786// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]787// CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])788// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]])789// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]790// CHECK1-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 8791// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8792// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4793// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)794// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4795// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1796// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]797// CHECK1: cond.true:798// CHECK1-NEXT: br label [[COND_END:%.*]]799// CHECK1: cond.false:800// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4801// CHECK1-NEXT: br label [[COND_END]]802// CHECK1: cond.end:803// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]804// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4805// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4806// CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4807// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]808// CHECK1: omp.inner.for.cond:809// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]]810// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP15]]811// CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]812// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]813// CHECK1: omp.inner.for.cond.cleanup:814// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]815// CHECK1: omp.inner.for.body:816// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]817// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1818// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]819// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]]820// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP15]]821// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]]822// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64823// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]]824// CHECK1-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]]825// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP15]]826// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]]827// CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP16]] to i64828// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM9]]829// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group [[ACC_GRP15]]830// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]831// CHECK1: omp.body.continue:832// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]833// CHECK1: omp.inner.for.inc:834// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]835// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1836// CHECK1-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]837// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]838// CHECK1: omp.inner.for.end:839// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]840// CHECK1: omp.loop.exit:841// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8842// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4843// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]])844// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4845// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0846// CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]847// CHECK1: .omp.final.then:848// CHECK1-NEXT: store i32 2, ptr [[I]], align 4849// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]850// CHECK1: .omp.final.done:851// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]852// CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0853// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2854// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]855// CHECK1: arraydestroy.body:856// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]857// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1858// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]859// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]860// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]861// CHECK1: arraydestroy.done13:862// CHECK1-NEXT: ret void863//864//865// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St866// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {867// CHECK1-NEXT: entry:868// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8869// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8870// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8871// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8872// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8873// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8874// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8875// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8876// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])877// CHECK1-NEXT: ret void878//879//880// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev881// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {882// CHECK1-NEXT: entry:883// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8884// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8885// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8886// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]887// CHECK1-NEXT: ret void888//889//890// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev891// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {892// CHECK1-NEXT: entry:893// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8894// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8895// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8896// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0897// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4898// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4899// CHECK1-NEXT: ret void900//901//902// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei903// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {904// CHECK1-NEXT: entry:905// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8906// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4907// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8908// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4909// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8910// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0911// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4912// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4913// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]914// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4915// CHECK1-NEXT: ret void916//917//918// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St919// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {920// CHECK1-NEXT: entry:921// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8922// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8923// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8924// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8925// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8926// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8927// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8928// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0929// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]930// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0931// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4932// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0933// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4934// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]935// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4936// CHECK1-NEXT: ret void937//938//939// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev940// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {941// CHECK1-NEXT: entry:942// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8943// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8944// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8945// CHECK1-NEXT: ret void946//947//948// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp949// CHECK1-SAME: () #[[ATTR0]] {950// CHECK1-NEXT: entry:951// CHECK1-NEXT: call void @__cxx_global_var_init()952// CHECK1-NEXT: call void @__cxx_global_var_init.1()953// CHECK1-NEXT: call void @__cxx_global_var_init.2()954// CHECK1-NEXT: ret void955//956//957// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init958// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {959// CHECK3-NEXT: entry:960// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)961// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]962// CHECK3-NEXT: ret void963//964//965// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev966// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {967// CHECK3-NEXT: entry:968// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4969// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4970// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4971// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])972// CHECK3-NEXT: ret void973//974//975// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev976// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {977// CHECK3-NEXT: entry:978// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4979// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4980// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4981// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]982// CHECK3-NEXT: ret void983//984//985// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev986// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {987// CHECK3-NEXT: entry:988// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4989// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4990// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4991// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0992// CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4993// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float994// CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4995// CHECK3-NEXT: ret void996//997//998// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev999// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1000// CHECK3-NEXT: entry:1001// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41002// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41003// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41004// CHECK3-NEXT: ret void1005//1006//1007// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.11008// CHECK3-SAME: () #[[ATTR0]] {1009// CHECK3-NEXT: entry:1010// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)1011// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00)1012// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]1013// CHECK3-NEXT: ret void1014//1015//1016// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef1017// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1018// CHECK3-NEXT: entry:1019// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41020// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 41021// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41022// CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 41023// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41024// CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41025// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])1026// CHECK3-NEXT: ret void1027//1028//1029// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor1030// CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {1031// CHECK3-NEXT: entry:1032// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 41033// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 41034// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1035// CHECK3: arraydestroy.body:1036// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1037// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11038// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1039// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr1040// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]1041// CHECK3: arraydestroy.done1:1042// CHECK3-NEXT: ret void1043//1044//1045// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef1046// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1047// CHECK3-NEXT: entry:1048// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41049// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 41050// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41051// CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 41052// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41053// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01054// CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41055// CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 41056// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float1057// CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]1058// CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 41059// CHECK3-NEXT: ret void1060//1061//1062// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.21063// CHECK3-SAME: () #[[ATTR0]] {1064// CHECK3-NEXT: entry:1065// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)1066// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]1067// CHECK3-NEXT: ret void1068//1069//1070// CHECK3-LABEL: define {{[^@]+}}@main1071// CHECK3-SAME: () #[[ATTR3:[0-9]+]] {1072// CHECK3-NEXT: entry:1073// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 41074// CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 41075// CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 41076// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 41077// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 41078// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 41079// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 41080// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81081// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 41082// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr @t_var, align 41083// CHECK3-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 41084// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41085// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 41086// CHECK3-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 41087// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 41088// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01089// CHECK3-NEXT: store ptr @vec, ptr [[TMP4]], align 41090// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01091// CHECK3-NEXT: store ptr @vec, ptr [[TMP5]], align 41092// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 01093// CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 41094// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11095// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP7]], align 41096// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11097// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP8]], align 41098// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 11099// CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 41100// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21101// CHECK3-NEXT: store ptr @s_arr, ptr [[TMP10]], align 41102// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21103// CHECK3-NEXT: store ptr @s_arr, ptr [[TMP11]], align 41104// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 21105// CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 41106// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31107// CHECK3-NEXT: store ptr @var, ptr [[TMP13]], align 41108// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31109// CHECK3-NEXT: store ptr @var, ptr [[TMP14]], align 41110// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 31111// CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 41112// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 41113// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP16]], align 41114// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 41115// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP17]], align 41116// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 41117// CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 41118// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01119// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01120// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01121// CHECK3-NEXT: store i32 3, ptr [[TMP21]], align 41122// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11123// CHECK3-NEXT: store i32 5, ptr [[TMP22]], align 41124// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21125// CHECK3-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 41126// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31127// CHECK3-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 41128// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41129// CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP25]], align 41130// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51131// CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 41132// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61133// CHECK3-NEXT: store ptr null, ptr [[TMP27]], align 41134// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71135// CHECK3-NEXT: store ptr null, ptr [[TMP28]], align 41136// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81137// CHECK3-NEXT: store i64 2, ptr [[TMP29]], align 81138// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91139// CHECK3-NEXT: store i64 0, ptr [[TMP30]], align 81140// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101141// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 41142// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111143// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP32]], align 41144// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121145// CHECK3-NEXT: store i32 0, ptr [[TMP33]], align 41146// CHECK3-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.region_id, ptr [[KERNEL_ARGS]])1147// CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 01148// CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1149// CHECK3: omp_offload.failed:1150// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92(ptr @vec, i32 [[TMP1]], ptr @s_arr, ptr @var, i32 [[TMP3]]) #[[ATTR2]]1151// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]1152// CHECK3: omp_offload.cont:1153// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()1154// CHECK3-NEXT: ret i32 [[CALL]]1155//1156//1157// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l921158// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {1159// CHECK3-NEXT: entry:1160// CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 41161// CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 41162// CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 41163// CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 41164// CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 41165// CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 41166// CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 41167// CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 41168// CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41169// CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41170// CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 41171// CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 41172// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]]1173// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1174// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1175// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 41176// CHECK3-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 41177// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41178// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 41179// CHECK3-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 41180// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 41181// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i32 [[TMP6]])1182// CHECK3-NEXT: ret void1183//1184//1185// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.omp_outlined1186// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] {1187// CHECK3-NEXT: entry:1188// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41189// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41190// CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 41191// CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 41192// CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 41193// CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 41194// CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 41195// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41196// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 41197// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41198// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41199// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41200// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41201// CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 41202// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 41203// CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 41204// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 41205// CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 41206// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 41207// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41208// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41209// CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 41210// CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41211// CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41212// CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 41213// CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 41214// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1215// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1216// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1217// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41218// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 41219// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41220// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41221// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false)1222// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 01223// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 21224// CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]1225// CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1226// CHECK3: omp.arraycpy.body:1227// CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1228// CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1229// CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])1230// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])1231// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]1232// CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11233// CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11234// CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]1235// CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]1236// CHECK3: omp.arraycpy.done3:1237// CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]])1238// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]])1239// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]1240// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41241// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 41242// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1243// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41244// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 11245// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1246// CHECK3: cond.true:1247// CHECK3-NEXT: br label [[COND_END:%.*]]1248// CHECK3: cond.false:1249// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41250// CHECK3-NEXT: br label [[COND_END]]1251// CHECK3: cond.end:1252// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]1253// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41254// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41255// CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 41256// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1257// CHECK3: omp.inner.for.cond:1258// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]]1259// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]]1260// CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]1261// CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1262// CHECK3: omp.inner.for.cond.cleanup:1263// CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]1264// CHECK3: omp.inner.for.body:1265// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]1266// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 11267// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1268// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]1269// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]]1270// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]1271// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP13]]1272// CHECK3-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]]1273// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]1274// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP14]]1275// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]]1276// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]1277// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]]1278// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]1279// CHECK3-NEXT: store i32 [[ADD8]], ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]]1280// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1281// CHECK3: omp.body.continue:1282// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1283// CHECK3: omp.inner.for.inc:1284// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]1285// CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP17]], 11286// CHECK3-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]1287// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]1288// CHECK3: omp.inner.for.end:1289// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1290// CHECK3: omp.loop.exit:1291// CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41292// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 41293// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]])1294// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41295// CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 01296// CHECK3-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1297// CHECK3: .omp.final.then:1298// CHECK3-NEXT: store i32 2, ptr [[I]], align 41299// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]1300// CHECK3: .omp.final.done:1301// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]1302// CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 01303// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 21304// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1305// CHECK3: arraydestroy.body:1306// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1307// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11308// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1309// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]1310// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]1311// CHECK3: arraydestroy.done11:1312// CHECK3-NEXT: ret void1313//1314//1315// CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev1316// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1317// CHECK3-NEXT: entry:1318// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41319// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41320// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41321// CHECK3-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])1322// CHECK3-NEXT: ret void1323//1324//1325// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St1326// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1327// CHECK3-NEXT: entry:1328// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41329// CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 41330// CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 41331// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41332// CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 41333// CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 41334// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41335// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 41336// CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])1337// CHECK3-NEXT: ret void1338//1339//1340// CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev1341// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1342// CHECK3-NEXT: entry:1343// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41344// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41345// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41346// CHECK3-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]1347// CHECK3-NEXT: ret void1348//1349//1350// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v1351// CHECK3-SAME: () #[[ATTR1]] comdat {1352// CHECK3-NEXT: entry:1353// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 41354// CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41355// CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 41356// CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 41357// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 41358// CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 41359// CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 41360// CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 41361// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 41362// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 41363// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 41364// CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 41365// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81366// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])1367// CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 41368// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)1369// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)1370// CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 11371// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)1372// CHECK3-NEXT: store ptr [[TEST]], ptr [[VAR]], align 41373// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META8]], !align [[META9]]1374// CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 41375// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 41376// CHECK3-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 41377// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41378// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1379// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01380// CHECK3-NEXT: store ptr [[VEC]], ptr [[TMP4]], align 41381// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01382// CHECK3-NEXT: store ptr [[VEC]], ptr [[TMP5]], align 41383// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 01384// CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 41385// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11386// CHECK3-NEXT: store i32 [[TMP2]], ptr [[TMP7]], align 41387// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11388// CHECK3-NEXT: store i32 [[TMP2]], ptr [[TMP8]], align 41389// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 11390// CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 41391// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21392// CHECK3-NEXT: store ptr [[S_ARR]], ptr [[TMP10]], align 41393// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21394// CHECK3-NEXT: store ptr [[S_ARR]], ptr [[TMP11]], align 41395// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 21396// CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 41397// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31398// CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 41399// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31400// CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 41401// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 31402// CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 41403// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01404// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01405// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01406// CHECK3-NEXT: store i32 3, ptr [[TMP18]], align 41407// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11408// CHECK3-NEXT: store i32 4, ptr [[TMP19]], align 41409// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21410// CHECK3-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 41411// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31412// CHECK3-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 41413// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41414// CHECK3-NEXT: store ptr @.offload_sizes.3, ptr [[TMP22]], align 41415// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51416// CHECK3-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP23]], align 41417// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61418// CHECK3-NEXT: store ptr null, ptr [[TMP24]], align 41419// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71420// CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 41421// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81422// CHECK3-NEXT: store i64 2, ptr [[TMP26]], align 81423// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91424// CHECK3-NEXT: store i64 0, ptr [[TMP27]], align 81425// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101426// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 41427// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111428// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 41429// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121430// CHECK3-NEXT: store i32 0, ptr [[TMP30]], align 41431// CHECK3-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])1432// CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 01433// CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1434// CHECK3: omp_offload.failed:1435// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(ptr [[VEC]], i32 [[TMP2]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]]1436// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]1437// CHECK3: omp_offload.cont:1438// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 41439// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01440// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 21441// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1442// CHECK3: arraydestroy.body:1443// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1444// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11445// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1446// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]1447// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]1448// CHECK3: arraydestroy.done2:1449// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]1450// CHECK3-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 41451// CHECK3-NEXT: ret i32 [[TMP34]]1452//1453//1454// CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev1455// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1456// CHECK3-NEXT: entry:1457// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41458// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41459// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41460// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 01461// CHECK3-NEXT: store i32 0, ptr [[A]], align 41462// CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 11463// CHECK3-NEXT: store i32 0, ptr [[B]], align 41464// CHECK3-NEXT: ret void1465//1466//1467// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St1468// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1469// CHECK3-NEXT: entry:1470// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41471// CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 41472// CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 41473// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41474// CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 41475// CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 41476// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41477// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01478// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1479// CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 01480// CHECK3-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 41481// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 01482// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 41483// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float1484// CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]1485// CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 41486// CHECK3-NEXT: ret void1487//1488//1489// CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev1490// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1491// CHECK3-NEXT: entry:1492// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41493// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41494// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41495// CHECK3-NEXT: ret void1496//1497//1498// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev1499// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1500// CHECK3-NEXT: entry:1501// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41502// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41503// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41504// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1505// CHECK3-NEXT: ret void1506//1507//1508// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei1509// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1510// CHECK3-NEXT: entry:1511// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41512// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 41513// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41514// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 41515// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41516// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41517// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])1518// CHECK3-NEXT: ret void1519//1520//1521// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l561522// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {1523// CHECK3-NEXT: entry:1524// CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 41525// CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 41526// CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 41527// CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 41528// CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 41529// CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 41530// CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 41531// CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41532// CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41533// CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 41534// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1535// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1536// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1537// CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 41538// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 41539// CHECK3-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 41540// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41541// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1542// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]])1543// CHECK3-NEXT: ret void1544//1545//1546// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined1547// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {1548// CHECK3-NEXT: entry:1549// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41550// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41551// CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 41552// CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 41553// CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 41554// CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 41555// CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 41556// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41557// CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 41558// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41559// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41560// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41561// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41562// CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 41563// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 41564// CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 41565// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41566// CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 41567// CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 41568// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 41569// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41570// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41571// CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 41572// CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41573// CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41574// CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 41575// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1576// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1577// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1578// CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 41579// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41580// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 41581// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41582// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41583// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false)1584// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 01585// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 21586// CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]1587// CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1588// CHECK3: omp.arraycpy.body:1589// CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1590// CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1591// CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])1592// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])1593// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]1594// CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11595// CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11596// CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]1597// CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]1598// CHECK3: omp.arraycpy.done4:1599// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1600// CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])1601// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]])1602// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]1603// CHECK3-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 41604// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41605// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 41606// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1607// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41608// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 11609// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1610// CHECK3: cond.true:1611// CHECK3-NEXT: br label [[COND_END:%.*]]1612// CHECK3: cond.false:1613// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41614// CHECK3-NEXT: br label [[COND_END]]1615// CHECK3: cond.end:1616// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]1617// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41618// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41619// CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 41620// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1621// CHECK3: omp.inner.for.cond:1622// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]]1623// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP16]]1624// CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]1625// CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1626// CHECK3: omp.inner.for.cond.cleanup:1627// CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]1628// CHECK3: omp.inner.for.body:1629// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]]1630// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 11631// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1632// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]]1633// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP16]]1634// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]]1635// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP14]]1636// CHECK3-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]]1637// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP16]]1638// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]]1639// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP16]]1640// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group [[ACC_GRP16]]1641// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1642// CHECK3: omp.body.continue:1643// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1644// CHECK3: omp.inner.for.inc:1645// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]]1646// CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP17]], 11647// CHECK3-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]]1648// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]1649// CHECK3: omp.inner.for.end:1650// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1651// CHECK3: omp.loop.exit:1652// CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41653// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 41654// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]])1655// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41656// CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 01657// CHECK3-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1658// CHECK3: .omp.final.then:1659// CHECK3-NEXT: store i32 2, ptr [[I]], align 41660// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]1661// CHECK3: .omp.final.done:1662// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]1663// CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 01664// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 21665// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1666// CHECK3: arraydestroy.body:1667// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1668// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11669// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1670// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]1671// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]1672// CHECK3: arraydestroy.done12:1673// CHECK3-NEXT: ret void1674//1675//1676// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St1677// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1678// CHECK3-NEXT: entry:1679// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41680// CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 41681// CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 41682// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41683// CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 41684// CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 41685// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41686// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 41687// CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])1688// CHECK3-NEXT: ret void1689//1690//1691// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev1692// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1693// CHECK3-NEXT: entry:1694// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41695// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41696// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41697// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]1698// CHECK3-NEXT: ret void1699//1700//1701// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev1702// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1703// CHECK3-NEXT: entry:1704// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41705// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41706// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41707// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01708// CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 41709// CHECK3-NEXT: store i32 [[TMP0]], ptr [[F]], align 41710// CHECK3-NEXT: ret void1711//1712//1713// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei1714// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1715// CHECK3-NEXT: entry:1716// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41717// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 41718// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41719// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 41720// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41721// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01722// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41723// CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 41724// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]1725// CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 41726// CHECK3-NEXT: ret void1727//1728//1729// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St1730// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1731// CHECK3-NEXT: entry:1732// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41733// CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 41734// CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 41735// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41736// CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 41737// CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 41738// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41739// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01740// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1741// CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 01742// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 41743// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 01744// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 41745// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]1746// CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 41747// CHECK3-NEXT: ret void1748//1749//1750// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev1751// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1752// CHECK3-NEXT: entry:1753// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41754// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41755// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41756// CHECK3-NEXT: ret void1757//1758//1759// CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp1760// CHECK3-SAME: () #[[ATTR0]] {1761// CHECK3-NEXT: entry:1762// CHECK3-NEXT: call void @__cxx_global_var_init()1763// CHECK3-NEXT: call void @__cxx_global_var_init.1()1764// CHECK3-NEXT: call void @__cxx_global_var_init.2()1765// CHECK3-NEXT: ret void1766//1767//1768// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init1769// CHECK5-SAME: () #[[ATTR0:[0-9]+]] {1770// CHECK5-NEXT: entry:1771// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)1772// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]1773// CHECK5-NEXT: ret void1774//1775//1776// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev1777// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {1778// CHECK5-NEXT: entry:1779// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81780// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81781// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81782// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1783// CHECK5-NEXT: ret void1784//1785//1786// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev1787// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1788// CHECK5-NEXT: entry:1789// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81790// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81791// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81792// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]1793// CHECK5-NEXT: ret void1794//1795//1796// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.11797// CHECK5-SAME: () #[[ATTR0]] {1798// CHECK5-NEXT: entry:1799// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)1800// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)1801// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]1802// CHECK5-NEXT: ret void1803//1804//1805// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef1806// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1807// CHECK5-NEXT: entry:1808// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81809// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 41810// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81811// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 41812// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81813// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41814// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])1815// CHECK5-NEXT: ret void1816//1817//1818// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor1819// CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {1820// CHECK5-NEXT: entry:1821// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 81822// CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 81823// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1824// CHECK5: arraydestroy.body:1825// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1826// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11827// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1828// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr1829// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]1830// CHECK5: arraydestroy.done1:1831// CHECK5-NEXT: ret void1832//1833//1834// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.21835// CHECK5-SAME: () #[[ATTR0]] {1836// CHECK5-NEXT: entry:1837// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)1838// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]1839// CHECK5-NEXT: ret void1840//1841//1842// CHECK5-LABEL: define {{[^@]+}}@main1843// CHECK5-SAME: () #[[ATTR3:[0-9]+]] {1844// CHECK5-NEXT: entry:1845// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 41846// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 41847// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41848// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41849// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41850// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 41851// CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 41852// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41853// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 41854// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41855// CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 41856// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1857// CHECK5: omp.inner.for.cond:1858// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]1859// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]1860// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]1861// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1862// CHECK5: omp.inner.for.body:1863// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]1864// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 11865// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1866// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]1867// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr @t_var, align 4, !llvm.access.group [[ACC_GRP2]]1868// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]1869// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i641870// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, i64 0, i64 [[IDXPROM]]1871// CHECK5-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]]1872// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]1873// CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i641874// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i64 0, i64 [[IDXPROM1]]1875// CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 @var, i64 4, i1 false), !llvm.access.group [[ACC_GRP2]]1876// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]1877// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]]1878// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]]1879// CHECK5-NEXT: store i32 [[ADD3]], ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]]1880// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1881// CHECK5: omp.body.continue:1882// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1883// CHECK5: omp.inner.for.inc:1884// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]1885// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 11886// CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]1887// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]1888// CHECK5: omp.inner.for.end:1889// CHECK5-NEXT: store i32 2, ptr [[I]], align 41890// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()1891// CHECK5-NEXT: ret i32 [[CALL]]1892//1893//1894// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v1895// CHECK5-SAME: () #[[ATTR1]] comdat {1896// CHECK5-NEXT: entry:1897// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 41898// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41899// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 41900// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 41901// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 41902// CHECK5-NEXT: [[VAR:%.*]] = alloca ptr, align 81903// CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 81904// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 41905// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41906// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41907// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41908// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 41909// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])1910// CHECK5-NEXT: store i32 0, ptr [[T_VAR]], align 41911// CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)1912// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1)1913// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 11914// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)1915// CHECK5-NEXT: store ptr [[TEST]], ptr [[VAR]], align 81916// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]1917// CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 81918// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META6]], !align [[META7]]1919// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META6]], !align [[META7]]1920// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41921// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 41922// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41923// CHECK5-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 41924// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1925// CHECK5: omp.inner.for.cond:1926// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]]1927// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]]1928// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]1929// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1930// CHECK5: omp.inner.for.body:1931// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]1932// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 11933// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1934// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]1935// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP8]]1936// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]1937// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP8]] to i641938// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]1939// CHECK5-NEXT: store i32 [[TMP7]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]]1940// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META6]], !align [[META7]], !llvm.access.group [[ACC_GRP8]]1941// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]1942// CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i641943// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]]1944// CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[TMP9]], i64 4, i1 false), !llvm.access.group [[ACC_GRP8]]1945// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1946// CHECK5: omp.body.continue:1947// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1948// CHECK5: omp.inner.for.inc:1949// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]1950// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 11951// CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]1952// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]1953// CHECK5: omp.inner.for.end:1954// CHECK5-NEXT: store i32 2, ptr [[I]], align 41955// CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 41956// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01957// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 21958// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1959// CHECK5: arraydestroy.body:1960// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1961// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11962// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1963// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]1964// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]1965// CHECK5: arraydestroy.done5:1966// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]1967// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[RETVAL]], align 41968// CHECK5-NEXT: ret i32 [[TMP13]]1969//1970//1971// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev1972// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1973// CHECK5-NEXT: entry:1974// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81975// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81976// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81977// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01978// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 41979// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float1980// CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 41981// CHECK5-NEXT: ret void1982//1983//1984// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev1985// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1986// CHECK5-NEXT: entry:1987// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81988// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81989// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81990// CHECK5-NEXT: ret void1991//1992//1993// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef1994// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1995// CHECK5-NEXT: entry:1996// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81997// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 41998// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81999// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 42000// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82001// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02002// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42003// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 42004// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float2005// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]2006// CHECK5-NEXT: store float [[ADD]], ptr [[F]], align 42007// CHECK5-NEXT: ret void2008//2009//2010// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev2011// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2012// CHECK5-NEXT: entry:2013// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82014// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82015// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82016// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])2017// CHECK5-NEXT: ret void2018//2019//2020// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei2021// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2022// CHECK5-NEXT: entry:2023// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82024// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42025// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82026// CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42027// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82028// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42029// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])2030// CHECK5-NEXT: ret void2031//2032//2033// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev2034// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2035// CHECK5-NEXT: entry:2036// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82037// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82038// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82039// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]2040// CHECK5-NEXT: ret void2041//2042//2043// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev2044// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2045// CHECK5-NEXT: entry:2046// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82047// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82048// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82049// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 02050// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 42051// CHECK5-NEXT: store i32 [[TMP0]], ptr [[F]], align 42052// CHECK5-NEXT: ret void2053//2054//2055// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei2056// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2057// CHECK5-NEXT: entry:2058// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82059// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42060// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82061// CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42062// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82063// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 02064// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42065// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 42066// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]2067// CHECK5-NEXT: store i32 [[ADD]], ptr [[F]], align 42068// CHECK5-NEXT: ret void2069//2070//2071// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev2072// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2073// CHECK5-NEXT: entry:2074// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82075// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82076// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82077// CHECK5-NEXT: ret void2078//2079//2080// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp2081// CHECK5-SAME: () #[[ATTR0]] {2082// CHECK5-NEXT: entry:2083// CHECK5-NEXT: call void @__cxx_global_var_init()2084// CHECK5-NEXT: call void @__cxx_global_var_init.1()2085// CHECK5-NEXT: call void @__cxx_global_var_init.2()2086// CHECK5-NEXT: ret void2087//2088//2089// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init2090// CHECK7-SAME: () #[[ATTR0:[0-9]+]] {2091// CHECK7-NEXT: entry:2092// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)2093// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]2094// CHECK7-NEXT: ret void2095//2096//2097// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev2098// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {2099// CHECK7-NEXT: entry:2100// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42101// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42102// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42103// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])2104// CHECK7-NEXT: ret void2105//2106//2107// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev2108// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2109// CHECK7-NEXT: entry:2110// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42111// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42112// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42113// CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]2114// CHECK7-NEXT: ret void2115//2116//2117// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.12118// CHECK7-SAME: () #[[ATTR0]] {2119// CHECK7-NEXT: entry:2120// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)2121// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00)2122// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]2123// CHECK7-NEXT: ret void2124//2125//2126// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef2127// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2128// CHECK7-NEXT: entry:2129// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42130// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 42131// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42132// CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 42133// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42134// CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42135// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])2136// CHECK7-NEXT: ret void2137//2138//2139// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor2140// CHECK7-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {2141// CHECK7-NEXT: entry:2142// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 42143// CHECK7-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 42144// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]2145// CHECK7: arraydestroy.body:2146// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2147// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -12148// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]2149// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr2150// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]2151// CHECK7: arraydestroy.done1:2152// CHECK7-NEXT: ret void2153//2154//2155// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.22156// CHECK7-SAME: () #[[ATTR0]] {2157// CHECK7-NEXT: entry:2158// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)2159// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]2160// CHECK7-NEXT: ret void2161//2162//2163// CHECK7-LABEL: define {{[^@]+}}@main2164// CHECK7-SAME: () #[[ATTR3:[0-9]+]] {2165// CHECK7-NEXT: entry:2166// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 42167// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 42168// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42169// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42170// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42171// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 42172// CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 42173// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42174// CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 42175// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42176// CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 42177// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2178// CHECK7: omp.inner.for.cond:2179// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]2180// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]]2181// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]2182// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2183// CHECK7: omp.inner.for.body:2184// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]2185// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 12186// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2187// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]2188// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr @t_var, align 4, !llvm.access.group [[ACC_GRP3]]2189// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]2190// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, i32 0, i32 [[TMP5]]2191// CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]]2192// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]2193// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i32 0, i32 [[TMP6]]2194// CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 @var, i32 4, i1 false), !llvm.access.group [[ACC_GRP3]]2195// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]2196// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP3]]2197// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], [[TMP7]]2198// CHECK7-NEXT: store i32 [[ADD2]], ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP3]]2199// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2200// CHECK7: omp.body.continue:2201// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2202// CHECK7: omp.inner.for.inc:2203// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]2204// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 12205// CHECK7-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]2206// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]2207// CHECK7: omp.inner.for.end:2208// CHECK7-NEXT: store i32 2, ptr [[I]], align 42209// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()2210// CHECK7-NEXT: ret i32 [[CALL]]2211//2212//2213// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v2214// CHECK7-SAME: () #[[ATTR1]] comdat {2215// CHECK7-NEXT: entry:2216// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 42217// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 42218// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 42219// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 42220// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 42221// CHECK7-NEXT: [[VAR:%.*]] = alloca ptr, align 42222// CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 42223// CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 42224// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42225// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42226// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42227// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 42228// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])2229// CHECK7-NEXT: store i32 0, ptr [[T_VAR]], align 42230// CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)2231// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)2232// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 12233// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)2234// CHECK7-NEXT: store ptr [[TEST]], ptr [[VAR]], align 42235// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]]2236// CHECK7-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 42237// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META7]], !align [[META8]]2238// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META7]], !align [[META8]]2239// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42240// CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 42241// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42242// CHECK7-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 42243// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2244// CHECK7: omp.inner.for.cond:2245// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]]2246// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]]2247// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]2248// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2249// CHECK7: omp.inner.for.body:2250// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]2251// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 12252// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2253// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]2254// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP9]]2255// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]2256// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP8]]2257// CHECK7-NEXT: store i32 [[TMP7]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]]2258// CHECK7-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP9]]2259// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]2260// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP10]]2261// CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[TMP9]], i32 4, i1 false), !llvm.access.group [[ACC_GRP9]]2262// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2263// CHECK7: omp.body.continue:2264// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2265// CHECK7: omp.inner.for.inc:2266// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]2267// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 12268// CHECK7-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]2269// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]2270// CHECK7: omp.inner.for.end:2271// CHECK7-NEXT: store i32 2, ptr [[I]], align 42272// CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 42273// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 02274// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 22275// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]2276// CHECK7: arraydestroy.body:2277// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2278// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -12279// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]2280// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]2281// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]]2282// CHECK7: arraydestroy.done4:2283// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]2284// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[RETVAL]], align 42285// CHECK7-NEXT: ret i32 [[TMP13]]2286//2287//2288// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev2289// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2290// CHECK7-NEXT: entry:2291// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42292// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42293// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42294// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02295// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 42296// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float2297// CHECK7-NEXT: store float [[CONV]], ptr [[F]], align 42298// CHECK7-NEXT: ret void2299//2300//2301// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev2302// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2303// CHECK7-NEXT: entry:2304// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42305// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42306// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42307// CHECK7-NEXT: ret void2308//2309//2310// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef2311// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2312// CHECK7-NEXT: entry:2313// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42314// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 42315// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42316// CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 42317// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42318// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02319// CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42320// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 42321// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float2322// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]2323// CHECK7-NEXT: store float [[ADD]], ptr [[F]], align 42324// CHECK7-NEXT: ret void2325//2326//2327// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev2328// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2329// CHECK7-NEXT: entry:2330// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42331// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42332// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42333// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])2334// CHECK7-NEXT: ret void2335//2336//2337// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei2338// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2339// CHECK7-NEXT: entry:2340// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42341// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42342// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42343// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42344// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42345// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42346// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])2347// CHECK7-NEXT: ret void2348//2349//2350// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev2351// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2352// CHECK7-NEXT: entry:2353// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42354// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42355// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42356// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]2357// CHECK7-NEXT: ret void2358//2359//2360// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev2361// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2362// CHECK7-NEXT: entry:2363// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42364// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42365// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42366// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 02367// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 42368// CHECK7-NEXT: store i32 [[TMP0]], ptr [[F]], align 42369// CHECK7-NEXT: ret void2370//2371//2372// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei2373// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2374// CHECK7-NEXT: entry:2375// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42376// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42377// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42378// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42379// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42380// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 02381// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42382// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 42383// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]2384// CHECK7-NEXT: store i32 [[ADD]], ptr [[F]], align 42385// CHECK7-NEXT: ret void2386//2387//2388// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev2389// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2390// CHECK7-NEXT: entry:2391// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42392// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42393// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42394// CHECK7-NEXT: ret void2395//2396//2397// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp2398// CHECK7-SAME: () #[[ATTR0]] {2399// CHECK7-NEXT: entry:2400// CHECK7-NEXT: call void @__cxx_global_var_init()2401// CHECK7-NEXT: call void @__cxx_global_var_init.1()2402// CHECK7-NEXT: call void @__cxx_global_var_init.2()2403// CHECK7-NEXT: ret void2404//2405//2406// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init2407// CHECK9-SAME: () #[[ATTR0:[0-9]+]] {2408// CHECK9-NEXT: entry:2409// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)2410// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]2411// CHECK9-NEXT: ret void2412//2413//2414// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev2415// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {2416// CHECK9-NEXT: entry:2417// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82418// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82419// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82420// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])2421// CHECK9-NEXT: ret void2422//2423//2424// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev2425// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2426// CHECK9-NEXT: entry:2427// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82428// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82429// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82430// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]2431// CHECK9-NEXT: ret void2432//2433//2434// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev2435// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2436// CHECK9-NEXT: entry:2437// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82438// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82439// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82440// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02441// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 42442// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float2443// CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 42444// CHECK9-NEXT: ret void2445//2446//2447// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev2448// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2449// CHECK9-NEXT: entry:2450// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82451// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82452// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82453// CHECK9-NEXT: ret void2454//2455//2456// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.12457// CHECK9-SAME: () #[[ATTR0]] {2458// CHECK9-NEXT: entry:2459// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)2460// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)2461// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]2462// CHECK9-NEXT: ret void2463//2464//2465// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef2466// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2467// CHECK9-NEXT: entry:2468// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82469// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 42470// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82471// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 42472// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82473// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42474// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])2475// CHECK9-NEXT: ret void2476//2477//2478// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor2479// CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {2480// CHECK9-NEXT: entry:2481// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 82482// CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 82483// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]2484// CHECK9: arraydestroy.body:2485// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2486// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -12487// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]2488// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr2489// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]2490// CHECK9: arraydestroy.done1:2491// CHECK9-NEXT: ret void2492//2493//2494// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef2495// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2496// CHECK9-NEXT: entry:2497// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82498// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 42499// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82500// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 42501// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82502// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02503// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42504// CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 42505// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float2506// CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]2507// CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 42508// CHECK9-NEXT: ret void2509//2510//2511// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.22512// CHECK9-SAME: () #[[ATTR0]] {2513// CHECK9-NEXT: entry:2514// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)2515// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]2516// CHECK9-NEXT: ret void2517//2518//2519// CHECK9-LABEL: define {{[^@]+}}@main2520// CHECK9-SAME: () #[[ATTR3:[0-9]+]] {2521// CHECK9-NEXT: entry:2522// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 42523// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 12524// CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 42525// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])2526// CHECK9-NEXT: ret i32 02527//2528//2529// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l742530// CHECK9-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {2531// CHECK9-NEXT: entry:2532// CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 82533// CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 82534// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 82535// CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 82536// CHECK9-NEXT: [[G_CASTED:%.*]] = alloca i64, align 82537// CHECK9-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 82538// CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 82539// CHECK9-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 82540// CHECK9-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 82541// CHECK9-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 82542// CHECK9-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 82543// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[G_ADDR]], align 42544// CHECK9-NEXT: store i32 [[TMP0]], ptr [[G_CASTED]], align 42545// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 82546// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]2547// CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, ptr [[TMP2]], align 42548// CHECK9-NEXT: store i32 [[TMP3]], ptr [[G1_CASTED]], align 42549// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[G1_CASTED]], align 82550// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 42551// CHECK9-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 42552// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 82553// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined, i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])2554// CHECK9-NEXT: ret void2555//2556//2557// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined2558// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] {2559// CHECK9-NEXT: entry:2560// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82561// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82562// CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 82563// CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 82564// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 82565// CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 82566// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42567// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 42568// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42569// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42570// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42571// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42572// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 42573// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 82574// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82575// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82576// CHECK9-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 82577// CHECK9-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 82578// CHECK9-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 82579// CHECK9-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 82580// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42581// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 42582// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42583// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42584// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82585// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42586// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2587// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42588// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 12589// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2590// CHECK9: cond.true:2591// CHECK9-NEXT: br label [[COND_END:%.*]]2592// CHECK9: cond.false:2593// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42594// CHECK9-NEXT: br label [[COND_END]]2595// CHECK9: cond.end:2596// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2597// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 42598// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42599// CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42600// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2601// CHECK9: omp.inner.for.cond:2602// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]2603// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]]2604// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2605// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2606// CHECK9: omp.inner.for.body:2607// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]2608// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12609// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2610// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]2611// CHECK9-NEXT: store i32 1, ptr [[G_ADDR]], align 4, !llvm.access.group [[ACC_GRP7]]2612// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]], !llvm.access.group [[ACC_GRP7]]2613// CHECK9-NEXT: store volatile i32 1, ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP7]]2614// CHECK9-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP7]]2615// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 02616// CHECK9-NEXT: store ptr [[G_ADDR]], ptr [[TMP9]], align 8, !llvm.access.group [[ACC_GRP7]]2617// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 12618// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]], !llvm.access.group [[ACC_GRP7]]2619// CHECK9-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP7]]2620// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 22621// CHECK9-NEXT: store ptr [[SIVAR_ADDR]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP7]]2622// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group [[ACC_GRP7]]2623// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2624// CHECK9: omp.body.continue:2625// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2626// CHECK9: omp.inner.for.inc:2627// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]2628// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP13]], 12629// CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]2630// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]2631// CHECK9: omp.inner.for.end:2632// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2633// CHECK9: omp.loop.exit:2634// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2635// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42636// CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 02637// CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]2638// CHECK9: .omp.final.then:2639// CHECK9-NEXT: store i32 2, ptr [[I]], align 42640// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]2641// CHECK9: .omp.final.done:2642// CHECK9-NEXT: ret void2643//2644//2645// CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp2646// CHECK9-SAME: () #[[ATTR0]] {2647// CHECK9-NEXT: entry:2648// CHECK9-NEXT: call void @__cxx_global_var_init()2649// CHECK9-NEXT: call void @__cxx_global_var_init.1()2650// CHECK9-NEXT: call void @__cxx_global_var_init.2()2651// CHECK9-NEXT: ret void2652//2653//2654// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init2655// CHECK11-SAME: () #[[ATTR0:[0-9]+]] {2656// CHECK11-NEXT: entry:2657// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)2658// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]2659// CHECK11-NEXT: ret void2660//2661//2662// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev2663// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {2664// CHECK11-NEXT: entry:2665// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82666// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82667// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82668// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])2669// CHECK11-NEXT: ret void2670//2671//2672// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev2673// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2674// CHECK11-NEXT: entry:2675// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82676// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82677// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82678// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]2679// CHECK11-NEXT: ret void2680//2681//2682// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.12683// CHECK11-SAME: () #[[ATTR0]] {2684// CHECK11-NEXT: entry:2685// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)2686// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)2687// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]2688// CHECK11-NEXT: ret void2689//2690//2691// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef2692// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2693// CHECK11-NEXT: entry:2694// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82695// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 42696// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82697// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 42698// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82699// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42700// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])2701// CHECK11-NEXT: ret void2702//2703//2704// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor2705// CHECK11-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {2706// CHECK11-NEXT: entry:2707// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 82708// CHECK11-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 82709// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]2710// CHECK11: arraydestroy.body:2711// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2712// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -12713// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]2714// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr2715// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]2716// CHECK11: arraydestroy.done1:2717// CHECK11-NEXT: ret void2718//2719//2720// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.22721// CHECK11-SAME: () #[[ATTR0]] {2722// CHECK11-NEXT: entry:2723// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)2724// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]2725// CHECK11-NEXT: ret void2726//2727//2728// CHECK11-LABEL: define {{[^@]+}}@main2729// CHECK11-SAME: () #[[ATTR3:[0-9]+]] {2730// CHECK11-NEXT: entry:2731// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 42732// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 12733// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 42734// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])2735// CHECK11-NEXT: ret i32 02736//2737//2738// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev2739// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2740// CHECK11-NEXT: entry:2741// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82742// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82743// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82744// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02745// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 42746// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float2747// CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 42748// CHECK11-NEXT: ret void2749//2750//2751// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev2752// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2753// CHECK11-NEXT: entry:2754// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82755// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82756// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82757// CHECK11-NEXT: ret void2758//2759//2760// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef2761// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2762// CHECK11-NEXT: entry:2763// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82764// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 42765// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82766// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 42767// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82768// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02769// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42770// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 42771// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float2772// CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]2773// CHECK11-NEXT: store float [[ADD]], ptr [[F]], align 42774// CHECK11-NEXT: ret void2775//2776//2777// CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp2778// CHECK11-SAME: () #[[ATTR0]] {2779// CHECK11-NEXT: entry:2780// CHECK11-NEXT: call void @__cxx_global_var_init()2781// CHECK11-NEXT: call void @__cxx_global_var_init.1()2782// CHECK11-NEXT: call void @__cxx_global_var_init.2()2783// CHECK11-NEXT: ret void2784//2785