2307 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s4// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK36// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s7// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK38 9// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK510// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s11// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK512// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK713// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s14// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK715 16// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK917// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s18// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK919 20// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1121// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s22// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1123 24// expected-no-diagnostics25#ifndef HEADER26#define HEADER27 28struct St {29 int a, b;30 St() : a(0), b(0) {}31 St(const St &st) : a(st.a + st.b), b(0) {}32 ~St() {}33};34 35volatile int g = 1212;36volatile int &g1 = g;37 38template <class T>39struct S {40 T f;41 S(T a) : f(a + g) {}42 S() : f(g) {}43 S(const S &s, St t = St()) : f(s.f + t.a) {}44 operator T() { return T(); }45 ~S() {}46};47 48 49template <typename T>50T tmain() {51 S<T> test;52 T t_var = T();53 T vec[] = {1, 2};54 S<T> s_arr[] = {1, 2};55 S<T> &var = test;56#pragma omp target teams distribute simd private(t_var, vec, s_arr, var)57 for (int i = 0; i < 2; ++i) {58 vec[i] = t_var;59 s_arr[i] = var;60 }61 return T();62}63 64S<float> test;65int t_var = 333;66int vec[] = {1, 2};67S<float> s_arr[] = {1, 2};68S<float> var(3);69 70int main() {71 static int sivar;72#ifdef LAMBDA73 [&]() {74#pragma omp target teams distribute simd private(g, g1, sivar)75 for (int i = 0; i < 2; ++i) {76 77 // Skip global, bound tid and loop vars78 g = 1;79 g1 = 1;80 sivar = 2;81 [&]() {82 g = 2;83 g1 = 2;84 sivar = 4;85 86 }();87 }88 }();89 return 0;90#else91#pragma omp target teams distribute simd private(t_var, vec, s_arr, var, sivar)92 for (int i = 0; i < 2; ++i) {93 vec[i] = t_var;94 s_arr[i] = var;95 sivar += i;96 }97 return tmain<int>();98#endif99}100 101 102 103// Skip global, bound tid and loop vars104 105// private(s_arr)106 107// private(var)108 109 110 111 112 113// Skip global, bound tid and loop vars114 115// private(s_arr)116 117 118// private(var)119 120 121#endif122// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init123// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {124// CHECK1-NEXT: entry:125// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)126// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]127// CHECK1-NEXT: ret void128//129//130// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev131// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {132// CHECK1-NEXT: entry:133// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8134// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8135// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8136// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])137// CHECK1-NEXT: ret void138//139//140// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev141// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {142// CHECK1-NEXT: entry:143// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8144// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8145// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8146// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]147// CHECK1-NEXT: ret void148//149//150// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev151// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {152// CHECK1-NEXT: entry:153// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8154// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8155// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8156// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0157// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4158// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float159// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4160// CHECK1-NEXT: ret void161//162//163// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev164// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {165// CHECK1-NEXT: entry:166// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8167// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8168// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8169// CHECK1-NEXT: ret void170//171//172// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1173// CHECK1-SAME: () #[[ATTR0]] {174// CHECK1-NEXT: entry:175// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)176// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)177// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]178// CHECK1-NEXT: ret void179//180//181// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef182// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {183// CHECK1-NEXT: entry:184// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8185// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4186// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8187// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4188// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8189// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4190// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])191// CHECK1-NEXT: ret void192//193//194// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor195// CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {196// CHECK1-NEXT: entry:197// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8198// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8199// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]200// CHECK1: arraydestroy.body:201// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]202// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1203// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]204// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr205// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]206// CHECK1: arraydestroy.done1:207// CHECK1-NEXT: ret void208//209//210// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef211// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {212// CHECK1-NEXT: entry:213// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8214// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4215// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8216// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4217// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8218// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0219// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4220// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4221// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float222// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]223// CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4224// CHECK1-NEXT: ret void225//226//227// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2228// CHECK1-SAME: () #[[ATTR0]] {229// CHECK1-NEXT: entry:230// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)231// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]232// CHECK1-NEXT: ret void233//234//235// CHECK1-LABEL: define {{[^@]+}}@main236// CHECK1-SAME: () #[[ATTR3:[0-9]+]] {237// CHECK1-NEXT: entry:238// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4239// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4240// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8241// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4242// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0243// CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4244// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1245// CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4246// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2247// CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8248// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3249// CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8250// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4251// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8252// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5253// CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8254// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6255// CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8256// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7257// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8258// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8259// CHECK1-NEXT: store i64 2, ptr [[TMP8]], align 8260// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9261// CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8262// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10263// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4264// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11265// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP11]], align 4266// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12267// CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4268// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.region_id, ptr [[KERNEL_ARGS]])269// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0270// CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]271// CHECK1: omp_offload.failed:272// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]]273// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]274// CHECK1: omp_offload.cont:275// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()276// CHECK1-NEXT: ret i32 [[CALL]]277//278//279// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91280// CHECK1-SAME: () #[[ATTR4:[0-9]+]] {281// CHECK1-NEXT: entry:282// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.omp_outlined)283// CHECK1-NEXT: ret void284//285//286// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.omp_outlined287// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {288// CHECK1-NEXT: entry:289// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8290// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8291// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4292// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4293// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4294// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4295// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4296// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4297// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4298// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4299// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4300// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4301// CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4302// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4303// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8304// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8305// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4306// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4307// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4308// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4309// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0310// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2311// CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]312// CHECK1: arrayctor.loop:313// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]314// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])315// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1316// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]317// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]318// CHECK1: arrayctor.cont:319// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])320// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8321// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4322// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)323// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4324// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1325// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]326// CHECK1: cond.true:327// CHECK1-NEXT: br label [[COND_END:%.*]]328// CHECK1: cond.false:329// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4330// CHECK1-NEXT: br label [[COND_END]]331// CHECK1: cond.end:332// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]333// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4334// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4335// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4336// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]337// CHECK1: omp.inner.for.cond:338// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]339// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]]340// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]341// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]342// CHECK1: omp.inner.for.cond.cleanup:343// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]344// CHECK1: omp.inner.for.body:345// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]346// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1347// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]348// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]349// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP7]]350// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]351// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64352// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]353// CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]]354// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]355// CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64356// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]]357// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP7]]358// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]359// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP7]]360// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]361// CHECK1-NEXT: store i32 [[ADD4]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP7]]362// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]363// CHECK1: omp.body.continue:364// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]365// CHECK1: omp.inner.for.inc:366// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]367// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1368// CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]369// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]370// CHECK1: omp.inner.for.end:371// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]372// CHECK1: omp.loop.exit:373// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8374// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4375// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]])376// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4377// CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0378// CHECK1-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]379// CHECK1: .omp.final.then:380// CHECK1-NEXT: store i32 2, ptr [[I]], align 4381// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]382// CHECK1: .omp.final.done:383// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]384// CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0385// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 2386// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]387// CHECK1: arraydestroy.body:388// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]389// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1390// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]391// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]392// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]393// CHECK1: arraydestroy.done7:394// CHECK1-NEXT: ret void395//396//397// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v398// CHECK1-SAME: () #[[ATTR1]] comdat {399// CHECK1-NEXT: entry:400// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4401// CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4402// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4403// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4404// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4405// CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8406// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4407// CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8408// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8409// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])410// CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4411// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)412// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1)413// CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1414// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)415// CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8416// CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8417// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0418// CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4419// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1420// CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4421// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2422// CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8423// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3424// CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8425// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4426// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8427// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5428// CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8429// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6430// CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8431// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7432// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8433// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8434// CHECK1-NEXT: store i64 2, ptr [[TMP8]], align 8435// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9436// CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8437// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10438// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4439// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11440// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP11]], align 4441// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12442// CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4443// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])444// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0445// CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]446// CHECK1: omp_offload.failed:447// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]448// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]449// CHECK1: omp_offload.cont:450// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4451// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0452// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2453// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]454// CHECK1: arraydestroy.body:455// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]456// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1457// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]458// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]459// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]460// CHECK1: arraydestroy.done2:461// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]462// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4463// CHECK1-NEXT: ret i32 [[TMP16]]464//465//466// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev467// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {468// CHECK1-NEXT: entry:469// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8470// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8471// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8472// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])473// CHECK1-NEXT: ret void474//475//476// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei477// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {478// CHECK1-NEXT: entry:479// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8480// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4481// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8482// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4483// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8484// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4485// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])486// CHECK1-NEXT: ret void487//488//489// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56490// CHECK1-SAME: () #[[ATTR4]] {491// CHECK1-NEXT: entry:492// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined)493// CHECK1-NEXT: ret void494//495//496// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined497// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {498// CHECK1-NEXT: entry:499// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8500// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8501// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4502// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4503// CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8504// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4505// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4506// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4507// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4508// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4509// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4510// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4511// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4512// CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8513// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4514// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8515// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8516// CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8517// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4518// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4519// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4520// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4521// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0522// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2523// CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]524// CHECK1: arrayctor.loop:525// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]526// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])527// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1528// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]529// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]530// CHECK1: arrayctor.cont:531// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])532// CHECK1-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 8533// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8534// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4535// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)536// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4537// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1538// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]539// CHECK1: cond.true:540// CHECK1-NEXT: br label [[COND_END:%.*]]541// CHECK1: cond.false:542// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4543// CHECK1-NEXT: br label [[COND_END]]544// CHECK1: cond.end:545// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]546// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4547// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4548// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4549// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]550// CHECK1: omp.inner.for.cond:551// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]]552// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]]553// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]554// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]555// CHECK1: omp.inner.for.cond.cleanup:556// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]557// CHECK1: omp.inner.for.body:558// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]559// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1560// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]561// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]]562// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP13]]563// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]]564// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64565// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]566// CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]]567// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META14:![0-9]+]], !align [[META15:![0-9]+]], !llvm.access.group [[ACC_GRP13]]568// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]]569// CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64570// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]]571// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP13]]572// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]573// CHECK1: omp.body.continue:574// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]575// CHECK1: omp.inner.for.inc:576// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]577// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1578// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]579// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]580// CHECK1: omp.inner.for.end:581// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]582// CHECK1: omp.loop.exit:583// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8584// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4585// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]])586// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4587// CHECK1-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0588// CHECK1-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]589// CHECK1: .omp.final.then:590// CHECK1-NEXT: store i32 2, ptr [[I]], align 4591// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]592// CHECK1: .omp.final.done:593// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]594// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0595// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2596// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]597// CHECK1: arraydestroy.body:598// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]599// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1600// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]601// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]602// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]603// CHECK1: arraydestroy.done8:604// CHECK1-NEXT: ret void605//606//607// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev608// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {609// CHECK1-NEXT: entry:610// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8611// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8612// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8613// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]614// CHECK1-NEXT: ret void615//616//617// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev618// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {619// CHECK1-NEXT: entry:620// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8621// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8622// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8623// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0624// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4625// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4626// CHECK1-NEXT: ret void627//628//629// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei630// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {631// CHECK1-NEXT: entry:632// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8633// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4634// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8635// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4636// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8637// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0638// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4639// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4640// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]641// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4642// CHECK1-NEXT: ret void643//644//645// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev646// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {647// CHECK1-NEXT: entry:648// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8649// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8650// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8651// CHECK1-NEXT: ret void652//653//654// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp655// CHECK1-SAME: () #[[ATTR0]] {656// CHECK1-NEXT: entry:657// CHECK1-NEXT: call void @__cxx_global_var_init()658// CHECK1-NEXT: call void @__cxx_global_var_init.1()659// CHECK1-NEXT: call void @__cxx_global_var_init.2()660// CHECK1-NEXT: ret void661//662//663// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init664// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {665// CHECK3-NEXT: entry:666// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)667// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]668// CHECK3-NEXT: ret void669//670//671// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev672// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {673// CHECK3-NEXT: entry:674// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4675// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4676// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4677// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])678// CHECK3-NEXT: ret void679//680//681// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev682// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {683// CHECK3-NEXT: entry:684// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4685// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4686// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4687// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]688// CHECK3-NEXT: ret void689//690//691// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev692// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {693// CHECK3-NEXT: entry:694// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4695// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4696// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4697// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0698// CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4699// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float700// CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4701// CHECK3-NEXT: ret void702//703//704// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev705// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {706// CHECK3-NEXT: entry:707// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4708// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4709// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4710// CHECK3-NEXT: ret void711//712//713// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1714// CHECK3-SAME: () #[[ATTR0]] {715// CHECK3-NEXT: entry:716// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)717// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00)718// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]719// CHECK3-NEXT: ret void720//721//722// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef723// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {724// CHECK3-NEXT: entry:725// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4726// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4727// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4728// CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4729// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4730// CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4731// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])732// CHECK3-NEXT: ret void733//734//735// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor736// CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {737// CHECK3-NEXT: entry:738// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4739// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4740// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]741// CHECK3: arraydestroy.body:742// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]743// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1744// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]745// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr746// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]747// CHECK3: arraydestroy.done1:748// CHECK3-NEXT: ret void749//750//751// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef752// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {753// CHECK3-NEXT: entry:754// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4755// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4756// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4757// CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4758// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4759// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0760// CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4761// CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4762// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float763// CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]764// CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4765// CHECK3-NEXT: ret void766//767//768// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2769// CHECK3-SAME: () #[[ATTR0]] {770// CHECK3-NEXT: entry:771// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)772// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]773// CHECK3-NEXT: ret void774//775//776// CHECK3-LABEL: define {{[^@]+}}@main777// CHECK3-SAME: () #[[ATTR3:[0-9]+]] {778// CHECK3-NEXT: entry:779// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4780// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4781// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8782// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4783// CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0784// CHECK3-NEXT: store i32 3, ptr [[TMP0]], align 4785// CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1786// CHECK3-NEXT: store i32 0, ptr [[TMP1]], align 4787// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2788// CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4789// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3790// CHECK3-NEXT: store ptr null, ptr [[TMP3]], align 4791// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4792// CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4793// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5794// CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4795// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6796// CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4797// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7798// CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4799// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8800// CHECK3-NEXT: store i64 2, ptr [[TMP8]], align 8801// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9802// CHECK3-NEXT: store i64 0, ptr [[TMP9]], align 8803// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10804// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4805// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11806// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP11]], align 4807// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12808// CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4809// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.region_id, ptr [[KERNEL_ARGS]])810// CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0811// CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]812// CHECK3: omp_offload.failed:813// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]]814// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]815// CHECK3: omp_offload.cont:816// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()817// CHECK3-NEXT: ret i32 [[CALL]]818//819//820// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91821// CHECK3-SAME: () #[[ATTR4:[0-9]+]] {822// CHECK3-NEXT: entry:823// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.omp_outlined)824// CHECK3-NEXT: ret void825//826//827// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.omp_outlined828// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {829// CHECK3-NEXT: entry:830// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4831// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4832// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4833// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4834// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4835// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4836// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4837// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4838// CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4839// CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4840// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4841// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4842// CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4843// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4844// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4845// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4846// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4847// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4848// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4849// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4850// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0851// CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2852// CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]853// CHECK3: arrayctor.loop:854// CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]855// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])856// CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1857// CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]858// CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]859// CHECK3: arrayctor.cont:860// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])861// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4862// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4863// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)864// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4865// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1866// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]867// CHECK3: cond.true:868// CHECK3-NEXT: br label [[COND_END:%.*]]869// CHECK3: cond.false:870// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4871// CHECK3-NEXT: br label [[COND_END]]872// CHECK3: cond.end:873// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]874// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4875// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4876// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4877// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]878// CHECK3: omp.inner.for.cond:879// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]]880// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]]881// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]882// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]883// CHECK3: omp.inner.for.cond.cleanup:884// CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]885// CHECK3: omp.inner.for.body:886// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]887// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1888// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]889// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]890// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP8]]891// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]892// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]]893// CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]]894// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]895// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]]896// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP8]]897// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]898// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP8]]899// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]900// CHECK3-NEXT: store i32 [[ADD3]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP8]]901// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]902// CHECK3: omp.body.continue:903// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]904// CHECK3: omp.inner.for.inc:905// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]906// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1907// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]908// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]909// CHECK3: omp.inner.for.end:910// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]911// CHECK3: omp.loop.exit:912// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4913// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4914// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]])915// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4916// CHECK3-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0917// CHECK3-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]918// CHECK3: .omp.final.then:919// CHECK3-NEXT: store i32 2, ptr [[I]], align 4920// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]921// CHECK3: .omp.final.done:922// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]923// CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0924// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2925// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]926// CHECK3: arraydestroy.body:927// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]928// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1929// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]930// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]931// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]932// CHECK3: arraydestroy.done6:933// CHECK3-NEXT: ret void934//935//936// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v937// CHECK3-SAME: () #[[ATTR1]] comdat {938// CHECK3-NEXT: entry:939// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4940// CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4941// CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4942// CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4943// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4944// CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4945// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4946// CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4947// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8948// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])949// CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4950// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)951// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)952// CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1953// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)954// CHECK3-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4955// CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4956// CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0957// CHECK3-NEXT: store i32 3, ptr [[TMP0]], align 4958// CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1959// CHECK3-NEXT: store i32 0, ptr [[TMP1]], align 4960// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2961// CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4962// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3963// CHECK3-NEXT: store ptr null, ptr [[TMP3]], align 4964// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4965// CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4966// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5967// CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4968// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6969// CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4970// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7971// CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4972// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8973// CHECK3-NEXT: store i64 2, ptr [[TMP8]], align 8974// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9975// CHECK3-NEXT: store i64 0, ptr [[TMP9]], align 8976// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10977// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4978// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11979// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP11]], align 4980// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12981// CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4982// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])983// CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0984// CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]985// CHECK3: omp_offload.failed:986// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]987// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]988// CHECK3: omp_offload.cont:989// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4990// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0991// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2992// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]993// CHECK3: arraydestroy.body:994// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]995// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1996// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]997// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]998// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]999// CHECK3: arraydestroy.done2:1000// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]1001// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 41002// CHECK3-NEXT: ret i32 [[TMP16]]1003//1004//1005// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev1006// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1007// CHECK3-NEXT: entry:1008// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41009// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41010// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41011// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1012// CHECK3-NEXT: ret void1013//1014//1015// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei1016// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1017// CHECK3-NEXT: entry:1018// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41019// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 41020// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41021// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 41022// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41023// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41024// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])1025// CHECK3-NEXT: ret void1026//1027//1028// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l561029// CHECK3-SAME: () #[[ATTR4]] {1030// CHECK3-NEXT: entry:1031// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined)1032// CHECK3-NEXT: ret void1033//1034//1035// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined1036// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {1037// CHECK3-NEXT: entry:1038// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41039// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41040// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41041// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 41042// CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 41043// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41044// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41045// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41046// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41047// CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 41048// CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 41049// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 41050// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41051// CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 41052// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 41053// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41054// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41055// CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 41056// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41057// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 41058// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41059// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41060// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01061// CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 21062// CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]1063// CHECK3: arrayctor.loop:1064// CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]1065// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])1066// CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 11067// CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]1068// CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]1069// CHECK3: arrayctor.cont:1070// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])1071// CHECK3-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 41072// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41073// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41074// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1075// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41076// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 11077// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1078// CHECK3: cond.true:1079// CHECK3-NEXT: br label [[COND_END:%.*]]1080// CHECK3: cond.false:1081// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41082// CHECK3-NEXT: br label [[COND_END]]1083// CHECK3: cond.end:1084// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]1085// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41086// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41087// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 41088// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1089// CHECK3: omp.inner.for.cond:1090// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]]1091// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]]1092// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]1093// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1094// CHECK3: omp.inner.for.cond.cleanup:1095// CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]1096// CHECK3: omp.inner.for.body:1097// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]1098// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 11099// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1100// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]]1101// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP14]]1102// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]]1103// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]]1104// CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]]1105// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META15:![0-9]+]], !align [[META16:![0-9]+]], !llvm.access.group [[ACC_GRP14]]1106// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]]1107// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]]1108// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP14]]1109// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1110// CHECK3: omp.body.continue:1111// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1112// CHECK3: omp.inner.for.inc:1113// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]1114// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], 11115// CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]1116// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]1117// CHECK3: omp.inner.for.end:1118// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1119// CHECK3: omp.loop.exit:1120// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41121// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 41122// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]])1123// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41124// CHECK3-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 01125// CHECK3-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1126// CHECK3: .omp.final.then:1127// CHECK3-NEXT: store i32 2, ptr [[I]], align 41128// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]1129// CHECK3: .omp.final.done:1130// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]1131// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01132// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 21133// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1134// CHECK3: arraydestroy.body:1135// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1136// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11137// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1138// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]1139// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]1140// CHECK3: arraydestroy.done7:1141// CHECK3-NEXT: ret void1142//1143//1144// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev1145// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1146// CHECK3-NEXT: entry:1147// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41148// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41149// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41150// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]1151// CHECK3-NEXT: ret void1152//1153//1154// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev1155// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1156// CHECK3-NEXT: entry:1157// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41158// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41159// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41160// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01161// CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 41162// CHECK3-NEXT: store i32 [[TMP0]], ptr [[F]], align 41163// CHECK3-NEXT: ret void1164//1165//1166// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei1167// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1168// CHECK3-NEXT: entry:1169// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41170// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 41171// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41172// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 41173// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41174// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01175// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41176// CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 41177// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]1178// CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 41179// CHECK3-NEXT: ret void1180//1181//1182// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev1183// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1184// CHECK3-NEXT: entry:1185// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41186// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41187// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41188// CHECK3-NEXT: ret void1189//1190//1191// CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp1192// CHECK3-SAME: () #[[ATTR0]] {1193// CHECK3-NEXT: entry:1194// CHECK3-NEXT: call void @__cxx_global_var_init()1195// CHECK3-NEXT: call void @__cxx_global_var_init.1()1196// CHECK3-NEXT: call void @__cxx_global_var_init.2()1197// CHECK3-NEXT: ret void1198//1199//1200// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init1201// CHECK5-SAME: () #[[ATTR0:[0-9]+]] {1202// CHECK5-NEXT: entry:1203// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)1204// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]1205// CHECK5-NEXT: ret void1206//1207//1208// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev1209// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {1210// CHECK5-NEXT: entry:1211// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81212// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81213// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81214// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1215// CHECK5-NEXT: ret void1216//1217//1218// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev1219// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1220// CHECK5-NEXT: entry:1221// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81222// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81223// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81224// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]1225// CHECK5-NEXT: ret void1226//1227//1228// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.11229// CHECK5-SAME: () #[[ATTR0]] {1230// CHECK5-NEXT: entry:1231// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)1232// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)1233// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]1234// CHECK5-NEXT: ret void1235//1236//1237// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef1238// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1239// CHECK5-NEXT: entry:1240// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81241// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 41242// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81243// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 41244// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81245// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41246// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])1247// CHECK5-NEXT: ret void1248//1249//1250// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor1251// CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {1252// CHECK5-NEXT: entry:1253// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 81254// CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 81255// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1256// CHECK5: arraydestroy.body:1257// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1258// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11259// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1260// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr1261// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]1262// CHECK5: arraydestroy.done1:1263// CHECK5-NEXT: ret void1264//1265//1266// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.21267// CHECK5-SAME: () #[[ATTR0]] {1268// CHECK5-NEXT: entry:1269// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)1270// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]1271// CHECK5-NEXT: ret void1272//1273//1274// CHECK5-LABEL: define {{[^@]+}}@main1275// CHECK5-SAME: () #[[ATTR3:[0-9]+]] {1276// CHECK5-NEXT: entry:1277// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 41278// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 41279// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41280// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41281// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41282// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 41283// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 41284// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 41285// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 41286// CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 41287// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 41288// CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 41289// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41290// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 41291// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41292// CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 41293// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 01294// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 21295// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]1296// CHECK5: arrayctor.loop:1297// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]1298// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])1299// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 11300// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]1301// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]1302// CHECK5: arrayctor.cont:1303// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])1304// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1305// CHECK5: omp.inner.for.cond:1306// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]1307// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]1308// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]1309// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1310// CHECK5: omp.inner.for.cond.cleanup:1311// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]1312// CHECK5: omp.inner.for.body:1313// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]1314// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 11315// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1316// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]1317// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]]1318// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]1319// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i641320// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]1321// CHECK5-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]]1322// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]1323// CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i641324// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM1]]1325// CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]]1326// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]1327// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]]1328// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]]1329// CHECK5-NEXT: store i32 [[ADD3]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]]1330// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1331// CHECK5: omp.body.continue:1332// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1333// CHECK5: omp.inner.for.inc:1334// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]1335// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 11336// CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]1337// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]1338// CHECK5: omp.inner.for.end:1339// CHECK5-NEXT: store i32 2, ptr [[I]], align 41340// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]1341// CHECK5-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 01342// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i64 21343// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1344// CHECK5: arraydestroy.body:1345// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP10]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1346// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11347// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1348// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]1349// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]1350// CHECK5: arraydestroy.done6:1351// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()1352// CHECK5-NEXT: ret i32 [[CALL]]1353//1354//1355// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v1356// CHECK5-SAME: () #[[ATTR1]] comdat {1357// CHECK5-NEXT: entry:1358// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 41359// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41360// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 41361// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 41362// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 41363// CHECK5-NEXT: [[VAR:%.*]] = alloca ptr, align 81364// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 41365// CHECK5-NEXT: [[_TMP1:%.*]] = alloca ptr, align 81366// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41367// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41368// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41369// CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 41370// CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 41371// CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 41372// CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 41373// CHECK5-NEXT: [[_TMP6:%.*]] = alloca ptr, align 81374// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 41375// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])1376// CHECK5-NEXT: store i32 0, ptr [[T_VAR]], align 41377// CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)1378// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1)1379// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 11380// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)1381// CHECK5-NEXT: store ptr [[TEST]], ptr [[VAR]], align 81382// CHECK5-NEXT: store ptr undef, ptr [[_TMP1]], align 81383// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41384// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 41385// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41386// CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 41387// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 01388// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 21389// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]1390// CHECK5: arrayctor.loop:1391// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]1392// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])1393// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 11394// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]1395// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]1396// CHECK5: arrayctor.cont:1397// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]])1398// CHECK5-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 81399// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1400// CHECK5: omp.inner.for.cond:1401// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]1402// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]]1403// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]1404// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1405// CHECK5: omp.inner.for.cond.cleanup:1406// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]1407// CHECK5: omp.inner.for.body:1408// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]1409// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 11410// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1411// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]1412// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP6]]1413// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]1414// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i641415// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]]1416// CHECK5-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]]1417// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]], !llvm.access.group [[ACC_GRP6]]1418// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]1419// CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i641420// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]]1421// CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]]1422// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1423// CHECK5: omp.body.continue:1424// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1425// CHECK5: omp.inner.for.inc:1426// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]1427// CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP8]], 11428// CHECK5-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]1429// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]1430// CHECK5: omp.inner.for.end:1431// CHECK5-NEXT: store i32 2, ptr [[I]], align 41432// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]1433// CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 01434// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 21435// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1436// CHECK5: arraydestroy.body:1437// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1438// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11439// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1440// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]1441// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]1442// CHECK5: arraydestroy.done11:1443// CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 41444// CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01445// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 21446// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]]1447// CHECK5: arraydestroy.body13:1448// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ]1449// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST14]], i64 -11450// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]]1451// CHECK5-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]]1452// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]]1453// CHECK5: arraydestroy.done17:1454// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]1455// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 41456// CHECK5-NEXT: ret i32 [[TMP11]]1457//1458//1459// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev1460// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1461// CHECK5-NEXT: entry:1462// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81463// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81464// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81465// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01466// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 41467// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float1468// CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 41469// CHECK5-NEXT: ret void1470//1471//1472// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev1473// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1474// CHECK5-NEXT: entry:1475// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81476// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81477// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81478// CHECK5-NEXT: ret void1479//1480//1481// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef1482// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1483// CHECK5-NEXT: entry:1484// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81485// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 41486// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81487// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 41488// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81489// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01490// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41491// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 41492// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float1493// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]1494// CHECK5-NEXT: store float [[ADD]], ptr [[F]], align 41495// CHECK5-NEXT: ret void1496//1497//1498// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev1499// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1500// CHECK5-NEXT: entry:1501// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81502// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81503// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81504// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1505// CHECK5-NEXT: ret void1506//1507//1508// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei1509// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1510// CHECK5-NEXT: entry:1511// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81512// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 41513// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81514// CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 41515// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81516// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41517// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])1518// CHECK5-NEXT: ret void1519//1520//1521// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev1522// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1523// CHECK5-NEXT: entry:1524// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81525// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81526// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81527// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]1528// CHECK5-NEXT: ret void1529//1530//1531// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev1532// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1533// CHECK5-NEXT: entry:1534// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81535// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81536// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81537// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01538// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 41539// CHECK5-NEXT: store i32 [[TMP0]], ptr [[F]], align 41540// CHECK5-NEXT: ret void1541//1542//1543// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei1544// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1545// CHECK5-NEXT: entry:1546// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81547// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 41548// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81549// CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 41550// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81551// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01552// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41553// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 41554// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]1555// CHECK5-NEXT: store i32 [[ADD]], ptr [[F]], align 41556// CHECK5-NEXT: ret void1557//1558//1559// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev1560// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1561// CHECK5-NEXT: entry:1562// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81563// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81564// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81565// CHECK5-NEXT: ret void1566//1567//1568// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp1569// CHECK5-SAME: () #[[ATTR0]] {1570// CHECK5-NEXT: entry:1571// CHECK5-NEXT: call void @__cxx_global_var_init()1572// CHECK5-NEXT: call void @__cxx_global_var_init.1()1573// CHECK5-NEXT: call void @__cxx_global_var_init.2()1574// CHECK5-NEXT: ret void1575//1576//1577// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init1578// CHECK7-SAME: () #[[ATTR0:[0-9]+]] {1579// CHECK7-NEXT: entry:1580// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)1581// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]1582// CHECK7-NEXT: ret void1583//1584//1585// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev1586// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {1587// CHECK7-NEXT: entry:1588// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41589// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41590// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41591// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1592// CHECK7-NEXT: ret void1593//1594//1595// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev1596// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1597// CHECK7-NEXT: entry:1598// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41599// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41600// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41601// CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]1602// CHECK7-NEXT: ret void1603//1604//1605// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.11606// CHECK7-SAME: () #[[ATTR0]] {1607// CHECK7-NEXT: entry:1608// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)1609// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00)1610// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]1611// CHECK7-NEXT: ret void1612//1613//1614// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef1615// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1616// CHECK7-NEXT: entry:1617// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41618// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 41619// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41620// CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 41621// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41622// CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41623// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])1624// CHECK7-NEXT: ret void1625//1626//1627// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor1628// CHECK7-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {1629// CHECK7-NEXT: entry:1630// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 41631// CHECK7-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 41632// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1633// CHECK7: arraydestroy.body:1634// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1635// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11636// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1637// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr1638// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]1639// CHECK7: arraydestroy.done1:1640// CHECK7-NEXT: ret void1641//1642//1643// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.21644// CHECK7-SAME: () #[[ATTR0]] {1645// CHECK7-NEXT: entry:1646// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)1647// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]1648// CHECK7-NEXT: ret void1649//1650//1651// CHECK7-LABEL: define {{[^@]+}}@main1652// CHECK7-SAME: () #[[ATTR3:[0-9]+]] {1653// CHECK7-NEXT: entry:1654// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 41655// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 41656// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41657// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41658// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41659// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 41660// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 41661// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 41662// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 41663// CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 41664// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 41665// CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 41666// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41667// CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 41668// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41669// CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 41670// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 01671// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 21672// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]1673// CHECK7: arrayctor.loop:1674// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]1675// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])1676// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 11677// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]1678// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]1679// CHECK7: arrayctor.cont:1680// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])1681// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1682// CHECK7: omp.inner.for.cond:1683// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]1684// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]]1685// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]1686// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1687// CHECK7: omp.inner.for.cond.cleanup:1688// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]1689// CHECK7: omp.inner.for.body:1690// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]1691// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 11692// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1693// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]1694// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP3]]1695// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]1696// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP5]]1697// CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]]1698// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]1699// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP6]]1700// CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]]1701// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]1702// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]]1703// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], [[TMP7]]1704// CHECK7-NEXT: store i32 [[ADD2]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]]1705// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1706// CHECK7: omp.body.continue:1707// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1708// CHECK7: omp.inner.for.inc:1709// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]1710// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 11711// CHECK7-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]1712// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]1713// CHECK7: omp.inner.for.end:1714// CHECK7-NEXT: store i32 2, ptr [[I]], align 41715// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]1716// CHECK7-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 01717// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i32 21718// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1719// CHECK7: arraydestroy.body:1720// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP10]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1721// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11722// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1723// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]1724// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]1725// CHECK7: arraydestroy.done5:1726// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()1727// CHECK7-NEXT: ret i32 [[CALL]]1728//1729//1730// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v1731// CHECK7-SAME: () #[[ATTR1]] comdat {1732// CHECK7-NEXT: entry:1733// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 41734// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41735// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 41736// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 41737// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 41738// CHECK7-NEXT: [[VAR:%.*]] = alloca ptr, align 41739// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 41740// CHECK7-NEXT: [[_TMP1:%.*]] = alloca ptr, align 41741// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41742// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41743// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41744// CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 41745// CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 41746// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 41747// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 41748// CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 41749// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 41750// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])1751// CHECK7-NEXT: store i32 0, ptr [[T_VAR]], align 41752// CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)1753// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)1754// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 11755// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)1756// CHECK7-NEXT: store ptr [[TEST]], ptr [[VAR]], align 41757// CHECK7-NEXT: store ptr undef, ptr [[_TMP1]], align 41758// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41759// CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 41760// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41761// CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 41762// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 01763// CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 21764// CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]1765// CHECK7: arrayctor.loop:1766// CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]1767// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])1768// CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 11769// CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]1770// CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]1771// CHECK7: arrayctor.cont:1772// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]])1773// CHECK7-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 41774// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1775// CHECK7: omp.inner.for.cond:1776// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]1777// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]]1778// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]1779// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1780// CHECK7: omp.inner.for.cond.cleanup:1781// CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]1782// CHECK7: omp.inner.for.body:1783// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]1784// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 11785// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1786// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]1787// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP7]]1788// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]1789// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP5]]1790// CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]]1791// CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]], !llvm.access.group [[ACC_GRP7]]1792// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]1793// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP7]]1794// CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]]1795// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1796// CHECK7: omp.body.continue:1797// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1798// CHECK7: omp.inner.for.inc:1799// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]1800// CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 11801// CHECK7-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]1802// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]1803// CHECK7: omp.inner.for.end:1804// CHECK7-NEXT: store i32 2, ptr [[I]], align 41805// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]1806// CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 01807// CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 21808// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1809// CHECK7: arraydestroy.body:1810// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1811// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11812// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1813// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]1814// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]1815// CHECK7: arraydestroy.done10:1816// CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 41817// CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01818// CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 21819// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY12:%.*]]1820// CHECK7: arraydestroy.body12:1821// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ]1822// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST13]], i32 -11823// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]]1824// CHECK7-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]]1825// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]]1826// CHECK7: arraydestroy.done16:1827// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]1828// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 41829// CHECK7-NEXT: ret i32 [[TMP11]]1830//1831//1832// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev1833// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1834// CHECK7-NEXT: entry:1835// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41836// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41837// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41838// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01839// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 41840// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float1841// CHECK7-NEXT: store float [[CONV]], ptr [[F]], align 41842// CHECK7-NEXT: ret void1843//1844//1845// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev1846// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1847// CHECK7-NEXT: entry:1848// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41849// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41850// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41851// CHECK7-NEXT: ret void1852//1853//1854// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef1855// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1856// CHECK7-NEXT: entry:1857// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41858// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 41859// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41860// CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 41861// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41862// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01863// CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41864// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 41865// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float1866// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]1867// CHECK7-NEXT: store float [[ADD]], ptr [[F]], align 41868// CHECK7-NEXT: ret void1869//1870//1871// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev1872// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1873// CHECK7-NEXT: entry:1874// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41875// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41876// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41877// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1878// CHECK7-NEXT: ret void1879//1880//1881// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei1882// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1883// CHECK7-NEXT: entry:1884// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41885// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 41886// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41887// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 41888// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41889// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41890// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])1891// CHECK7-NEXT: ret void1892//1893//1894// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev1895// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1896// CHECK7-NEXT: entry:1897// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41898// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41899// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41900// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]1901// CHECK7-NEXT: ret void1902//1903//1904// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev1905// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1906// CHECK7-NEXT: entry:1907// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41908// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41909// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41910// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01911// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 41912// CHECK7-NEXT: store i32 [[TMP0]], ptr [[F]], align 41913// CHECK7-NEXT: ret void1914//1915//1916// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei1917// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1918// CHECK7-NEXT: entry:1919// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41920// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 41921// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41922// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 41923// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41924// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01925// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41926// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 41927// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]1928// CHECK7-NEXT: store i32 [[ADD]], ptr [[F]], align 41929// CHECK7-NEXT: ret void1930//1931//1932// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev1933// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1934// CHECK7-NEXT: entry:1935// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41936// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41937// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41938// CHECK7-NEXT: ret void1939//1940//1941// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp1942// CHECK7-SAME: () #[[ATTR0]] {1943// CHECK7-NEXT: entry:1944// CHECK7-NEXT: call void @__cxx_global_var_init()1945// CHECK7-NEXT: call void @__cxx_global_var_init.1()1946// CHECK7-NEXT: call void @__cxx_global_var_init.2()1947// CHECK7-NEXT: ret void1948//1949//1950// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init1951// CHECK9-SAME: () #[[ATTR0:[0-9]+]] {1952// CHECK9-NEXT: entry:1953// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)1954// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]1955// CHECK9-NEXT: ret void1956//1957//1958// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev1959// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {1960// CHECK9-NEXT: entry:1961// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81962// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81963// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81964// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1965// CHECK9-NEXT: ret void1966//1967//1968// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev1969// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1970// CHECK9-NEXT: entry:1971// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81972// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81973// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81974// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]1975// CHECK9-NEXT: ret void1976//1977//1978// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev1979// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1980// CHECK9-NEXT: entry:1981// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81982// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81983// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81984// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01985// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 41986// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float1987// CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 41988// CHECK9-NEXT: ret void1989//1990//1991// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev1992// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1993// CHECK9-NEXT: entry:1994// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81995// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81996// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81997// CHECK9-NEXT: ret void1998//1999//2000// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.12001// CHECK9-SAME: () #[[ATTR0]] {2002// CHECK9-NEXT: entry:2003// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)2004// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)2005// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]2006// CHECK9-NEXT: ret void2007//2008//2009// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef2010// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2011// CHECK9-NEXT: entry:2012// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82013// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 42014// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82015// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 42016// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82017// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42018// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])2019// CHECK9-NEXT: ret void2020//2021//2022// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor2023// CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {2024// CHECK9-NEXT: entry:2025// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 82026// CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 82027// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]2028// CHECK9: arraydestroy.body:2029// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2030// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -12031// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]2032// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr2033// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]2034// CHECK9: arraydestroy.done1:2035// CHECK9-NEXT: ret void2036//2037//2038// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef2039// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2040// CHECK9-NEXT: entry:2041// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82042// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 42043// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82044// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 42045// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82046// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02047// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42048// CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 42049// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float2050// CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]2051// CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 42052// CHECK9-NEXT: ret void2053//2054//2055// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.22056// CHECK9-SAME: () #[[ATTR0]] {2057// CHECK9-NEXT: entry:2058// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)2059// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]2060// CHECK9-NEXT: ret void2061//2062//2063// CHECK9-LABEL: define {{[^@]+}}@main2064// CHECK9-SAME: () #[[ATTR3:[0-9]+]] {2065// CHECK9-NEXT: entry:2066// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 42067// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 12068// CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 42069// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])2070// CHECK9-NEXT: ret i32 02071//2072//2073// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l742074// CHECK9-SAME: () #[[ATTR4:[0-9]+]] {2075// CHECK9-NEXT: entry:2076// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined)2077// CHECK9-NEXT: ret void2078//2079//2080// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined2081// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {2082// CHECK9-NEXT: entry:2083// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82084// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82085// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42086// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 42087// CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 82088// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42089// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42090// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42091// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42092// CHECK9-NEXT: [[G:%.*]] = alloca i32, align 42093// CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 42094// CHECK9-NEXT: [[_TMP2:%.*]] = alloca ptr, align 82095// CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 42096// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 42097// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 82098// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82099// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82100// CHECK9-NEXT: store ptr undef, ptr [[_TMP1]], align 82101// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42102// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 42103// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42104// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42105// CHECK9-NEXT: store ptr [[G1]], ptr [[_TMP2]], align 82106// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82107// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42108// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2109// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42110// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 12111// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2112// CHECK9: cond.true:2113// CHECK9-NEXT: br label [[COND_END:%.*]]2114// CHECK9: cond.false:2115// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42116// CHECK9-NEXT: br label [[COND_END]]2117// CHECK9: cond.end:2118// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2119// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 42120// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42121// CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42122// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2123// CHECK9: omp.inner.for.cond:2124// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]2125// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]]2126// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2127// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2128// CHECK9: omp.inner.for.body:2129// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]2130// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12131// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2132// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]2133// CHECK9-NEXT: store i32 1, ptr [[G]], align 4, !llvm.access.group [[ACC_GRP5]]2134// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]], !llvm.access.group [[ACC_GRP5]]2135// CHECK9-NEXT: store volatile i32 1, ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP5]]2136// CHECK9-NEXT: store i32 2, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP5]]2137// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 02138// CHECK9-NEXT: store ptr [[G]], ptr [[TMP9]], align 8, !llvm.access.group [[ACC_GRP5]]2139// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 12140// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META6]], !align [[META7]], !llvm.access.group [[ACC_GRP5]]2141// CHECK9-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP5]]2142// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 22143// CHECK9-NEXT: store ptr [[SIVAR]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP5]]2144// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group [[ACC_GRP5]]2145// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2146// CHECK9: omp.body.continue:2147// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2148// CHECK9: omp.inner.for.inc:2149// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]2150// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 12151// CHECK9-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]2152// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]2153// CHECK9: omp.inner.for.end:2154// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2155// CHECK9: omp.loop.exit:2156// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2157// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42158// CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 02159// CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]2160// CHECK9: .omp.final.then:2161// CHECK9-NEXT: store i32 2, ptr [[I]], align 42162// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]2163// CHECK9: .omp.final.done:2164// CHECK9-NEXT: ret void2165//2166//2167// CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp2168// CHECK9-SAME: () #[[ATTR0]] {2169// CHECK9-NEXT: entry:2170// CHECK9-NEXT: call void @__cxx_global_var_init()2171// CHECK9-NEXT: call void @__cxx_global_var_init.1()2172// CHECK9-NEXT: call void @__cxx_global_var_init.2()2173// CHECK9-NEXT: ret void2174//2175//2176// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init2177// CHECK11-SAME: () #[[ATTR0:[0-9]+]] {2178// CHECK11-NEXT: entry:2179// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)2180// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]2181// CHECK11-NEXT: ret void2182//2183//2184// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev2185// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {2186// CHECK11-NEXT: entry:2187// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82188// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82189// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82190// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])2191// CHECK11-NEXT: ret void2192//2193//2194// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev2195// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2196// CHECK11-NEXT: entry:2197// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82198// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82199// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82200// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]2201// CHECK11-NEXT: ret void2202//2203//2204// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.12205// CHECK11-SAME: () #[[ATTR0]] {2206// CHECK11-NEXT: entry:2207// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)2208// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)2209// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]2210// CHECK11-NEXT: ret void2211//2212//2213// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef2214// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2215// CHECK11-NEXT: entry:2216// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82217// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 42218// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82219// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 42220// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82221// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42222// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])2223// CHECK11-NEXT: ret void2224//2225//2226// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor2227// CHECK11-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {2228// CHECK11-NEXT: entry:2229// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 82230// CHECK11-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 82231// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]2232// CHECK11: arraydestroy.body:2233// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2234// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -12235// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]2236// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr2237// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]2238// CHECK11: arraydestroy.done1:2239// CHECK11-NEXT: ret void2240//2241//2242// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.22243// CHECK11-SAME: () #[[ATTR0]] {2244// CHECK11-NEXT: entry:2245// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)2246// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]2247// CHECK11-NEXT: ret void2248//2249//2250// CHECK11-LABEL: define {{[^@]+}}@main2251// CHECK11-SAME: () #[[ATTR3:[0-9]+]] {2252// CHECK11-NEXT: entry:2253// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 42254// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 12255// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 42256// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])2257// CHECK11-NEXT: ret i32 02258//2259//2260// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev2261// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2262// CHECK11-NEXT: entry:2263// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82264// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82265// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82266// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02267// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 42268// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float2269// CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 42270// CHECK11-NEXT: ret void2271//2272//2273// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev2274// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2275// CHECK11-NEXT: entry:2276// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82277// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82278// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82279// CHECK11-NEXT: ret void2280//2281//2282// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef2283// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2284// CHECK11-NEXT: entry:2285// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82286// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 42287// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82288// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 42289// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82290// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02291// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42292// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 42293// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float2294// CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]2295// CHECK11-NEXT: store float [[ADD]], ptr [[F]], align 42296// CHECK11-NEXT: ret void2297//2298//2299// CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp2300// CHECK11-SAME: () #[[ATTR0]] {2301// CHECK11-NEXT: entry:2302// CHECK11-NEXT: call void @__cxx_global_var_init()2303// CHECK11-NEXT: call void @__cxx_global_var_init.1()2304// CHECK11-NEXT: call void @__cxx_global_var_init.2()2305// CHECK11-NEXT: ret void2306//2307