2154 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s4// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK36// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s7// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK38 9// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK510// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s11// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK512 13// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"14// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s15// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"16// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"17// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s18// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"19 20// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"21// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s22// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"23 24// Test target codegen - host bc file has to be created first. (no significant differences with host version of target region)25// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc26// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1327// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s28// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1329// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc30// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1531// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s32// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1533 34// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc35// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1736 37// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc38// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"39// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s40// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"41// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc42// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"43// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s44// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"45// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc46// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"47 48// expected-no-diagnostics49#ifndef HEADER50#define HEADER51 52struct St {53 int a, b;54 St() : a(0), b(0) {}55 St(const St &st) : a(st.a + st.b), b(0) {}56 ~St() {}57};58 59volatile int g = 1212;60volatile int &g1 = g;61 62template <class T>63struct S {64 T f;65 S(T a) : f(a + g) {}66 S() : f(g) {}67 S(const S &s, St t = St()) : f(s.f + t.a) {}68 operator T() { return T(); }69 ~S() {}70};71 72 73template <typename T>74T tmain() {75 S<T> test;76 T t_var = T();77 T vec[] = {1, 2};78 S<T> s_arr[] = {1, 2};79 S<T> &var = test;80#pragma omp target teams loop private(t_var, vec, s_arr, var)81 for (int i = 0; i < 2; ++i) {82 vec[i] = t_var;83 s_arr[i] = var;84 }85 return T();86}87 88// HCHECK-DAG: [[TEST:@.+]] ={{.*}} global [[S_FLOAT_TY]] zeroinitializer,89S<float> test;90// HCHECK-DAG: [[T_VAR:@.+]] ={{.+}} global i{{[0-9]+}} 333,91int t_var = 333;92// HCHECK-DAG: [[VEC:@.+]] ={{.+}} global [2 x i{{[0-9]+}}] [i{{[0-9]+}} 1, i{{[0-9]+}} 2],93int vec[] = {1, 2};94// HCHECK-DAG: [[S_ARR:@.+]] ={{.+}} global [2 x [[S_FLOAT_TY]]] zeroinitializer,95S<float> s_arr[] = {1, 2};96// HCHECK-DAG: [[VAR:@.+]] ={{.+}} global [[S_FLOAT_TY]] zeroinitializer,97S<float> var(3);98// HCHECK-DAG: [[SIVAR:@.+]] = internal global i{{[0-9]+}} 0,99 100int main() {101 static int sivar;102#ifdef LAMBDA103 [&]() {104#pragma omp target teams loop private(g, g1, sivar)105 for (int i = 0; i < 2; ++i) {106 107 // Skip global, bound tid and loop vars108 109 g = 1;110 g1 = 1;111 sivar = 2;112 113 // Skip global, bound tid and loop vars114 [&]() {115 g = 2;116 g1 = 2;117 sivar = 4;118 119 }();120 }121 }();122 return 0;123#else124#pragma omp target teams loop private(t_var, vec, s_arr, var, sivar)125 for (int i = 0; i < 2; ++i) {126 vec[i] = t_var;127 s_arr[i] = var;128 sivar += i;129 }130 return tmain<int>();131#endif132}133 134// HCHECK: define {{.*}}i{{[0-9]+}} @main()135// HCHECK: call i32 @__tgt_target_teams_mapper(ptr @{{.+}}, i64 -1, ptr @{{[^,]+}}, i32 0, ptr null, ptr null, {{.+}} null, {{.+}} null, ptr null, ptr null, i32 0, i32 0)136// HCHECK: call void @[[OFFL1:.+]]()137// HCHECK: {{%.+}} = call{{.*}} i32 @[[TMAIN_INT:.+]]()138// HCHECK: ret139 140// HCHECK: define{{.*}} void @[[OFFL1]]()141 142// Skip global, bound tid and loop vars143 144// private(s_arr)145 146// private(var)147 148 149// Skip global, bound tid and loop vars150 151// private(s_arr)152 153// private(var)154 155 156// HCHECK: define{{.*}} i{{[0-9]+}} @[[TMAIN_INT]]()157// HCHECK: call i32 @__tgt_target_teams_mapper(ptr @{{.+}}, i64 -1, ptr @{{[^,]+}}, i32 0,158// HCHECK: call void @[[TOFFL1:.+]]()159// HCHECK: ret160 161// HCHECK: define {{.*}}void @[[TOFFL1]]()162 163// Skip global, bound tid and loop vars164 165// private(s_arr)166 167 168// private(var)169 170 171// Skip global, bound tid and loop vars172// prev lb and ub173// iter variables174 175// private(s_arr)176 177 178// private(var)179 180 181 182#endif183// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init184// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {185// CHECK1-NEXT: entry:186// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)187// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]188// CHECK1-NEXT: ret void189//190//191// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev192// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {193// CHECK1-NEXT: entry:194// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8195// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8196// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8197// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])198// CHECK1-NEXT: ret void199//200//201// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev202// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {203// CHECK1-NEXT: entry:204// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8205// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8206// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8207// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]208// CHECK1-NEXT: ret void209//210//211// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev212// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {213// CHECK1-NEXT: entry:214// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8215// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8216// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8217// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0218// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4219// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float220// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4221// CHECK1-NEXT: ret void222//223//224// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev225// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {226// CHECK1-NEXT: entry:227// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8228// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8229// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8230// CHECK1-NEXT: ret void231//232//233// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1234// CHECK1-SAME: () #[[ATTR0]] {235// CHECK1-NEXT: entry:236// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)237// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)238// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]239// CHECK1-NEXT: ret void240//241//242// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef243// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {244// CHECK1-NEXT: entry:245// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8246// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4247// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8248// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4249// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8250// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4251// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])252// CHECK1-NEXT: ret void253//254//255// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor256// CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {257// CHECK1-NEXT: entry:258// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8259// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8260// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]261// CHECK1: arraydestroy.body:262// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]263// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1264// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]265// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr266// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]267// CHECK1: arraydestroy.done1:268// CHECK1-NEXT: ret void269//270//271// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef272// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {273// CHECK1-NEXT: entry:274// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8275// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4276// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8277// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4278// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8279// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0280// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4281// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4282// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float283// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]284// CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4285// CHECK1-NEXT: ret void286//287//288// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2289// CHECK1-SAME: () #[[ATTR0]] {290// CHECK1-NEXT: entry:291// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)292// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]293// CHECK1-NEXT: ret void294//295//296// CHECK1-LABEL: define {{[^@]+}}@main297// CHECK1-SAME: () #[[ATTR3:[0-9]+]] {298// CHECK1-NEXT: entry:299// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4300// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4301// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8302// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4303// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0304// CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4305// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1306// CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4307// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2308// CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8309// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3310// CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8311// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4312// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8313// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5314// CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8315// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6316// CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8317// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7318// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8319// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8320// CHECK1-NEXT: store i64 2, ptr [[TMP8]], align 8321// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9322// CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8323// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10324// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4325// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11326// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4327// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12328// CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4329// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.region_id, ptr [[KERNEL_ARGS]])330// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0331// CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]332// CHECK1: omp_offload.failed:333// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124() #[[ATTR2]]334// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]335// CHECK1: omp_offload.cont:336// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()337// CHECK1-NEXT: ret i32 [[CALL]]338//339//340// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124341// CHECK1-SAME: () #[[ATTR4:[0-9]+]] {342// CHECK1-NEXT: entry:343// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined)344// CHECK1-NEXT: ret void345//346//347// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined348// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {349// CHECK1-NEXT: entry:350// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8351// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8352// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4353// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4354// CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4355// CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4356// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4357// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4358// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4359// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4360// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4361// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4362// CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4363// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4364// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8365// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8366// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4367// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4368// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4369// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4370// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0371// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2372// CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]373// CHECK1: arrayctor.loop:374// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]375// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])376// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1377// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]378// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]379// CHECK1: arrayctor.cont:380// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])381// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8382// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4383// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)384// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4385// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1386// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]387// CHECK1: cond.true:388// CHECK1-NEXT: br label [[COND_END:%.*]]389// CHECK1: cond.false:390// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4391// CHECK1-NEXT: br label [[COND_END]]392// CHECK1: cond.end:393// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]394// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4395// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4396// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4397// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]398// CHECK1: omp.inner.for.cond:399// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4400// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4401// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]402// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]403// CHECK1: omp.inner.for.cond.cleanup:404// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]405// CHECK1: omp.inner.for.body:406// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4407// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1408// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]409// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4410// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4411// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4412// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64413// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]414// CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4415// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4416// CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64417// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]]418// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false)419// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4420// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4421// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]422// CHECK1-NEXT: store i32 [[ADD4]], ptr [[SIVAR]], align 4423// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]424// CHECK1: omp.body.continue:425// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]426// CHECK1: omp.inner.for.inc:427// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4428// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1429// CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4430// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]431// CHECK1: omp.inner.for.end:432// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]433// CHECK1: omp.loop.exit:434// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8435// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4436// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]])437// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]438// CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0439// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 2440// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]441// CHECK1: arraydestroy.body:442// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]443// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1444// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]445// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]446// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]447// CHECK1: arraydestroy.done7:448// CHECK1-NEXT: ret void449//450//451// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v452// CHECK1-SAME: () #[[ATTR1]] comdat {453// CHECK1-NEXT: entry:454// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4455// CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4456// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4457// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4458// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4459// CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8460// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4461// CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8462// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8463// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])464// CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4465// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)466// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1)467// CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1468// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)469// CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8470// CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8471// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0472// CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4473// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1474// CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4475// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2476// CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8477// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3478// CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8479// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4480// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8481// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5482// CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8483// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6484// CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8485// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7486// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8487// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8488// CHECK1-NEXT: store i64 2, ptr [[TMP8]], align 8489// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9490// CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8491// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10492// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4493// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11494// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4495// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12496// CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4497// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.region_id, ptr [[KERNEL_ARGS]])498// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0499// CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]500// CHECK1: omp_offload.failed:501// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80() #[[ATTR2]]502// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]503// CHECK1: omp_offload.cont:504// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4505// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0506// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2507// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]508// CHECK1: arraydestroy.body:509// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]510// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1511// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]512// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]513// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]514// CHECK1: arraydestroy.done2:515// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]516// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4517// CHECK1-NEXT: ret i32 [[TMP16]]518//519//520// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev521// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {522// CHECK1-NEXT: entry:523// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8524// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8525// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8526// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])527// CHECK1-NEXT: ret void528//529//530// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei531// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {532// CHECK1-NEXT: entry:533// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8534// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4535// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8536// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4537// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8538// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4539// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])540// CHECK1-NEXT: ret void541//542//543// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80544// CHECK1-SAME: () #[[ATTR4]] {545// CHECK1-NEXT: entry:546// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined)547// CHECK1-NEXT: ret void548//549//550// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined551// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {552// CHECK1-NEXT: entry:553// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8554// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8555// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4556// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4557// CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8558// CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4559// CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4560// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4561// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4562// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4563// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4564// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4565// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4566// CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8567// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4568// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8569// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8570// CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8571// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4572// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4573// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4574// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4575// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0576// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2577// CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]578// CHECK1: arrayctor.loop:579// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]580// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])581// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1582// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]583// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]584// CHECK1: arrayctor.cont:585// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])586// CHECK1-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 8587// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8588// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4589// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)590// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4591// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1592// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]593// CHECK1: cond.true:594// CHECK1-NEXT: br label [[COND_END:%.*]]595// CHECK1: cond.false:596// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4597// CHECK1-NEXT: br label [[COND_END]]598// CHECK1: cond.end:599// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]600// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4601// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4602// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4603// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]604// CHECK1: omp.inner.for.cond:605// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4606// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4607// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]608// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]609// CHECK1: omp.inner.for.cond.cleanup:610// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]611// CHECK1: omp.inner.for.body:612// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4613// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1614// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]615// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4616// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4617// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4618// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64619// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]620// CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4621// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8622// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4623// CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64624// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]]625// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false)626// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]627// CHECK1: omp.body.continue:628// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]629// CHECK1: omp.inner.for.inc:630// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4631// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1632// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4633// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]634// CHECK1: omp.inner.for.end:635// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]636// CHECK1: omp.loop.exit:637// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8638// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4639// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]])640// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]641// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0642// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2643// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]644// CHECK1: arraydestroy.body:645// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]646// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1647// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]648// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]649// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]650// CHECK1: arraydestroy.done8:651// CHECK1-NEXT: ret void652//653//654// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev655// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {656// CHECK1-NEXT: entry:657// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8658// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8659// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8660// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]661// CHECK1-NEXT: ret void662//663//664// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev665// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {666// CHECK1-NEXT: entry:667// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8668// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8669// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8670// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0671// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4672// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4673// CHECK1-NEXT: ret void674//675//676// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei677// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {678// CHECK1-NEXT: entry:679// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8680// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4681// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8682// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4683// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8684// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0685// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4686// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4687// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]688// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4689// CHECK1-NEXT: ret void690//691//692// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev693// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {694// CHECK1-NEXT: entry:695// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8696// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8697// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8698// CHECK1-NEXT: ret void699//700//701// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_generic_loop_private_codegen.cpp702// CHECK1-SAME: () #[[ATTR0]] {703// CHECK1-NEXT: entry:704// CHECK1-NEXT: call void @__cxx_global_var_init()705// CHECK1-NEXT: call void @__cxx_global_var_init.1()706// CHECK1-NEXT: call void @__cxx_global_var_init.2()707// CHECK1-NEXT: ret void708//709//710// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init711// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {712// CHECK3-NEXT: entry:713// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)714// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]715// CHECK3-NEXT: ret void716//717//718// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev719// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {720// CHECK3-NEXT: entry:721// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4722// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4723// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4724// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])725// CHECK3-NEXT: ret void726//727//728// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev729// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {730// CHECK3-NEXT: entry:731// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4732// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4733// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4734// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]735// CHECK3-NEXT: ret void736//737//738// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev739// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {740// CHECK3-NEXT: entry:741// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4742// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4743// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4744// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0745// CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4746// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float747// CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4748// CHECK3-NEXT: ret void749//750//751// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev752// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {753// CHECK3-NEXT: entry:754// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4755// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4756// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4757// CHECK3-NEXT: ret void758//759//760// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1761// CHECK3-SAME: () #[[ATTR0]] {762// CHECK3-NEXT: entry:763// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)764// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00)765// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]766// CHECK3-NEXT: ret void767//768//769// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef770// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {771// CHECK3-NEXT: entry:772// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4773// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4774// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4775// CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4776// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4777// CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4778// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])779// CHECK3-NEXT: ret void780//781//782// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor783// CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {784// CHECK3-NEXT: entry:785// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4786// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4787// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]788// CHECK3: arraydestroy.body:789// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]790// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1791// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]792// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr793// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]794// CHECK3: arraydestroy.done1:795// CHECK3-NEXT: ret void796//797//798// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef799// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {800// CHECK3-NEXT: entry:801// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4802// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4803// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4804// CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4805// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4806// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0807// CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4808// CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4809// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float810// CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]811// CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4812// CHECK3-NEXT: ret void813//814//815// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2816// CHECK3-SAME: () #[[ATTR0]] {817// CHECK3-NEXT: entry:818// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)819// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]820// CHECK3-NEXT: ret void821//822//823// CHECK3-LABEL: define {{[^@]+}}@main824// CHECK3-SAME: () #[[ATTR3:[0-9]+]] {825// CHECK3-NEXT: entry:826// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4827// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4828// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8829// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4830// CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0831// CHECK3-NEXT: store i32 3, ptr [[TMP0]], align 4832// CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1833// CHECK3-NEXT: store i32 0, ptr [[TMP1]], align 4834// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2835// CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4836// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3837// CHECK3-NEXT: store ptr null, ptr [[TMP3]], align 4838// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4839// CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4840// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5841// CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4842// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6843// CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4844// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7845// CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4846// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8847// CHECK3-NEXT: store i64 2, ptr [[TMP8]], align 8848// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9849// CHECK3-NEXT: store i64 0, ptr [[TMP9]], align 8850// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10851// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4852// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11853// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4854// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12855// CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4856// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.region_id, ptr [[KERNEL_ARGS]])857// CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0858// CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]859// CHECK3: omp_offload.failed:860// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124() #[[ATTR2]]861// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]862// CHECK3: omp_offload.cont:863// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()864// CHECK3-NEXT: ret i32 [[CALL]]865//866//867// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124868// CHECK3-SAME: () #[[ATTR4:[0-9]+]] {869// CHECK3-NEXT: entry:870// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined)871// CHECK3-NEXT: ret void872//873//874// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined875// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {876// CHECK3-NEXT: entry:877// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4878// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4879// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4880// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4881// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4882// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4883// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4884// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4885// CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4886// CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4887// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4888// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4889// CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4890// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4891// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4892// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4893// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4894// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4895// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4896// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4897// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0898// CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2899// CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]900// CHECK3: arrayctor.loop:901// CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]902// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])903// CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1904// CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]905// CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]906// CHECK3: arrayctor.cont:907// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])908// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4909// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4910// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)911// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4912// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1913// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]914// CHECK3: cond.true:915// CHECK3-NEXT: br label [[COND_END:%.*]]916// CHECK3: cond.false:917// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4918// CHECK3-NEXT: br label [[COND_END]]919// CHECK3: cond.end:920// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]921// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4922// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4923// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4924// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]925// CHECK3: omp.inner.for.cond:926// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4927// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4928// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]929// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]930// CHECK3: omp.inner.for.cond.cleanup:931// CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]932// CHECK3: omp.inner.for.body:933// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4934// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1935// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]936// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4937// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4938// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4939// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]]940// CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4941// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4942// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]]943// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false)944// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4945// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4946// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]947// CHECK3-NEXT: store i32 [[ADD3]], ptr [[SIVAR]], align 4948// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]949// CHECK3: omp.body.continue:950// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]951// CHECK3: omp.inner.for.inc:952// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4953// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1954// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4955// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]956// CHECK3: omp.inner.for.end:957// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]958// CHECK3: omp.loop.exit:959// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4960// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4961// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]])962// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]963// CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0964// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2965// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]966// CHECK3: arraydestroy.body:967// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]968// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1969// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]970// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]971// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]972// CHECK3: arraydestroy.done6:973// CHECK3-NEXT: ret void974//975//976// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v977// CHECK3-SAME: () #[[ATTR1]] comdat {978// CHECK3-NEXT: entry:979// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4980// CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4981// CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4982// CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4983// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4984// CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4985// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4986// CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4987// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8988// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])989// CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4990// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)991// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)992// CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1993// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)994// CHECK3-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4995// CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4996// CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0997// CHECK3-NEXT: store i32 3, ptr [[TMP0]], align 4998// CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1999// CHECK3-NEXT: store i32 0, ptr [[TMP1]], align 41000// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21001// CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 41002// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31003// CHECK3-NEXT: store ptr null, ptr [[TMP3]], align 41004// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41005// CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 41006// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51007// CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 41008// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61009// CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 41010// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71011// CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 41012// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81013// CHECK3-NEXT: store i64 2, ptr [[TMP8]], align 81014// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91015// CHECK3-NEXT: store i64 0, ptr [[TMP9]], align 81016// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101017// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 41018// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111019// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 41020// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121021// CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 41022// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.region_id, ptr [[KERNEL_ARGS]])1023// CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 01024// CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1025// CHECK3: omp_offload.failed:1026// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80() #[[ATTR2]]1027// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]1028// CHECK3: omp_offload.cont:1029// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 41030// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01031// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 21032// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1033// CHECK3: arraydestroy.body:1034// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1035// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11036// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1037// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]1038// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]1039// CHECK3: arraydestroy.done2:1040// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]1041// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 41042// CHECK3-NEXT: ret i32 [[TMP16]]1043//1044//1045// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev1046// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1047// CHECK3-NEXT: entry:1048// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41049// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41050// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41051// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1052// CHECK3-NEXT: ret void1053//1054//1055// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei1056// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1057// CHECK3-NEXT: entry:1058// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41059// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 41060// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41061// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 41062// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41063// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41064// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])1065// CHECK3-NEXT: ret void1066//1067//1068// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l801069// CHECK3-SAME: () #[[ATTR4]] {1070// CHECK3-NEXT: entry:1071// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined)1072// CHECK3-NEXT: ret void1073//1074//1075// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined1076// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {1077// CHECK3-NEXT: entry:1078// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41079// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41080// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41081// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 41082// CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 41083// CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 41084// CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 41085// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41086// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41087// CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 41088// CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 41089// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 41090// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41091// CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 41092// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 41093// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41094// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41095// CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 41096// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 41097// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 41098// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41099// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41100// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01101// CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 21102// CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]1103// CHECK3: arrayctor.loop:1104// CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]1105// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])1106// CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 11107// CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]1108// CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]1109// CHECK3: arrayctor.cont:1110// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])1111// CHECK3-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 41112// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41113// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41114// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1115// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41116// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 11117// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1118// CHECK3: cond.true:1119// CHECK3-NEXT: br label [[COND_END:%.*]]1120// CHECK3: cond.false:1121// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41122// CHECK3-NEXT: br label [[COND_END]]1123// CHECK3: cond.end:1124// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]1125// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 41126// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 41127// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 41128// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1129// CHECK3: omp.inner.for.cond:1130// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41131// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41132// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]1133// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1134// CHECK3: omp.inner.for.cond.cleanup:1135// CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]1136// CHECK3: omp.inner.for.body:1137// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41138// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 11139// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1140// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 41141// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 41142// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 41143// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]]1144// CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 41145// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 41146// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 41147// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]]1148// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false)1149// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1150// CHECK3: omp.body.continue:1151// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1152// CHECK3: omp.inner.for.inc:1153// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41154// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], 11155// CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 41156// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]1157// CHECK3: omp.inner.for.end:1158// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1159// CHECK3: omp.loop.exit:1160// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41161// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 41162// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]])1163// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]1164// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01165// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 21166// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1167// CHECK3: arraydestroy.body:1168// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1169// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11170// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1171// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]1172// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]1173// CHECK3: arraydestroy.done7:1174// CHECK3-NEXT: ret void1175//1176//1177// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev1178// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1179// CHECK3-NEXT: entry:1180// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41181// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41182// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41183// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]1184// CHECK3-NEXT: ret void1185//1186//1187// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev1188// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1189// CHECK3-NEXT: entry:1190// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41191// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41192// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41193// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01194// CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 41195// CHECK3-NEXT: store i32 [[TMP0]], ptr [[F]], align 41196// CHECK3-NEXT: ret void1197//1198//1199// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei1200// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1201// CHECK3-NEXT: entry:1202// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41203// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 41204// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41205// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 41206// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41207// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01208// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41209// CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 41210// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]1211// CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 41212// CHECK3-NEXT: ret void1213//1214//1215// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev1216// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1217// CHECK3-NEXT: entry:1218// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41219// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41220// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41221// CHECK3-NEXT: ret void1222//1223//1224// CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_generic_loop_private_codegen.cpp1225// CHECK3-SAME: () #[[ATTR0]] {1226// CHECK3-NEXT: entry:1227// CHECK3-NEXT: call void @__cxx_global_var_init()1228// CHECK3-NEXT: call void @__cxx_global_var_init.1()1229// CHECK3-NEXT: call void @__cxx_global_var_init.2()1230// CHECK3-NEXT: ret void1231//1232//1233// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init1234// CHECK5-SAME: () #[[ATTR0:[0-9]+]] {1235// CHECK5-NEXT: entry:1236// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)1237// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]1238// CHECK5-NEXT: ret void1239//1240//1241// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev1242// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {1243// CHECK5-NEXT: entry:1244// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81245// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81246// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81247// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1248// CHECK5-NEXT: ret void1249//1250//1251// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev1252// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1253// CHECK5-NEXT: entry:1254// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81255// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81256// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81257// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]1258// CHECK5-NEXT: ret void1259//1260//1261// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev1262// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1263// CHECK5-NEXT: entry:1264// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81265// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81266// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81267// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01268// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 41269// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float1270// CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 41271// CHECK5-NEXT: ret void1272//1273//1274// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev1275// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1276// CHECK5-NEXT: entry:1277// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81278// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81279// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81280// CHECK5-NEXT: ret void1281//1282//1283// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.11284// CHECK5-SAME: () #[[ATTR0]] {1285// CHECK5-NEXT: entry:1286// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)1287// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)1288// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]1289// CHECK5-NEXT: ret void1290//1291//1292// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef1293// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1294// CHECK5-NEXT: entry:1295// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81296// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 41297// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81298// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 41299// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81300// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41301// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])1302// CHECK5-NEXT: ret void1303//1304//1305// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor1306// CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {1307// CHECK5-NEXT: entry:1308// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 81309// CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 81310// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1311// CHECK5: arraydestroy.body:1312// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1313// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11314// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1315// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr1316// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]1317// CHECK5: arraydestroy.done1:1318// CHECK5-NEXT: ret void1319//1320//1321// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef1322// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1323// CHECK5-NEXT: entry:1324// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81325// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 41326// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81327// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 41328// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81329// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01330// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41331// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 41332// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float1333// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]1334// CHECK5-NEXT: store float [[ADD]], ptr [[F]], align 41335// CHECK5-NEXT: ret void1336//1337//1338// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.21339// CHECK5-SAME: () #[[ATTR0]] {1340// CHECK5-NEXT: entry:1341// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)1342// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]1343// CHECK5-NEXT: ret void1344//1345//1346// CHECK5-LABEL: define {{[^@]+}}@main1347// CHECK5-SAME: () #[[ATTR3:[0-9]+]] {1348// CHECK5-NEXT: entry:1349// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 41350// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 11351// CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 41352// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])1353// CHECK5-NEXT: ret i32 01354//1355//1356// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l1041357// CHECK5-SAME: () #[[ATTR4:[0-9]+]] {1358// CHECK5-NEXT: entry:1359// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined)1360// CHECK5-NEXT: ret void1361//1362//1363// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined1364// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {1365// CHECK5-NEXT: entry:1366// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81367// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81368// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41369// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 41370// CHECK5-NEXT: [[_TMP1:%.*]] = alloca ptr, align 81371// CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 41372// CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 41373// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41374// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41375// CHECK5-NEXT: [[G:%.*]] = alloca i32, align 41376// CHECK5-NEXT: [[G1:%.*]] = alloca i32, align 41377// CHECK5-NEXT: [[_TMP2:%.*]] = alloca ptr, align 81378// CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 41379// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 41380// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 81381// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81382// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81383// CHECK5-NEXT: store ptr undef, ptr [[_TMP1]], align 81384// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 41385// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 41386// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41387// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41388// CHECK5-NEXT: store ptr [[G1]], ptr [[_TMP2]], align 81389// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81390// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41391// CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1392// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41393// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 11394// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1395// CHECK5: cond.true:1396// CHECK5-NEXT: br label [[COND_END:%.*]]1397// CHECK5: cond.false:1398// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41399// CHECK5-NEXT: br label [[COND_END]]1400// CHECK5: cond.end:1401// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]1402// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 41403// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 41404// CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 41405// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1406// CHECK5: omp.inner.for.cond:1407// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41408// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41409// CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]1410// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1411// CHECK5: omp.inner.for.body:1412// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41413// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 11414// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1415// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 41416// CHECK5-NEXT: store i32 1, ptr [[G]], align 41417// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 81418// CHECK5-NEXT: store volatile i32 1, ptr [[TMP8]], align 41419// CHECK5-NEXT: store i32 2, ptr [[SIVAR]], align 41420// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 01421// CHECK5-NEXT: store ptr [[G]], ptr [[TMP9]], align 81422// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 11423// CHECK5-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 81424// CHECK5-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 81425// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 21426// CHECK5-NEXT: store ptr [[SIVAR]], ptr [[TMP12]], align 81427// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]])1428// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1429// CHECK5: omp.body.continue:1430// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1431// CHECK5: omp.inner.for.inc:1432// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41433// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 11434// CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 41435// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]1436// CHECK5: omp.inner.for.end:1437// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1438// CHECK5: omp.loop.exit:1439// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])1440// CHECK5-NEXT: ret void1441//1442//1443// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_generic_loop_private_codegen.cpp1444// CHECK5-SAME: () #[[ATTR0]] {1445// CHECK5-NEXT: entry:1446// CHECK5-NEXT: call void @__cxx_global_var_init()1447// CHECK5-NEXT: call void @__cxx_global_var_init.1()1448// CHECK5-NEXT: call void @__cxx_global_var_init.2()1449// CHECK5-NEXT: ret void1450//1451//1452// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l1241453// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {1454// CHECK13-NEXT: entry:1455// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 81456// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 81457// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined)1458// CHECK13-NEXT: ret void1459//1460//1461// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined1462// CHECK13-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {1463// CHECK13-NEXT: entry:1464// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81465// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81466// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41467// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 41468// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 41469// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 41470// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41471// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41472// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 41473// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 41474// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 41475// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 41476// CHECK13-NEXT: [[SIVAR:%.*]] = alloca i32, align 41477// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 41478// CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81479// CHECK13-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81480// CHECK13-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 41481// CHECK13-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 41482// CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41483// CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41484// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 01485// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 21486// CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]1487// CHECK13: arrayctor.loop:1488// CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]1489// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])1490// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 11491// CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]1492// CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]1493// CHECK13: arrayctor.cont:1494// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])1495// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81496// CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41497// CHECK13-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1498// CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41499// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 11500// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1501// CHECK13: cond.true:1502// CHECK13-NEXT: br label [[COND_END:%.*]]1503// CHECK13: cond.false:1504// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41505// CHECK13-NEXT: br label [[COND_END]]1506// CHECK13: cond.end:1507// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]1508// CHECK13-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 41509// CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 41510// CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 41511// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1512// CHECK13: omp.inner.for.cond:1513// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41514// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41515// CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]1516// CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1517// CHECK13: omp.inner.for.cond.cleanup:1518// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]]1519// CHECK13: omp.inner.for.body:1520// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41521// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 11522// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1523// CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 41524// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 41525// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 41526// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i641527// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]1528// CHECK13-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 41529// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 41530// CHECK13-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i641531// CHECK13-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]]1532// CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false)1533// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 41534// CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 41535// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]1536// CHECK13-NEXT: store i32 [[ADD4]], ptr [[SIVAR]], align 41537// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1538// CHECK13: omp.body.continue:1539// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1540// CHECK13: omp.inner.for.inc:1541// CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41542// CHECK13-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 11543// CHECK13-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 41544// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]]1545// CHECK13: omp.inner.for.end:1546// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1547// CHECK13: omp.loop.exit:1548// CHECK13-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81549// CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 41550// CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]])1551// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2:[0-9]+]]1552// CHECK13-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 01553// CHECK13-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 21554// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1555// CHECK13: arraydestroy.body:1556// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1557// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11558// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1559// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]1560// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]1561// CHECK13: arraydestroy.done7:1562// CHECK13-NEXT: ret void1563//1564//1565// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev1566// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {1567// CHECK13-NEXT: entry:1568// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81569// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81570// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81571// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1572// CHECK13-NEXT: ret void1573//1574//1575// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev1576// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1577// CHECK13-NEXT: entry:1578// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81579// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81580// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81581// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]1582// CHECK13-NEXT: ret void1583//1584//1585// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l801586// CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {1587// CHECK13-NEXT: entry:1588// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 81589// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 81590// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined)1591// CHECK13-NEXT: ret void1592//1593//1594// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined1595// CHECK13-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {1596// CHECK13-NEXT: entry:1597// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81598// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81599// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41600// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 41601// CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 81602// CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 41603// CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 41604// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41605// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41606// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 41607// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 41608// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 41609// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41610// CHECK13-NEXT: [[_TMP2:%.*]] = alloca ptr, align 81611// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 41612// CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81613// CHECK13-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81614// CHECK13-NEXT: store ptr undef, ptr [[_TMP1]], align 81615// CHECK13-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 41616// CHECK13-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 41617// CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41618// CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41619// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01620// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 21621// CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]1622// CHECK13: arrayctor.loop:1623// CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]1624// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])1625// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 11626// CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]1627// CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]1628// CHECK13: arrayctor.cont:1629// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])1630// CHECK13-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 81631// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81632// CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41633// CHECK13-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1634// CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41635// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 11636// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1637// CHECK13: cond.true:1638// CHECK13-NEXT: br label [[COND_END:%.*]]1639// CHECK13: cond.false:1640// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41641// CHECK13-NEXT: br label [[COND_END]]1642// CHECK13: cond.end:1643// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]1644// CHECK13-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 41645// CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 41646// CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 41647// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1648// CHECK13: omp.inner.for.cond:1649// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41650// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41651// CHECK13-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]1652// CHECK13-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1653// CHECK13: omp.inner.for.cond.cleanup:1654// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]]1655// CHECK13: omp.inner.for.body:1656// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41657// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 11658// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1659// CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 41660// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 41661// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 41662// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i641663// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]1664// CHECK13-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 41665// CHECK13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 81666// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 41667// CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i641668// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]]1669// CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false)1670// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1671// CHECK13: omp.body.continue:1672// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1673// CHECK13: omp.inner.for.inc:1674// CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41675// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 11676// CHECK13-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 41677// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]]1678// CHECK13: omp.inner.for.end:1679// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1680// CHECK13: omp.loop.exit:1681// CHECK13-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81682// CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 41683// CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]])1684// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]1685// CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01686// CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 21687// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1688// CHECK13: arraydestroy.body:1689// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1690// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11691// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1692// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]1693// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]1694// CHECK13: arraydestroy.done8:1695// CHECK13-NEXT: ret void1696//1697//1698// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev1699// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1700// CHECK13-NEXT: entry:1701// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81702// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81703// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81704// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1705// CHECK13-NEXT: ret void1706//1707//1708// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev1709// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1710// CHECK13-NEXT: entry:1711// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81712// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81713// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81714// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]1715// CHECK13-NEXT: ret void1716//1717//1718// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev1719// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1720// CHECK13-NEXT: entry:1721// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81722// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81723// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81724// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01725// CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 41726// CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float1727// CHECK13-NEXT: store float [[CONV]], ptr [[F]], align 41728// CHECK13-NEXT: ret void1729//1730//1731// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev1732// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1733// CHECK13-NEXT: entry:1734// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81735// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81736// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81737// CHECK13-NEXT: ret void1738//1739//1740// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev1741// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1742// CHECK13-NEXT: entry:1743// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81744// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81745// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81746// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01747// CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 41748// CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 41749// CHECK13-NEXT: ret void1750//1751//1752// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev1753// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1754// CHECK13-NEXT: entry:1755// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81756// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81757// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81758// CHECK13-NEXT: ret void1759//1760//1761// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l1241762// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {1763// CHECK15-NEXT: entry:1764// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 41765// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 41766// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined)1767// CHECK15-NEXT: ret void1768//1769//1770// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined1771// CHECK15-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {1772// CHECK15-NEXT: entry:1773// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41774// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41775// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41776// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 41777// CHECK15-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 41778// CHECK15-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 41779// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41780// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41781// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 41782// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 41783// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 41784// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 41785// CHECK15-NEXT: [[SIVAR:%.*]] = alloca i32, align 41786// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 41787// CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41788// CHECK15-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41789// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 41790// CHECK15-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 41791// CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41792// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41793// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 01794// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 21795// CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]1796// CHECK15: arrayctor.loop:1797// CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]1798// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])1799// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 11800// CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]1801// CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]1802// CHECK15: arrayctor.cont:1803// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])1804// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41805// CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41806// CHECK15-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1807// CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41808// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 11809// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1810// CHECK15: cond.true:1811// CHECK15-NEXT: br label [[COND_END:%.*]]1812// CHECK15: cond.false:1813// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41814// CHECK15-NEXT: br label [[COND_END]]1815// CHECK15: cond.end:1816// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]1817// CHECK15-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 41818// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 41819// CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 41820// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1821// CHECK15: omp.inner.for.cond:1822// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41823// CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41824// CHECK15-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]1825// CHECK15-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1826// CHECK15: omp.inner.for.cond.cleanup:1827// CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]]1828// CHECK15: omp.inner.for.body:1829// CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41830// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 11831// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1832// CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 41833// CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 41834// CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 41835// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]]1836// CHECK15-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 41837// CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 41838// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]]1839// CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false)1840// CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 41841// CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 41842// CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]1843// CHECK15-NEXT: store i32 [[ADD3]], ptr [[SIVAR]], align 41844// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1845// CHECK15: omp.body.continue:1846// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1847// CHECK15: omp.inner.for.inc:1848// CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41849// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 11850// CHECK15-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 41851// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]]1852// CHECK15: omp.inner.for.end:1853// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1854// CHECK15: omp.loop.exit:1855// CHECK15-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41856// CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 41857// CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]])1858// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2:[0-9]+]]1859// CHECK15-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 01860// CHECK15-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 21861// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1862// CHECK15: arraydestroy.body:1863// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1864// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11865// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1866// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]1867// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]1868// CHECK15: arraydestroy.done6:1869// CHECK15-NEXT: ret void1870//1871//1872// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev1873// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {1874// CHECK15-NEXT: entry:1875// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41876// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41877// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41878// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1879// CHECK15-NEXT: ret void1880//1881//1882// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev1883// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1884// CHECK15-NEXT: entry:1885// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41886// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41887// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41888// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]1889// CHECK15-NEXT: ret void1890//1891//1892// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l801893// CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {1894// CHECK15-NEXT: entry:1895// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 41896// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 41897// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined)1898// CHECK15-NEXT: ret void1899//1900//1901// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined1902// CHECK15-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {1903// CHECK15-NEXT: entry:1904// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41905// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41906// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41907// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 41908// CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 41909// CHECK15-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 41910// CHECK15-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 41911// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41912// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41913// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 41914// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 41915// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 41916// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41917// CHECK15-NEXT: [[_TMP2:%.*]] = alloca ptr, align 41918// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 41919// CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41920// CHECK15-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41921// CHECK15-NEXT: store ptr undef, ptr [[_TMP1]], align 41922// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 41923// CHECK15-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 41924// CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41925// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41926// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01927// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 21928// CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]1929// CHECK15: arrayctor.loop:1930// CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]1931// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])1932// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 11933// CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]1934// CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]1935// CHECK15: arrayctor.cont:1936// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])1937// CHECK15-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 41938// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41939// CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41940// CHECK15-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1941// CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41942// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 11943// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1944// CHECK15: cond.true:1945// CHECK15-NEXT: br label [[COND_END:%.*]]1946// CHECK15: cond.false:1947// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41948// CHECK15-NEXT: br label [[COND_END]]1949// CHECK15: cond.end:1950// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]1951// CHECK15-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 41952// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 41953// CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 41954// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1955// CHECK15: omp.inner.for.cond:1956// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41957// CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41958// CHECK15-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]1959// CHECK15-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1960// CHECK15: omp.inner.for.cond.cleanup:1961// CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]]1962// CHECK15: omp.inner.for.body:1963// CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41964// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 11965// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1966// CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 41967// CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 41968// CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 41969// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]]1970// CHECK15-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 41971// CHECK15-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 41972// CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 41973// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]]1974// CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false)1975// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1976// CHECK15: omp.body.continue:1977// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1978// CHECK15: omp.inner.for.inc:1979// CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41980// CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], 11981// CHECK15-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 41982// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]]1983// CHECK15: omp.inner.for.end:1984// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1985// CHECK15: omp.loop.exit:1986// CHECK15-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41987// CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 41988// CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]])1989// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]1990// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01991// CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 21992// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1993// CHECK15: arraydestroy.body:1994// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1995// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11996// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1997// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]1998// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]1999// CHECK15: arraydestroy.done7:2000// CHECK15-NEXT: ret void2001//2002//2003// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev2004// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2005// CHECK15-NEXT: entry:2006// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42007// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42008// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42009// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])2010// CHECK15-NEXT: ret void2011//2012//2013// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev2014// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2015// CHECK15-NEXT: entry:2016// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42017// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42018// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42019// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]2020// CHECK15-NEXT: ret void2021//2022//2023// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev2024// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2025// CHECK15-NEXT: entry:2026// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42027// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42028// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42029// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02030// CHECK15-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 42031// CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float2032// CHECK15-NEXT: store float [[CONV]], ptr [[F]], align 42033// CHECK15-NEXT: ret void2034//2035//2036// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev2037// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2038// CHECK15-NEXT: entry:2039// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42040// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42041// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42042// CHECK15-NEXT: ret void2043//2044//2045// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev2046// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2047// CHECK15-NEXT: entry:2048// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42049// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42050// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42051// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 02052// CHECK15-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 42053// CHECK15-NEXT: store i32 [[TMP0]], ptr [[F]], align 42054// CHECK15-NEXT: ret void2055//2056//2057// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev2058// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2059// CHECK15-NEXT: entry:2060// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42061// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42062// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42063// CHECK15-NEXT: ret void2064//2065//2066// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l1042067// CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {2068// CHECK17-NEXT: entry:2069// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 82070// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 82071// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined)2072// CHECK17-NEXT: ret void2073//2074//2075// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined2076// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {2077// CHECK17-NEXT: entry:2078// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82079// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82080// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42081// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 42082// CHECK17-NEXT: [[_TMP1:%.*]] = alloca ptr, align 82083// CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 42084// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 42085// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42086// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42087// CHECK17-NEXT: [[G:%.*]] = alloca i32, align 42088// CHECK17-NEXT: [[G1:%.*]] = alloca i32, align 42089// CHECK17-NEXT: [[_TMP2:%.*]] = alloca ptr, align 82090// CHECK17-NEXT: [[SIVAR:%.*]] = alloca i32, align 42091// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 42092// CHECK17-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 82093// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82094// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82095// CHECK17-NEXT: store ptr undef, ptr [[_TMP1]], align 82096// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 42097// CHECK17-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 42098// CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42099// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42100// CHECK17-NEXT: store ptr [[G1]], ptr [[_TMP2]], align 82101// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82102// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42103// CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2104// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 42105// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 12106// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2107// CHECK17: cond.true:2108// CHECK17-NEXT: br label [[COND_END:%.*]]2109// CHECK17: cond.false:2110// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 42111// CHECK17-NEXT: br label [[COND_END]]2112// CHECK17: cond.end:2113// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2114// CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 42115// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 42116// CHECK17-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42117// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2118// CHECK17: omp.inner.for.cond:2119// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42120// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 42121// CHECK17-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2122// CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2123// CHECK17: omp.inner.for.body:2124// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42125// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12126// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2127// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 42128// CHECK17-NEXT: store i32 1, ptr [[G]], align 42129// CHECK17-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 82130// CHECK17-NEXT: store volatile i32 1, ptr [[TMP8]], align 42131// CHECK17-NEXT: store i32 2, ptr [[SIVAR]], align 42132// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 02133// CHECK17-NEXT: store ptr [[G]], ptr [[TMP9]], align 82134// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 12135// CHECK17-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 82136// CHECK17-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 82137// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 22138// CHECK17-NEXT: store ptr [[SIVAR]], ptr [[TMP12]], align 82139// CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]])2140// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2141// CHECK17: omp.body.continue:2142// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2143// CHECK17: omp.inner.for.inc:2144// CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42145// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 12146// CHECK17-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 42147// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]2148// CHECK17: omp.inner.for.end:2149// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2150// CHECK17: omp.loop.exit:2151// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2152// CHECK17-NEXT: ret void2153//2154