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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK13// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping4// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK15// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK36// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping7// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK38 9// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"10// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping11// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"12// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"13// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping14// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"15 16// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK917// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping18// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++  -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK919 20// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"21// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping22// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++  -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"23 24// expected-no-diagnostics25#ifndef HEADER26#define HEADER27 28struct St {29  int a, b;30  St() : a(0), b(0) {}31  St(const St &st) : a(st.a + st.b), b(0) {}32  ~St() {}33};34 35volatile int g = 1212;36volatile int &g1 = g;37 38template <class T>39struct S {40  T f;41  S(T a) : f(a + g) {}42  S() : f(g) {}43  S(const S &s, St t = St()) : f(s.f + t.a) {}44  operator T() { return T(); }45  ~S() {}46};47 48 49template <typename T>50T tmain() {51  S<T> test;52  T t_var = T();53  T vec[] = {1, 2};54  S<T> s_arr[] = {1, 2};55  S<T> &var = test;56#pragma omp target57#pragma omp teams distribute firstprivate(t_var, vec, s_arr, var)58  for (int i = 0; i < 2; ++i) {59    vec[i] = t_var;60    s_arr[i] = var;61  }62  return T();63}64 65S<float> test;66int t_var = 333;67int vec[] = {1, 2};68S<float> s_arr[] = {1, 2};69S<float> var(3);70 71int main() {72  static int sivar;73#ifdef LAMBDA74  [&]() {75#pragma omp target76#pragma omp teams distribute firstprivate(g, g1, sivar)77  for (int i = 0; i < 2; ++i) {78 79    // Skip global and bound tid vars80    // skip loop vars81    g = 1;82    g1 = 1;83    sivar = 2;84    [&]() {85      g = 2;86      g1 = 2;87      sivar = 4;88 89    }();90  }91  }();92  return 0;93#else94#pragma omp target95#pragma omp teams distribute firstprivate(t_var, vec, s_arr, var, sivar)96  for (int i = 0; i < 2; ++i) {97    vec[i] = t_var;98    s_arr[i] = var;99    sivar += i;100  }101  return tmain<int>();102#endif103}104 105 106 107 108 109// Skip global and bound tid vars110// Skip temp vars for loop111 112// param copy113 114// T_VAR and SIVAR115 116// preparation vars117 118// firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2119 120// firstprivate(s_arr)121 122// firstprivate(var)123 124 125 126 127 128 129// Skip global and bound tid vars130// Skip temp vars for loop131 132// param copy133 134 135// T_VAR and preparation variables136 137// firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2138 139// firstprivate(s_arr)140 141// firstprivate(var)142 143 144#endif145// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init146// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {147// CHECK1-NEXT:  entry:148// CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)149// CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]150// CHECK1-NEXT:    ret void151//152//153// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev154// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {155// CHECK1-NEXT:  entry:156// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8157// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8158// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8159// CHECK1-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])160// CHECK1-NEXT:    ret void161//162//163// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev164// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {165// CHECK1-NEXT:  entry:166// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8167// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8168// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8169// CHECK1-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]170// CHECK1-NEXT:    ret void171//172//173// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev174// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {175// CHECK1-NEXT:  entry:176// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8177// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8178// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8179// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0180// CHECK1-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4181// CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float182// CHECK1-NEXT:    store float [[CONV]], ptr [[F]], align 4183// CHECK1-NEXT:    ret void184//185//186// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev187// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {188// CHECK1-NEXT:  entry:189// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8190// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8191// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8192// CHECK1-NEXT:    ret void193//194//195// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1196// CHECK1-SAME: () #[[ATTR0]] {197// CHECK1-NEXT:  entry:198// CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)199// CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)200// CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]201// CHECK1-NEXT:    ret void202//203//204// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef205// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {206// CHECK1-NEXT:  entry:207// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8208// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4209// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8210// CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4211// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8212// CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4213// CHECK1-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])214// CHECK1-NEXT:    ret void215//216//217// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor218// CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {219// CHECK1-NEXT:  entry:220// CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8221// CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8222// CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]223// CHECK1:       arraydestroy.body:224// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]225// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1226// CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]227// CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr228// CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]229// CHECK1:       arraydestroy.done1:230// CHECK1-NEXT:    ret void231//232//233// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef234// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {235// CHECK1-NEXT:  entry:236// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8237// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4238// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8239// CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4240// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8241// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0242// CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4243// CHECK1-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4244// CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float245// CHECK1-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]246// CHECK1-NEXT:    store float [[ADD]], ptr [[F]], align 4247// CHECK1-NEXT:    ret void248//249//250// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2251// CHECK1-SAME: () #[[ATTR0]] {252// CHECK1-NEXT:  entry:253// CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)254// CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]255// CHECK1-NEXT:    ret void256//257//258// CHECK1-LABEL: define {{[^@]+}}@main259// CHECK1-SAME: () #[[ATTR3:[0-9]+]] {260// CHECK1-NEXT:  entry:261// CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4262// CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8263// CHECK1-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 8264// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8265// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8266// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8267// CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4268// CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8269// CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4270// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr @t_var, align 4271// CHECK1-NEXT:    store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4272// CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8273// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4274// CHECK1-NEXT:    store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4275// CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8276// CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0277// CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP4]], align 8278// CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0279// CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP5]], align 8280// CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0281// CHECK1-NEXT:    store ptr null, ptr [[TMP6]], align 8282// CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1283// CHECK1-NEXT:    store ptr @vec, ptr [[TMP7]], align 8284// CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1285// CHECK1-NEXT:    store ptr @vec, ptr [[TMP8]], align 8286// CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1287// CHECK1-NEXT:    store ptr null, ptr [[TMP9]], align 8288// CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2289// CHECK1-NEXT:    store ptr @s_arr, ptr [[TMP10]], align 8290// CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2291// CHECK1-NEXT:    store ptr @s_arr, ptr [[TMP11]], align 8292// CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2293// CHECK1-NEXT:    store ptr null, ptr [[TMP12]], align 8294// CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3295// CHECK1-NEXT:    store ptr @var, ptr [[TMP13]], align 8296// CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3297// CHECK1-NEXT:    store ptr @var, ptr [[TMP14]], align 8298// CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3299// CHECK1-NEXT:    store ptr null, ptr [[TMP15]], align 8300// CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4301// CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP16]], align 8302// CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4303// CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP17]], align 8304// CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4305// CHECK1-NEXT:    store ptr null, ptr [[TMP18]], align 8306// CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0307// CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0308// CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0309// CHECK1-NEXT:    store i32 3, ptr [[TMP21]], align 4310// CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1311// CHECK1-NEXT:    store i32 5, ptr [[TMP22]], align 4312// CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2313// CHECK1-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 8314// CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3315// CHECK1-NEXT:    store ptr [[TMP20]], ptr [[TMP24]], align 8316// CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4317// CHECK1-NEXT:    store ptr @.offload_sizes, ptr [[TMP25]], align 8318// CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5319// CHECK1-NEXT:    store ptr @.offload_maptypes, ptr [[TMP26]], align 8320// CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6321// CHECK1-NEXT:    store ptr null, ptr [[TMP27]], align 8322// CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7323// CHECK1-NEXT:    store ptr null, ptr [[TMP28]], align 8324// CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8325// CHECK1-NEXT:    store i64 2, ptr [[TMP29]], align 8326// CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9327// CHECK1-NEXT:    store i64 0, ptr [[TMP30]], align 8328// CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10329// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4330// CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11331// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4332// CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12333// CHECK1-NEXT:    store i32 0, ptr [[TMP33]], align 4334// CHECK1-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, ptr [[KERNEL_ARGS]])335// CHECK1-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0336// CHECK1-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]337// CHECK1:       omp_offload.failed:338// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i64 [[TMP1]], ptr @vec, ptr @s_arr, ptr @var, i64 [[TMP3]]) #[[ATTR2]]339// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]340// CHECK1:       omp_offload.cont:341// CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()342// CHECK1-NEXT:    ret i32 [[CALL]]343//344//345// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94346// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {347// CHECK1-NEXT:  entry:348// CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8349// CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8350// CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8351// CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8352// CHECK1-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8353// CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8354// CHECK1-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 8355// CHECK1-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8356// CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8357// CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8358// CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8359// CHECK1-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8360// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]]361// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]362// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]363// CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4364// CHECK1-NEXT:    store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4365// CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8366// CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4367// CHECK1-NEXT:    store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4368// CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8369// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i64 [[TMP6]])370// CHECK1-NEXT:    ret void371//372//373// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined374// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] {375// CHECK1-NEXT:  entry:376// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8377// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8378// CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8379// CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8380// CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8381// CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8382// CHECK1-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8383// CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4384// CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4385// CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4386// CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4387// CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4388// CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4389// CHECK1-NEXT:    [[VEC1:%.*]] = alloca [2 x i32], align 4390// CHECK1-NEXT:    [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4391// CHECK1-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4392// CHECK1-NEXT:    [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4393// CHECK1-NEXT:    [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4394// CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4395// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8396// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8397// CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8398// CHECK1-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8399// CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8400// CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8401// CHECK1-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8402// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]403// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]404// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]405// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4406// CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4407// CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4408// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4409// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false)410// CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0411// CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2412// CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]413// CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]414// CHECK1:       omp.arraycpy.body:415// CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]416// CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]417// CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])418// CHECK1-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])419// CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]420// CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1421// CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1422// CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]423// CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]424// CHECK1:       omp.arraycpy.done3:425// CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]])426// CHECK1-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]])427// CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]428// CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8429// CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4430// CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)431// CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4432// CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1433// CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]434// CHECK1:       cond.true:435// CHECK1-NEXT:    br label [[COND_END:%.*]]436// CHECK1:       cond.false:437// CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4438// CHECK1-NEXT:    br label [[COND_END]]439// CHECK1:       cond.end:440// CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]441// CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4442// CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4443// CHECK1-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4444// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]445// CHECK1:       omp.inner.for.cond:446// CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4447// CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4448// CHECK1-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]449// CHECK1-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]450// CHECK1:       omp.inner.for.cond.cleanup:451// CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]452// CHECK1:       omp.inner.for.body:453// CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4454// CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1455// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]456// CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4457// CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4458// CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4459// CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64460// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 [[IDXPROM]]461// CHECK1-NEXT:    store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4462// CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I]], align 4463// CHECK1-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64464// CHECK1-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i64 0, i64 [[IDXPROM7]]465// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[VAR4]], i64 4, i1 false)466// CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4467// CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4468// CHECK1-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]469// CHECK1-NEXT:    store i32 [[ADD9]], ptr [[SIVAR_ADDR]], align 4470// CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]471// CHECK1:       omp.body.continue:472// CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]473// CHECK1:       omp.inner.for.inc:474// CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4475// CHECK1-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP17]], 1476// CHECK1-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4477// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]478// CHECK1:       omp.inner.for.end:479// CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]480// CHECK1:       omp.loop.exit:481// CHECK1-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8482// CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4483// CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]])484// CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]485// CHECK1-NEXT:    [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0486// CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2487// CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]488// CHECK1:       arraydestroy.body:489// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]490// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1491// CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]492// CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]493// CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]494// CHECK1:       arraydestroy.done12:495// CHECK1-NEXT:    ret void496//497//498// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev499// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {500// CHECK1-NEXT:  entry:501// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8502// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8503// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8504// CHECK1-NEXT:    call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])505// CHECK1-NEXT:    ret void506//507//508// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St509// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {510// CHECK1-NEXT:  entry:511// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8512// CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8513// CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8514// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8515// CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8516// CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8517// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8518// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8519// CHECK1-NEXT:    call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])520// CHECK1-NEXT:    ret void521//522//523// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev524// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {525// CHECK1-NEXT:  entry:526// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8527// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8528// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8529// CHECK1-NEXT:    call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]530// CHECK1-NEXT:    ret void531//532//533// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v534// CHECK1-SAME: () #[[ATTR1]] comdat {535// CHECK1-NEXT:  entry:536// CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4537// CHECK1-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4538// CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4539// CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4540// CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4541// CHECK1-NEXT:    [[VAR:%.*]] = alloca ptr, align 8542// CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 8543// CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8544// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8545// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8546// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8547// CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4548// CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8549// CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])550// CHECK1-NEXT:    store i32 0, ptr [[T_VAR]], align 4551// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)552// CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1)553// CHECK1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1554// CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)555// CHECK1-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8556// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META7]], !align [[META8]]557// CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 8558// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4559// CHECK1-NEXT:    store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4560// CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8561// CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]562// CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]563// CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]564// CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0565// CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP6]], align 8566// CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0567// CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP7]], align 8568// CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0569// CHECK1-NEXT:    store ptr null, ptr [[TMP8]], align 8570// CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1571// CHECK1-NEXT:    store ptr [[VEC]], ptr [[TMP9]], align 8572// CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1573// CHECK1-NEXT:    store ptr [[VEC]], ptr [[TMP10]], align 8574// CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1575// CHECK1-NEXT:    store ptr null, ptr [[TMP11]], align 8576// CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2577// CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[TMP12]], align 8578// CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2579// CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[TMP13]], align 8580// CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2581// CHECK1-NEXT:    store ptr null, ptr [[TMP14]], align 8582// CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3583// CHECK1-NEXT:    store ptr [[TMP4]], ptr [[TMP15]], align 8584// CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3585// CHECK1-NEXT:    store ptr [[TMP5]], ptr [[TMP16]], align 8586// CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3587// CHECK1-NEXT:    store ptr null, ptr [[TMP17]], align 8588// CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0589// CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0590// CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0591// CHECK1-NEXT:    store i32 3, ptr [[TMP20]], align 4592// CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1593// CHECK1-NEXT:    store i32 4, ptr [[TMP21]], align 4594// CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2595// CHECK1-NEXT:    store ptr [[TMP18]], ptr [[TMP22]], align 8596// CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3597// CHECK1-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 8598// CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4599// CHECK1-NEXT:    store ptr @.offload_sizes.3, ptr [[TMP24]], align 8600// CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5601// CHECK1-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP25]], align 8602// CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6603// CHECK1-NEXT:    store ptr null, ptr [[TMP26]], align 8604// CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7605// CHECK1-NEXT:    store ptr null, ptr [[TMP27]], align 8606// CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8607// CHECK1-NEXT:    store i64 2, ptr [[TMP28]], align 8608// CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9609// CHECK1-NEXT:    store i64 0, ptr [[TMP29]], align 8610// CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10611// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP30]], align 4612// CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11613// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4614// CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12615// CHECK1-NEXT:    store i32 0, ptr [[TMP32]], align 4616// CHECK1-NEXT:    [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])617// CHECK1-NEXT:    [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0618// CHECK1-NEXT:    br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]619// CHECK1:       omp_offload.failed:620// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i64 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]]621// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]622// CHECK1:       omp_offload.cont:623// CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4624// CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0625// CHECK1-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2626// CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]627// CHECK1:       arraydestroy.body:628// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]629// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1630// CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]631// CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]632// CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]633// CHECK1:       arraydestroy.done2:634// CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]635// CHECK1-NEXT:    [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4636// CHECK1-NEXT:    ret i32 [[TMP36]]637//638//639// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev640// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {641// CHECK1-NEXT:  entry:642// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8643// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8644// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8645// CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0646// CHECK1-NEXT:    store i32 0, ptr [[A]], align 4647// CHECK1-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1648// CHECK1-NEXT:    store i32 0, ptr [[B]], align 4649// CHECK1-NEXT:    ret void650//651//652// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St653// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {654// CHECK1-NEXT:  entry:655// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8656// CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8657// CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8658// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8659// CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8660// CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8661// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8662// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0663// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]664// CHECK1-NEXT:    [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0665// CHECK1-NEXT:    [[TMP1:%.*]] = load float, ptr [[F2]], align 4666// CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0667// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 4668// CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP2]] to float669// CHECK1-NEXT:    [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]670// CHECK1-NEXT:    store float [[ADD]], ptr [[F]], align 4671// CHECK1-NEXT:    ret void672//673//674// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev675// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {676// CHECK1-NEXT:  entry:677// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8678// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8679// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8680// CHECK1-NEXT:    ret void681//682//683// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev684// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {685// CHECK1-NEXT:  entry:686// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8687// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8688// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8689// CHECK1-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])690// CHECK1-NEXT:    ret void691//692//693// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei694// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {695// CHECK1-NEXT:  entry:696// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8697// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4698// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8699// CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4700// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8701// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4702// CHECK1-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])703// CHECK1-NEXT:    ret void704//705//706// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56707// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {708// CHECK1-NEXT:  entry:709// CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8710// CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8711// CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8712// CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8713// CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 8714// CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8715// CHECK1-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8716// CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8717// CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8718// CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8719// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]720// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]721// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]722// CHECK1-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 8723// CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4724// CHECK1-NEXT:    store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4725// CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8726// CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]727// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]])728// CHECK1-NEXT:    ret void729//730//731// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined732// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {733// CHECK1-NEXT:  entry:734// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8735// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8736// CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8737// CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8738// CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8739// CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8740// CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 8741// CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4742// CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4743// CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4744// CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4745// CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4746// CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4747// CHECK1-NEXT:    [[VEC2:%.*]] = alloca [2 x i32], align 4748// CHECK1-NEXT:    [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4749// CHECK1-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4750// CHECK1-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4751// CHECK1-NEXT:    [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4752// CHECK1-NEXT:    [[_TMP7:%.*]] = alloca ptr, align 8753// CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4754// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8755// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8756// CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8757// CHECK1-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8758// CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8759// CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8760// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]761// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]762// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]763// CHECK1-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 8764// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4765// CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4766// CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4767// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4768// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false)769// CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0770// CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2771// CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]772// CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]773// CHECK1:       omp.arraycpy.body:774// CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]775// CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]776// CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])777// CHECK1-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])778// CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]779// CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1780// CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1781// CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]782// CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]783// CHECK1:       omp.arraycpy.done4:784// CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]785// CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])786// CHECK1-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]])787// CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]788// CHECK1-NEXT:    store ptr [[VAR5]], ptr [[_TMP7]], align 8789// CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8790// CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4791// CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)792// CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4793// CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1794// CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]795// CHECK1:       cond.true:796// CHECK1-NEXT:    br label [[COND_END:%.*]]797// CHECK1:       cond.false:798// CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4799// CHECK1-NEXT:    br label [[COND_END]]800// CHECK1:       cond.end:801// CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]802// CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4803// CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4804// CHECK1-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4805// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]806// CHECK1:       omp.inner.for.cond:807// CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4808// CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4809// CHECK1-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]810// CHECK1-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]811// CHECK1:       omp.inner.for.cond.cleanup:812// CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]813// CHECK1:       omp.inner.for.body:814// CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4815// CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1816// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]817// CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4818// CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4819// CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I]], align 4820// CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64821// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]]822// CHECK1-NEXT:    store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4823// CHECK1-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]]824// CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4825// CHECK1-NEXT:    [[IDXPROM9:%.*]] = sext i32 [[TMP16]] to i64826// CHECK1-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM9]]827// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP15]], i64 4, i1 false)828// CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]829// CHECK1:       omp.body.continue:830// CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]831// CHECK1:       omp.inner.for.inc:832// CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4833// CHECK1-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1834// CHECK1-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4835// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]836// CHECK1:       omp.inner.for.end:837// CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]838// CHECK1:       omp.loop.exit:839// CHECK1-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8840// CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4841// CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]])842// CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]843// CHECK1-NEXT:    [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0844// CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2845// CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]846// CHECK1:       arraydestroy.body:847// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]848// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1849// CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]850// CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]851// CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]852// CHECK1:       arraydestroy.done13:853// CHECK1-NEXT:    ret void854//855//856// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St857// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {858// CHECK1-NEXT:  entry:859// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8860// CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8861// CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8862// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8863// CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8864// CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8865// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8866// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8867// CHECK1-NEXT:    call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])868// CHECK1-NEXT:    ret void869//870//871// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev872// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {873// CHECK1-NEXT:  entry:874// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8875// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8876// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8877// CHECK1-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]878// CHECK1-NEXT:    ret void879//880//881// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev882// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {883// CHECK1-NEXT:  entry:884// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8885// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8886// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8887// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0888// CHECK1-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4889// CHECK1-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4890// CHECK1-NEXT:    ret void891//892//893// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei894// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {895// CHECK1-NEXT:  entry:896// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8897// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4898// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8899// CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4900// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8901// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0902// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4903// CHECK1-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4904// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]905// CHECK1-NEXT:    store i32 [[ADD]], ptr [[F]], align 4906// CHECK1-NEXT:    ret void907//908//909// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St910// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {911// CHECK1-NEXT:  entry:912// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8913// CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8914// CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8915// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8916// CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8917// CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8918// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8919// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0920// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]921// CHECK1-NEXT:    [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0922// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[F2]], align 4923// CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0924// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 4925// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]926// CHECK1-NEXT:    store i32 [[ADD]], ptr [[F]], align 4927// CHECK1-NEXT:    ret void928//929//930// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev931// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {932// CHECK1-NEXT:  entry:933// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8934// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8935// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8936// CHECK1-NEXT:    ret void937//938//939// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp940// CHECK1-SAME: () #[[ATTR0]] {941// CHECK1-NEXT:  entry:942// CHECK1-NEXT:    call void @__cxx_global_var_init()943// CHECK1-NEXT:    call void @__cxx_global_var_init.1()944// CHECK1-NEXT:    call void @__cxx_global_var_init.2()945// CHECK1-NEXT:    ret void946//947//948// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init949// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {950// CHECK3-NEXT:  entry:951// CHECK3-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)952// CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]953// CHECK3-NEXT:    ret void954//955//956// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev957// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {958// CHECK3-NEXT:  entry:959// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4960// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4961// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4962// CHECK3-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])963// CHECK3-NEXT:    ret void964//965//966// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev967// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {968// CHECK3-NEXT:  entry:969// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4970// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4971// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4972// CHECK3-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]973// CHECK3-NEXT:    ret void974//975//976// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev977// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {978// CHECK3-NEXT:  entry:979// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4980// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4981// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4982// CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0983// CHECK3-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4984// CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float985// CHECK3-NEXT:    store float [[CONV]], ptr [[F]], align 4986// CHECK3-NEXT:    ret void987//988//989// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev990// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {991// CHECK3-NEXT:  entry:992// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4993// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4994// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4995// CHECK3-NEXT:    ret void996//997//998// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1999// CHECK3-SAME: () #[[ATTR0]] {1000// CHECK3-NEXT:  entry:1001// CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)1002// CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00)1003// CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]1004// CHECK3-NEXT:    ret void1005//1006//1007// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef1008// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1009// CHECK3-NEXT:  entry:1010// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41011// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca float, align 41012// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41013// CHECK3-NEXT:    store float [[A]], ptr [[A_ADDR]], align 41014// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41015// CHECK3-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41016// CHECK3-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])1017// CHECK3-NEXT:    ret void1018//1019//1020// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor1021// CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {1022// CHECK3-NEXT:  entry:1023// CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 41024// CHECK3-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 41025// CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1026// CHECK3:       arraydestroy.body:1027// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1028// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11029// CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1030// CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr1031// CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]1032// CHECK3:       arraydestroy.done1:1033// CHECK3-NEXT:    ret void1034//1035//1036// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef1037// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1038// CHECK3-NEXT:  entry:1039// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41040// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca float, align 41041// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41042// CHECK3-NEXT:    store float [[A]], ptr [[A_ADDR]], align 41043// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41044// CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01045// CHECK3-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41046// CHECK3-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 41047// CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float1048// CHECK3-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]1049// CHECK3-NEXT:    store float [[ADD]], ptr [[F]], align 41050// CHECK3-NEXT:    ret void1051//1052//1053// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.21054// CHECK3-SAME: () #[[ATTR0]] {1055// CHECK3-NEXT:  entry:1056// CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)1057// CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]1058// CHECK3-NEXT:    ret void1059//1060//1061// CHECK3-LABEL: define {{[^@]+}}@main1062// CHECK3-SAME: () #[[ATTR3:[0-9]+]] {1063// CHECK3-NEXT:  entry:1064// CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 41065// CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 41066// CHECK3-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i32, align 41067// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 41068// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 41069// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 41070// CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 41071// CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81072// CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 41073// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr @t_var, align 41074// CHECK3-NEXT:    store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 41075// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41076// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 41077// CHECK3-NEXT:    store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 41078// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 41079// CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01080// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP4]], align 41081// CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01082// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP5]], align 41083// CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 01084// CHECK3-NEXT:    store ptr null, ptr [[TMP6]], align 41085// CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11086// CHECK3-NEXT:    store ptr @vec, ptr [[TMP7]], align 41087// CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11088// CHECK3-NEXT:    store ptr @vec, ptr [[TMP8]], align 41089// CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 11090// CHECK3-NEXT:    store ptr null, ptr [[TMP9]], align 41091// CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21092// CHECK3-NEXT:    store ptr @s_arr, ptr [[TMP10]], align 41093// CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21094// CHECK3-NEXT:    store ptr @s_arr, ptr [[TMP11]], align 41095// CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 21096// CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 41097// CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31098// CHECK3-NEXT:    store ptr @var, ptr [[TMP13]], align 41099// CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31100// CHECK3-NEXT:    store ptr @var, ptr [[TMP14]], align 41101// CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 31102// CHECK3-NEXT:    store ptr null, ptr [[TMP15]], align 41103// CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 41104// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP16]], align 41105// CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 41106// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP17]], align 41107// CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 41108// CHECK3-NEXT:    store ptr null, ptr [[TMP18]], align 41109// CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01110// CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01111// CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01112// CHECK3-NEXT:    store i32 3, ptr [[TMP21]], align 41113// CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11114// CHECK3-NEXT:    store i32 5, ptr [[TMP22]], align 41115// CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21116// CHECK3-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 41117// CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31118// CHECK3-NEXT:    store ptr [[TMP20]], ptr [[TMP24]], align 41119// CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41120// CHECK3-NEXT:    store ptr @.offload_sizes, ptr [[TMP25]], align 41121// CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51122// CHECK3-NEXT:    store ptr @.offload_maptypes, ptr [[TMP26]], align 41123// CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61124// CHECK3-NEXT:    store ptr null, ptr [[TMP27]], align 41125// CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71126// CHECK3-NEXT:    store ptr null, ptr [[TMP28]], align 41127// CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81128// CHECK3-NEXT:    store i64 2, ptr [[TMP29]], align 81129// CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91130// CHECK3-NEXT:    store i64 0, ptr [[TMP30]], align 81131// CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101132// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP31]], align 41133// CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111134// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP32]], align 41135// CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121136// CHECK3-NEXT:    store i32 0, ptr [[TMP33]], align 41137// CHECK3-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, ptr [[KERNEL_ARGS]])1138// CHECK3-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 01139// CHECK3-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1140// CHECK3:       omp_offload.failed:1141// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i32 [[TMP1]], ptr @vec, ptr @s_arr, ptr @var, i32 [[TMP3]]) #[[ATTR2]]1142// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]1143// CHECK3:       omp_offload.cont:1144// CHECK3-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()1145// CHECK3-NEXT:    ret i32 [[CALL]]1146//1147//1148// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l941149// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {1150// CHECK3-NEXT:  entry:1151// CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 41152// CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 41153// CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 41154// CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 41155// CHECK3-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i32, align 41156// CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 41157// CHECK3-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i32, align 41158// CHECK3-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41159// CHECK3-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 41160// CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41161// CHECK3-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 41162// CHECK3-NEXT:    store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 41163// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]]1164// CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1165// CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1166// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 41167// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 41168// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41169// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 41170// CHECK3-NEXT:    store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 41171// CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 41172// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i32 [[TMP6]])1173// CHECK3-NEXT:    ret void1174//1175//1176// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined1177// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] {1178// CHECK3-NEXT:  entry:1179// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41180// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41181// CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 41182// CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 41183// CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 41184// CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 41185// CHECK3-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i32, align 41186// CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41187// CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 41188// CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41189// CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41190// CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41191// CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41192// CHECK3-NEXT:    [[VEC1:%.*]] = alloca [2 x i32], align 41193// CHECK3-NEXT:    [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 41194// CHECK3-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 41195// CHECK3-NEXT:    [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 41196// CHECK3-NEXT:    [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 41197// CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 41198// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41199// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41200// CHECK3-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 41201// CHECK3-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41202// CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41203// CHECK3-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 41204// CHECK3-NEXT:    store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 41205// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1206// CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1207// CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1208// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41209// CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 41210// CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41211// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41212// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false)1213// CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 01214// CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 21215// CHECK3-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]1216// CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1217// CHECK3:       omp.arraycpy.body:1218// CHECK3-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1219// CHECK3-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1220// CHECK3-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])1221// CHECK3-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])1222// CHECK3-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]1223// CHECK3-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11224// CHECK3-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11225// CHECK3-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]1226// CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]1227// CHECK3:       omp.arraycpy.done3:1228// CHECK3-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]])1229// CHECK3-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]])1230// CHECK3-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]1231// CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41232// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 41233// CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1234// CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41235// CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 11236// CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1237// CHECK3:       cond.true:1238// CHECK3-NEXT:    br label [[COND_END:%.*]]1239// CHECK3:       cond.false:1240// CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41241// CHECK3-NEXT:    br label [[COND_END]]1242// CHECK3:       cond.end:1243// CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]1244// CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 41245// CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41246// CHECK3-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 41247// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1248// CHECK3:       omp.inner.for.cond:1249// CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41250// CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41251// CHECK3-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]1252// CHECK3-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1253// CHECK3:       omp.inner.for.cond.cleanup:1254// CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]1255// CHECK3:       omp.inner.for.body:1256// CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41257// CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 11258// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1259// CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 41260// CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 41261// CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 41262// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP13]]1263// CHECK3-NEXT:    store i32 [[TMP12]], ptr [[ARRAYIDX]], align 41264// CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I]], align 41265// CHECK3-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP14]]1266// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false)1267// CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 41268// CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 41269// CHECK3-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]1270// CHECK3-NEXT:    store i32 [[ADD8]], ptr [[SIVAR_ADDR]], align 41271// CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1272// CHECK3:       omp.body.continue:1273// CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1274// CHECK3:       omp.inner.for.inc:1275// CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41276// CHECK3-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP17]], 11277// CHECK3-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 41278// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]1279// CHECK3:       omp.inner.for.end:1280// CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]1281// CHECK3:       omp.loop.exit:1282// CHECK3-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41283// CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 41284// CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]])1285// CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]1286// CHECK3-NEXT:    [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 01287// CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 21288// CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1289// CHECK3:       arraydestroy.body:1290// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1291// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11292// CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1293// CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]1294// CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]1295// CHECK3:       arraydestroy.done11:1296// CHECK3-NEXT:    ret void1297//1298//1299// CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev1300// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1301// CHECK3-NEXT:  entry:1302// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41303// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41304// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41305// CHECK3-NEXT:    call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])1306// CHECK3-NEXT:    ret void1307//1308//1309// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St1310// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1311// CHECK3-NEXT:  entry:1312// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41313// CHECK3-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 41314// CHECK3-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 41315// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41316// CHECK3-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 41317// CHECK3-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 41318// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41319// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 41320// CHECK3-NEXT:    call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])1321// CHECK3-NEXT:    ret void1322//1323//1324// CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev1325// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1326// CHECK3-NEXT:  entry:1327// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41328// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41329// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41330// CHECK3-NEXT:    call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]1331// CHECK3-NEXT:    ret void1332//1333//1334// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v1335// CHECK3-SAME: () #[[ATTR1]] comdat {1336// CHECK3-NEXT:  entry:1337// CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 41338// CHECK3-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41339// CHECK3-NEXT:    [[T_VAR:%.*]] = alloca i32, align 41340// CHECK3-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 41341// CHECK3-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 41342// CHECK3-NEXT:    [[VAR:%.*]] = alloca ptr, align 41343// CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 41344// CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 41345// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 41346// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 41347// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 41348// CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41349// CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81350// CHECK3-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])1351// CHECK3-NEXT:    store i32 0, ptr [[T_VAR]], align 41352// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)1353// CHECK3-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)1354// CHECK3-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 11355// CHECK3-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)1356// CHECK3-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 41357// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META8]], !align [[META9]]1358// CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 41359// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 41360// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 41361// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41362// CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1363// CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1364// CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1365// CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01366// CHECK3-NEXT:    store i32 [[TMP2]], ptr [[TMP6]], align 41367// CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01368// CHECK3-NEXT:    store i32 [[TMP2]], ptr [[TMP7]], align 41369// CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 01370// CHECK3-NEXT:    store ptr null, ptr [[TMP8]], align 41371// CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11372// CHECK3-NEXT:    store ptr [[VEC]], ptr [[TMP9]], align 41373// CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11374// CHECK3-NEXT:    store ptr [[VEC]], ptr [[TMP10]], align 41375// CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 11376// CHECK3-NEXT:    store ptr null, ptr [[TMP11]], align 41377// CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21378// CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[TMP12]], align 41379// CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21380// CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[TMP13]], align 41381// CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 21382// CHECK3-NEXT:    store ptr null, ptr [[TMP14]], align 41383// CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31384// CHECK3-NEXT:    store ptr [[TMP4]], ptr [[TMP15]], align 41385// CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31386// CHECK3-NEXT:    store ptr [[TMP5]], ptr [[TMP16]], align 41387// CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 31388// CHECK3-NEXT:    store ptr null, ptr [[TMP17]], align 41389// CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01390// CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01391// CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01392// CHECK3-NEXT:    store i32 3, ptr [[TMP20]], align 41393// CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11394// CHECK3-NEXT:    store i32 4, ptr [[TMP21]], align 41395// CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21396// CHECK3-NEXT:    store ptr [[TMP18]], ptr [[TMP22]], align 41397// CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31398// CHECK3-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 41399// CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41400// CHECK3-NEXT:    store ptr @.offload_sizes.3, ptr [[TMP24]], align 41401// CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51402// CHECK3-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP25]], align 41403// CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61404// CHECK3-NEXT:    store ptr null, ptr [[TMP26]], align 41405// CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71406// CHECK3-NEXT:    store ptr null, ptr [[TMP27]], align 41407// CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81408// CHECK3-NEXT:    store i64 2, ptr [[TMP28]], align 81409// CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91410// CHECK3-NEXT:    store i64 0, ptr [[TMP29]], align 81411// CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101412// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP30]], align 41413// CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111414// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP31]], align 41415// CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121416// CHECK3-NEXT:    store i32 0, ptr [[TMP32]], align 41417// CHECK3-NEXT:    [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])1418// CHECK3-NEXT:    [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 01419// CHECK3-NEXT:    br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1420// CHECK3:       omp_offload.failed:1421// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i32 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]]1422// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]1423// CHECK3:       omp_offload.cont:1424// CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 41425// CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01426// CHECK3-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 21427// CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1428// CHECK3:       arraydestroy.body:1429// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1430// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11431// CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1432// CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]1433// CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]1434// CHECK3:       arraydestroy.done2:1435// CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]1436// CHECK3-NEXT:    [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 41437// CHECK3-NEXT:    ret i32 [[TMP36]]1438//1439//1440// CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev1441// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1442// CHECK3-NEXT:  entry:1443// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41444// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41445// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41446// CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 01447// CHECK3-NEXT:    store i32 0, ptr [[A]], align 41448// CHECK3-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 11449// CHECK3-NEXT:    store i32 0, ptr [[B]], align 41450// CHECK3-NEXT:    ret void1451//1452//1453// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St1454// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1455// CHECK3-NEXT:  entry:1456// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41457// CHECK3-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 41458// CHECK3-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 41459// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41460// CHECK3-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 41461// CHECK3-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 41462// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41463// CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01464// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1465// CHECK3-NEXT:    [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 01466// CHECK3-NEXT:    [[TMP1:%.*]] = load float, ptr [[F2]], align 41467// CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 01468// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 41469// CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP2]] to float1470// CHECK3-NEXT:    [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]1471// CHECK3-NEXT:    store float [[ADD]], ptr [[F]], align 41472// CHECK3-NEXT:    ret void1473//1474//1475// CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev1476// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1477// CHECK3-NEXT:  entry:1478// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41479// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41480// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41481// CHECK3-NEXT:    ret void1482//1483//1484// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev1485// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1486// CHECK3-NEXT:  entry:1487// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41488// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41489// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41490// CHECK3-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1491// CHECK3-NEXT:    ret void1492//1493//1494// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei1495// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1496// CHECK3-NEXT:  entry:1497// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41498// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 41499// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41500// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 41501// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41502// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41503// CHECK3-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])1504// CHECK3-NEXT:    ret void1505//1506//1507// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l561508// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {1509// CHECK3-NEXT:  entry:1510// CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 41511// CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 41512// CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 41513// CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 41514// CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 41515// CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 41516// CHECK3-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41517// CHECK3-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 41518// CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41519// CHECK3-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 41520// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1521// CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1522// CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1523// CHECK3-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 41524// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 41525// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 41526// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41527// CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1528// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]])1529// CHECK3-NEXT:    ret void1530//1531//1532// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined1533// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {1534// CHECK3-NEXT:  entry:1535// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41536// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41537// CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 41538// CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 41539// CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 41540// CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 41541// CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 41542// CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41543// CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41544// CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41545// CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41546// CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41547// CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41548// CHECK3-NEXT:    [[VEC2:%.*]] = alloca [2 x i32], align 41549// CHECK3-NEXT:    [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 41550// CHECK3-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 41551// CHECK3-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41552// CHECK3-NEXT:    [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 41553// CHECK3-NEXT:    [[_TMP7:%.*]] = alloca ptr, align 41554// CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 41555// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41556// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41557// CHECK3-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 41558// CHECK3-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41559// CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41560// CHECK3-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 41561// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1562// CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1563// CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1564// CHECK3-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 41565// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41566// CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 41567// CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41568// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41569// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false)1570// CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 01571// CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 21572// CHECK3-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]1573// CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1574// CHECK3:       omp.arraycpy.body:1575// CHECK3-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1576// CHECK3-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1577// CHECK3-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])1578// CHECK3-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])1579// CHECK3-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]1580// CHECK3-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11581// CHECK3-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11582// CHECK3-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]1583// CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]1584// CHECK3:       omp.arraycpy.done4:1585// CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1586// CHECK3-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])1587// CHECK3-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]])1588// CHECK3-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]1589// CHECK3-NEXT:    store ptr [[VAR5]], ptr [[_TMP7]], align 41590// CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41591// CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 41592// CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1593// CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41594// CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 11595// CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1596// CHECK3:       cond.true:1597// CHECK3-NEXT:    br label [[COND_END:%.*]]1598// CHECK3:       cond.false:1599// CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41600// CHECK3-NEXT:    br label [[COND_END]]1601// CHECK3:       cond.end:1602// CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]1603// CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 41604// CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41605// CHECK3-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 41606// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1607// CHECK3:       omp.inner.for.cond:1608// CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41609// CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41610// CHECK3-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]1611// CHECK3-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1612// CHECK3:       omp.inner.for.cond.cleanup:1613// CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]1614// CHECK3:       omp.inner.for.body:1615// CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41616// CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 11617// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1618// CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 41619// CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 41620// CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I]], align 41621// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP14]]1622// CHECK3-NEXT:    store i32 [[TMP13]], ptr [[ARRAYIDX]], align 41623// CHECK3-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META8]], !align [[META9]]1624// CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 41625// CHECK3-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP16]]1626// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP15]], i32 4, i1 false)1627// CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1628// CHECK3:       omp.body.continue:1629// CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1630// CHECK3:       omp.inner.for.inc:1631// CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41632// CHECK3-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP17]], 11633// CHECK3-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 41634// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]1635// CHECK3:       omp.inner.for.end:1636// CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]1637// CHECK3:       omp.loop.exit:1638// CHECK3-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41639// CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 41640// CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]])1641// CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]1642// CHECK3-NEXT:    [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 01643// CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 21644// CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1645// CHECK3:       arraydestroy.body:1646// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1647// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11648// CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1649// CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]1650// CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]1651// CHECK3:       arraydestroy.done12:1652// CHECK3-NEXT:    ret void1653//1654//1655// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St1656// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1657// CHECK3-NEXT:  entry:1658// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41659// CHECK3-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 41660// CHECK3-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 41661// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41662// CHECK3-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 41663// CHECK3-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 41664// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41665// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 41666// CHECK3-NEXT:    call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])1667// CHECK3-NEXT:    ret void1668//1669//1670// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev1671// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1672// CHECK3-NEXT:  entry:1673// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41674// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41675// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41676// CHECK3-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]1677// CHECK3-NEXT:    ret void1678//1679//1680// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev1681// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1682// CHECK3-NEXT:  entry:1683// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41684// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41685// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41686// CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01687// CHECK3-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 41688// CHECK3-NEXT:    store i32 [[TMP0]], ptr [[F]], align 41689// CHECK3-NEXT:    ret void1690//1691//1692// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei1693// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1694// CHECK3-NEXT:  entry:1695// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41696// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 41697// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41698// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 41699// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41700// CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01701// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41702// CHECK3-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 41703// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]1704// CHECK3-NEXT:    store i32 [[ADD]], ptr [[F]], align 41705// CHECK3-NEXT:    ret void1706//1707//1708// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St1709// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1710// CHECK3-NEXT:  entry:1711// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41712// CHECK3-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 41713// CHECK3-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 41714// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41715// CHECK3-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 41716// CHECK3-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 41717// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41718// CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01719// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1720// CHECK3-NEXT:    [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 01721// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[F2]], align 41722// CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 01723// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 41724// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]1725// CHECK3-NEXT:    store i32 [[ADD]], ptr [[F]], align 41726// CHECK3-NEXT:    ret void1727//1728//1729// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev1730// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1731// CHECK3-NEXT:  entry:1732// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41733// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41734// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41735// CHECK3-NEXT:    ret void1736//1737//1738// CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp1739// CHECK3-SAME: () #[[ATTR0]] {1740// CHECK3-NEXT:  entry:1741// CHECK3-NEXT:    call void @__cxx_global_var_init()1742// CHECK3-NEXT:    call void @__cxx_global_var_init.1()1743// CHECK3-NEXT:    call void @__cxx_global_var_init.2()1744// CHECK3-NEXT:    ret void1745//1746//1747// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init1748// CHECK9-SAME: () #[[ATTR0:[0-9]+]] {1749// CHECK9-NEXT:  entry:1750// CHECK9-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)1751// CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]1752// CHECK9-NEXT:    ret void1753//1754//1755// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev1756// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {1757// CHECK9-NEXT:  entry:1758// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81759// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81760// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81761// CHECK9-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1762// CHECK9-NEXT:    ret void1763//1764//1765// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev1766// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1767// CHECK9-NEXT:  entry:1768// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81769// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81770// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81771// CHECK9-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]1772// CHECK9-NEXT:    ret void1773//1774//1775// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev1776// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1777// CHECK9-NEXT:  entry:1778// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81779// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81780// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81781// CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01782// CHECK9-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 41783// CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float1784// CHECK9-NEXT:    store float [[CONV]], ptr [[F]], align 41785// CHECK9-NEXT:    ret void1786//1787//1788// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev1789// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1790// CHECK9-NEXT:  entry:1791// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81792// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81793// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81794// CHECK9-NEXT:    ret void1795//1796//1797// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.11798// CHECK9-SAME: () #[[ATTR0]] {1799// CHECK9-NEXT:  entry:1800// CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)1801// CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)1802// CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]1803// CHECK9-NEXT:    ret void1804//1805//1806// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef1807// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1808// CHECK9-NEXT:  entry:1809// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81810// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca float, align 41811// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81812// CHECK9-NEXT:    store float [[A]], ptr [[A_ADDR]], align 41813// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81814// CHECK9-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41815// CHECK9-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])1816// CHECK9-NEXT:    ret void1817//1818//1819// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor1820// CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {1821// CHECK9-NEXT:  entry:1822// CHECK9-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 81823// CHECK9-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 81824// CHECK9-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1825// CHECK9:       arraydestroy.body:1826// CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1827// CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11828// CHECK9-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1829// CHECK9-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr1830// CHECK9-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]1831// CHECK9:       arraydestroy.done1:1832// CHECK9-NEXT:    ret void1833//1834//1835// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef1836// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1837// CHECK9-NEXT:  entry:1838// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81839// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca float, align 41840// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81841// CHECK9-NEXT:    store float [[A]], ptr [[A_ADDR]], align 41842// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81843// CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01844// CHECK9-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41845// CHECK9-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 41846// CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float1847// CHECK9-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]1848// CHECK9-NEXT:    store float [[ADD]], ptr [[F]], align 41849// CHECK9-NEXT:    ret void1850//1851//1852// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.21853// CHECK9-SAME: () #[[ATTR0]] {1854// CHECK9-NEXT:  entry:1855// CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)1856// CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]1857// CHECK9-NEXT:    ret void1858//1859//1860// CHECK9-LABEL: define {{[^@]+}}@main1861// CHECK9-SAME: () #[[ATTR3:[0-9]+]] {1862// CHECK9-NEXT:  entry:1863// CHECK9-NEXT:    [[RETVAL:%.*]] = alloca i32, align 41864// CHECK9-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 11865// CHECK9-NEXT:    store i32 0, ptr [[RETVAL]], align 41866// CHECK9-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])1867// CHECK9-NEXT:    ret i32 01868//1869//1870// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l751871// CHECK9-SAME: (i64 noundef [[G:%.*]], i64 noundef [[SIVAR:%.*]], i64 noundef [[G1:%.*]]) #[[ATTR4:[0-9]+]] {1872// CHECK9-NEXT:  entry:1873// CHECK9-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 81874// CHECK9-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 81875// CHECK9-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 81876// CHECK9-NEXT:    [[TMP:%.*]] = alloca ptr, align 81877// CHECK9-NEXT:    [[G_CASTED:%.*]] = alloca i64, align 81878// CHECK9-NEXT:    [[G1_CASTED:%.*]] = alloca i64, align 81879// CHECK9-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 81880// CHECK9-NEXT:    store i64 [[G]], ptr [[G_ADDR]], align 81881// CHECK9-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 81882// CHECK9-NEXT:    store i64 [[G1]], ptr [[G1_ADDR]], align 81883// CHECK9-NEXT:    store ptr [[G1_ADDR]], ptr [[TMP]], align 81884// CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[G_ADDR]], align 41885// CHECK9-NEXT:    store i32 [[TMP0]], ptr [[G_CASTED]], align 41886// CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 81887// CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]1888// CHECK9-NEXT:    [[TMP3:%.*]] = load volatile i32, ptr [[TMP2]], align 41889// CHECK9-NEXT:    store i32 [[TMP3]], ptr [[G1_CASTED]], align 41890// CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[G1_CASTED]], align 81891// CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 41892// CHECK9-NEXT:    store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 41893// CHECK9-NEXT:    [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 81894// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined, i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])1895// CHECK9-NEXT:    ret void1896//1897//1898// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined1899// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] {1900// CHECK9-NEXT:  entry:1901// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81902// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81903// CHECK9-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 81904// CHECK9-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 81905// CHECK9-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 81906// CHECK9-NEXT:    [[TMP:%.*]] = alloca ptr, align 81907// CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41908// CHECK9-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41909// CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41910// CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41911// CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41912// CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41913// CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 41914// CHECK9-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 81915// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81916// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81917// CHECK9-NEXT:    store i64 [[G]], ptr [[G_ADDR]], align 81918// CHECK9-NEXT:    store i64 [[G1]], ptr [[G1_ADDR]], align 81919// CHECK9-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 81920// CHECK9-NEXT:    store ptr [[G1_ADDR]], ptr [[TMP]], align 81921// CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41922// CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 41923// CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41924// CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41925// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81926// CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41927// CHECK9-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1928// CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41929// CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 11930// CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1931// CHECK9:       cond.true:1932// CHECK9-NEXT:    br label [[COND_END:%.*]]1933// CHECK9:       cond.false:1934// CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41935// CHECK9-NEXT:    br label [[COND_END]]1936// CHECK9:       cond.end:1937// CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]1938// CHECK9-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 41939// CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41940// CHECK9-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 41941// CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1942// CHECK9:       omp.inner.for.cond:1943// CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41944// CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41945// CHECK9-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]1946// CHECK9-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1947// CHECK9:       omp.inner.for.body:1948// CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41949// CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 11950// CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1951// CHECK9-NEXT:    store i32 [[ADD]], ptr [[I]], align 41952// CHECK9-NEXT:    store i32 1, ptr [[G_ADDR]], align 41953// CHECK9-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]]1954// CHECK9-NEXT:    store volatile i32 1, ptr [[TMP8]], align 41955// CHECK9-NEXT:    store i32 2, ptr [[SIVAR_ADDR]], align 41956// CHECK9-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 01957// CHECK9-NEXT:    store ptr [[G_ADDR]], ptr [[TMP9]], align 81958// CHECK9-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 11959// CHECK9-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]]1960// CHECK9-NEXT:    store ptr [[TMP11]], ptr [[TMP10]], align 81961// CHECK9-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 21962// CHECK9-NEXT:    store ptr [[SIVAR_ADDR]], ptr [[TMP12]], align 81963// CHECK9-NEXT:    call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]])1964// CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1965// CHECK9:       omp.body.continue:1966// CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1967// CHECK9:       omp.inner.for.inc:1968// CHECK9-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41969// CHECK9-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP13]], 11970// CHECK9-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 41971// CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]]1972// CHECK9:       omp.inner.for.end:1973// CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]1974// CHECK9:       omp.loop.exit:1975// CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])1976// CHECK9-NEXT:    ret void1977//1978//1979// CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp1980// CHECK9-SAME: () #[[ATTR0]] {1981// CHECK9-NEXT:  entry:1982// CHECK9-NEXT:    call void @__cxx_global_var_init()1983// CHECK9-NEXT:    call void @__cxx_global_var_init.1()1984// CHECK9-NEXT:    call void @__cxx_global_var_init.2()1985// CHECK9-NEXT:    ret void1986//1987