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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK13// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping4// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK15// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK36// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping7// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK38 9// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"10// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping11// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"12// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"13// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping14// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"15 16// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK917// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping18// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++  -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK919 20// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"21// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping22// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++  -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"23 24// expected-no-diagnostics25#ifndef HEADER26#define HEADER27 28struct St {29  int a, b;30  St() : a(0), b(0) {}31  St(const St &st) : a(st.a + st.b), b(0) {}32  ~St() {}33};34 35volatile int g = 1212;36volatile int &g1 = g;37 38template <class T>39struct S {40  T f;41  S(T a) : f(a + g) {}42  S() : f(g) {}43  S(const S &s, St t = St()) : f(s.f + t.a) {}44  operator T() { return T(); }45  ~S() {}46};47 48 49template <typename T>50T tmain() {51  S<T> test;52  T t_var = T();53  T vec[] = {1, 2};54  S<T> s_arr[] = {1, 2};55  S<T> &var = test;56#pragma omp target57#pragma omp teams distribute parallel for firstprivate(t_var, vec, s_arr, var)58  for (int i = 0; i < 2; ++i) {59    vec[i] = t_var;60    s_arr[i] = var;61  }62  return T();63}64 65S<float> test;66int t_var = 333;67int vec[] = {1, 2};68S<float> s_arr[] = {1, 2};69S<float> var(3);70 71int main() {72  static int sivar;73#ifdef LAMBDA74  [&]() {75#pragma omp target76#pragma omp teams distribute parallel for firstprivate(g, g1, sivar)77  for (int i = 0; i < 2; ++i) {78 79    // Skip global and bound tid vars80    // skip loop vars81    g = 1;82    g1 = 1;83    sivar = 2;84 85    // Skip global and bound tid vars, and prev lb and ub vars86    // skip loop vars87 88    // use of private vars89    [&]() {90      g = 2;91      g1 = 2;92      sivar = 4;93 94    }();95  }96  }();97  return 0;98#else99#pragma omp target100#pragma omp teams distribute parallel for firstprivate(t_var, vec, s_arr, var, sivar)101  for (int i = 0; i < 2; ++i) {102    vec[i] = t_var;103    s_arr[i] = var;104    sivar += i;105  }106  return tmain<int>();107#endif108}109 110 111 112 113 114// Skip global and bound tid vars115// Skip temp vars for loop116 117// param copy118 119// T_VAR and SIVAR120 121// preparation vars122 123// firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2124 125// firstprivate(s_arr)126 127// firstprivate(var)128 129 130// Skip global and bound tid vars, and prev lb ub vars131// Skip temp vars for loop132 133// param copy134 135// T_VAR and SIVAR136 137// preparation vars138 139// firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2140 141// firstprivate(s_arr)142 143// firstprivate(var)144 145 146 147 148 149 150// Skip global and bound tid vars151// Skip temp vars for loop152 153// param copy154 155// T_VAR and preparation variables156 157// firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2158 159// firstprivate(s_arr)160 161// firstprivate(var)162 163 164// Skip global and bound tid vars165// Skip temp vars for loop166 167// param copy168 169// T_VAR and preparation variables170 171// firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2172 173// firstprivate(s_arr)174 175// firstprivate(var)176 177 178#endif179// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init180// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {181// CHECK1-NEXT:  entry:182// CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)183// CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]184// CHECK1-NEXT:    ret void185//186//187// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev188// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {189// CHECK1-NEXT:  entry:190// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8191// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8192// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8193// CHECK1-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])194// CHECK1-NEXT:    ret void195//196//197// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev198// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {199// CHECK1-NEXT:  entry:200// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8201// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8202// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8203// CHECK1-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]204// CHECK1-NEXT:    ret void205//206//207// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev208// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {209// CHECK1-NEXT:  entry:210// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8211// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8212// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8213// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0214// CHECK1-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4215// CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float216// CHECK1-NEXT:    store float [[CONV]], ptr [[F]], align 4217// CHECK1-NEXT:    ret void218//219//220// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev221// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {222// CHECK1-NEXT:  entry:223// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8224// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8225// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8226// CHECK1-NEXT:    ret void227//228//229// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1230// CHECK1-SAME: () #[[ATTR0]] {231// CHECK1-NEXT:  entry:232// CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)233// CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)234// CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]235// CHECK1-NEXT:    ret void236//237//238// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef239// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {240// CHECK1-NEXT:  entry:241// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8242// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4243// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8244// CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4245// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8246// CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4247// CHECK1-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])248// CHECK1-NEXT:    ret void249//250//251// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor252// CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {253// CHECK1-NEXT:  entry:254// CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8255// CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8256// CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]257// CHECK1:       arraydestroy.body:258// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]259// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1260// CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]261// CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr262// CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]263// CHECK1:       arraydestroy.done1:264// CHECK1-NEXT:    ret void265//266//267// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef268// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {269// CHECK1-NEXT:  entry:270// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8271// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4272// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8273// CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4274// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8275// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0276// CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4277// CHECK1-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4278// CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float279// CHECK1-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]280// CHECK1-NEXT:    store float [[ADD]], ptr [[F]], align 4281// CHECK1-NEXT:    ret void282//283//284// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2285// CHECK1-SAME: () #[[ATTR0]] {286// CHECK1-NEXT:  entry:287// CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)288// CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]289// CHECK1-NEXT:    ret void290//291//292// CHECK1-LABEL: define {{[^@]+}}@main293// CHECK1-SAME: () #[[ATTR3:[0-9]+]] {294// CHECK1-NEXT:  entry:295// CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4296// CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8297// CHECK1-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 8298// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8299// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8300// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8301// CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4302// CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8303// CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4304// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr @t_var, align 4305// CHECK1-NEXT:    store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4306// CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8307// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4308// CHECK1-NEXT:    store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4309// CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8310// CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0311// CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP4]], align 8312// CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0313// CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP5]], align 8314// CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0315// CHECK1-NEXT:    store ptr null, ptr [[TMP6]], align 8316// CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1317// CHECK1-NEXT:    store ptr @vec, ptr [[TMP7]], align 8318// CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1319// CHECK1-NEXT:    store ptr @vec, ptr [[TMP8]], align 8320// CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1321// CHECK1-NEXT:    store ptr null, ptr [[TMP9]], align 8322// CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2323// CHECK1-NEXT:    store ptr @s_arr, ptr [[TMP10]], align 8324// CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2325// CHECK1-NEXT:    store ptr @s_arr, ptr [[TMP11]], align 8326// CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2327// CHECK1-NEXT:    store ptr null, ptr [[TMP12]], align 8328// CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3329// CHECK1-NEXT:    store ptr @var, ptr [[TMP13]], align 8330// CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3331// CHECK1-NEXT:    store ptr @var, ptr [[TMP14]], align 8332// CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3333// CHECK1-NEXT:    store ptr null, ptr [[TMP15]], align 8334// CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4335// CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP16]], align 8336// CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4337// CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP17]], align 8338// CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4339// CHECK1-NEXT:    store ptr null, ptr [[TMP18]], align 8340// CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0341// CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0342// CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0343// CHECK1-NEXT:    store i32 3, ptr [[TMP21]], align 4344// CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1345// CHECK1-NEXT:    store i32 5, ptr [[TMP22]], align 4346// CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2347// CHECK1-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 8348// CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3349// CHECK1-NEXT:    store ptr [[TMP20]], ptr [[TMP24]], align 8350// CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4351// CHECK1-NEXT:    store ptr @.offload_sizes, ptr [[TMP25]], align 8352// CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5353// CHECK1-NEXT:    store ptr @.offload_maptypes, ptr [[TMP26]], align 8354// CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6355// CHECK1-NEXT:    store ptr null, ptr [[TMP27]], align 8356// CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7357// CHECK1-NEXT:    store ptr null, ptr [[TMP28]], align 8358// CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8359// CHECK1-NEXT:    store i64 2, ptr [[TMP29]], align 8360// CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9361// CHECK1-NEXT:    store i64 0, ptr [[TMP30]], align 8362// CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10363// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4364// CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11365// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4366// CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12367// CHECK1-NEXT:    store i32 0, ptr [[TMP33]], align 4368// CHECK1-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.region_id, ptr [[KERNEL_ARGS]])369// CHECK1-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0370// CHECK1-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]371// CHECK1:       omp_offload.failed:372// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99(i64 [[TMP1]], ptr @vec, ptr @s_arr, ptr @var, i64 [[TMP3]]) #[[ATTR2]]373// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]374// CHECK1:       omp_offload.cont:375// CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()376// CHECK1-NEXT:    ret i32 [[CALL]]377//378//379// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99380// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {381// CHECK1-NEXT:  entry:382// CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8383// CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8384// CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8385// CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8386// CHECK1-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8387// CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8388// CHECK1-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 8389// CHECK1-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8390// CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8391// CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8392// CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8393// CHECK1-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8394// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]]395// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]396// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]397// CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4398// CHECK1-NEXT:    store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4399// CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8400// CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4401// CHECK1-NEXT:    store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4402// CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8403// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i64 [[TMP6]])404// CHECK1-NEXT:    ret void405//406//407// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined408// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] {409// CHECK1-NEXT:  entry:410// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8411// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8412// CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8413// CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8414// CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8415// CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8416// CHECK1-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8417// CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4418// CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4419// CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4420// CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4421// CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4422// CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4423// CHECK1-NEXT:    [[VEC1:%.*]] = alloca [2 x i32], align 4424// CHECK1-NEXT:    [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4425// CHECK1-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4426// CHECK1-NEXT:    [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4427// CHECK1-NEXT:    [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4428// CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4429// CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8430// CHECK1-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 8431// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8432// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8433// CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8434// CHECK1-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8435// CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8436// CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8437// CHECK1-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8438// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]439// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]440// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]441// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4442// CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4443// CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4444// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4445// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false)446// CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0447// CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2448// CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]449// CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]450// CHECK1:       omp.arraycpy.body:451// CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]452// CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]453// CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])454// CHECK1-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])455// CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]456// CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1457// CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1458// CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]459// CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]460// CHECK1:       omp.arraycpy.done3:461// CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]])462// CHECK1-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]])463// CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]464// CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8465// CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4466// CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)467// CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4468// CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1469// CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]470// CHECK1:       cond.true:471// CHECK1-NEXT:    br label [[COND_END:%.*]]472// CHECK1:       cond.false:473// CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4474// CHECK1-NEXT:    br label [[COND_END]]475// CHECK1:       cond.end:476// CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]477// CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4478// CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4479// CHECK1-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4480// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]481// CHECK1:       omp.inner.for.cond:482// CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4483// CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4484// CHECK1-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]485// CHECK1-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]486// CHECK1:       omp.inner.for.cond.cleanup:487// CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]488// CHECK1:       omp.inner.for.body:489// CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4490// CHECK1-NEXT:    [[TMP12:%.*]] = zext i32 [[TMP11]] to i64491// CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4492// CHECK1-NEXT:    [[TMP14:%.*]] = zext i32 [[TMP13]] to i64493// CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4494// CHECK1-NEXT:    store i32 [[TMP15]], ptr [[T_VAR_CASTED]], align 4495// CHECK1-NEXT:    [[TMP16:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8496// CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4497// CHECK1-NEXT:    store i32 [[TMP17]], ptr [[SIVAR_CASTED]], align 4498// CHECK1-NEXT:    [[TMP18:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8499// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined.omp_outlined, i64 [[TMP12]], i64 [[TMP14]], ptr [[VEC1]], i64 [[TMP16]], ptr [[S_ARR2]], ptr [[VAR4]], i64 [[TMP18]])500// CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]501// CHECK1:       omp.inner.for.inc:502// CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4503// CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4504// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]]505// CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4506// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]507// CHECK1:       omp.inner.for.end:508// CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]509// CHECK1:       omp.loop.exit:510// CHECK1-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8511// CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4512// CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]])513// CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]514// CHECK1-NEXT:    [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0515// CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2516// CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]517// CHECK1:       arraydestroy.body:518// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]519// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1520// CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]521// CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]522// CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]523// CHECK1:       arraydestroy.done8:524// CHECK1-NEXT:    ret void525//526//527// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev528// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {529// CHECK1-NEXT:  entry:530// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8531// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8532// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8533// CHECK1-NEXT:    call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])534// CHECK1-NEXT:    ret void535//536//537// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St538// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {539// CHECK1-NEXT:  entry:540// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8541// CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8542// CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8543// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8544// CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8545// CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8546// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8547// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8548// CHECK1-NEXT:    call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])549// CHECK1-NEXT:    ret void550//551//552// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev553// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {554// CHECK1-NEXT:  entry:555// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8556// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8557// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8558// CHECK1-NEXT:    call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]559// CHECK1-NEXT:    ret void560//561//562// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined.omp_outlined563// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] {564// CHECK1-NEXT:  entry:565// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8566// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8567// CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8568// CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8569// CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8570// CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8571// CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8572// CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8573// CHECK1-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8574// CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4575// CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4576// CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4577// CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4578// CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4579// CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4580// CHECK1-NEXT:    [[VEC2:%.*]] = alloca [2 x i32], align 4581// CHECK1-NEXT:    [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4582// CHECK1-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4583// CHECK1-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4584// CHECK1-NEXT:    [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4585// CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4586// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8587// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8588// CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8589// CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8590// CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8591// CHECK1-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8592// CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8593// CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8594// CHECK1-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8595// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]596// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]597// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]598// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4599// CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4600// CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8601// CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP3]] to i32602// CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8603// CHECK1-NEXT:    [[CONV1:%.*]] = trunc i64 [[TMP4]] to i32604// CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4605// CHECK1-NEXT:    store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4606// CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4607// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4608// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false)609// CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0610// CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2611// CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]612// CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]613// CHECK1:       omp.arraycpy.body:614// CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]615// CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]616// CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])617// CHECK1-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])618// CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]619// CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1620// CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1621// CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]622// CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]623// CHECK1:       omp.arraycpy.done4:624// CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])625// CHECK1-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP6]])626// CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]627// CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8628// CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4629// CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)630// CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4631// CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1632// CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]633// CHECK1:       cond.true:634// CHECK1-NEXT:    br label [[COND_END:%.*]]635// CHECK1:       cond.false:636// CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4637// CHECK1-NEXT:    br label [[COND_END]]638// CHECK1:       cond.end:639// CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]640// CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4641// CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4642// CHECK1-NEXT:    store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4643// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]644// CHECK1:       omp.inner.for.cond:645// CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4646// CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4647// CHECK1-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]648// CHECK1-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]649// CHECK1:       omp.inner.for.cond.cleanup:650// CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]651// CHECK1:       omp.inner.for.body:652// CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4653// CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1654// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]655// CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4656// CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4657// CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4658// CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64659// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]]660// CHECK1-NEXT:    store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4661// CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4662// CHECK1-NEXT:    [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64663// CHECK1-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM8]]664// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[VAR5]], i64 4, i1 false)665// CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4666// CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4667// CHECK1-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP18]], [[TMP17]]668// CHECK1-NEXT:    store i32 [[ADD10]], ptr [[SIVAR_ADDR]], align 4669// CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]670// CHECK1:       omp.body.continue:671// CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]672// CHECK1:       omp.inner.for.inc:673// CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4674// CHECK1-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP19]], 1675// CHECK1-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4676// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]677// CHECK1:       omp.inner.for.end:678// CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]679// CHECK1:       omp.loop.exit:680// CHECK1-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8681// CHECK1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4682// CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]])683// CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]684// CHECK1-NEXT:    [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0685// CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2686// CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]687// CHECK1:       arraydestroy.body:688// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]689// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1690// CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]691// CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]692// CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]693// CHECK1:       arraydestroy.done13:694// CHECK1-NEXT:    ret void695//696//697// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v698// CHECK1-SAME: () #[[ATTR1]] comdat {699// CHECK1-NEXT:  entry:700// CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4701// CHECK1-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4702// CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4703// CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4704// CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4705// CHECK1-NEXT:    [[VAR:%.*]] = alloca ptr, align 8706// CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 8707// CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8708// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8709// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8710// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8711// CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4712// CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8713// CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])714// CHECK1-NEXT:    store i32 0, ptr [[T_VAR]], align 4715// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)716// CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1)717// CHECK1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1718// CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)719// CHECK1-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8720// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META7]], !align [[META8]]721// CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 8722// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4723// CHECK1-NEXT:    store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4724// CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8725// CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]726// CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]727// CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]728// CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0729// CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP6]], align 8730// CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0731// CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP7]], align 8732// CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0733// CHECK1-NEXT:    store ptr null, ptr [[TMP8]], align 8734// CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1735// CHECK1-NEXT:    store ptr [[VEC]], ptr [[TMP9]], align 8736// CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1737// CHECK1-NEXT:    store ptr [[VEC]], ptr [[TMP10]], align 8738// CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1739// CHECK1-NEXT:    store ptr null, ptr [[TMP11]], align 8740// CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2741// CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[TMP12]], align 8742// CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2743// CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[TMP13]], align 8744// CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2745// CHECK1-NEXT:    store ptr null, ptr [[TMP14]], align 8746// CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3747// CHECK1-NEXT:    store ptr [[TMP4]], ptr [[TMP15]], align 8748// CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3749// CHECK1-NEXT:    store ptr [[TMP5]], ptr [[TMP16]], align 8750// CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3751// CHECK1-NEXT:    store ptr null, ptr [[TMP17]], align 8752// CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0753// CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0754// CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0755// CHECK1-NEXT:    store i32 3, ptr [[TMP20]], align 4756// CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1757// CHECK1-NEXT:    store i32 4, ptr [[TMP21]], align 4758// CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2759// CHECK1-NEXT:    store ptr [[TMP18]], ptr [[TMP22]], align 8760// CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3761// CHECK1-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 8762// CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4763// CHECK1-NEXT:    store ptr @.offload_sizes.3, ptr [[TMP24]], align 8764// CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5765// CHECK1-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP25]], align 8766// CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6767// CHECK1-NEXT:    store ptr null, ptr [[TMP26]], align 8768// CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7769// CHECK1-NEXT:    store ptr null, ptr [[TMP27]], align 8770// CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8771// CHECK1-NEXT:    store i64 2, ptr [[TMP28]], align 8772// CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9773// CHECK1-NEXT:    store i64 0, ptr [[TMP29]], align 8774// CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10775// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP30]], align 4776// CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11777// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4778// CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12779// CHECK1-NEXT:    store i32 0, ptr [[TMP32]], align 4780// CHECK1-NEXT:    [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])781// CHECK1-NEXT:    [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0782// CHECK1-NEXT:    br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]783// CHECK1:       omp_offload.failed:784// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i64 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]]785// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]786// CHECK1:       omp_offload.cont:787// CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4788// CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0789// CHECK1-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2790// CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]791// CHECK1:       arraydestroy.body:792// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]793// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1794// CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]795// CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]796// CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]797// CHECK1:       arraydestroy.done2:798// CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]799// CHECK1-NEXT:    [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4800// CHECK1-NEXT:    ret i32 [[TMP36]]801//802//803// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev804// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {805// CHECK1-NEXT:  entry:806// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8807// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8808// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8809// CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0810// CHECK1-NEXT:    store i32 0, ptr [[A]], align 4811// CHECK1-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1812// CHECK1-NEXT:    store i32 0, ptr [[B]], align 4813// CHECK1-NEXT:    ret void814//815//816// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St817// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {818// CHECK1-NEXT:  entry:819// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8820// CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8821// CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8822// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8823// CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8824// CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8825// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8826// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0827// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]828// CHECK1-NEXT:    [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0829// CHECK1-NEXT:    [[TMP1:%.*]] = load float, ptr [[F2]], align 4830// CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0831// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 4832// CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP2]] to float833// CHECK1-NEXT:    [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]834// CHECK1-NEXT:    store float [[ADD]], ptr [[F]], align 4835// CHECK1-NEXT:    ret void836//837//838// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev839// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {840// CHECK1-NEXT:  entry:841// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8842// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8843// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8844// CHECK1-NEXT:    ret void845//846//847// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev848// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {849// CHECK1-NEXT:  entry:850// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8851// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8852// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8853// CHECK1-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])854// CHECK1-NEXT:    ret void855//856//857// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei858// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {859// CHECK1-NEXT:  entry:860// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8861// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4862// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8863// CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4864// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8865// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4866// CHECK1-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])867// CHECK1-NEXT:    ret void868//869//870// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56871// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {872// CHECK1-NEXT:  entry:873// CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8874// CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8875// CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8876// CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8877// CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 8878// CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8879// CHECK1-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8880// CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8881// CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8882// CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8883// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]884// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]885// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]886// CHECK1-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 8887// CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4888// CHECK1-NEXT:    store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4889// CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8890// CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]891// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]])892// CHECK1-NEXT:    ret void893//894//895// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined896// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {897// CHECK1-NEXT:  entry:898// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8899// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8900// CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8901// CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8902// CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8903// CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8904// CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 8905// CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4906// CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4907// CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4908// CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4909// CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4910// CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4911// CHECK1-NEXT:    [[VEC2:%.*]] = alloca [2 x i32], align 4912// CHECK1-NEXT:    [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4913// CHECK1-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4914// CHECK1-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4915// CHECK1-NEXT:    [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4916// CHECK1-NEXT:    [[_TMP7:%.*]] = alloca ptr, align 8917// CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4918// CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8919// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8920// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8921// CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8922// CHECK1-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8923// CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8924// CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8925// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]926// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]927// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]928// CHECK1-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 8929// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4930// CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4931// CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4932// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4933// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false)934// CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0935// CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2936// CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]937// CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]938// CHECK1:       omp.arraycpy.body:939// CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]940// CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]941// CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])942// CHECK1-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])943// CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]944// CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1945// CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1946// CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]947// CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]948// CHECK1:       omp.arraycpy.done4:949// CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]950// CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])951// CHECK1-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]])952// CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]953// CHECK1-NEXT:    store ptr [[VAR5]], ptr [[_TMP7]], align 8954// CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8955// CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4956// CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)957// CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4958// CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1959// CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]960// CHECK1:       cond.true:961// CHECK1-NEXT:    br label [[COND_END:%.*]]962// CHECK1:       cond.false:963// CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4964// CHECK1-NEXT:    br label [[COND_END]]965// CHECK1:       cond.end:966// CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]967// CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4968// CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4969// CHECK1-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4970// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]971// CHECK1:       omp.inner.for.cond:972// CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4973// CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4974// CHECK1-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]975// CHECK1-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]976// CHECK1:       omp.inner.for.cond.cleanup:977// CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]978// CHECK1:       omp.inner.for.body:979// CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4980// CHECK1-NEXT:    [[TMP13:%.*]] = zext i32 [[TMP12]] to i64981// CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4982// CHECK1-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP14]] to i64983// CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4984// CHECK1-NEXT:    store i32 [[TMP16]], ptr [[T_VAR_CASTED]], align 4985// CHECK1-NEXT:    [[TMP17:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8986// CHECK1-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]]987// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined, i64 [[TMP13]], i64 [[TMP15]], ptr [[VEC2]], i64 [[TMP17]], ptr [[S_ARR3]], ptr [[TMP18]])988// CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]989// CHECK1:       omp.inner.for.inc:990// CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4991// CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4992// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]]993// CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4994// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]995// CHECK1:       omp.inner.for.end:996// CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]997// CHECK1:       omp.loop.exit:998// CHECK1-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8999// CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 41000// CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]])1001// CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]1002// CHECK1-NEXT:    [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 01003// CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i64 21004// CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1005// CHECK1:       arraydestroy.body:1006// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1007// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11008// CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1009// CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]1010// CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]1011// CHECK1:       arraydestroy.done10:1012// CHECK1-NEXT:    ret void1013//1014//1015// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St1016// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {1017// CHECK1-NEXT:  entry:1018// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81019// CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 81020// CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 81021// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81022// CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 81023// CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 81024// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81025// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 81026// CHECK1-NEXT:    call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])1027// CHECK1-NEXT:    ret void1028//1029//1030// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined1031// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {1032// CHECK1-NEXT:  entry:1033// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81034// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81035// CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 81036// CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 81037// CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 81038// CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 81039// CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 81040// CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 81041// CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 81042// CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41043// CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41044// CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41045// CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41046// CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41047// CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41048// CHECK1-NEXT:    [[VEC3:%.*]] = alloca [2 x i32], align 41049// CHECK1-NEXT:    [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 41050// CHECK1-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 41051// CHECK1-NEXT:    [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41052// CHECK1-NEXT:    [[AGG_TMP7:%.*]] = alloca [[STRUCT_ST]], align 41053// CHECK1-NEXT:    [[_TMP8:%.*]] = alloca ptr, align 81054// CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 41055// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81056// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81057// CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 81058// CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 81059// CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 81060// CHECK1-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 81061// CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 81062// CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 81063// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1064// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1065// CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1066// CHECK1-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 81067// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41068// CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 41069// CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 81070// CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP3]] to i321071// CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 81072// CHECK1-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP4]] to i321073// CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 41074// CHECK1-NEXT:    store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 41075// CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41076// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41077// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false)1078// CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 01079// CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 21080// CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]1081// CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1082// CHECK1:       omp.arraycpy.body:1083// CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1084// CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1085// CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])1086// CHECK1-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])1087// CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]1088// CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11089// CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11090// CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]1091// CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]1092// CHECK1:       omp.arraycpy.done5:1093// CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]1094// CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]])1095// CHECK1-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP7]])1096// CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]]) #[[ATTR2]]1097// CHECK1-NEXT:    store ptr [[VAR6]], ptr [[_TMP8]], align 81098// CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81099// CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 41100// CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1101// CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41102// CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 11103// CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1104// CHECK1:       cond.true:1105// CHECK1-NEXT:    br label [[COND_END:%.*]]1106// CHECK1:       cond.false:1107// CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41108// CHECK1-NEXT:    br label [[COND_END]]1109// CHECK1:       cond.end:1110// CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]1111// CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 41112// CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41113// CHECK1-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 41114// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1115// CHECK1:       omp.inner.for.cond:1116// CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41117// CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41118// CHECK1-NEXT:    [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]1119// CHECK1-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1120// CHECK1:       omp.inner.for.cond.cleanup:1121// CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]1122// CHECK1:       omp.inner.for.body:1123// CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41124// CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP14]], 11125// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1126// CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 41127// CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 41128// CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 41129// CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i641130// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]]1131// CHECK1-NEXT:    store i32 [[TMP15]], ptr [[ARRAYIDX]], align 41132// CHECK1-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META7]], !align [[META8]]1133// CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I]], align 41134// CHECK1-NEXT:    [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i641135// CHECK1-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]]1136// CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false)1137// CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1138// CHECK1:       omp.body.continue:1139// CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1140// CHECK1:       omp.inner.for.inc:1141// CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41142// CHECK1-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP19]], 11143// CHECK1-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 41144// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]1145// CHECK1:       omp.inner.for.end:1146// CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]1147// CHECK1:       omp.loop.exit:1148// CHECK1-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81149// CHECK1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 41150// CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]])1151// CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR2]]1152// CHECK1-NEXT:    [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 01153// CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 21154// CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1155// CHECK1:       arraydestroy.body:1156// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1157// CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11158// CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1159// CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]]1160// CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]]1161// CHECK1:       arraydestroy.done14:1162// CHECK1-NEXT:    ret void1163//1164//1165// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev1166// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1167// CHECK1-NEXT:  entry:1168// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81169// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81170// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81171// CHECK1-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]1172// CHECK1-NEXT:    ret void1173//1174//1175// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev1176// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1177// CHECK1-NEXT:  entry:1178// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81179// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81180// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81181// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01182// CHECK1-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 41183// CHECK1-NEXT:    store i32 [[TMP0]], ptr [[F]], align 41184// CHECK1-NEXT:    ret void1185//1186//1187// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei1188// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1189// CHECK1-NEXT:  entry:1190// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81191// CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 41192// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81193// CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 41194// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81195// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01196// CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41197// CHECK1-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 41198// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]1199// CHECK1-NEXT:    store i32 [[ADD]], ptr [[F]], align 41200// CHECK1-NEXT:    ret void1201//1202//1203// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St1204// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {1205// CHECK1-NEXT:  entry:1206// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81207// CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 81208// CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 81209// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81210// CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 81211// CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 81212// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81213// CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01214// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]1215// CHECK1-NEXT:    [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 01216// CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[F2]], align 41217// CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 01218// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 41219// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]1220// CHECK1-NEXT:    store i32 [[ADD]], ptr [[F]], align 41221// CHECK1-NEXT:    ret void1222//1223//1224// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev1225// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1226// CHECK1-NEXT:  entry:1227// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 81228// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 81229// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81230// CHECK1-NEXT:    ret void1231//1232//1233// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp1234// CHECK1-SAME: () #[[ATTR0]] {1235// CHECK1-NEXT:  entry:1236// CHECK1-NEXT:    call void @__cxx_global_var_init()1237// CHECK1-NEXT:    call void @__cxx_global_var_init.1()1238// CHECK1-NEXT:    call void @__cxx_global_var_init.2()1239// CHECK1-NEXT:    ret void1240//1241//1242// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init1243// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {1244// CHECK3-NEXT:  entry:1245// CHECK3-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)1246// CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]1247// CHECK3-NEXT:    ret void1248//1249//1250// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev1251// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {1252// CHECK3-NEXT:  entry:1253// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41254// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41255// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41256// CHECK3-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1257// CHECK3-NEXT:    ret void1258//1259//1260// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev1261// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1262// CHECK3-NEXT:  entry:1263// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41264// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41265// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41266// CHECK3-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]1267// CHECK3-NEXT:    ret void1268//1269//1270// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev1271// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1272// CHECK3-NEXT:  entry:1273// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41274// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41275// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41276// CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01277// CHECK3-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 41278// CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float1279// CHECK3-NEXT:    store float [[CONV]], ptr [[F]], align 41280// CHECK3-NEXT:    ret void1281//1282//1283// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev1284// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1285// CHECK3-NEXT:  entry:1286// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41287// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41288// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41289// CHECK3-NEXT:    ret void1290//1291//1292// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.11293// CHECK3-SAME: () #[[ATTR0]] {1294// CHECK3-NEXT:  entry:1295// CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)1296// CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00)1297// CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]1298// CHECK3-NEXT:    ret void1299//1300//1301// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef1302// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1303// CHECK3-NEXT:  entry:1304// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41305// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca float, align 41306// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41307// CHECK3-NEXT:    store float [[A]], ptr [[A_ADDR]], align 41308// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41309// CHECK3-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41310// CHECK3-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])1311// CHECK3-NEXT:    ret void1312//1313//1314// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor1315// CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {1316// CHECK3-NEXT:  entry:1317// CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 41318// CHECK3-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 41319// CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1320// CHECK3:       arraydestroy.body:1321// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1322// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11323// CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1324// CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr1325// CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]1326// CHECK3:       arraydestroy.done1:1327// CHECK3-NEXT:    ret void1328//1329//1330// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef1331// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1332// CHECK3-NEXT:  entry:1333// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41334// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca float, align 41335// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41336// CHECK3-NEXT:    store float [[A]], ptr [[A_ADDR]], align 41337// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41338// CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01339// CHECK3-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41340// CHECK3-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 41341// CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float1342// CHECK3-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]1343// CHECK3-NEXT:    store float [[ADD]], ptr [[F]], align 41344// CHECK3-NEXT:    ret void1345//1346//1347// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.21348// CHECK3-SAME: () #[[ATTR0]] {1349// CHECK3-NEXT:  entry:1350// CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)1351// CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]1352// CHECK3-NEXT:    ret void1353//1354//1355// CHECK3-LABEL: define {{[^@]+}}@main1356// CHECK3-SAME: () #[[ATTR3:[0-9]+]] {1357// CHECK3-NEXT:  entry:1358// CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 41359// CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 41360// CHECK3-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i32, align 41361// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 41362// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 41363// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 41364// CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 41365// CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81366// CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 41367// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr @t_var, align 41368// CHECK3-NEXT:    store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 41369// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41370// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 41371// CHECK3-NEXT:    store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 41372// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 41373// CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01374// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP4]], align 41375// CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01376// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP5]], align 41377// CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 01378// CHECK3-NEXT:    store ptr null, ptr [[TMP6]], align 41379// CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11380// CHECK3-NEXT:    store ptr @vec, ptr [[TMP7]], align 41381// CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11382// CHECK3-NEXT:    store ptr @vec, ptr [[TMP8]], align 41383// CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 11384// CHECK3-NEXT:    store ptr null, ptr [[TMP9]], align 41385// CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21386// CHECK3-NEXT:    store ptr @s_arr, ptr [[TMP10]], align 41387// CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21388// CHECK3-NEXT:    store ptr @s_arr, ptr [[TMP11]], align 41389// CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 21390// CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 41391// CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31392// CHECK3-NEXT:    store ptr @var, ptr [[TMP13]], align 41393// CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31394// CHECK3-NEXT:    store ptr @var, ptr [[TMP14]], align 41395// CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 31396// CHECK3-NEXT:    store ptr null, ptr [[TMP15]], align 41397// CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 41398// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP16]], align 41399// CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 41400// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP17]], align 41401// CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 41402// CHECK3-NEXT:    store ptr null, ptr [[TMP18]], align 41403// CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01404// CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01405// CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01406// CHECK3-NEXT:    store i32 3, ptr [[TMP21]], align 41407// CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11408// CHECK3-NEXT:    store i32 5, ptr [[TMP22]], align 41409// CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21410// CHECK3-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 41411// CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31412// CHECK3-NEXT:    store ptr [[TMP20]], ptr [[TMP24]], align 41413// CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41414// CHECK3-NEXT:    store ptr @.offload_sizes, ptr [[TMP25]], align 41415// CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51416// CHECK3-NEXT:    store ptr @.offload_maptypes, ptr [[TMP26]], align 41417// CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61418// CHECK3-NEXT:    store ptr null, ptr [[TMP27]], align 41419// CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71420// CHECK3-NEXT:    store ptr null, ptr [[TMP28]], align 41421// CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81422// CHECK3-NEXT:    store i64 2, ptr [[TMP29]], align 81423// CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91424// CHECK3-NEXT:    store i64 0, ptr [[TMP30]], align 81425// CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101426// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP31]], align 41427// CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111428// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP32]], align 41429// CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121430// CHECK3-NEXT:    store i32 0, ptr [[TMP33]], align 41431// CHECK3-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.region_id, ptr [[KERNEL_ARGS]])1432// CHECK3-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 01433// CHECK3-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1434// CHECK3:       omp_offload.failed:1435// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99(i32 [[TMP1]], ptr @vec, ptr @s_arr, ptr @var, i32 [[TMP3]]) #[[ATTR2]]1436// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]1437// CHECK3:       omp_offload.cont:1438// CHECK3-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()1439// CHECK3-NEXT:    ret i32 [[CALL]]1440//1441//1442// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l991443// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {1444// CHECK3-NEXT:  entry:1445// CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 41446// CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 41447// CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 41448// CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 41449// CHECK3-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i32, align 41450// CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 41451// CHECK3-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i32, align 41452// CHECK3-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41453// CHECK3-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 41454// CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41455// CHECK3-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 41456// CHECK3-NEXT:    store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 41457// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]]1458// CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1459// CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1460// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 41461// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 41462// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41463// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 41464// CHECK3-NEXT:    store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 41465// CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 41466// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i32 [[TMP6]])1467// CHECK3-NEXT:    ret void1468//1469//1470// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined1471// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] {1472// CHECK3-NEXT:  entry:1473// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41474// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41475// CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 41476// CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 41477// CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 41478// CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 41479// CHECK3-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i32, align 41480// CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41481// CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 41482// CHECK3-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 41483// CHECK3-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 41484// CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41485// CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41486// CHECK3-NEXT:    [[VEC1:%.*]] = alloca [2 x i32], align 41487// CHECK3-NEXT:    [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 41488// CHECK3-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 41489// CHECK3-NEXT:    [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 41490// CHECK3-NEXT:    [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 41491// CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 41492// CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 41493// CHECK3-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i32, align 41494// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41495// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41496// CHECK3-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 41497// CHECK3-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41498// CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41499// CHECK3-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 41500// CHECK3-NEXT:    store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 41501// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1502// CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1503// CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1504// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 41505// CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 41506// CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41507// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41508// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false)1509// CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 01510// CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 21511// CHECK3-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]1512// CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1513// CHECK3:       omp.arraycpy.body:1514// CHECK3-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1515// CHECK3-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1516// CHECK3-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])1517// CHECK3-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])1518// CHECK3-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]1519// CHECK3-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11520// CHECK3-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11521// CHECK3-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]1522// CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]1523// CHECK3:       omp.arraycpy.done3:1524// CHECK3-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]])1525// CHECK3-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]])1526// CHECK3-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]1527// CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41528// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 41529// CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1530// CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41531// CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 11532// CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1533// CHECK3:       cond.true:1534// CHECK3-NEXT:    br label [[COND_END:%.*]]1535// CHECK3:       cond.false:1536// CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41537// CHECK3-NEXT:    br label [[COND_END]]1538// CHECK3:       cond.end:1539// CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]1540// CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 41541// CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 41542// CHECK3-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 41543// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1544// CHECK3:       omp.inner.for.cond:1545// CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41546// CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41547// CHECK3-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]1548// CHECK3-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1549// CHECK3:       omp.inner.for.cond.cleanup:1550// CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]1551// CHECK3:       omp.inner.for.body:1552// CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 41553// CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 41554// CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 41555// CHECK3-NEXT:    store i32 [[TMP13]], ptr [[T_VAR_CASTED]], align 41556// CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41557// CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 41558// CHECK3-NEXT:    store i32 [[TMP15]], ptr [[SIVAR_CASTED]], align 41559// CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 41560// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined.omp_outlined, i32 [[TMP11]], i32 [[TMP12]], ptr [[VEC1]], i32 [[TMP14]], ptr [[S_ARR2]], ptr [[VAR4]], i32 [[TMP16]])1561// CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1562// CHECK3:       omp.inner.for.inc:1563// CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41564// CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 41565// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]1566// CHECK3-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 41567// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]1568// CHECK3:       omp.inner.for.end:1569// CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]1570// CHECK3:       omp.loop.exit:1571// CHECK3-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41572// CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 41573// CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]])1574// CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]1575// CHECK3-NEXT:    [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 01576// CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i32 21577// CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1578// CHECK3:       arraydestroy.body:1579// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP21]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1580// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11581// CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1582// CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]1583// CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]1584// CHECK3:       arraydestroy.done8:1585// CHECK3-NEXT:    ret void1586//1587//1588// CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev1589// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1590// CHECK3-NEXT:  entry:1591// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41592// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41593// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41594// CHECK3-NEXT:    call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])1595// CHECK3-NEXT:    ret void1596//1597//1598// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St1599// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1600// CHECK3-NEXT:  entry:1601// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41602// CHECK3-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 41603// CHECK3-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 41604// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41605// CHECK3-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 41606// CHECK3-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 41607// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41608// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 41609// CHECK3-NEXT:    call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])1610// CHECK3-NEXT:    ret void1611//1612//1613// CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev1614// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1615// CHECK3-NEXT:  entry:1616// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41617// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41618// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41619// CHECK3-NEXT:    call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]1620// CHECK3-NEXT:    ret void1621//1622//1623// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined.omp_outlined1624// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] {1625// CHECK3-NEXT:  entry:1626// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41627// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41628// CHECK3-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 41629// CHECK3-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 41630// CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 41631// CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 41632// CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 41633// CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 41634// CHECK3-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i32, align 41635// CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41636// CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 41637// CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41638// CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41639// CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41640// CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41641// CHECK3-NEXT:    [[VEC1:%.*]] = alloca [2 x i32], align 41642// CHECK3-NEXT:    [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 41643// CHECK3-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 41644// CHECK3-NEXT:    [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 41645// CHECK3-NEXT:    [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 41646// CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 41647// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41648// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41649// CHECK3-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 41650// CHECK3-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 41651// CHECK3-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 41652// CHECK3-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41653// CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41654// CHECK3-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 41655// CHECK3-NEXT:    store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 41656// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1657// CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1658// CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1659// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41660// CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 41661// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 41662// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 41663// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 41664// CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 41665// CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41666// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41667// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false)1668// CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 01669// CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 21670// CHECK3-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]1671// CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1672// CHECK3:       omp.arraycpy.body:1673// CHECK3-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1674// CHECK3-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1675// CHECK3-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])1676// CHECK3-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])1677// CHECK3-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]1678// CHECK3-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11679// CHECK3-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11680// CHECK3-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]1681// CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]1682// CHECK3:       omp.arraycpy.done3:1683// CHECK3-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]])1684// CHECK3-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]])1685// CHECK3-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]1686// CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41687// CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 41688// CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1689// CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41690// CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 11691// CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1692// CHECK3:       cond.true:1693// CHECK3-NEXT:    br label [[COND_END:%.*]]1694// CHECK3:       cond.false:1695// CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41696// CHECK3-NEXT:    br label [[COND_END]]1697// CHECK3:       cond.end:1698// CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]1699// CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 41700// CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41701// CHECK3-NEXT:    store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 41702// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1703// CHECK3:       omp.inner.for.cond:1704// CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41705// CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41706// CHECK3-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]1707// CHECK3-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1708// CHECK3:       omp.inner.for.cond.cleanup:1709// CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]1710// CHECK3:       omp.inner.for.body:1711// CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41712// CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP13]], 11713// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1714// CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 41715// CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 41716// CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 41717// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP15]]1718// CHECK3-NEXT:    store i32 [[TMP14]], ptr [[ARRAYIDX]], align 41719// CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 41720// CHECK3-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP16]]1721// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false)1722// CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 41723// CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 41724// CHECK3-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP18]], [[TMP17]]1725// CHECK3-NEXT:    store i32 [[ADD8]], ptr [[SIVAR_ADDR]], align 41726// CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1727// CHECK3:       omp.body.continue:1728// CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1729// CHECK3:       omp.inner.for.inc:1730// CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41731// CHECK3-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP19]], 11732// CHECK3-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 41733// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]1734// CHECK3:       omp.inner.for.end:1735// CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]1736// CHECK3:       omp.loop.exit:1737// CHECK3-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41738// CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 41739// CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]])1740// CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]1741// CHECK3-NEXT:    [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 01742// CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 21743// CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1744// CHECK3:       arraydestroy.body:1745// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1746// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11747// CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1748// CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]1749// CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]1750// CHECK3:       arraydestroy.done11:1751// CHECK3-NEXT:    ret void1752//1753//1754// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v1755// CHECK3-SAME: () #[[ATTR1]] comdat {1756// CHECK3-NEXT:  entry:1757// CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 41758// CHECK3-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41759// CHECK3-NEXT:    [[T_VAR:%.*]] = alloca i32, align 41760// CHECK3-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 41761// CHECK3-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 41762// CHECK3-NEXT:    [[VAR:%.*]] = alloca ptr, align 41763// CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 41764// CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 41765// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 41766// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 41767// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 41768// CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41769// CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81770// CHECK3-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])1771// CHECK3-NEXT:    store i32 0, ptr [[T_VAR]], align 41772// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)1773// CHECK3-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)1774// CHECK3-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 11775// CHECK3-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)1776// CHECK3-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 41777// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META8]], !align [[META9]]1778// CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 41779// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 41780// CHECK3-NEXT:    store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 41781// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41782// CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1783// CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1784// CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1785// CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01786// CHECK3-NEXT:    store i32 [[TMP2]], ptr [[TMP6]], align 41787// CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01788// CHECK3-NEXT:    store i32 [[TMP2]], ptr [[TMP7]], align 41789// CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 01790// CHECK3-NEXT:    store ptr null, ptr [[TMP8]], align 41791// CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11792// CHECK3-NEXT:    store ptr [[VEC]], ptr [[TMP9]], align 41793// CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11794// CHECK3-NEXT:    store ptr [[VEC]], ptr [[TMP10]], align 41795// CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 11796// CHECK3-NEXT:    store ptr null, ptr [[TMP11]], align 41797// CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21798// CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[TMP12]], align 41799// CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21800// CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[TMP13]], align 41801// CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 21802// CHECK3-NEXT:    store ptr null, ptr [[TMP14]], align 41803// CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31804// CHECK3-NEXT:    store ptr [[TMP4]], ptr [[TMP15]], align 41805// CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31806// CHECK3-NEXT:    store ptr [[TMP5]], ptr [[TMP16]], align 41807// CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 31808// CHECK3-NEXT:    store ptr null, ptr [[TMP17]], align 41809// CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01810// CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01811// CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01812// CHECK3-NEXT:    store i32 3, ptr [[TMP20]], align 41813// CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11814// CHECK3-NEXT:    store i32 4, ptr [[TMP21]], align 41815// CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21816// CHECK3-NEXT:    store ptr [[TMP18]], ptr [[TMP22]], align 41817// CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31818// CHECK3-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 41819// CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41820// CHECK3-NEXT:    store ptr @.offload_sizes.3, ptr [[TMP24]], align 41821// CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51822// CHECK3-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP25]], align 41823// CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61824// CHECK3-NEXT:    store ptr null, ptr [[TMP26]], align 41825// CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71826// CHECK3-NEXT:    store ptr null, ptr [[TMP27]], align 41827// CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81828// CHECK3-NEXT:    store i64 2, ptr [[TMP28]], align 81829// CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91830// CHECK3-NEXT:    store i64 0, ptr [[TMP29]], align 81831// CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101832// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP30]], align 41833// CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111834// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP31]], align 41835// CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121836// CHECK3-NEXT:    store i32 0, ptr [[TMP32]], align 41837// CHECK3-NEXT:    [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])1838// CHECK3-NEXT:    [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 01839// CHECK3-NEXT:    br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1840// CHECK3:       omp_offload.failed:1841// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i32 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]]1842// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]1843// CHECK3:       omp_offload.cont:1844// CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 41845// CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01846// CHECK3-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 21847// CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]1848// CHECK3:       arraydestroy.body:1849// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1850// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11851// CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1852// CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]1853// CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]1854// CHECK3:       arraydestroy.done2:1855// CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]1856// CHECK3-NEXT:    [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 41857// CHECK3-NEXT:    ret i32 [[TMP36]]1858//1859//1860// CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev1861// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1862// CHECK3-NEXT:  entry:1863// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41864// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41865// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41866// CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 01867// CHECK3-NEXT:    store i32 0, ptr [[A]], align 41868// CHECK3-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 11869// CHECK3-NEXT:    store i32 0, ptr [[B]], align 41870// CHECK3-NEXT:    ret void1871//1872//1873// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St1874// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1875// CHECK3-NEXT:  entry:1876// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41877// CHECK3-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 41878// CHECK3-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 41879// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41880// CHECK3-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 41881// CHECK3-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 41882// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41883// CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01884// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1885// CHECK3-NEXT:    [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 01886// CHECK3-NEXT:    [[TMP1:%.*]] = load float, ptr [[F2]], align 41887// CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 01888// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 41889// CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP2]] to float1890// CHECK3-NEXT:    [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]1891// CHECK3-NEXT:    store float [[ADD]], ptr [[F]], align 41892// CHECK3-NEXT:    ret void1893//1894//1895// CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev1896// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1897// CHECK3-NEXT:  entry:1898// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41899// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41900// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41901// CHECK3-NEXT:    ret void1902//1903//1904// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev1905// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1906// CHECK3-NEXT:  entry:1907// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41908// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41909// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41910// CHECK3-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1911// CHECK3-NEXT:    ret void1912//1913//1914// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei1915// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1916// CHECK3-NEXT:  entry:1917// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 41918// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 41919// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 41920// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 41921// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41922// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41923// CHECK3-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])1924// CHECK3-NEXT:    ret void1925//1926//1927// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l561928// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {1929// CHECK3-NEXT:  entry:1930// CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 41931// CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 41932// CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 41933// CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 41934// CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 41935// CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 41936// CHECK3-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41937// CHECK3-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 41938// CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41939// CHECK3-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 41940// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1941// CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1942// CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1943// CHECK3-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 41944// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 41945// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 41946// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41947// CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1948// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]])1949// CHECK3-NEXT:    ret void1950//1951//1952// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined1953// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {1954// CHECK3-NEXT:  entry:1955// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41956// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41957// CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 41958// CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 41959// CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 41960// CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 41961// CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 41962// CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41963// CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41964// CHECK3-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 41965// CHECK3-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 41966// CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41967// CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41968// CHECK3-NEXT:    [[VEC2:%.*]] = alloca [2 x i32], align 41969// CHECK3-NEXT:    [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 41970// CHECK3-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 41971// CHECK3-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41972// CHECK3-NEXT:    [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 41973// CHECK3-NEXT:    [[_TMP7:%.*]] = alloca ptr, align 41974// CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 41975// CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 41976// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41977// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41978// CHECK3-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 41979// CHECK3-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41980// CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41981// CHECK3-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 41982// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1983// CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1984// CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1985// CHECK3-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 41986// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 41987// CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 41988// CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41989// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41990// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false)1991// CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 01992// CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 21993// CHECK3-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]1994// CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1995// CHECK3:       omp.arraycpy.body:1996// CHECK3-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1997// CHECK3-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1998// CHECK3-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])1999// CHECK3-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])2000// CHECK3-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]2001// CHECK3-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 12002// CHECK3-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 12003// CHECK3-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]2004// CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]2005// CHECK3:       omp.arraycpy.done4:2006// CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]2007// CHECK3-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])2008// CHECK3-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]])2009// CHECK3-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]2010// CHECK3-NEXT:    store ptr [[VAR5]], ptr [[_TMP7]], align 42011// CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42012// CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 42013// CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2014// CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 42015// CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 12016// CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2017// CHECK3:       cond.true:2018// CHECK3-NEXT:    br label [[COND_END:%.*]]2019// CHECK3:       cond.false:2020// CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 42021// CHECK3-NEXT:    br label [[COND_END]]2022// CHECK3:       cond.end:2023// CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]2024// CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 42025// CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 42026// CHECK3-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 42027// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2028// CHECK3:       omp.inner.for.cond:2029// CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42030// CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 42031// CHECK3-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]2032// CHECK3-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]2033// CHECK3:       omp.inner.for.cond.cleanup:2034// CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]2035// CHECK3:       omp.inner.for.body:2036// CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 42037// CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 42038// CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 42039// CHECK3-NEXT:    store i32 [[TMP14]], ptr [[T_VAR_CASTED]], align 42040// CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 42041// CHECK3-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META8]], !align [[META9]]2042// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined, i32 [[TMP12]], i32 [[TMP13]], ptr [[VEC2]], i32 [[TMP15]], ptr [[S_ARR3]], ptr [[TMP16]])2043// CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2044// CHECK3:       omp.inner.for.inc:2045// CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42046// CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 42047// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]2048// CHECK3-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 42049// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]2050// CHECK3:       omp.inner.for.end:2051// CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]2052// CHECK3:       omp.loop.exit:2053// CHECK3-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42054// CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 42055// CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]])2056// CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]2057// CHECK3-NEXT:    [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 02058// CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 22059// CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]2060// CHECK3:       arraydestroy.body:2061// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP21]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2062// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -12063// CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]2064// CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]2065// CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]2066// CHECK3:       arraydestroy.done10:2067// CHECK3-NEXT:    ret void2068//2069//2070// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St2071// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2072// CHECK3-NEXT:  entry:2073// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 42074// CHECK3-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 42075// CHECK3-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 42076// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 42077// CHECK3-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 42078// CHECK3-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 42079// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42080// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 42081// CHECK3-NEXT:    call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])2082// CHECK3-NEXT:    ret void2083//2084//2085// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined2086// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {2087// CHECK3-NEXT:  entry:2088// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 42089// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 42090// CHECK3-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 42091// CHECK3-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 42092// CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 42093// CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 42094// CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 42095// CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 42096// CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 42097// CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42098// CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 42099// CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 42100// CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 42101// CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42102// CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42103// CHECK3-NEXT:    [[VEC2:%.*]] = alloca [2 x i32], align 42104// CHECK3-NEXT:    [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 42105// CHECK3-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 42106// CHECK3-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 42107// CHECK3-NEXT:    [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 42108// CHECK3-NEXT:    [[_TMP7:%.*]] = alloca ptr, align 42109// CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 42110// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 42111// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 42112// CHECK3-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 42113// CHECK3-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 42114// CHECK3-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 42115// CHECK3-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 42116// CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 42117// CHECK3-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 42118// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]2119// CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]2120// CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]2121// CHECK3-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 42122// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 42123// CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 42124// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 42125// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 42126// CHECK3-NEXT:    store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 42127// CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 42128// CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 42129// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42130// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false)2131// CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 02132// CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 22133// CHECK3-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]2134// CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]2135// CHECK3:       omp.arraycpy.body:2136// CHECK3-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]2137// CHECK3-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]2138// CHECK3-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])2139// CHECK3-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])2140// CHECK3-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]2141// CHECK3-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 12142// CHECK3-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 12143// CHECK3-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]2144// CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]2145// CHECK3:       omp.arraycpy.done4:2146// CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]2147// CHECK3-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])2148// CHECK3-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP6]])2149// CHECK3-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]2150// CHECK3-NEXT:    store ptr [[VAR5]], ptr [[_TMP7]], align 42151// CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42152// CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 42153// CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2154// CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42155// CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 12156// CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2157// CHECK3:       cond.true:2158// CHECK3-NEXT:    br label [[COND_END:%.*]]2159// CHECK3:       cond.false:2160// CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42161// CHECK3-NEXT:    br label [[COND_END]]2162// CHECK3:       cond.end:2163// CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]2164// CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 42165// CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42166// CHECK3-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 42167// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2168// CHECK3:       omp.inner.for.cond:2169// CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42170// CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42171// CHECK3-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]2172// CHECK3-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]2173// CHECK3:       omp.inner.for.cond.cleanup:2174// CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]2175// CHECK3:       omp.inner.for.body:2176// CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42177// CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP14]], 12178// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]2179// CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 42180// CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 42181// CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 42182// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]]2183// CHECK3-NEXT:    store i32 [[TMP15]], ptr [[ARRAYIDX]], align 42184// CHECK3-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META8]], !align [[META9]]2185// CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I]], align 42186// CHECK3-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]]2187// CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP17]], i32 4, i1 false)2188// CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2189// CHECK3:       omp.body.continue:2190// CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2191// CHECK3:       omp.inner.for.inc:2192// CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42193// CHECK3-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP19]], 12194// CHECK3-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 42195// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]2196// CHECK3:       omp.inner.for.end:2197// CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]2198// CHECK3:       omp.loop.exit:2199// CHECK3-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 42200// CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 42201// CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]])2202// CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]2203// CHECK3-NEXT:    [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 02204// CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 22205// CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]2206// CHECK3:       arraydestroy.body:2207// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2208// CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -12209// CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]2210// CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]2211// CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]2212// CHECK3:       arraydestroy.done12:2213// CHECK3-NEXT:    ret void2214//2215//2216// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev2217// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2218// CHECK3-NEXT:  entry:2219// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 42220// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 42221// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42222// CHECK3-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]2223// CHECK3-NEXT:    ret void2224//2225//2226// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev2227// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2228// CHECK3-NEXT:  entry:2229// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 42230// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 42231// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42232// CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 02233// CHECK3-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 42234// CHECK3-NEXT:    store i32 [[TMP0]], ptr [[F]], align 42235// CHECK3-NEXT:    ret void2236//2237//2238// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei2239// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2240// CHECK3-NEXT:  entry:2241// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 42242// CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 42243// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 42244// CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 42245// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42246// CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 02247// CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42248// CHECK3-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 42249// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]2250// CHECK3-NEXT:    store i32 [[ADD]], ptr [[F]], align 42251// CHECK3-NEXT:    ret void2252//2253//2254// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St2255// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2256// CHECK3-NEXT:  entry:2257// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 42258// CHECK3-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 42259// CHECK3-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 42260// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 42261// CHECK3-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 42262// CHECK3-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 42263// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42264// CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 02265// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]2266// CHECK3-NEXT:    [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 02267// CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[F2]], align 42268// CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 02269// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 42270// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]2271// CHECK3-NEXT:    store i32 [[ADD]], ptr [[F]], align 42272// CHECK3-NEXT:    ret void2273//2274//2275// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev2276// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2277// CHECK3-NEXT:  entry:2278// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 42279// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 42280// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42281// CHECK3-NEXT:    ret void2282//2283//2284// CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp2285// CHECK3-SAME: () #[[ATTR0]] {2286// CHECK3-NEXT:  entry:2287// CHECK3-NEXT:    call void @__cxx_global_var_init()2288// CHECK3-NEXT:    call void @__cxx_global_var_init.1()2289// CHECK3-NEXT:    call void @__cxx_global_var_init.2()2290// CHECK3-NEXT:    ret void2291//2292//2293// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init2294// CHECK9-SAME: () #[[ATTR0:[0-9]+]] {2295// CHECK9-NEXT:  entry:2296// CHECK9-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)2297// CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]2298// CHECK9-NEXT:    ret void2299//2300//2301// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev2302// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {2303// CHECK9-NEXT:  entry:2304// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82305// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82306// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82307// CHECK9-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])2308// CHECK9-NEXT:    ret void2309//2310//2311// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev2312// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2313// CHECK9-NEXT:  entry:2314// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82315// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82316// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82317// CHECK9-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]2318// CHECK9-NEXT:    ret void2319//2320//2321// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev2322// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2323// CHECK9-NEXT:  entry:2324// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82325// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82326// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82327// CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02328// CHECK9-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 42329// CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float2330// CHECK9-NEXT:    store float [[CONV]], ptr [[F]], align 42331// CHECK9-NEXT:    ret void2332//2333//2334// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev2335// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2336// CHECK9-NEXT:  entry:2337// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82338// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82339// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82340// CHECK9-NEXT:    ret void2341//2342//2343// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.12344// CHECK9-SAME: () #[[ATTR0]] {2345// CHECK9-NEXT:  entry:2346// CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)2347// CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)2348// CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]2349// CHECK9-NEXT:    ret void2350//2351//2352// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef2353// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2354// CHECK9-NEXT:  entry:2355// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82356// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca float, align 42357// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82358// CHECK9-NEXT:    store float [[A]], ptr [[A_ADDR]], align 42359// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82360// CHECK9-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42361// CHECK9-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])2362// CHECK9-NEXT:    ret void2363//2364//2365// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor2366// CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {2367// CHECK9-NEXT:  entry:2368// CHECK9-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 82369// CHECK9-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 82370// CHECK9-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]2371// CHECK9:       arraydestroy.body:2372// CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2373// CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -12374// CHECK9-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]2375// CHECK9-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr2376// CHECK9-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]2377// CHECK9:       arraydestroy.done1:2378// CHECK9-NEXT:    ret void2379//2380//2381// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef2382// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2383// CHECK9-NEXT:  entry:2384// CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 82385// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca float, align 42386// CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 82387// CHECK9-NEXT:    store float [[A]], ptr [[A_ADDR]], align 42388// CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82389// CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02390// CHECK9-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42391// CHECK9-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 42392// CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float2393// CHECK9-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]2394// CHECK9-NEXT:    store float [[ADD]], ptr [[F]], align 42395// CHECK9-NEXT:    ret void2396//2397//2398// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.22399// CHECK9-SAME: () #[[ATTR0]] {2400// CHECK9-NEXT:  entry:2401// CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)2402// CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]2403// CHECK9-NEXT:    ret void2404//2405//2406// CHECK9-LABEL: define {{[^@]+}}@main2407// CHECK9-SAME: () #[[ATTR3:[0-9]+]] {2408// CHECK9-NEXT:  entry:2409// CHECK9-NEXT:    [[RETVAL:%.*]] = alloca i32, align 42410// CHECK9-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 12411// CHECK9-NEXT:    store i32 0, ptr [[RETVAL]], align 42412// CHECK9-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])2413// CHECK9-NEXT:    ret i32 02414//2415//2416// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l752417// CHECK9-SAME: (i64 noundef [[G:%.*]], i64 noundef [[SIVAR:%.*]], i64 noundef [[G1:%.*]]) #[[ATTR4:[0-9]+]] {2418// CHECK9-NEXT:  entry:2419// CHECK9-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 82420// CHECK9-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 82421// CHECK9-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 82422// CHECK9-NEXT:    [[TMP:%.*]] = alloca ptr, align 82423// CHECK9-NEXT:    [[G_CASTED:%.*]] = alloca i64, align 82424// CHECK9-NEXT:    [[G1_CASTED:%.*]] = alloca i64, align 82425// CHECK9-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 82426// CHECK9-NEXT:    store i64 [[G]], ptr [[G_ADDR]], align 82427// CHECK9-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 82428// CHECK9-NEXT:    store i64 [[G1]], ptr [[G1_ADDR]], align 82429// CHECK9-NEXT:    store ptr [[G1_ADDR]], ptr [[TMP]], align 82430// CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[G_ADDR]], align 42431// CHECK9-NEXT:    store i32 [[TMP0]], ptr [[G_CASTED]], align 42432// CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 82433// CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]2434// CHECK9-NEXT:    [[TMP3:%.*]] = load volatile i32, ptr [[TMP2]], align 42435// CHECK9-NEXT:    store i32 [[TMP3]], ptr [[G1_CASTED]], align 42436// CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[G1_CASTED]], align 82437// CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 42438// CHECK9-NEXT:    store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 42439// CHECK9-NEXT:    [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 82440// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined, i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])2441// CHECK9-NEXT:    ret void2442//2443//2444// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined2445// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] {2446// CHECK9-NEXT:  entry:2447// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82448// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82449// CHECK9-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 82450// CHECK9-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 82451// CHECK9-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 82452// CHECK9-NEXT:    [[TMP:%.*]] = alloca ptr, align 82453// CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42454// CHECK9-NEXT:    [[_TMP1:%.*]] = alloca i32, align 42455// CHECK9-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 42456// CHECK9-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 42457// CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42458// CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42459// CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 42460// CHECK9-NEXT:    [[G_CASTED:%.*]] = alloca i64, align 82461// CHECK9-NEXT:    [[G1_CASTED:%.*]] = alloca i64, align 82462// CHECK9-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 82463// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82464// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82465// CHECK9-NEXT:    store i64 [[G]], ptr [[G_ADDR]], align 82466// CHECK9-NEXT:    store i64 [[G1]], ptr [[G1_ADDR]], align 82467// CHECK9-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 82468// CHECK9-NEXT:    store ptr [[G1_ADDR]], ptr [[TMP]], align 82469// CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 42470// CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 42471// CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 42472// CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42473// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82474// CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42475// CHECK9-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2476// CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 42477// CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 12478// CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2479// CHECK9:       cond.true:2480// CHECK9-NEXT:    br label [[COND_END:%.*]]2481// CHECK9:       cond.false:2482// CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 42483// CHECK9-NEXT:    br label [[COND_END]]2484// CHECK9:       cond.end:2485// CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2486// CHECK9-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 42487// CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 42488// CHECK9-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42489// CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2490// CHECK9:       omp.inner.for.cond:2491// CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42492// CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 42493// CHECK9-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2494// CHECK9-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2495// CHECK9:       omp.inner.for.body:2496// CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 42497// CHECK9-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i642498// CHECK9-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 42499// CHECK9-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i642500// CHECK9-NEXT:    [[TMP11:%.*]] = load i32, ptr [[G_ADDR]], align 42501// CHECK9-NEXT:    store i32 [[TMP11]], ptr [[G_CASTED]], align 42502// CHECK9-NEXT:    [[TMP12:%.*]] = load i64, ptr [[G_CASTED]], align 82503// CHECK9-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]]2504// CHECK9-NEXT:    [[TMP14:%.*]] = load volatile i32, ptr [[TMP13]], align 42505// CHECK9-NEXT:    store i32 [[TMP14]], ptr [[G1_CASTED]], align 42506// CHECK9-NEXT:    [[TMP15:%.*]] = load i64, ptr [[G1_CASTED]], align 82507// CHECK9-NEXT:    [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 42508// CHECK9-NEXT:    store i32 [[TMP16]], ptr [[SIVAR_CASTED]], align 42509// CHECK9-NEXT:    [[TMP17:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 82510// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]])2511// CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2512// CHECK9:       omp.inner.for.inc:2513// CHECK9-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42514// CHECK9-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 42515// CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]2516// CHECK9-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 42517// CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]]2518// CHECK9:       omp.inner.for.end:2519// CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]2520// CHECK9:       omp.loop.exit:2521// CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2522// CHECK9-NEXT:    ret void2523//2524//2525// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined.omp_outlined2526// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] {2527// CHECK9-NEXT:  entry:2528// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82529// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82530// CHECK9-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 82531// CHECK9-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 82532// CHECK9-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 82533// CHECK9-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 82534// CHECK9-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 82535// CHECK9-NEXT:    [[TMP:%.*]] = alloca ptr, align 82536// CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 42537// CHECK9-NEXT:    [[_TMP1:%.*]] = alloca i32, align 42538// CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 42539// CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 42540// CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42541// CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42542// CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 42543// CHECK9-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 82544// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82545// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82546// CHECK9-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 82547// CHECK9-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 82548// CHECK9-NEXT:    store i64 [[G]], ptr [[G_ADDR]], align 82549// CHECK9-NEXT:    store i64 [[G1]], ptr [[G1_ADDR]], align 82550// CHECK9-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 82551// CHECK9-NEXT:    store ptr [[G1_ADDR]], ptr [[TMP]], align 82552// CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 42553// CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 42554// CHECK9-NEXT:    [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 82555// CHECK9-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP0]] to i322556// CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 82557// CHECK9-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP1]] to i322558// CHECK9-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 42559// CHECK9-NEXT:    store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 42560// CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 42561// CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 42562// CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82563// CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 42564// CHECK9-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2565// CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42566// CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 12567// CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2568// CHECK9:       cond.true:2569// CHECK9-NEXT:    br label [[COND_END:%.*]]2570// CHECK9:       cond.false:2571// CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42572// CHECK9-NEXT:    br label [[COND_END]]2573// CHECK9:       cond.end:2574// CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]2575// CHECK9-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 42576// CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42577// CHECK9-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 42578// CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]2579// CHECK9:       omp.inner.for.cond:2580// CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42581// CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42582// CHECK9-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]2583// CHECK9-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2584// CHECK9:       omp.inner.for.body:2585// CHECK9-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42586// CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 12587// CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]2588// CHECK9-NEXT:    store i32 [[ADD]], ptr [[I]], align 42589// CHECK9-NEXT:    store i32 1, ptr [[G_ADDR]], align 42590// CHECK9-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]]2591// CHECK9-NEXT:    store volatile i32 1, ptr [[TMP10]], align 42592// CHECK9-NEXT:    store i32 2, ptr [[SIVAR_ADDR]], align 42593// CHECK9-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 02594// CHECK9-NEXT:    store ptr [[G_ADDR]], ptr [[TMP11]], align 82595// CHECK9-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 12596// CHECK9-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]]2597// CHECK9-NEXT:    store ptr [[TMP13]], ptr [[TMP12]], align 82598// CHECK9-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 22599// CHECK9-NEXT:    store ptr [[SIVAR_ADDR]], ptr [[TMP14]], align 82600// CHECK9-NEXT:    call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]])2601// CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]2602// CHECK9:       omp.body.continue:2603// CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]2604// CHECK9:       omp.inner.for.inc:2605// CHECK9-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 42606// CHECK9-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP15]], 12607// CHECK9-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 42608// CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]]2609// CHECK9:       omp.inner.for.end:2610// CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]2611// CHECK9:       omp.loop.exit:2612// CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]])2613// CHECK9-NEXT:    ret void2614//2615//2616// CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_firstprivate_codegen.cpp2617// CHECK9-SAME: () #[[ATTR0]] {2618// CHECK9-NEXT:  entry:2619// CHECK9-NEXT:    call void @__cxx_global_var_init()2620// CHECK9-NEXT:    call void @__cxx_global_var_init.1()2621// CHECK9-NEXT:    call void @__cxx_global_var_init.2()2622// CHECK9-NEXT:    ret void2623//2624