1397 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s4// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK36// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s7// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK38 9// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"10// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s11// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"12// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"13// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s14// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"15 16// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK917// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s18// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK919 20// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"21// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s22// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"23 24// expected-no-diagnostics25#ifndef HEADER26#define HEADER27 28struct St {29 int a, b;30 St() : a(0), b(0) {}31 St(const St &st) : a(st.a + st.b), b(0) {}32 ~St() {}33};34 35volatile int g = 1212;36volatile int &g1 = g;37 38template <class T>39struct S {40 T f;41 S(T a) : f(a + g) {}42 S() : f(g) {}43 S(const S &s, St t = St()) : f(s.f + t.a) {}44 operator T() { return T(); }45 ~S() {}46};47 48 49template <typename T>50T tmain() {51 S<T> test;52 T t_var = T();53 T vec[] = {1, 2};54 S<T> s_arr[] = {1, 2};55 S<T> &var = test;56#pragma omp target57#pragma omp teams distribute private(t_var, vec, s_arr, var)58 for (int i = 0; i < 2; ++i) {59 vec[i] = t_var;60 s_arr[i] = var;61 }62 return T();63}64 65S<float> test;66int t_var = 333;67int vec[] = {1, 2};68S<float> s_arr[] = {1, 2};69S<float> var(3);70 71int main() {72 static int sivar;73#ifdef LAMBDA74 [&]() {75#pragma omp target76#pragma omp teams distribute private(g, g1, sivar)77 for (int i = 0; i < 2; ++i) {78 79 // Skip global, bound tid and loop vars80 g = 1;81 g1 = 1;82 sivar = 2;83 [&]() {84 g = 2;85 g1 = 2;86 sivar = 4;87 88 }();89 }90 }();91 return 0;92#else93#pragma omp target94#pragma omp teams distribute private(t_var, vec, s_arr, var, sivar)95 for (int i = 0; i < 2; ++i) {96 vec[i] = t_var;97 s_arr[i] = var;98 sivar += i;99 }100 return tmain<int>();101#endif102}103 104 105 106// Skip global, bound tid and loop vars107 108// private(s_arr)109 110// private(var)111 112 113 114 115 116// Skip global, bound tid and loop vars117 118// private(s_arr)119 120 121// private(var)122 123 124#endif125// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init126// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {127// CHECK1-NEXT: entry:128// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)129// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]130// CHECK1-NEXT: ret void131//132//133// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev134// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {135// CHECK1-NEXT: entry:136// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8137// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8138// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8139// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])140// CHECK1-NEXT: ret void141//142//143// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev144// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {145// CHECK1-NEXT: entry:146// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8147// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8148// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8149// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]150// CHECK1-NEXT: ret void151//152//153// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev154// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {155// CHECK1-NEXT: entry:156// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8157// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8158// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8159// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0160// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4161// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float162// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4163// CHECK1-NEXT: ret void164//165//166// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev167// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {168// CHECK1-NEXT: entry:169// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8170// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8171// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8172// CHECK1-NEXT: ret void173//174//175// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1176// CHECK1-SAME: () #[[ATTR0]] {177// CHECK1-NEXT: entry:178// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)179// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)180// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]181// CHECK1-NEXT: ret void182//183//184// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef185// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {186// CHECK1-NEXT: entry:187// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8188// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4189// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8190// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4191// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8192// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4193// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])194// CHECK1-NEXT: ret void195//196//197// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor198// CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {199// CHECK1-NEXT: entry:200// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8201// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8202// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]203// CHECK1: arraydestroy.body:204// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]205// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1206// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]207// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr208// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]209// CHECK1: arraydestroy.done1:210// CHECK1-NEXT: ret void211//212//213// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef214// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {215// CHECK1-NEXT: entry:216// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8217// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4218// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8219// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4220// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8221// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0222// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4223// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4224// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float225// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]226// CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4227// CHECK1-NEXT: ret void228//229//230// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2231// CHECK1-SAME: () #[[ATTR0]] {232// CHECK1-NEXT: entry:233// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)234// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]235// CHECK1-NEXT: ret void236//237//238// CHECK1-LABEL: define {{[^@]+}}@main239// CHECK1-SAME: () #[[ATTR3:[0-9]+]] {240// CHECK1-NEXT: entry:241// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4242// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4243// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8244// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4245// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0246// CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4247// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1248// CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4249// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2250// CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8251// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3252// CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8253// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4254// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8255// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5256// CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8257// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6258// CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8259// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7260// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8261// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8262// CHECK1-NEXT: store i64 2, ptr [[TMP8]], align 8263// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9264// CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8265// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10266// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4267// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11268// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4269// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12270// CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4271// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.region_id, ptr [[KERNEL_ARGS]])272// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0273// CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]274// CHECK1: omp_offload.failed:275// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93() #[[ATTR2]]276// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]277// CHECK1: omp_offload.cont:278// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()279// CHECK1-NEXT: ret i32 [[CALL]]280//281//282// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93283// CHECK1-SAME: () #[[ATTR4:[0-9]+]] {284// CHECK1-NEXT: entry:285// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.omp_outlined)286// CHECK1-NEXT: ret void287//288//289// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.omp_outlined290// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {291// CHECK1-NEXT: entry:292// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8293// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8294// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4295// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4296// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4297// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4298// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4299// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4300// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4301// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4302// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4303// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4304// CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4305// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4306// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8307// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8308// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4309// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4310// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4311// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4312// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0313// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2314// CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]315// CHECK1: arrayctor.loop:316// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]317// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])318// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1319// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]320// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]321// CHECK1: arrayctor.cont:322// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])323// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8324// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4325// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)326// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4327// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1328// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]329// CHECK1: cond.true:330// CHECK1-NEXT: br label [[COND_END:%.*]]331// CHECK1: cond.false:332// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4333// CHECK1-NEXT: br label [[COND_END]]334// CHECK1: cond.end:335// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]336// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4337// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4338// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4339// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]340// CHECK1: omp.inner.for.cond:341// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4342// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4343// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]344// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]345// CHECK1: omp.inner.for.cond.cleanup:346// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]347// CHECK1: omp.inner.for.body:348// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4349// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1350// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]351// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4352// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4353// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4354// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64355// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]356// CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4357// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4358// CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64359// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]]360// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false)361// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4362// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4363// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]364// CHECK1-NEXT: store i32 [[ADD4]], ptr [[SIVAR]], align 4365// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]366// CHECK1: omp.body.continue:367// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]368// CHECK1: omp.inner.for.inc:369// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4370// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1371// CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4372// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]373// CHECK1: omp.inner.for.end:374// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]375// CHECK1: omp.loop.exit:376// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8377// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4378// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]])379// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]380// CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0381// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 2382// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]383// CHECK1: arraydestroy.body:384// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]385// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1386// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]387// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]388// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]389// CHECK1: arraydestroy.done7:390// CHECK1-NEXT: ret void391//392//393// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v394// CHECK1-SAME: () #[[ATTR1]] comdat {395// CHECK1-NEXT: entry:396// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4397// CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4398// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4399// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4400// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4401// CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8402// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4403// CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8404// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8405// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])406// CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4407// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)408// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1)409// CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1410// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)411// CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8412// CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8413// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0414// CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4415// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1416// CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4417// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2418// CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8419// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3420// CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8421// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4422// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8423// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5424// CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8425// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6426// CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8427// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7428// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8429// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8430// CHECK1-NEXT: store i64 2, ptr [[TMP8]], align 8431// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9432// CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8433// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10434// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4435// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11436// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4437// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12438// CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4439// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])440// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0441// CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]442// CHECK1: omp_offload.failed:443// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]444// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]445// CHECK1: omp_offload.cont:446// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4447// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0448// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2449// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]450// CHECK1: arraydestroy.body:451// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]452// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1453// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]454// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]455// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]456// CHECK1: arraydestroy.done2:457// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]458// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4459// CHECK1-NEXT: ret i32 [[TMP16]]460//461//462// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev463// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {464// CHECK1-NEXT: entry:465// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8466// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8467// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8468// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])469// CHECK1-NEXT: ret void470//471//472// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei473// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {474// CHECK1-NEXT: entry:475// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8476// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4477// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8478// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4479// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8480// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4481// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])482// CHECK1-NEXT: ret void483//484//485// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56486// CHECK1-SAME: () #[[ATTR4]] {487// CHECK1-NEXT: entry:488// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined)489// CHECK1-NEXT: ret void490//491//492// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined493// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {494// CHECK1-NEXT: entry:495// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8496// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8497// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4498// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4499// CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8500// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4501// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4502// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4503// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4504// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4505// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4506// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4507// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4508// CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8509// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4510// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8511// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8512// CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8513// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4514// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4515// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4516// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4517// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0518// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2519// CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]520// CHECK1: arrayctor.loop:521// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]522// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])523// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1524// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]525// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]526// CHECK1: arrayctor.cont:527// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])528// CHECK1-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 8529// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8530// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4531// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)532// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4533// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1534// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]535// CHECK1: cond.true:536// CHECK1-NEXT: br label [[COND_END:%.*]]537// CHECK1: cond.false:538// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4539// CHECK1-NEXT: br label [[COND_END]]540// CHECK1: cond.end:541// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]542// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4543// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4544// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4545// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]546// CHECK1: omp.inner.for.cond:547// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4548// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4549// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]550// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]551// CHECK1: omp.inner.for.cond.cleanup:552// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]553// CHECK1: omp.inner.for.body:554// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4555// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1556// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]557// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4558// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4559// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4560// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64561// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]562// CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4563// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8564// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4565// CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64566// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]]567// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false)568// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]569// CHECK1: omp.body.continue:570// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]571// CHECK1: omp.inner.for.inc:572// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4573// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1574// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4575// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]576// CHECK1: omp.inner.for.end:577// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]578// CHECK1: omp.loop.exit:579// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8580// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4581// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]])582// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]583// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0584// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2585// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]586// CHECK1: arraydestroy.body:587// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]588// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1589// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]590// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]591// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]592// CHECK1: arraydestroy.done8:593// CHECK1-NEXT: ret void594//595//596// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev597// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {598// CHECK1-NEXT: entry:599// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8600// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8601// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8602// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]603// CHECK1-NEXT: ret void604//605//606// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev607// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {608// CHECK1-NEXT: entry:609// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8610// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8611// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8612// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0613// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4614// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4615// CHECK1-NEXT: ret void616//617//618// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei619// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {620// CHECK1-NEXT: entry:621// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8622// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4623// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8624// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4625// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8626// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0627// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4628// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4629// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]630// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4631// CHECK1-NEXT: ret void632//633//634// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev635// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {636// CHECK1-NEXT: entry:637// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8638// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8639// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8640// CHECK1-NEXT: ret void641//642//643// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp644// CHECK1-SAME: () #[[ATTR0]] {645// CHECK1-NEXT: entry:646// CHECK1-NEXT: call void @__cxx_global_var_init()647// CHECK1-NEXT: call void @__cxx_global_var_init.1()648// CHECK1-NEXT: call void @__cxx_global_var_init.2()649// CHECK1-NEXT: ret void650//651//652// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init653// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {654// CHECK3-NEXT: entry:655// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)656// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]657// CHECK3-NEXT: ret void658//659//660// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev661// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {662// CHECK3-NEXT: entry:663// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4664// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4665// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4666// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])667// CHECK3-NEXT: ret void668//669//670// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev671// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {672// CHECK3-NEXT: entry:673// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4674// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4675// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4676// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]677// CHECK3-NEXT: ret void678//679//680// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev681// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {682// CHECK3-NEXT: entry:683// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4684// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4685// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4686// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0687// CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4688// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float689// CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4690// CHECK3-NEXT: ret void691//692//693// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev694// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {695// CHECK3-NEXT: entry:696// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4697// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4698// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4699// CHECK3-NEXT: ret void700//701//702// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1703// CHECK3-SAME: () #[[ATTR0]] {704// CHECK3-NEXT: entry:705// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)706// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00)707// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]708// CHECK3-NEXT: ret void709//710//711// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef712// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {713// CHECK3-NEXT: entry:714// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4715// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4716// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4717// CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4718// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4719// CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4720// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])721// CHECK3-NEXT: ret void722//723//724// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor725// CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {726// CHECK3-NEXT: entry:727// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4728// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4729// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]730// CHECK3: arraydestroy.body:731// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]732// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1733// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]734// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr735// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]736// CHECK3: arraydestroy.done1:737// CHECK3-NEXT: ret void738//739//740// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef741// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {742// CHECK3-NEXT: entry:743// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4744// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4745// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4746// CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4747// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4748// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0749// CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4750// CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4751// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float752// CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]753// CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4754// CHECK3-NEXT: ret void755//756//757// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2758// CHECK3-SAME: () #[[ATTR0]] {759// CHECK3-NEXT: entry:760// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)761// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]762// CHECK3-NEXT: ret void763//764//765// CHECK3-LABEL: define {{[^@]+}}@main766// CHECK3-SAME: () #[[ATTR3:[0-9]+]] {767// CHECK3-NEXT: entry:768// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4769// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4770// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8771// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4772// CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0773// CHECK3-NEXT: store i32 3, ptr [[TMP0]], align 4774// CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1775// CHECK3-NEXT: store i32 0, ptr [[TMP1]], align 4776// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2777// CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4778// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3779// CHECK3-NEXT: store ptr null, ptr [[TMP3]], align 4780// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4781// CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4782// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5783// CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4784// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6785// CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4786// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7787// CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4788// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8789// CHECK3-NEXT: store i64 2, ptr [[TMP8]], align 8790// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9791// CHECK3-NEXT: store i64 0, ptr [[TMP9]], align 8792// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10793// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4794// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11795// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4796// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12797// CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4798// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.region_id, ptr [[KERNEL_ARGS]])799// CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0800// CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]801// CHECK3: omp_offload.failed:802// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93() #[[ATTR2]]803// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]804// CHECK3: omp_offload.cont:805// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()806// CHECK3-NEXT: ret i32 [[CALL]]807//808//809// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93810// CHECK3-SAME: () #[[ATTR4:[0-9]+]] {811// CHECK3-NEXT: entry:812// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.omp_outlined)813// CHECK3-NEXT: ret void814//815//816// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.omp_outlined817// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {818// CHECK3-NEXT: entry:819// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4820// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4821// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4822// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4823// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4824// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4825// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4826// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4827// CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4828// CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4829// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4830// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4831// CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4832// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4833// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4834// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4835// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4836// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4837// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4838// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4839// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0840// CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2841// CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]842// CHECK3: arrayctor.loop:843// CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]844// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])845// CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1846// CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]847// CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]848// CHECK3: arrayctor.cont:849// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])850// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4851// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4852// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)853// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4854// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1855// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]856// CHECK3: cond.true:857// CHECK3-NEXT: br label [[COND_END:%.*]]858// CHECK3: cond.false:859// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4860// CHECK3-NEXT: br label [[COND_END]]861// CHECK3: cond.end:862// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]863// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4864// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4865// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4866// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]867// CHECK3: omp.inner.for.cond:868// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4869// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4870// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]871// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]872// CHECK3: omp.inner.for.cond.cleanup:873// CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]874// CHECK3: omp.inner.for.body:875// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4876// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1877// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]878// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4879// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4880// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4881// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]]882// CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4883// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4884// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]]885// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false)886// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4887// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4888// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]889// CHECK3-NEXT: store i32 [[ADD3]], ptr [[SIVAR]], align 4890// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]891// CHECK3: omp.body.continue:892// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]893// CHECK3: omp.inner.for.inc:894// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4895// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1896// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4897// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]898// CHECK3: omp.inner.for.end:899// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]900// CHECK3: omp.loop.exit:901// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4902// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4903// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]])904// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]905// CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0906// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2907// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]908// CHECK3: arraydestroy.body:909// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]910// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1911// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]912// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]913// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]914// CHECK3: arraydestroy.done6:915// CHECK3-NEXT: ret void916//917//918// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v919// CHECK3-SAME: () #[[ATTR1]] comdat {920// CHECK3-NEXT: entry:921// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4922// CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4923// CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4924// CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4925// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4926// CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4927// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4928// CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4929// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8930// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])931// CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4932// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)933// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)934// CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1935// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)936// CHECK3-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4937// CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4938// CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0939// CHECK3-NEXT: store i32 3, ptr [[TMP0]], align 4940// CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1941// CHECK3-NEXT: store i32 0, ptr [[TMP1]], align 4942// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2943// CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4944// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3945// CHECK3-NEXT: store ptr null, ptr [[TMP3]], align 4946// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4947// CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4948// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5949// CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4950// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6951// CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4952// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7953// CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4954// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8955// CHECK3-NEXT: store i64 2, ptr [[TMP8]], align 8956// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9957// CHECK3-NEXT: store i64 0, ptr [[TMP9]], align 8958// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10959// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4960// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11961// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4962// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12963// CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4964// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])965// CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0966// CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]967// CHECK3: omp_offload.failed:968// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]969// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]970// CHECK3: omp_offload.cont:971// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4972// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0973// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2974// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]975// CHECK3: arraydestroy.body:976// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]977// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1978// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]979// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]980// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]981// CHECK3: arraydestroy.done2:982// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]983// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4984// CHECK3-NEXT: ret i32 [[TMP16]]985//986//987// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev988// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {989// CHECK3-NEXT: entry:990// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4991// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4992// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4993// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])994// CHECK3-NEXT: ret void995//996//997// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei998// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {999// CHECK3-NEXT: entry:1000// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41001// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 41002// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41003// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 41004// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41005// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41006// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])1007// CHECK3-NEXT: ret void1008//1009//1010// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l561011// CHECK3-SAME: () #[[ATTR4]] {1012// CHECK3-NEXT: entry:1013// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined)1014// CHECK3-NEXT: ret void1015//1016//1017// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined1018// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {1019// CHECK3-NEXT: entry:1020// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41021// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41022// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41023// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 41024// CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 41025// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41026// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41027// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41028// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41029// CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 41030// CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 41031// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 41032// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41033// CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 41034// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 41035// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41036// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41037// CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 41038// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41039// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 41040// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41041// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41042// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01043// CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 21044// CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]1045// CHECK3: arrayctor.loop:1046// CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]1047// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])1048// CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 11049// CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]1050// CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]1051// CHECK3: arrayctor.cont:1052// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])1053// CHECK3-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 41054// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41055// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41056// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1057// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41058// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 11059// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1060// CHECK3: cond.true:1061// CHECK3-NEXT: br label [[COND_END:%.*]]1062// CHECK3: cond.false:1063// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41064// CHECK3-NEXT: br label [[COND_END]]1065// CHECK3: cond.end:1066// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]1067// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41068// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41069// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 41070// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1071// CHECK3: omp.inner.for.cond:1072// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41073// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41074// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]1075// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1076// CHECK3: omp.inner.for.cond.cleanup:1077// CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]1078// CHECK3: omp.inner.for.body:1079// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41080// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 11081// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1082// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 41083// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 41084// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 41085// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]]1086// CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 41087// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 41088// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 41089// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]]1090// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false)1091// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1092// CHECK3: omp.body.continue:1093// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1094// CHECK3: omp.inner.for.inc:1095// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41096// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], 11097// CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 41098// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]1099// CHECK3: omp.inner.for.end:1100// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1101// CHECK3: omp.loop.exit:1102// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41103// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 41104// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]])1105// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]1106// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01107// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 21108// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1109// CHECK3: arraydestroy.body:1110// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1111// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11112// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1113// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]1114// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]1115// CHECK3: arraydestroy.done7:1116// CHECK3-NEXT: ret void1117//1118//1119// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev1120// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1121// CHECK3-NEXT: entry:1122// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41123// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41124// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41125// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]1126// CHECK3-NEXT: ret void1127//1128//1129// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev1130// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1131// CHECK3-NEXT: entry:1132// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41133// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41134// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41135// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01136// CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 41137// CHECK3-NEXT: store i32 [[TMP0]], ptr [[F]], align 41138// CHECK3-NEXT: ret void1139//1140//1141// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei1142// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1143// CHECK3-NEXT: entry:1144// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41145// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 41146// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41147// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 41148// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41149// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01150// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41151// CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 41152// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]1153// CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 41154// CHECK3-NEXT: ret void1155//1156//1157// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev1158// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1159// CHECK3-NEXT: entry:1160// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41161// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41162// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41163// CHECK3-NEXT: ret void1164//1165//1166// CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp1167// CHECK3-SAME: () #[[ATTR0]] {1168// CHECK3-NEXT: entry:1169// CHECK3-NEXT: call void @__cxx_global_var_init()1170// CHECK3-NEXT: call void @__cxx_global_var_init.1()1171// CHECK3-NEXT: call void @__cxx_global_var_init.2()1172// CHECK3-NEXT: ret void1173//1174//1175// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init1176// CHECK9-SAME: () #[[ATTR0:[0-9]+]] {1177// CHECK9-NEXT: entry:1178// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)1179// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]1180// CHECK9-NEXT: ret void1181//1182//1183// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev1184// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {1185// CHECK9-NEXT: entry:1186// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81187// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81188// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81189// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1190// CHECK9-NEXT: ret void1191//1192//1193// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev1194// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1195// CHECK9-NEXT: entry:1196// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81197// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81198// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81199// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]1200// CHECK9-NEXT: ret void1201//1202//1203// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev1204// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1205// CHECK9-NEXT: entry:1206// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81207// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81208// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81209// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01210// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 41211// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float1212// CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 41213// CHECK9-NEXT: ret void1214//1215//1216// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev1217// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1218// CHECK9-NEXT: entry:1219// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81220// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81221// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81222// CHECK9-NEXT: ret void1223//1224//1225// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.11226// CHECK9-SAME: () #[[ATTR0]] {1227// CHECK9-NEXT: entry:1228// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)1229// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)1230// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]1231// CHECK9-NEXT: ret void1232//1233//1234// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef1235// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1236// CHECK9-NEXT: entry:1237// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81238// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 41239// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81240// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 41241// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81242// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41243// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])1244// CHECK9-NEXT: ret void1245//1246//1247// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor1248// CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {1249// CHECK9-NEXT: entry:1250// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 81251// CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 81252// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1253// CHECK9: arraydestroy.body:1254// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1255// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11256// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1257// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr1258// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]1259// CHECK9: arraydestroy.done1:1260// CHECK9-NEXT: ret void1261//1262//1263// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef1264// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1265// CHECK9-NEXT: entry:1266// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81267// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 41268// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81269// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 41270// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81271// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01272// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41273// CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 41274// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float1275// CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]1276// CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 41277// CHECK9-NEXT: ret void1278//1279//1280// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.21281// CHECK9-SAME: () #[[ATTR0]] {1282// CHECK9-NEXT: entry:1283// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)1284// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]1285// CHECK9-NEXT: ret void1286//1287//1288// CHECK9-LABEL: define {{[^@]+}}@main1289// CHECK9-SAME: () #[[ATTR3:[0-9]+]] {1290// CHECK9-NEXT: entry:1291// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 41292// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 11293// CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 41294// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])1295// CHECK9-NEXT: ret i32 01296//1297//1298// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l751299// CHECK9-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR4:[0-9]+]] {1300// CHECK9-NEXT: entry:1301// CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 81302// CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 81303// CHECK9-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 81304// CHECK9-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 81305// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined)1306// CHECK9-NEXT: ret void1307//1308//1309// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined1310// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {1311// CHECK9-NEXT: entry:1312// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 81313// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 81314// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41315// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 41316// CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 81317// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41318// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41319// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41320// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41321// CHECK9-NEXT: [[G:%.*]] = alloca i32, align 41322// CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 41323// CHECK9-NEXT: [[_TMP2:%.*]] = alloca ptr, align 81324// CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 41325// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 41326// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 81327// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 81328// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 81329// CHECK9-NEXT: store ptr undef, ptr [[_TMP1]], align 81330// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41331// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 41332// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41333// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41334// CHECK9-NEXT: store ptr [[G1]], ptr [[_TMP2]], align 81335// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 81336// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 41337// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1338// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41339// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 11340// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1341// CHECK9: cond.true:1342// CHECK9-NEXT: br label [[COND_END:%.*]]1343// CHECK9: cond.false:1344// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41345// CHECK9-NEXT: br label [[COND_END]]1346// CHECK9: cond.end:1347// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]1348// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41349// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41350// CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 41351// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1352// CHECK9: omp.inner.for.cond:1353// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41354// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41355// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]1356// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1357// CHECK9: omp.inner.for.body:1358// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41359// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 11360// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1361// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 41362// CHECK9-NEXT: store i32 1, ptr [[G]], align 41363// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 81364// CHECK9-NEXT: store volatile i32 1, ptr [[TMP8]], align 41365// CHECK9-NEXT: store i32 2, ptr [[SIVAR]], align 41366// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 01367// CHECK9-NEXT: store ptr [[G]], ptr [[TMP9]], align 81368// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 11369// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 81370// CHECK9-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 81371// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 21372// CHECK9-NEXT: store ptr [[SIVAR]], ptr [[TMP12]], align 81373// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]])1374// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1375// CHECK9: omp.body.continue:1376// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1377// CHECK9: omp.inner.for.inc:1378// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 41379// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 11380// CHECK9-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 41381// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]1382// CHECK9: omp.inner.for.end:1383// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1384// CHECK9: omp.loop.exit:1385// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])1386// CHECK9-NEXT: ret void1387//1388//1389// CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp1390// CHECK9-SAME: () #[[ATTR0]] {1391// CHECK9-NEXT: entry:1392// CHECK9-NEXT: call void @__cxx_global_var_init()1393// CHECK9-NEXT: call void @__cxx_global_var_init.1()1394// CHECK9-NEXT: call void @__cxx_global_var_init.2()1395// CHECK9-NEXT: ret void1396//1397