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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// expected-no-diagnostics3#ifndef HEADER4#define HEADER5 6// Test host codegen.7// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK18// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s9// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK110// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK311// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s12// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK313 14// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK515// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s16// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK517// RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK718// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s19// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK720#ifdef CK121 22template <typename T, int X, long long Y>23struct SS{24  T a[X][Y];25 26  int foo(void) {27 28    #pragma omp target29    #pragma omp teams distribute simd collapse(2)30    for(int i = 0; i < X; i++) {31      for(int j = 0; j < Y; j++) {32        a[i][j] = (T)0;33      }34    }35 36    // discard loop variables not needed here37 38    return a[0][0];39  }40};41 42int teams_template_struct(void) {43  SS<int, 123, 456> V;44  return V.foo();45 46}47 48#endif // CK149 50// Test host codegen.51// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK952// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s53// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK954// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1155// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s56// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1157 58// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1359// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s60// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1361// RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1562// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s63// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1564#ifdef CK265 66template <typename T, int n, int m>67int tmain(T argc) {68  T a[n][m];69  #pragma omp target70  #pragma omp teams distribute simd collapse(2)71  for(int i = 0; i < n; i++) {72    for(int j = 0; j < m; j++) {73      a[i][j] = (T)0;74    }75  }76  return 0;77}78 79int main (int argc, char **argv) {80  int n = 100;81  int m = 2;82  int a[n][m];83  #pragma omp target84  #pragma omp teams distribute simd collapse(2)85  for(int i = 0; i < n; i++) {86    for(int j = 0; j < m; j++) {87      a[i][j] = 0;88    }89  }90  return tmain<int, 10, 2>(argc);91}92 93 94 95 96 97// discard loop variables not needed here98 99#endif // CK2100#endif // #ifndef HEADER101// CHECK1-LABEL: define {{[^@]+}}@_Z21teams_template_structv102// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {103// CHECK1-NEXT:  entry:104// CHECK1-NEXT:    [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4105// CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])106// CHECK1-NEXT:    ret i32 [[CALL]]107//108//109// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv110// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat {111// CHECK1-NEXT:  entry:112// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8113// CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8114// CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8115// CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8116// CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4117// CHECK1-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4118// CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8119// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8120// CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8121// CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0122// CHECK1-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0123// CHECK1-NEXT:    store ptr [[THIS1]], ptr [[TMP0]], align 8124// CHECK1-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0125// CHECK1-NEXT:    store ptr [[A]], ptr [[TMP1]], align 8126// CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0127// CHECK1-NEXT:    store ptr null, ptr [[TMP2]], align 8128// CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0129// CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0130// CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0131// CHECK1-NEXT:    store i32 3, ptr [[TMP5]], align 4132// CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1133// CHECK1-NEXT:    store i32 1, ptr [[TMP6]], align 4134// CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2135// CHECK1-NEXT:    store ptr [[TMP3]], ptr [[TMP7]], align 8136// CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3137// CHECK1-NEXT:    store ptr [[TMP4]], ptr [[TMP8]], align 8138// CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4139// CHECK1-NEXT:    store ptr @.offload_sizes, ptr [[TMP9]], align 8140// CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5141// CHECK1-NEXT:    store ptr @.offload_maptypes, ptr [[TMP10]], align 8142// CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6143// CHECK1-NEXT:    store ptr null, ptr [[TMP11]], align 8144// CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7145// CHECK1-NEXT:    store ptr null, ptr [[TMP12]], align 8146// CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8147// CHECK1-NEXT:    store i64 56088, ptr [[TMP13]], align 8148// CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9149// CHECK1-NEXT:    store i64 0, ptr [[TMP14]], align 8150// CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10151// CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4152// CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11153// CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP16]], align 4154// CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12155// CHECK1-NEXT:    store i32 0, ptr [[TMP17]], align 4156// CHECK1-NEXT:    [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, ptr [[KERNEL_ARGS]])157// CHECK1-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0158// CHECK1-NEXT:    br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]159// CHECK1:       omp_offload.failed:160// CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(ptr [[THIS1]]) #[[ATTR2:[0-9]+]]161// CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]162// CHECK1:       omp_offload.cont:163// CHECK1-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0164// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i64 0, i64 0165// CHECK1-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 0166// CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4167// CHECK1-NEXT:    ret i32 [[TMP20]]168//169//170// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28171// CHECK1-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] {172// CHECK1-NEXT:  entry:173// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8174// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8175// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8176// CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined, ptr [[TMP0]])177// CHECK1-NEXT:    ret void178//179//180// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined181// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR1]] {182// CHECK1-NEXT:  entry:183// CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8184// CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8185// CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8186// CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4187// CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4188// CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4189// CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4190// CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4191// CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4192// CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4193// CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4194// CHECK1-NEXT:    [[J:%.*]] = alloca i32, align 4195// CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8196// CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8197// CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8198// CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8199// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4200// CHECK1-NEXT:    store i32 56087, ptr [[DOTOMP_UB]], align 4201// CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4202// CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4203// CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8204// CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4205// CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)206// CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4207// CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087208// CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]209// CHECK1:       cond.true:210// CHECK1-NEXT:    br label [[COND_END:%.*]]211// CHECK1:       cond.false:212// CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4213// CHECK1-NEXT:    br label [[COND_END]]214// CHECK1:       cond.end:215// CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]216// CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4217// CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4218// CHECK1-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4219// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]220// CHECK1:       omp.inner.for.cond:221// CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]]222// CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP4]]223// CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]224// CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]225// CHECK1:       omp.inner.for.body:226// CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]227// CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP8]], 456228// CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1229// CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]230// CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]]231// CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]232// CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]233// CHECK1-NEXT:    [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456234// CHECK1-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456235// CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]236// CHECK1-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1237// CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]238// CHECK1-NEXT:    store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP4]]239// CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0240// CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]]241// CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64242// CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]]243// CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP4]]244// CHECK1-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64245// CHECK1-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]246// CHECK1-NEXT:    store i32 0, ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP4]]247// CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]248// CHECK1:       omp.body.continue:249// CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]250// CHECK1:       omp.inner.for.inc:251// CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]252// CHECK1-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1253// CHECK1-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]254// CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]255// CHECK1:       omp.inner.for.end:256// CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]257// CHECK1:       omp.loop.exit:258// CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])259// CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4260// CHECK1-NEXT:    [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0261// CHECK1-NEXT:    br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]262// CHECK1:       .omp.final.then:263// CHECK1-NEXT:    store i32 123, ptr [[I]], align 4264// CHECK1-NEXT:    store i32 456, ptr [[J]], align 4265// CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]266// CHECK1:       .omp.final.done:267// CHECK1-NEXT:    ret void268//269//270// CHECK3-LABEL: define {{[^@]+}}@_Z21teams_template_structv271// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {272// CHECK3-NEXT:  entry:273// CHECK3-NEXT:    [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4274// CHECK3-NEXT:    [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])275// CHECK3-NEXT:    ret i32 [[CALL]]276//277//278// CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv279// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {280// CHECK3-NEXT:  entry:281// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4282// CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4283// CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4284// CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4285// CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4286// CHECK3-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4287// CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8288// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4289// CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4290// CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0291// CHECK3-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0292// CHECK3-NEXT:    store ptr [[THIS1]], ptr [[TMP0]], align 4293// CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0294// CHECK3-NEXT:    store ptr [[A]], ptr [[TMP1]], align 4295// CHECK3-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0296// CHECK3-NEXT:    store ptr null, ptr [[TMP2]], align 4297// CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0298// CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0299// CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0300// CHECK3-NEXT:    store i32 3, ptr [[TMP5]], align 4301// CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1302// CHECK3-NEXT:    store i32 1, ptr [[TMP6]], align 4303// CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2304// CHECK3-NEXT:    store ptr [[TMP3]], ptr [[TMP7]], align 4305// CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3306// CHECK3-NEXT:    store ptr [[TMP4]], ptr [[TMP8]], align 4307// CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4308// CHECK3-NEXT:    store ptr @.offload_sizes, ptr [[TMP9]], align 4309// CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5310// CHECK3-NEXT:    store ptr @.offload_maptypes, ptr [[TMP10]], align 4311// CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6312// CHECK3-NEXT:    store ptr null, ptr [[TMP11]], align 4313// CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7314// CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 4315// CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8316// CHECK3-NEXT:    store i64 56088, ptr [[TMP13]], align 8317// CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9318// CHECK3-NEXT:    store i64 0, ptr [[TMP14]], align 8319// CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10320// CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4321// CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11322// CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP16]], align 4323// CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12324// CHECK3-NEXT:    store i32 0, ptr [[TMP17]], align 4325// CHECK3-NEXT:    [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, ptr [[KERNEL_ARGS]])326// CHECK3-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0327// CHECK3-NEXT:    br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]328// CHECK3:       omp_offload.failed:329// CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(ptr [[THIS1]]) #[[ATTR2:[0-9]+]]330// CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]331// CHECK3:       omp_offload.cont:332// CHECK3-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0333// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i32 0, i32 0334// CHECK3-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 0335// CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4336// CHECK3-NEXT:    ret i32 [[TMP20]]337//338//339// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28340// CHECK3-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] {341// CHECK3-NEXT:  entry:342// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4343// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4344// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4345// CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined, ptr [[TMP0]])346// CHECK3-NEXT:    ret void347//348//349// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined350// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR1]] {351// CHECK3-NEXT:  entry:352// CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4353// CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4354// CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4355// CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4356// CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4357// CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4358// CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4359// CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4360// CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4361// CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4362// CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4363// CHECK3-NEXT:    [[J:%.*]] = alloca i32, align 4364// CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4365// CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4366// CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4367// CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4368// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4369// CHECK3-NEXT:    store i32 56087, ptr [[DOTOMP_UB]], align 4370// CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4371// CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4372// CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4373// CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4374// CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)375// CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4376// CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087377// CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]378// CHECK3:       cond.true:379// CHECK3-NEXT:    br label [[COND_END:%.*]]380// CHECK3:       cond.false:381// CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4382// CHECK3-NEXT:    br label [[COND_END]]383// CHECK3:       cond.end:384// CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]385// CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4386// CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4387// CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4388// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]389// CHECK3:       omp.inner.for.cond:390// CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]391// CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]]392// CHECK3-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]393// CHECK3-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]394// CHECK3:       omp.inner.for.body:395// CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]396// CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP8]], 456397// CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1398// CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]399// CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]400// CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]401// CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]402// CHECK3-NEXT:    [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456403// CHECK3-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456404// CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]405// CHECK3-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1406// CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]407// CHECK3-NEXT:    store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP5]]408// CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0409// CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]410// CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i32 0, i32 [[TMP11]]411// CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP5]]412// CHECK3-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP12]]413// CHECK3-NEXT:    store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP5]]414// CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]415// CHECK3:       omp.body.continue:416// CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]417// CHECK3:       omp.inner.for.inc:418// CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]419// CHECK3-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1420// CHECK3-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]421// CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]422// CHECK3:       omp.inner.for.end:423// CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]424// CHECK3:       omp.loop.exit:425// CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])426// CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4427// CHECK3-NEXT:    [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0428// CHECK3-NEXT:    br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]429// CHECK3:       .omp.final.then:430// CHECK3-NEXT:    store i32 123, ptr [[I]], align 4431// CHECK3-NEXT:    store i32 456, ptr [[J]], align 4432// CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]433// CHECK3:       .omp.final.done:434// CHECK3-NEXT:    ret void435//436//437// CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv438// CHECK5-SAME: () #[[ATTR0:[0-9]+]] {439// CHECK5-NEXT:  entry:440// CHECK5-NEXT:    [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4441// CHECK5-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])442// CHECK5-NEXT:    ret i32 [[CALL]]443//444//445// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv446// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat {447// CHECK5-NEXT:  entry:448// CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8449// CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4450// CHECK5-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4451// CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4452// CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4453// CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4454// CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4455// CHECK5-NEXT:    [[J:%.*]] = alloca i32, align 4456// CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8457// CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8458// CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4459// CHECK5-NEXT:    store i32 56087, ptr [[DOTOMP_UB]], align 4460// CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4461// CHECK5-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4462// CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]463// CHECK5:       omp.inner.for.cond:464// CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]465// CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]466// CHECK5-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]467// CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]468// CHECK5:       omp.inner.for.body:469// CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]470// CHECK5-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP3]], 456471// CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1472// CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]473// CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]474// CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]475// CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]476// CHECK5-NEXT:    [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456477// CHECK5-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456478// CHECK5-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]]479// CHECK5-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1480// CHECK5-NEXT:    [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]481// CHECK5-NEXT:    store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP2]]482// CHECK5-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0483// CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]484// CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64485// CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]]486// CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP2]]487// CHECK5-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64488// CHECK5-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]489// CHECK5-NEXT:    store i32 0, ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP2]]490// CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]491// CHECK5:       omp.body.continue:492// CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]493// CHECK5:       omp.inner.for.inc:494// CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]495// CHECK5-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP8]], 1496// CHECK5-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]497// CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]498// CHECK5:       omp.inner.for.end:499// CHECK5-NEXT:    store i32 123, ptr [[I]], align 4500// CHECK5-NEXT:    store i32 456, ptr [[J]], align 4501// CHECK5-NEXT:    [[A10:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0502// CHECK5-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A10]], i64 0, i64 0503// CHECK5-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX11]], i64 0, i64 0504// CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX12]], align 4505// CHECK5-NEXT:    ret i32 [[TMP9]]506//507//508// CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv509// CHECK7-SAME: () #[[ATTR0:[0-9]+]] {510// CHECK7-NEXT:  entry:511// CHECK7-NEXT:    [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4512// CHECK7-NEXT:    [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])513// CHECK7-NEXT:    ret i32 [[CALL]]514//515//516// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv517// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {518// CHECK7-NEXT:  entry:519// CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4520// CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4521// CHECK7-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4522// CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4523// CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4524// CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4525// CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4526// CHECK7-NEXT:    [[J:%.*]] = alloca i32, align 4527// CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4528// CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4529// CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4530// CHECK7-NEXT:    store i32 56087, ptr [[DOTOMP_UB]], align 4531// CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4532// CHECK7-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4533// CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]534// CHECK7:       omp.inner.for.cond:535// CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]536// CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]]537// CHECK7-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]538// CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]539// CHECK7:       omp.inner.for.body:540// CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]541// CHECK7-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP3]], 456542// CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1543// CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]544// CHECK7-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]545// CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]546// CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]547// CHECK7-NEXT:    [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456548// CHECK7-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456549// CHECK7-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]]550// CHECK7-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1551// CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]552// CHECK7-NEXT:    store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP3]]553// CHECK7-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0554// CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]555// CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i32 0, i32 [[TMP6]]556// CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP3]]557// CHECK7-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP7]]558// CHECK7-NEXT:    store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP3]]559// CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]560// CHECK7:       omp.body.continue:561// CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]562// CHECK7:       omp.inner.for.inc:563// CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]564// CHECK7-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1565// CHECK7-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]566// CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]567// CHECK7:       omp.inner.for.end:568// CHECK7-NEXT:    store i32 123, ptr [[I]], align 4569// CHECK7-NEXT:    store i32 456, ptr [[J]], align 4570// CHECK7-NEXT:    [[A9:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0571// CHECK7-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A9]], i32 0, i32 0572// CHECK7-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX10]], i32 0, i32 0573// CHECK7-NEXT:    [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX11]], align 4574// CHECK7-NEXT:    ret i32 [[TMP9]]575//576//577// CHECK9-LABEL: define {{[^@]+}}@main578// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {579// CHECK9-NEXT:  entry:580// CHECK9-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4581// CHECK9-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 4582// CHECK9-NEXT:    [[ARGV_ADDR:%.*]] = alloca ptr, align 8583// CHECK9-NEXT:    [[N:%.*]] = alloca i32, align 4584// CHECK9-NEXT:    [[M:%.*]] = alloca i32, align 4585// CHECK9-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8586// CHECK9-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8587// CHECK9-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8588// CHECK9-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8589// CHECK9-NEXT:    [[M_CASTED:%.*]] = alloca i64, align 8590// CHECK9-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8591// CHECK9-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8592// CHECK9-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8593// CHECK9-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8594// CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4595// CHECK9-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4596// CHECK9-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4597// CHECK9-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4598// CHECK9-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8599// CHECK9-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8600// CHECK9-NEXT:    store i32 0, ptr [[RETVAL]], align 4601// CHECK9-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4602// CHECK9-NEXT:    store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8603// CHECK9-NEXT:    store i32 100, ptr [[N]], align 4604// CHECK9-NEXT:    store i32 2, ptr [[M]], align 4605// CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N]], align 4606// CHECK9-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64607// CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[M]], align 4608// CHECK9-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64609// CHECK9-NEXT:    [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()610// CHECK9-NEXT:    store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8611// CHECK9-NEXT:    [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]612// CHECK9-NEXT:    [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4613// CHECK9-NEXT:    store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8614// CHECK9-NEXT:    store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8615// CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N]], align 4616// CHECK9-NEXT:    store i32 [[TMP6]], ptr [[N_CASTED]], align 4617// CHECK9-NEXT:    [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8618// CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[M]], align 4619// CHECK9-NEXT:    store i32 [[TMP8]], ptr [[M_CASTED]], align 4620// CHECK9-NEXT:    [[TMP9:%.*]] = load i64, ptr [[M_CASTED]], align 8621// CHECK9-NEXT:    [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]622// CHECK9-NEXT:    [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4623// CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 40, i1 false)624// CHECK9-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0625// CHECK9-NEXT:    store i64 [[TMP7]], ptr [[TMP12]], align 8626// CHECK9-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0627// CHECK9-NEXT:    store i64 [[TMP7]], ptr [[TMP13]], align 8628// CHECK9-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0629// CHECK9-NEXT:    store ptr null, ptr [[TMP14]], align 8630// CHECK9-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1631// CHECK9-NEXT:    store i64 [[TMP9]], ptr [[TMP15]], align 8632// CHECK9-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1633// CHECK9-NEXT:    store i64 [[TMP9]], ptr [[TMP16]], align 8634// CHECK9-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1635// CHECK9-NEXT:    store ptr null, ptr [[TMP17]], align 8636// CHECK9-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2637// CHECK9-NEXT:    store i64 [[TMP1]], ptr [[TMP18]], align 8638// CHECK9-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2639// CHECK9-NEXT:    store i64 [[TMP1]], ptr [[TMP19]], align 8640// CHECK9-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2641// CHECK9-NEXT:    store ptr null, ptr [[TMP20]], align 8642// CHECK9-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3643// CHECK9-NEXT:    store i64 [[TMP3]], ptr [[TMP21]], align 8644// CHECK9-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3645// CHECK9-NEXT:    store i64 [[TMP3]], ptr [[TMP22]], align 8646// CHECK9-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3647// CHECK9-NEXT:    store ptr null, ptr [[TMP23]], align 8648// CHECK9-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4649// CHECK9-NEXT:    store ptr [[VLA]], ptr [[TMP24]], align 8650// CHECK9-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4651// CHECK9-NEXT:    store ptr [[VLA]], ptr [[TMP25]], align 8652// CHECK9-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4653// CHECK9-NEXT:    store i64 [[TMP11]], ptr [[TMP26]], align 8654// CHECK9-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4655// CHECK9-NEXT:    store ptr null, ptr [[TMP27]], align 8656// CHECK9-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0657// CHECK9-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0658// CHECK9-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0659// CHECK9-NEXT:    [[TMP31:%.*]] = load i32, ptr [[N]], align 4660// CHECK9-NEXT:    store i32 [[TMP31]], ptr [[DOTCAPTURE_EXPR_]], align 4661// CHECK9-NEXT:    [[TMP32:%.*]] = load i32, ptr [[M]], align 4662// CHECK9-NEXT:    store i32 [[TMP32]], ptr [[DOTCAPTURE_EXPR_2]], align 4663// CHECK9-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4664// CHECK9-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP33]], 0665// CHECK9-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1666// CHECK9-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i64667// CHECK9-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4668// CHECK9-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP34]], 0669// CHECK9-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1670// CHECK9-NEXT:    [[CONV6:%.*]] = sext i32 [[DIV5]] to i64671// CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]672// CHECK9-NEXT:    [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1673// CHECK9-NEXT:    store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 8674// CHECK9-NEXT:    [[TMP35:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8675// CHECK9-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP35]], 1676// CHECK9-NEXT:    [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0677// CHECK9-NEXT:    store i32 3, ptr [[TMP36]], align 4678// CHECK9-NEXT:    [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1679// CHECK9-NEXT:    store i32 5, ptr [[TMP37]], align 4680// CHECK9-NEXT:    [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2681// CHECK9-NEXT:    store ptr [[TMP28]], ptr [[TMP38]], align 8682// CHECK9-NEXT:    [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3683// CHECK9-NEXT:    store ptr [[TMP29]], ptr [[TMP39]], align 8684// CHECK9-NEXT:    [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4685// CHECK9-NEXT:    store ptr [[TMP30]], ptr [[TMP40]], align 8686// CHECK9-NEXT:    [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5687// CHECK9-NEXT:    store ptr @.offload_maptypes, ptr [[TMP41]], align 8688// CHECK9-NEXT:    [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6689// CHECK9-NEXT:    store ptr null, ptr [[TMP42]], align 8690// CHECK9-NEXT:    [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7691// CHECK9-NEXT:    store ptr null, ptr [[TMP43]], align 8692// CHECK9-NEXT:    [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8693// CHECK9-NEXT:    store i64 [[ADD]], ptr [[TMP44]], align 8694// CHECK9-NEXT:    [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9695// CHECK9-NEXT:    store i64 0, ptr [[TMP45]], align 8696// CHECK9-NEXT:    [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10697// CHECK9-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP46]], align 4698// CHECK9-NEXT:    [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11699// CHECK9-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP47]], align 4700// CHECK9-NEXT:    [[TMP48:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12701// CHECK9-NEXT:    store i32 0, ptr [[TMP48]], align 4702// CHECK9-NEXT:    [[TMP49:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.region_id, ptr [[KERNEL_ARGS]])703// CHECK9-NEXT:    [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0704// CHECK9-NEXT:    br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]705// CHECK9:       omp_offload.failed:706// CHECK9-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]707// CHECK9-NEXT:    br label [[OMP_OFFLOAD_CONT]]708// CHECK9:       omp_offload.cont:709// CHECK9-NEXT:    [[TMP51:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4710// CHECK9-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP51]])711// CHECK9-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 4712// CHECK9-NEXT:    [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8713// CHECK9-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP52]])714// CHECK9-NEXT:    [[TMP53:%.*]] = load i32, ptr [[RETVAL]], align 4715// CHECK9-NEXT:    ret i32 [[TMP53]]716//717//718// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83719// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {720// CHECK9-NEXT:  entry:721// CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8722// CHECK9-NEXT:    [[M_ADDR:%.*]] = alloca i64, align 8723// CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8724// CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8725// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8726// CHECK9-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8727// CHECK9-NEXT:    store i64 [[M]], ptr [[M_ADDR]], align 8728// CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8729// CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8730// CHECK9-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8731// CHECK9-NEXT:    [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8732// CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8733// CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8734// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.omp_outlined, ptr [[N_ADDR]], ptr [[M_ADDR]], i64 [[TMP0]], i64 [[TMP1]], ptr [[TMP2]])735// CHECK9-NEXT:    ret void736//737//738// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.omp_outlined739// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {740// CHECK9-NEXT:  entry:741// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8742// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8743// CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca ptr, align 8744// CHECK9-NEXT:    [[M_ADDR:%.*]] = alloca ptr, align 8745// CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8746// CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8747// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8748// CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8749// CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4750// CHECK9-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4751// CHECK9-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4752// CHECK9-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4753// CHECK9-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8754// CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4755// CHECK9-NEXT:    [[J:%.*]] = alloca i32, align 4756// CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8757// CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8758// CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8759// CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4760// CHECK9-NEXT:    [[I11:%.*]] = alloca i32, align 4761// CHECK9-NEXT:    [[J12:%.*]] = alloca i32, align 4762// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8763// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8764// CHECK9-NEXT:    store ptr [[N]], ptr [[N_ADDR]], align 8765// CHECK9-NEXT:    store ptr [[M]], ptr [[M_ADDR]], align 8766// CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8767// CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8768// CHECK9-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8769// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 8770// CHECK9-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[M_ADDR]], align 8771// CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR]], align 8772// CHECK9-NEXT:    [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8773// CHECK9-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[A_ADDR]], align 8774// CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4775// CHECK9-NEXT:    store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4776// CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP1]], align 4777// CHECK9-NEXT:    store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_4]], align 4778// CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4779// CHECK9-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0780// CHECK9-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1781// CHECK9-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i64782// CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4783// CHECK9-NEXT:    [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0784// CHECK9-NEXT:    [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1785// CHECK9-NEXT:    [[CONV8:%.*]] = sext i32 [[DIV7]] to i64786// CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]]787// CHECK9-NEXT:    [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1788// CHECK9-NEXT:    store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 8789// CHECK9-NEXT:    store i32 0, ptr [[I]], align 4790// CHECK9-NEXT:    store i32 0, ptr [[J]], align 4791// CHECK9-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4792// CHECK9-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP9]]793// CHECK9-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]794// CHECK9:       land.lhs.true:795// CHECK9-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4796// CHECK9-NEXT:    [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]]797// CHECK9-NEXT:    br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]798// CHECK9:       omp.precond.then:799// CHECK9-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8800// CHECK9-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8801// CHECK9-NEXT:    store i64 [[TMP11]], ptr [[DOTOMP_UB]], align 8802// CHECK9-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8803// CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4804// CHECK9-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8805// CHECK9-NEXT:    [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4806// CHECK9-NEXT:    call void @__kmpc_for_static_init_8(ptr @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)807// CHECK9-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8808// CHECK9-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8809// CHECK9-NEXT:    [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]]810// CHECK9-NEXT:    br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]811// CHECK9:       cond.true:812// CHECK9-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8813// CHECK9-NEXT:    br label [[COND_END:%.*]]814// CHECK9:       cond.false:815// CHECK9-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8816// CHECK9-NEXT:    br label [[COND_END]]817// CHECK9:       cond.end:818// CHECK9-NEXT:    [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]819// CHECK9-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8820// CHECK9-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8821// CHECK9-NEXT:    store i64 [[TMP18]], ptr [[DOTOMP_IV]], align 8822// CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]823// CHECK9:       omp.inner.for.cond:824// CHECK9-NEXT:    [[TMP19:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5:![0-9]+]]825// CHECK9-NEXT:    [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP5]]826// CHECK9-NEXT:    [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]827// CHECK9-NEXT:    br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]828// CHECK9:       omp.inner.for.body:829// CHECK9-NEXT:    [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]830// CHECK9-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP5]]831// CHECK9-NEXT:    [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0832// CHECK9-NEXT:    [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1833// CHECK9-NEXT:    [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]834// CHECK9-NEXT:    [[CONV18:%.*]] = sext i32 [[MUL17]] to i64835// CHECK9-NEXT:    [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]]836// CHECK9-NEXT:    [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1837// CHECK9-NEXT:    [[ADD:%.*]] = add nsw i64 0, [[MUL20]]838// CHECK9-NEXT:    [[CONV21:%.*]] = trunc i64 [[ADD]] to i32839// CHECK9-NEXT:    store i32 [[CONV21]], ptr [[I11]], align 4, !llvm.access.group [[ACC_GRP5]]840// CHECK9-NEXT:    [[TMP23:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]841// CHECK9-NEXT:    [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]842// CHECK9-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP5]]843// CHECK9-NEXT:    [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0844// CHECK9-NEXT:    [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1845// CHECK9-NEXT:    [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]846// CHECK9-NEXT:    [[CONV25:%.*]] = sext i32 [[MUL24]] to i64847// CHECK9-NEXT:    [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]]848// CHECK9-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP5]]849// CHECK9-NEXT:    [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0850// CHECK9-NEXT:    [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1851// CHECK9-NEXT:    [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]852// CHECK9-NEXT:    [[CONV30:%.*]] = sext i32 [[MUL29]] to i64853// CHECK9-NEXT:    [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]854// CHECK9-NEXT:    [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]]855// CHECK9-NEXT:    [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1856// CHECK9-NEXT:    [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]857// CHECK9-NEXT:    [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32858// CHECK9-NEXT:    store i32 [[CONV35]], ptr [[J12]], align 4, !llvm.access.group [[ACC_GRP5]]859// CHECK9-NEXT:    [[TMP27:%.*]] = load i32, ptr [[I11]], align 4, !llvm.access.group [[ACC_GRP5]]860// CHECK9-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64861// CHECK9-NEXT:    [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]]862// CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 [[TMP28]]863// CHECK9-NEXT:    [[TMP29:%.*]] = load i32, ptr [[J12]], align 4, !llvm.access.group [[ACC_GRP5]]864// CHECK9-NEXT:    [[IDXPROM36:%.*]] = sext i32 [[TMP29]] to i64865// CHECK9-NEXT:    [[ARRAYIDX37:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i64 [[IDXPROM36]]866// CHECK9-NEXT:    store i32 0, ptr [[ARRAYIDX37]], align 4, !llvm.access.group [[ACC_GRP5]]867// CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]868// CHECK9:       omp.body.continue:869// CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]870// CHECK9:       omp.inner.for.inc:871// CHECK9-NEXT:    [[TMP30:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]872// CHECK9-NEXT:    [[ADD38:%.*]] = add nsw i64 [[TMP30]], 1873// CHECK9-NEXT:    store i64 [[ADD38]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]874// CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]875// CHECK9:       omp.inner.for.end:876// CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]877// CHECK9:       omp.loop.exit:878// CHECK9-NEXT:    [[TMP31:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8879// CHECK9-NEXT:    [[TMP32:%.*]] = load i32, ptr [[TMP31]], align 4880// CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP32]])881// CHECK9-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4882// CHECK9-NEXT:    [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0883// CHECK9-NEXT:    br i1 [[TMP34]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]884// CHECK9:       .omp.final.then:885// CHECK9-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4886// CHECK9-NEXT:    [[SUB39:%.*]] = sub nsw i32 [[TMP35]], 0887// CHECK9-NEXT:    [[DIV40:%.*]] = sdiv i32 [[SUB39]], 1888// CHECK9-NEXT:    [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 1889// CHECK9-NEXT:    [[ADD42:%.*]] = add nsw i32 0, [[MUL41]]890// CHECK9-NEXT:    store i32 [[ADD42]], ptr [[I11]], align 4891// CHECK9-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4892// CHECK9-NEXT:    [[SUB43:%.*]] = sub nsw i32 [[TMP36]], 0893// CHECK9-NEXT:    [[DIV44:%.*]] = sdiv i32 [[SUB43]], 1894// CHECK9-NEXT:    [[MUL45:%.*]] = mul nsw i32 [[DIV44]], 1895// CHECK9-NEXT:    [[ADD46:%.*]] = add nsw i32 0, [[MUL45]]896// CHECK9-NEXT:    store i32 [[ADD46]], ptr [[J12]], align 4897// CHECK9-NEXT:    br label [[DOTOMP_FINAL_DONE]]898// CHECK9:       .omp.final.done:899// CHECK9-NEXT:    br label [[OMP_PRECOND_END]]900// CHECK9:       omp.precond.end:901// CHECK9-NEXT:    ret void902//903//904// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_905// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat {906// CHECK9-NEXT:  entry:907// CHECK9-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 4908// CHECK9-NEXT:    [[A:%.*]] = alloca [10 x [2 x i32]], align 4909// CHECK9-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8910// CHECK9-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8911// CHECK9-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8912// CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4913// CHECK9-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4914// CHECK9-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8915// CHECK9-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4916// CHECK9-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0917// CHECK9-NEXT:    store ptr [[A]], ptr [[TMP0]], align 8918// CHECK9-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0919// CHECK9-NEXT:    store ptr [[A]], ptr [[TMP1]], align 8920// CHECK9-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0921// CHECK9-NEXT:    store ptr null, ptr [[TMP2]], align 8922// CHECK9-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0923// CHECK9-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0924// CHECK9-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0925// CHECK9-NEXT:    store i32 3, ptr [[TMP5]], align 4926// CHECK9-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1927// CHECK9-NEXT:    store i32 1, ptr [[TMP6]], align 4928// CHECK9-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2929// CHECK9-NEXT:    store ptr [[TMP3]], ptr [[TMP7]], align 8930// CHECK9-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3931// CHECK9-NEXT:    store ptr [[TMP4]], ptr [[TMP8]], align 8932// CHECK9-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4933// CHECK9-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP9]], align 8934// CHECK9-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5935// CHECK9-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP10]], align 8936// CHECK9-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6937// CHECK9-NEXT:    store ptr null, ptr [[TMP11]], align 8938// CHECK9-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7939// CHECK9-NEXT:    store ptr null, ptr [[TMP12]], align 8940// CHECK9-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8941// CHECK9-NEXT:    store i64 20, ptr [[TMP13]], align 8942// CHECK9-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9943// CHECK9-NEXT:    store i64 0, ptr [[TMP14]], align 8944// CHECK9-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10945// CHECK9-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4946// CHECK9-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11947// CHECK9-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP16]], align 4948// CHECK9-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12949// CHECK9-NEXT:    store i32 0, ptr [[TMP17]], align 4950// CHECK9-NEXT:    [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.region_id, ptr [[KERNEL_ARGS]])951// CHECK9-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0952// CHECK9-NEXT:    br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]953// CHECK9:       omp_offload.failed:954// CHECK9-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69(ptr [[A]]) #[[ATTR3]]955// CHECK9-NEXT:    br label [[OMP_OFFLOAD_CONT]]956// CHECK9:       omp_offload.cont:957// CHECK9-NEXT:    ret i32 0958//959//960// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69961// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {962// CHECK9-NEXT:  entry:963// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8964// CHECK9-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8965// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8966// CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.omp_outlined, ptr [[TMP0]])967// CHECK9-NEXT:    ret void968//969//970// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.omp_outlined971// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {972// CHECK9-NEXT:  entry:973// CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8974// CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8975// CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8976// CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4977// CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4978// CHECK9-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4979// CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4980// CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4981// CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4982// CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4983// CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4984// CHECK9-NEXT:    [[J:%.*]] = alloca i32, align 4985// CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8986// CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8987// CHECK9-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8988// CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8989// CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4990// CHECK9-NEXT:    store i32 19, ptr [[DOTOMP_UB]], align 4991// CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4992// CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4993// CHECK9-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8994// CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4995// CHECK9-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)996// CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4997// CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19998// CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]999// CHECK9:       cond.true:1000// CHECK9-NEXT:    br label [[COND_END:%.*]]1001// CHECK9:       cond.false:1002// CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41003// CHECK9-NEXT:    br label [[COND_END]]1004// CHECK9:       cond.end:1005// CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]1006// CHECK9-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 41007// CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41008// CHECK9-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 41009// CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1010// CHECK9:       omp.inner.for.cond:1011// CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]1012// CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]]1013// CHECK9-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]1014// CHECK9-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1015// CHECK9:       omp.inner.for.body:1016// CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]1017// CHECK9-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP8]], 21018// CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 11019// CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1020// CHECK9-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]1021// CHECK9-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]1022// CHECK9-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]1023// CHECK9-NEXT:    [[DIV3:%.*]] = sdiv i32 [[TMP10]], 21024// CHECK9-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 21025// CHECK9-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]1026// CHECK9-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[SUB]], 11027// CHECK9-NEXT:    [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]1028// CHECK9-NEXT:    store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP11]]1029// CHECK9-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]1030// CHECK9-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i641031// CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]1032// CHECK9-NEXT:    [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP11]]1033// CHECK9-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i641034// CHECK9-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]1035// CHECK9-NEXT:    store i32 0, ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP11]]1036// CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1037// CHECK9:       omp.body.continue:1038// CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1039// CHECK9:       omp.inner.for.inc:1040// CHECK9-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]1041// CHECK9-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 11042// CHECK9-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]1043// CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]1044// CHECK9:       omp.inner.for.end:1045// CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]1046// CHECK9:       omp.loop.exit:1047// CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])1048// CHECK9-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41049// CHECK9-NEXT:    [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 01050// CHECK9-NEXT:    br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1051// CHECK9:       .omp.final.then:1052// CHECK9-NEXT:    store i32 10, ptr [[I]], align 41053// CHECK9-NEXT:    store i32 2, ptr [[J]], align 41054// CHECK9-NEXT:    br label [[DOTOMP_FINAL_DONE]]1055// CHECK9:       .omp.final.done:1056// CHECK9-NEXT:    ret void1057//1058//1059// CHECK11-LABEL: define {{[^@]+}}@main1060// CHECK11-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {1061// CHECK11-NEXT:  entry:1062// CHECK11-NEXT:    [[RETVAL:%.*]] = alloca i32, align 41063// CHECK11-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 41064// CHECK11-NEXT:    [[ARGV_ADDR:%.*]] = alloca ptr, align 41065// CHECK11-NEXT:    [[N:%.*]] = alloca i32, align 41066// CHECK11-NEXT:    [[M:%.*]] = alloca i32, align 41067// CHECK11-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 41068// CHECK11-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 41069// CHECK11-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 41070// CHECK11-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 41071// CHECK11-NEXT:    [[M_CASTED:%.*]] = alloca i32, align 41072// CHECK11-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 41073// CHECK11-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 41074// CHECK11-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 41075// CHECK11-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 41076// CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 41077// CHECK11-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41078// CHECK11-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 41079// CHECK11-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 41080// CHECK11-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 81081// CHECK11-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81082// CHECK11-NEXT:    store i32 0, ptr [[RETVAL]], align 41083// CHECK11-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 41084// CHECK11-NEXT:    store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 41085// CHECK11-NEXT:    store i32 100, ptr [[N]], align 41086// CHECK11-NEXT:    store i32 2, ptr [[M]], align 41087// CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N]], align 41088// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[M]], align 41089// CHECK11-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()1090// CHECK11-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 41091// CHECK11-NEXT:    [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]1092// CHECK11-NEXT:    [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 41093// CHECK11-NEXT:    store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 41094// CHECK11-NEXT:    store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 41095// CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N]], align 41096// CHECK11-NEXT:    store i32 [[TMP4]], ptr [[N_CASTED]], align 41097// CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 41098// CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[M]], align 41099// CHECK11-NEXT:    store i32 [[TMP6]], ptr [[M_CASTED]], align 41100// CHECK11-NEXT:    [[TMP7:%.*]] = load i32, ptr [[M_CASTED]], align 41101// CHECK11-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]1102// CHECK11-NEXT:    [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 41103// CHECK11-NEXT:    [[TMP10:%.*]] = sext i32 [[TMP9]] to i641104// CHECK11-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes, i32 40, i1 false)1105// CHECK11-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01106// CHECK11-NEXT:    store i32 [[TMP5]], ptr [[TMP11]], align 41107// CHECK11-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01108// CHECK11-NEXT:    store i32 [[TMP5]], ptr [[TMP12]], align 41109// CHECK11-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 01110// CHECK11-NEXT:    store ptr null, ptr [[TMP13]], align 41111// CHECK11-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11112// CHECK11-NEXT:    store i32 [[TMP7]], ptr [[TMP14]], align 41113// CHECK11-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11114// CHECK11-NEXT:    store i32 [[TMP7]], ptr [[TMP15]], align 41115// CHECK11-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 11116// CHECK11-NEXT:    store ptr null, ptr [[TMP16]], align 41117// CHECK11-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21118// CHECK11-NEXT:    store i32 [[TMP0]], ptr [[TMP17]], align 41119// CHECK11-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21120// CHECK11-NEXT:    store i32 [[TMP0]], ptr [[TMP18]], align 41121// CHECK11-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 21122// CHECK11-NEXT:    store ptr null, ptr [[TMP19]], align 41123// CHECK11-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31124// CHECK11-NEXT:    store i32 [[TMP1]], ptr [[TMP20]], align 41125// CHECK11-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31126// CHECK11-NEXT:    store i32 [[TMP1]], ptr [[TMP21]], align 41127// CHECK11-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 31128// CHECK11-NEXT:    store ptr null, ptr [[TMP22]], align 41129// CHECK11-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 41130// CHECK11-NEXT:    store ptr [[VLA]], ptr [[TMP23]], align 41131// CHECK11-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 41132// CHECK11-NEXT:    store ptr [[VLA]], ptr [[TMP24]], align 41133// CHECK11-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 41134// CHECK11-NEXT:    store i64 [[TMP10]], ptr [[TMP25]], align 41135// CHECK11-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 41136// CHECK11-NEXT:    store ptr null, ptr [[TMP26]], align 41137// CHECK11-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01138// CHECK11-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01139// CHECK11-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 01140// CHECK11-NEXT:    [[TMP30:%.*]] = load i32, ptr [[N]], align 41141// CHECK11-NEXT:    store i32 [[TMP30]], ptr [[DOTCAPTURE_EXPR_]], align 41142// CHECK11-NEXT:    [[TMP31:%.*]] = load i32, ptr [[M]], align 41143// CHECK11-NEXT:    store i32 [[TMP31]], ptr [[DOTCAPTURE_EXPR_2]], align 41144// CHECK11-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41145// CHECK11-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP32]], 01146// CHECK11-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 11147// CHECK11-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i641148// CHECK11-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41149// CHECK11-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP33]], 01150// CHECK11-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 11151// CHECK11-NEXT:    [[CONV6:%.*]] = sext i32 [[DIV5]] to i641152// CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]1153// CHECK11-NEXT:    [[SUB7:%.*]] = sub nsw i64 [[MUL]], 11154// CHECK11-NEXT:    store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 81155// CHECK11-NEXT:    [[TMP34:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 81156// CHECK11-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP34]], 11157// CHECK11-NEXT:    [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01158// CHECK11-NEXT:    store i32 3, ptr [[TMP35]], align 41159// CHECK11-NEXT:    [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11160// CHECK11-NEXT:    store i32 5, ptr [[TMP36]], align 41161// CHECK11-NEXT:    [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21162// CHECK11-NEXT:    store ptr [[TMP27]], ptr [[TMP37]], align 41163// CHECK11-NEXT:    [[TMP38:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31164// CHECK11-NEXT:    store ptr [[TMP28]], ptr [[TMP38]], align 41165// CHECK11-NEXT:    [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41166// CHECK11-NEXT:    store ptr [[TMP29]], ptr [[TMP39]], align 41167// CHECK11-NEXT:    [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51168// CHECK11-NEXT:    store ptr @.offload_maptypes, ptr [[TMP40]], align 41169// CHECK11-NEXT:    [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61170// CHECK11-NEXT:    store ptr null, ptr [[TMP41]], align 41171// CHECK11-NEXT:    [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71172// CHECK11-NEXT:    store ptr null, ptr [[TMP42]], align 41173// CHECK11-NEXT:    [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81174// CHECK11-NEXT:    store i64 [[ADD]], ptr [[TMP43]], align 81175// CHECK11-NEXT:    [[TMP44:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91176// CHECK11-NEXT:    store i64 0, ptr [[TMP44]], align 81177// CHECK11-NEXT:    [[TMP45:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101178// CHECK11-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP45]], align 41179// CHECK11-NEXT:    [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111180// CHECK11-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP46]], align 41181// CHECK11-NEXT:    [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121182// CHECK11-NEXT:    store i32 0, ptr [[TMP47]], align 41183// CHECK11-NEXT:    [[TMP48:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.region_id, ptr [[KERNEL_ARGS]])1184// CHECK11-NEXT:    [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 01185// CHECK11-NEXT:    br i1 [[TMP49]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1186// CHECK11:       omp_offload.failed:1187// CHECK11-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]1188// CHECK11-NEXT:    br label [[OMP_OFFLOAD_CONT]]1189// CHECK11:       omp_offload.cont:1190// CHECK11-NEXT:    [[TMP50:%.*]] = load i32, ptr [[ARGC_ADDR]], align 41191// CHECK11-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP50]])1192// CHECK11-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 41193// CHECK11-NEXT:    [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 41194// CHECK11-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP51]])1195// CHECK11-NEXT:    [[TMP52:%.*]] = load i32, ptr [[RETVAL]], align 41196// CHECK11-NEXT:    ret i32 [[TMP52]]1197//1198//1199// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l831200// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {1201// CHECK11-NEXT:  entry:1202// CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 41203// CHECK11-NEXT:    [[M_ADDR:%.*]] = alloca i32, align 41204// CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 41205// CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 41206// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 41207// CHECK11-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 41208// CHECK11-NEXT:    store i32 [[M]], ptr [[M_ADDR]], align 41209// CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 41210// CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 41211// CHECK11-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 41212// CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 41213// CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR2]], align 41214// CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 41215// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.omp_outlined, ptr [[N_ADDR]], ptr [[M_ADDR]], i32 [[TMP0]], i32 [[TMP1]], ptr [[TMP2]])1216// CHECK11-NEXT:    ret void1217//1218//1219// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.omp_outlined1220// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {1221// CHECK11-NEXT:  entry:1222// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41223// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41224// CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca ptr, align 41225// CHECK11-NEXT:    [[M_ADDR:%.*]] = alloca ptr, align 41226// CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 41227// CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 41228// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 41229// CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 81230// CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 41231// CHECK11-NEXT:    [[_TMP3:%.*]] = alloca i32, align 41232// CHECK11-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 41233// CHECK11-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 41234// CHECK11-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 81235// CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 41236// CHECK11-NEXT:    [[J:%.*]] = alloca i32, align 41237// CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 81238// CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 81239// CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 81240// CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41241// CHECK11-NEXT:    [[I11:%.*]] = alloca i32, align 41242// CHECK11-NEXT:    [[J12:%.*]] = alloca i32, align 41243// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41244// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41245// CHECK11-NEXT:    store ptr [[N]], ptr [[N_ADDR]], align 41246// CHECK11-NEXT:    store ptr [[M]], ptr [[M_ADDR]], align 41247// CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 41248// CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 41249// CHECK11-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 41250// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 41251// CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[M_ADDR]], align 41252// CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR]], align 41253// CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[VLA_ADDR2]], align 41254// CHECK11-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[A_ADDR]], align 41255// CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 41256// CHECK11-NEXT:    store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 41257// CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP1]], align 41258// CHECK11-NEXT:    store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_4]], align 41259// CHECK11-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41260// CHECK11-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP7]], 01261// CHECK11-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 11262// CHECK11-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i641263// CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 41264// CHECK11-NEXT:    [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 01265// CHECK11-NEXT:    [[DIV7:%.*]] = sdiv i32 [[SUB6]], 11266// CHECK11-NEXT:    [[CONV8:%.*]] = sext i32 [[DIV7]] to i641267// CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]]1268// CHECK11-NEXT:    [[SUB9:%.*]] = sub nsw i64 [[MUL]], 11269// CHECK11-NEXT:    store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 81270// CHECK11-NEXT:    store i32 0, ptr [[I]], align 41271// CHECK11-NEXT:    store i32 0, ptr [[J]], align 41272// CHECK11-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41273// CHECK11-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP9]]1274// CHECK11-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]1275// CHECK11:       land.lhs.true:1276// CHECK11-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 41277// CHECK11-NEXT:    [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]]1278// CHECK11-NEXT:    br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]1279// CHECK11:       omp.precond.then:1280// CHECK11-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 81281// CHECK11-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 81282// CHECK11-NEXT:    store i64 [[TMP11]], ptr [[DOTOMP_UB]], align 81283// CHECK11-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 81284// CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41285// CHECK11-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41286// CHECK11-NEXT:    [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 41287// CHECK11-NEXT:    call void @__kmpc_for_static_init_8(ptr @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)1288// CHECK11-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_UB]], align 81289// CHECK11-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 81290// CHECK11-NEXT:    [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]]1291// CHECK11-NEXT:    br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1292// CHECK11:       cond.true:1293// CHECK11-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 81294// CHECK11-NEXT:    br label [[COND_END:%.*]]1295// CHECK11:       cond.false:1296// CHECK11-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_UB]], align 81297// CHECK11-NEXT:    br label [[COND_END]]1298// CHECK11:       cond.end:1299// CHECK11-NEXT:    [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ]1300// CHECK11-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 81301// CHECK11-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_LB]], align 81302// CHECK11-NEXT:    store i64 [[TMP18]], ptr [[DOTOMP_IV]], align 81303// CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1304// CHECK11:       omp.inner.for.cond:1305// CHECK11-NEXT:    [[TMP19:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6:![0-9]+]]1306// CHECK11-NEXT:    [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP6]]1307// CHECK11-NEXT:    [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]]1308// CHECK11-NEXT:    br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1309// CHECK11:       omp.inner.for.body:1310// CHECK11-NEXT:    [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6]]1311// CHECK11-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP6]]1312// CHECK11-NEXT:    [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 01313// CHECK11-NEXT:    [[DIV16:%.*]] = sdiv i32 [[SUB15]], 11314// CHECK11-NEXT:    [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]1315// CHECK11-NEXT:    [[CONV18:%.*]] = sext i32 [[MUL17]] to i641316// CHECK11-NEXT:    [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]]1317// CHECK11-NEXT:    [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 11318// CHECK11-NEXT:    [[ADD:%.*]] = add nsw i64 0, [[MUL20]]1319// CHECK11-NEXT:    [[CONV21:%.*]] = trunc i64 [[ADD]] to i321320// CHECK11-NEXT:    store i32 [[CONV21]], ptr [[I11]], align 4, !llvm.access.group [[ACC_GRP6]]1321// CHECK11-NEXT:    [[TMP23:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6]]1322// CHECK11-NEXT:    [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6]]1323// CHECK11-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP6]]1324// CHECK11-NEXT:    [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 01325// CHECK11-NEXT:    [[DIV23:%.*]] = sdiv i32 [[SUB22]], 11326// CHECK11-NEXT:    [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]1327// CHECK11-NEXT:    [[CONV25:%.*]] = sext i32 [[MUL24]] to i641328// CHECK11-NEXT:    [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]]1329// CHECK11-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP6]]1330// CHECK11-NEXT:    [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 01331// CHECK11-NEXT:    [[DIV28:%.*]] = sdiv i32 [[SUB27]], 11332// CHECK11-NEXT:    [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]1333// CHECK11-NEXT:    [[CONV30:%.*]] = sext i32 [[MUL29]] to i641334// CHECK11-NEXT:    [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]1335// CHECK11-NEXT:    [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]]1336// CHECK11-NEXT:    [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 11337// CHECK11-NEXT:    [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]1338// CHECK11-NEXT:    [[CONV35:%.*]] = trunc i64 [[ADD34]] to i321339// CHECK11-NEXT:    store i32 [[CONV35]], ptr [[J12]], align 4, !llvm.access.group [[ACC_GRP6]]1340// CHECK11-NEXT:    [[TMP27:%.*]] = load i32, ptr [[I11]], align 4, !llvm.access.group [[ACC_GRP6]]1341// CHECK11-NEXT:    [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP3]]1342// CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i32 [[TMP28]]1343// CHECK11-NEXT:    [[TMP29:%.*]] = load i32, ptr [[J12]], align 4, !llvm.access.group [[ACC_GRP6]]1344// CHECK11-NEXT:    [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i32 [[TMP29]]1345// CHECK11-NEXT:    store i32 0, ptr [[ARRAYIDX36]], align 4, !llvm.access.group [[ACC_GRP6]]1346// CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1347// CHECK11:       omp.body.continue:1348// CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1349// CHECK11:       omp.inner.for.inc:1350// CHECK11-NEXT:    [[TMP30:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6]]1351// CHECK11-NEXT:    [[ADD37:%.*]] = add nsw i64 [[TMP30]], 11352// CHECK11-NEXT:    store i64 [[ADD37]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6]]1353// CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]1354// CHECK11:       omp.inner.for.end:1355// CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]1356// CHECK11:       omp.loop.exit:1357// CHECK11-NEXT:    [[TMP31:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41358// CHECK11-NEXT:    [[TMP32:%.*]] = load i32, ptr [[TMP31]], align 41359// CHECK11-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP32]])1360// CHECK11-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41361// CHECK11-NEXT:    [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 01362// CHECK11-NEXT:    br i1 [[TMP34]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1363// CHECK11:       .omp.final.then:1364// CHECK11-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41365// CHECK11-NEXT:    [[SUB38:%.*]] = sub nsw i32 [[TMP35]], 01366// CHECK11-NEXT:    [[DIV39:%.*]] = sdiv i32 [[SUB38]], 11367// CHECK11-NEXT:    [[MUL40:%.*]] = mul nsw i32 [[DIV39]], 11368// CHECK11-NEXT:    [[ADD41:%.*]] = add nsw i32 0, [[MUL40]]1369// CHECK11-NEXT:    store i32 [[ADD41]], ptr [[I11]], align 41370// CHECK11-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 41371// CHECK11-NEXT:    [[SUB42:%.*]] = sub nsw i32 [[TMP36]], 01372// CHECK11-NEXT:    [[DIV43:%.*]] = sdiv i32 [[SUB42]], 11373// CHECK11-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[DIV43]], 11374// CHECK11-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]1375// CHECK11-NEXT:    store i32 [[ADD45]], ptr [[J12]], align 41376// CHECK11-NEXT:    br label [[DOTOMP_FINAL_DONE]]1377// CHECK11:       .omp.final.done:1378// CHECK11-NEXT:    br label [[OMP_PRECOND_END]]1379// CHECK11:       omp.precond.end:1380// CHECK11-NEXT:    ret void1381//1382//1383// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_1384// CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat {1385// CHECK11-NEXT:  entry:1386// CHECK11-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 41387// CHECK11-NEXT:    [[A:%.*]] = alloca [10 x [2 x i32]], align 41388// CHECK11-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 41389// CHECK11-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 41390// CHECK11-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 41391// CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 41392// CHECK11-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41393// CHECK11-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81394// CHECK11-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 41395// CHECK11-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01396// CHECK11-NEXT:    store ptr [[A]], ptr [[TMP0]], align 41397// CHECK11-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01398// CHECK11-NEXT:    store ptr [[A]], ptr [[TMP1]], align 41399// CHECK11-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 01400// CHECK11-NEXT:    store ptr null, ptr [[TMP2]], align 41401// CHECK11-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01402// CHECK11-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01403// CHECK11-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01404// CHECK11-NEXT:    store i32 3, ptr [[TMP5]], align 41405// CHECK11-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11406// CHECK11-NEXT:    store i32 1, ptr [[TMP6]], align 41407// CHECK11-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21408// CHECK11-NEXT:    store ptr [[TMP3]], ptr [[TMP7]], align 41409// CHECK11-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31410// CHECK11-NEXT:    store ptr [[TMP4]], ptr [[TMP8]], align 41411// CHECK11-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41412// CHECK11-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP9]], align 41413// CHECK11-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51414// CHECK11-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP10]], align 41415// CHECK11-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61416// CHECK11-NEXT:    store ptr null, ptr [[TMP11]], align 41417// CHECK11-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71418// CHECK11-NEXT:    store ptr null, ptr [[TMP12]], align 41419// CHECK11-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81420// CHECK11-NEXT:    store i64 20, ptr [[TMP13]], align 81421// CHECK11-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91422// CHECK11-NEXT:    store i64 0, ptr [[TMP14]], align 81423// CHECK11-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101424// CHECK11-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP15]], align 41425// CHECK11-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111426// CHECK11-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP16]], align 41427// CHECK11-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121428// CHECK11-NEXT:    store i32 0, ptr [[TMP17]], align 41429// CHECK11-NEXT:    [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.region_id, ptr [[KERNEL_ARGS]])1430// CHECK11-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 01431// CHECK11-NEXT:    br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1432// CHECK11:       omp_offload.failed:1433// CHECK11-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69(ptr [[A]]) #[[ATTR3]]1434// CHECK11-NEXT:    br label [[OMP_OFFLOAD_CONT]]1435// CHECK11:       omp_offload.cont:1436// CHECK11-NEXT:    ret i32 01437//1438//1439// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l691440// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {1441// CHECK11-NEXT:  entry:1442// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 41443// CHECK11-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 41444// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 41445// CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.omp_outlined, ptr [[TMP0]])1446// CHECK11-NEXT:    ret void1447//1448//1449// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.omp_outlined1450// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {1451// CHECK11-NEXT:  entry:1452// CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41453// CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41454// CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 41455// CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41456// CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 41457// CHECK11-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41458// CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41459// CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41460// CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41461// CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41462// CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 41463// CHECK11-NEXT:    [[J:%.*]] = alloca i32, align 41464// CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41465// CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41466// CHECK11-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 41467// CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 41468// CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41469// CHECK11-NEXT:    store i32 19, ptr [[DOTOMP_UB]], align 41470// CHECK11-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 41471// CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 41472// CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41473// CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 41474// CHECK11-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1475// CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41476// CHECK11-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 191477// CHECK11-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1478// CHECK11:       cond.true:1479// CHECK11-NEXT:    br label [[COND_END:%.*]]1480// CHECK11:       cond.false:1481// CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41482// CHECK11-NEXT:    br label [[COND_END]]1483// CHECK11:       cond.end:1484// CHECK11-NEXT:    [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]1485// CHECK11-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 41486// CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41487// CHECK11-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 41488// CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1489// CHECK11:       omp.inner.for.cond:1490// CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]1491// CHECK11-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]1492// CHECK11-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]1493// CHECK11-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1494// CHECK11:       omp.inner.for.body:1495// CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]1496// CHECK11-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP8]], 21497// CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 11498// CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1499// CHECK11-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]1500// CHECK11-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]1501// CHECK11-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]1502// CHECK11-NEXT:    [[DIV3:%.*]] = sdiv i32 [[TMP10]], 21503// CHECK11-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 21504// CHECK11-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]1505// CHECK11-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[SUB]], 11506// CHECK11-NEXT:    [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]1507// CHECK11-NEXT:    store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP12]]1508// CHECK11-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]1509// CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP11]]1510// CHECK11-NEXT:    [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP12]]1511// CHECK11-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP12]]1512// CHECK11-NEXT:    store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP12]]1513// CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1514// CHECK11:       omp.body.continue:1515// CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1516// CHECK11:       omp.inner.for.inc:1517// CHECK11-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]1518// CHECK11-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP13]], 11519// CHECK11-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]1520// CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]1521// CHECK11:       omp.inner.for.end:1522// CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]1523// CHECK11:       omp.loop.exit:1524// CHECK11-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])1525// CHECK11-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41526// CHECK11-NEXT:    [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 01527// CHECK11-NEXT:    br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1528// CHECK11:       .omp.final.then:1529// CHECK11-NEXT:    store i32 10, ptr [[I]], align 41530// CHECK11-NEXT:    store i32 2, ptr [[J]], align 41531// CHECK11-NEXT:    br label [[DOTOMP_FINAL_DONE]]1532// CHECK11:       .omp.final.done:1533// CHECK11-NEXT:    ret void1534//1535//1536// CHECK13-LABEL: define {{[^@]+}}@main1537// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {1538// CHECK13-NEXT:  entry:1539// CHECK13-NEXT:    [[RETVAL:%.*]] = alloca i32, align 41540// CHECK13-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 41541// CHECK13-NEXT:    [[ARGV_ADDR:%.*]] = alloca ptr, align 81542// CHECK13-NEXT:    [[N:%.*]] = alloca i32, align 41543// CHECK13-NEXT:    [[M:%.*]] = alloca i32, align 41544// CHECK13-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 81545// CHECK13-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 81546// CHECK13-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 81547// CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 41548// CHECK13-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41549// CHECK13-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 41550// CHECK13-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 41551// CHECK13-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 81552// CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 81553// CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 81554// CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 41555// CHECK13-NEXT:    [[J:%.*]] = alloca i32, align 41556// CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 81557// CHECK13-NEXT:    [[I9:%.*]] = alloca i32, align 41558// CHECK13-NEXT:    [[J10:%.*]] = alloca i32, align 41559// CHECK13-NEXT:    store i32 0, ptr [[RETVAL]], align 41560// CHECK13-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 41561// CHECK13-NEXT:    store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 81562// CHECK13-NEXT:    store i32 100, ptr [[N]], align 41563// CHECK13-NEXT:    store i32 2, ptr [[M]], align 41564// CHECK13-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N]], align 41565// CHECK13-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i641566// CHECK13-NEXT:    [[TMP2:%.*]] = load i32, ptr [[M]], align 41567// CHECK13-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i641568// CHECK13-NEXT:    [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()1569// CHECK13-NEXT:    store ptr [[TMP4]], ptr [[SAVED_STACK]], align 81570// CHECK13-NEXT:    [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]1571// CHECK13-NEXT:    [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 41572// CHECK13-NEXT:    store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 81573// CHECK13-NEXT:    store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 81574// CHECK13-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N]], align 41575// CHECK13-NEXT:    store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 41576// CHECK13-NEXT:    [[TMP7:%.*]] = load i32, ptr [[M]], align 41577// CHECK13-NEXT:    store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_2]], align 41578// CHECK13-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41579// CHECK13-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP8]], 01580// CHECK13-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 11581// CHECK13-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i641582// CHECK13-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41583// CHECK13-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP9]], 01584// CHECK13-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 11585// CHECK13-NEXT:    [[CONV6:%.*]] = sext i32 [[DIV5]] to i641586// CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]1587// CHECK13-NEXT:    [[SUB7:%.*]] = sub nsw i64 [[MUL]], 11588// CHECK13-NEXT:    store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 81589// CHECK13-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 81590// CHECK13-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 81591// CHECK13-NEXT:    store i64 [[TMP10]], ptr [[DOTOMP_UB]], align 81592// CHECK13-NEXT:    store i32 0, ptr [[I]], align 41593// CHECK13-NEXT:    store i32 0, ptr [[J]], align 41594// CHECK13-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41595// CHECK13-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP11]]1596// CHECK13-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]]1597// CHECK13:       land.lhs.true:1598// CHECK13-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41599// CHECK13-NEXT:    [[CMP8:%.*]] = icmp slt i32 0, [[TMP12]]1600// CHECK13-NEXT:    br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]]1601// CHECK13:       simd.if.then:1602// CHECK13-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_LB]], align 81603// CHECK13-NEXT:    store i64 [[TMP13]], ptr [[DOTOMP_IV]], align 81604// CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1605// CHECK13:       omp.inner.for.cond:1606// CHECK13-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2:![0-9]+]]1607// CHECK13-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]]1608// CHECK13-NEXT:    [[CMP11:%.*]] = icmp sle i64 [[TMP14]], [[TMP15]]1609// CHECK13-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1610// CHECK13:       omp.inner.for.body:1611// CHECK13-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2]]1612// CHECK13-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP2]]1613// CHECK13-NEXT:    [[SUB12:%.*]] = sub nsw i32 [[TMP17]], 01614// CHECK13-NEXT:    [[DIV13:%.*]] = sdiv i32 [[SUB12]], 11615// CHECK13-NEXT:    [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]]1616// CHECK13-NEXT:    [[CONV15:%.*]] = sext i32 [[MUL14]] to i641617// CHECK13-NEXT:    [[DIV16:%.*]] = sdiv i64 [[TMP16]], [[CONV15]]1618// CHECK13-NEXT:    [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 11619// CHECK13-NEXT:    [[ADD:%.*]] = add nsw i64 0, [[MUL17]]1620// CHECK13-NEXT:    [[CONV18:%.*]] = trunc i64 [[ADD]] to i321621// CHECK13-NEXT:    store i32 [[CONV18]], ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP2]]1622// CHECK13-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2]]1623// CHECK13-NEXT:    [[TMP19:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2]]1624// CHECK13-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP2]]1625// CHECK13-NEXT:    [[SUB19:%.*]] = sub nsw i32 [[TMP20]], 01626// CHECK13-NEXT:    [[DIV20:%.*]] = sdiv i32 [[SUB19]], 11627// CHECK13-NEXT:    [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]]1628// CHECK13-NEXT:    [[CONV22:%.*]] = sext i32 [[MUL21]] to i641629// CHECK13-NEXT:    [[DIV23:%.*]] = sdiv i64 [[TMP19]], [[CONV22]]1630// CHECK13-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP2]]1631// CHECK13-NEXT:    [[SUB24:%.*]] = sub nsw i32 [[TMP21]], 01632// CHECK13-NEXT:    [[DIV25:%.*]] = sdiv i32 [[SUB24]], 11633// CHECK13-NEXT:    [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]]1634// CHECK13-NEXT:    [[CONV27:%.*]] = sext i32 [[MUL26]] to i641635// CHECK13-NEXT:    [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]]1636// CHECK13-NEXT:    [[SUB29:%.*]] = sub nsw i64 [[TMP18]], [[MUL28]]1637// CHECK13-NEXT:    [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 11638// CHECK13-NEXT:    [[ADD31:%.*]] = add nsw i64 0, [[MUL30]]1639// CHECK13-NEXT:    [[CONV32:%.*]] = trunc i64 [[ADD31]] to i321640// CHECK13-NEXT:    store i32 [[CONV32]], ptr [[J10]], align 4, !llvm.access.group [[ACC_GRP2]]1641// CHECK13-NEXT:    [[TMP22:%.*]] = load i32, ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP2]]1642// CHECK13-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i641643// CHECK13-NEXT:    [[TMP23:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]]1644// CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i64 [[TMP23]]1645// CHECK13-NEXT:    [[TMP24:%.*]] = load i32, ptr [[J10]], align 4, !llvm.access.group [[ACC_GRP2]]1646// CHECK13-NEXT:    [[IDXPROM33:%.*]] = sext i32 [[TMP24]] to i641647// CHECK13-NEXT:    [[ARRAYIDX34:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i64 [[IDXPROM33]]1648// CHECK13-NEXT:    store i32 0, ptr [[ARRAYIDX34]], align 4, !llvm.access.group [[ACC_GRP2]]1649// CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1650// CHECK13:       omp.body.continue:1651// CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1652// CHECK13:       omp.inner.for.inc:1653// CHECK13-NEXT:    [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2]]1654// CHECK13-NEXT:    [[ADD35:%.*]] = add nsw i64 [[TMP25]], 11655// CHECK13-NEXT:    store i64 [[ADD35]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2]]1656// CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]1657// CHECK13:       omp.inner.for.end:1658// CHECK13-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41659// CHECK13-NEXT:    [[SUB36:%.*]] = sub nsw i32 [[TMP26]], 01660// CHECK13-NEXT:    [[DIV37:%.*]] = sdiv i32 [[SUB36]], 11661// CHECK13-NEXT:    [[MUL38:%.*]] = mul nsw i32 [[DIV37]], 11662// CHECK13-NEXT:    [[ADD39:%.*]] = add nsw i32 0, [[MUL38]]1663// CHECK13-NEXT:    store i32 [[ADD39]], ptr [[I9]], align 41664// CHECK13-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41665// CHECK13-NEXT:    [[SUB40:%.*]] = sub nsw i32 [[TMP27]], 01666// CHECK13-NEXT:    [[DIV41:%.*]] = sdiv i32 [[SUB40]], 11667// CHECK13-NEXT:    [[MUL42:%.*]] = mul nsw i32 [[DIV41]], 11668// CHECK13-NEXT:    [[ADD43:%.*]] = add nsw i32 0, [[MUL42]]1669// CHECK13-NEXT:    store i32 [[ADD43]], ptr [[J10]], align 41670// CHECK13-NEXT:    br label [[SIMD_IF_END]]1671// CHECK13:       simd.if.end:1672// CHECK13-NEXT:    [[TMP28:%.*]] = load i32, ptr [[ARGC_ADDR]], align 41673// CHECK13-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]])1674// CHECK13-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 41675// CHECK13-NEXT:    [[TMP29:%.*]] = load ptr, ptr [[SAVED_STACK]], align 81676// CHECK13-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP29]])1677// CHECK13-NEXT:    [[TMP30:%.*]] = load i32, ptr [[RETVAL]], align 41678// CHECK13-NEXT:    ret i32 [[TMP30]]1679//1680//1681// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_1682// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {1683// CHECK13-NEXT:  entry:1684// CHECK13-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 41685// CHECK13-NEXT:    [[A:%.*]] = alloca [10 x [2 x i32]], align 41686// CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 41687// CHECK13-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41688// CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41689// CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41690// CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41691// CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 41692// CHECK13-NEXT:    [[J:%.*]] = alloca i32, align 41693// CHECK13-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 41694// CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41695// CHECK13-NEXT:    store i32 19, ptr [[DOTOMP_UB]], align 41696// CHECK13-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41697// CHECK13-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 41698// CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1699// CHECK13:       omp.inner.for.cond:1700// CHECK13-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]1701// CHECK13-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]]1702// CHECK13-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]1703// CHECK13-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1704// CHECK13:       omp.inner.for.body:1705// CHECK13-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]1706// CHECK13-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP3]], 21707// CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 11708// CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1709// CHECK13-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]1710// CHECK13-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]1711// CHECK13-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]1712// CHECK13-NEXT:    [[DIV2:%.*]] = sdiv i32 [[TMP5]], 21713// CHECK13-NEXT:    [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 21714// CHECK13-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]]1715// CHECK13-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[SUB]], 11716// CHECK13-NEXT:    [[ADD5:%.*]] = add nsw i32 0, [[MUL4]]1717// CHECK13-NEXT:    store i32 [[ADD5]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP6]]1718// CHECK13-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]1719// CHECK13-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i641720// CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]]1721// CHECK13-NEXT:    [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP6]]1722// CHECK13-NEXT:    [[IDXPROM6:%.*]] = sext i32 [[TMP7]] to i641723// CHECK13-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM6]]1724// CHECK13-NEXT:    store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP6]]1725// CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1726// CHECK13:       omp.body.continue:1727// CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1728// CHECK13:       omp.inner.for.inc:1729// CHECK13-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]1730// CHECK13-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP8]], 11731// CHECK13-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]1732// CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]1733// CHECK13:       omp.inner.for.end:1734// CHECK13-NEXT:    store i32 10, ptr [[I]], align 41735// CHECK13-NEXT:    store i32 2, ptr [[J]], align 41736// CHECK13-NEXT:    ret i32 01737//1738//1739// CHECK15-LABEL: define {{[^@]+}}@main1740// CHECK15-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {1741// CHECK15-NEXT:  entry:1742// CHECK15-NEXT:    [[RETVAL:%.*]] = alloca i32, align 41743// CHECK15-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 41744// CHECK15-NEXT:    [[ARGV_ADDR:%.*]] = alloca ptr, align 41745// CHECK15-NEXT:    [[N:%.*]] = alloca i32, align 41746// CHECK15-NEXT:    [[M:%.*]] = alloca i32, align 41747// CHECK15-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 41748// CHECK15-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 41749// CHECK15-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 41750// CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 41751// CHECK15-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41752// CHECK15-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 41753// CHECK15-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 41754// CHECK15-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 81755// CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 81756// CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 81757// CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 41758// CHECK15-NEXT:    [[J:%.*]] = alloca i32, align 41759// CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 81760// CHECK15-NEXT:    [[I9:%.*]] = alloca i32, align 41761// CHECK15-NEXT:    [[J10:%.*]] = alloca i32, align 41762// CHECK15-NEXT:    store i32 0, ptr [[RETVAL]], align 41763// CHECK15-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 41764// CHECK15-NEXT:    store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 41765// CHECK15-NEXT:    store i32 100, ptr [[N]], align 41766// CHECK15-NEXT:    store i32 2, ptr [[M]], align 41767// CHECK15-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N]], align 41768// CHECK15-NEXT:    [[TMP1:%.*]] = load i32, ptr [[M]], align 41769// CHECK15-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()1770// CHECK15-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 41771// CHECK15-NEXT:    [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]1772// CHECK15-NEXT:    [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 41773// CHECK15-NEXT:    store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 41774// CHECK15-NEXT:    store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 41775// CHECK15-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N]], align 41776// CHECK15-NEXT:    store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 41777// CHECK15-NEXT:    [[TMP5:%.*]] = load i32, ptr [[M]], align 41778// CHECK15-NEXT:    store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_2]], align 41779// CHECK15-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41780// CHECK15-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP6]], 01781// CHECK15-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 11782// CHECK15-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i641783// CHECK15-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41784// CHECK15-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP7]], 01785// CHECK15-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 11786// CHECK15-NEXT:    [[CONV6:%.*]] = sext i32 [[DIV5]] to i641787// CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]1788// CHECK15-NEXT:    [[SUB7:%.*]] = sub nsw i64 [[MUL]], 11789// CHECK15-NEXT:    store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 81790// CHECK15-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 81791// CHECK15-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 81792// CHECK15-NEXT:    store i64 [[TMP8]], ptr [[DOTOMP_UB]], align 81793// CHECK15-NEXT:    store i32 0, ptr [[I]], align 41794// CHECK15-NEXT:    store i32 0, ptr [[J]], align 41795// CHECK15-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41796// CHECK15-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP9]]1797// CHECK15-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]]1798// CHECK15:       land.lhs.true:1799// CHECK15-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41800// CHECK15-NEXT:    [[CMP8:%.*]] = icmp slt i32 0, [[TMP10]]1801// CHECK15-NEXT:    br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]]1802// CHECK15:       simd.if.then:1803// CHECK15-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_LB]], align 81804// CHECK15-NEXT:    store i64 [[TMP11]], ptr [[DOTOMP_IV]], align 81805// CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1806// CHECK15:       omp.inner.for.cond:1807// CHECK15-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3:![0-9]+]]1808// CHECK15-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP3]]1809// CHECK15-NEXT:    [[CMP11:%.*]] = icmp sle i64 [[TMP12]], [[TMP13]]1810// CHECK15-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1811// CHECK15:       omp.inner.for.body:1812// CHECK15-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]1813// CHECK15-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]1814// CHECK15-NEXT:    [[SUB12:%.*]] = sub nsw i32 [[TMP15]], 01815// CHECK15-NEXT:    [[DIV13:%.*]] = sdiv i32 [[SUB12]], 11816// CHECK15-NEXT:    [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]]1817// CHECK15-NEXT:    [[CONV15:%.*]] = sext i32 [[MUL14]] to i641818// CHECK15-NEXT:    [[DIV16:%.*]] = sdiv i64 [[TMP14]], [[CONV15]]1819// CHECK15-NEXT:    [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 11820// CHECK15-NEXT:    [[ADD:%.*]] = add nsw i64 0, [[MUL17]]1821// CHECK15-NEXT:    [[CONV18:%.*]] = trunc i64 [[ADD]] to i321822// CHECK15-NEXT:    store i32 [[CONV18]], ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP3]]1823// CHECK15-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]1824// CHECK15-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]1825// CHECK15-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]1826// CHECK15-NEXT:    [[SUB19:%.*]] = sub nsw i32 [[TMP18]], 01827// CHECK15-NEXT:    [[DIV20:%.*]] = sdiv i32 [[SUB19]], 11828// CHECK15-NEXT:    [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]]1829// CHECK15-NEXT:    [[CONV22:%.*]] = sext i32 [[MUL21]] to i641830// CHECK15-NEXT:    [[DIV23:%.*]] = sdiv i64 [[TMP17]], [[CONV22]]1831// CHECK15-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]1832// CHECK15-NEXT:    [[SUB24:%.*]] = sub nsw i32 [[TMP19]], 01833// CHECK15-NEXT:    [[DIV25:%.*]] = sdiv i32 [[SUB24]], 11834// CHECK15-NEXT:    [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]]1835// CHECK15-NEXT:    [[CONV27:%.*]] = sext i32 [[MUL26]] to i641836// CHECK15-NEXT:    [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]]1837// CHECK15-NEXT:    [[SUB29:%.*]] = sub nsw i64 [[TMP16]], [[MUL28]]1838// CHECK15-NEXT:    [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 11839// CHECK15-NEXT:    [[ADD31:%.*]] = add nsw i64 0, [[MUL30]]1840// CHECK15-NEXT:    [[CONV32:%.*]] = trunc i64 [[ADD31]] to i321841// CHECK15-NEXT:    store i32 [[CONV32]], ptr [[J10]], align 4, !llvm.access.group [[ACC_GRP3]]1842// CHECK15-NEXT:    [[TMP20:%.*]] = load i32, ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP3]]1843// CHECK15-NEXT:    [[TMP21:%.*]] = mul nsw i32 [[TMP20]], [[TMP1]]1844// CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i32 [[TMP21]]1845// CHECK15-NEXT:    [[TMP22:%.*]] = load i32, ptr [[J10]], align 4, !llvm.access.group [[ACC_GRP3]]1846// CHECK15-NEXT:    [[ARRAYIDX33:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i32 [[TMP22]]1847// CHECK15-NEXT:    store i32 0, ptr [[ARRAYIDX33]], align 4, !llvm.access.group [[ACC_GRP3]]1848// CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1849// CHECK15:       omp.body.continue:1850// CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1851// CHECK15:       omp.inner.for.inc:1852// CHECK15-NEXT:    [[TMP23:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]1853// CHECK15-NEXT:    [[ADD34:%.*]] = add nsw i64 [[TMP23]], 11854// CHECK15-NEXT:    store i64 [[ADD34]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]1855// CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]1856// CHECK15:       omp.inner.for.end:1857// CHECK15-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 41858// CHECK15-NEXT:    [[SUB35:%.*]] = sub nsw i32 [[TMP24]], 01859// CHECK15-NEXT:    [[DIV36:%.*]] = sdiv i32 [[SUB35]], 11860// CHECK15-NEXT:    [[MUL37:%.*]] = mul nsw i32 [[DIV36]], 11861// CHECK15-NEXT:    [[ADD38:%.*]] = add nsw i32 0, [[MUL37]]1862// CHECK15-NEXT:    store i32 [[ADD38]], ptr [[I9]], align 41863// CHECK15-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 41864// CHECK15-NEXT:    [[SUB39:%.*]] = sub nsw i32 [[TMP25]], 01865// CHECK15-NEXT:    [[DIV40:%.*]] = sdiv i32 [[SUB39]], 11866// CHECK15-NEXT:    [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 11867// CHECK15-NEXT:    [[ADD42:%.*]] = add nsw i32 0, [[MUL41]]1868// CHECK15-NEXT:    store i32 [[ADD42]], ptr [[J10]], align 41869// CHECK15-NEXT:    br label [[SIMD_IF_END]]1870// CHECK15:       simd.if.end:1871// CHECK15-NEXT:    [[TMP26:%.*]] = load i32, ptr [[ARGC_ADDR]], align 41872// CHECK15-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]])1873// CHECK15-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 41874// CHECK15-NEXT:    [[TMP27:%.*]] = load ptr, ptr [[SAVED_STACK]], align 41875// CHECK15-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP27]])1876// CHECK15-NEXT:    [[TMP28:%.*]] = load i32, ptr [[RETVAL]], align 41877// CHECK15-NEXT:    ret i32 [[TMP28]]1878//1879//1880// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_1881// CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {1882// CHECK15-NEXT:  entry:1883// CHECK15-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 41884// CHECK15-NEXT:    [[A:%.*]] = alloca [10 x [2 x i32]], align 41885// CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 41886// CHECK15-NEXT:    [[_TMP1:%.*]] = alloca i32, align 41887// CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 41888// CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 41889// CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 41890// CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 41891// CHECK15-NEXT:    [[J:%.*]] = alloca i32, align 41892// CHECK15-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 41893// CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 41894// CHECK15-NEXT:    store i32 19, ptr [[DOTOMP_UB]], align 41895// CHECK15-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41896// CHECK15-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 41897// CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]1898// CHECK15:       omp.inner.for.cond:1899// CHECK15-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]1900// CHECK15-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]]1901// CHECK15-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]1902// CHECK15-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1903// CHECK15:       omp.inner.for.body:1904// CHECK15-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]1905// CHECK15-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP3]], 21906// CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 11907// CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]1908// CHECK15-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]1909// CHECK15-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]1910// CHECK15-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]1911// CHECK15-NEXT:    [[DIV2:%.*]] = sdiv i32 [[TMP5]], 21912// CHECK15-NEXT:    [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 21913// CHECK15-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]]1914// CHECK15-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[SUB]], 11915// CHECK15-NEXT:    [[ADD5:%.*]] = add nsw i32 0, [[MUL4]]1916// CHECK15-NEXT:    store i32 [[ADD5]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP7]]1917// CHECK15-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]1918// CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], i32 0, i32 [[TMP6]]1919// CHECK15-NEXT:    [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP7]]1920// CHECK15-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP7]]1921// CHECK15-NEXT:    store i32 0, ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP7]]1922// CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]1923// CHECK15:       omp.body.continue:1924// CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]1925// CHECK15:       omp.inner.for.inc:1926// CHECK15-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]1927// CHECK15-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP8]], 11928// CHECK15-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]1929// CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]1930// CHECK15:       omp.inner.for.end:1931// CHECK15-NEXT:    store i32 10, ptr [[I]], align 41932// CHECK15-NEXT:    store i32 2, ptr [[J]], align 41933// CHECK15-NEXT:    ret i32 01934//1935