2796 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping4// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK36// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping7// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK38 9// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK510// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping11// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK512// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK713// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping14// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK715 16// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK917// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping18// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK919 20// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1121// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping22// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1123 24// expected-no-diagnostics25#ifndef HEADER26#define HEADER27 28struct St {29 int a, b;30 St() : a(0), b(0) {}31 St(const St &st) : a(st.a + st.b), b(0) {}32 ~St() {}33};34 35volatile int g = 1212;36volatile int &g1 = g;37 38template <class T>39struct S {40 T f;41 S(T a) : f(a + g) {}42 S() : f(g) {}43 S(const S &s, St t = St()) : f(s.f + t.a) {}44 operator T() { return T(); }45 ~S() {}46};47 48 49template <typename T>50T tmain() {51 S<T> test;52 T t_var = T();53 T vec[] = {1, 2};54 S<T> s_arr[] = {1, 2};55 S<T> &var = test;56#pragma omp target57#pragma omp teams distribute simd firstprivate(t_var, vec, s_arr, var)58 for (int i = 0; i < 2; ++i) {59 vec[i] = t_var;60 s_arr[i] = var;61 }62 return T();63}64 65S<float> test;66int t_var = 333;67int vec[] = {1, 2};68S<float> s_arr[] = {1, 2};69S<float> var(3);70 71int main() {72 static int sivar;73#ifdef LAMBDA74 [&]() {75#pragma omp target76#pragma omp teams distribute simd firstprivate(g, g1, sivar)77 for (int i = 0; i < 2; ++i) {78 79 // Skip global and bound tid vars80 // skip loop vars81 g = 1;82 g1 = 1;83 sivar = 2;84 [&]() {85 g = 2;86 g1 = 2;87 sivar = 4;88 89 }();90 }91 }();92 return 0;93#else94#pragma omp target95#pragma omp teams distribute simd firstprivate(t_var, vec, s_arr, var, sivar)96 for (int i = 0; i < 2; ++i) {97 vec[i] = t_var;98 s_arr[i] = var;99 sivar += i;100 }101 return tmain<int>();102#endif103}104 105 106 107 108 109// Skip global and bound tid vars110// Skip temp vars for loop111 112// param copy113 114// T_VAR and SIVAR115 116// preparation vars117 118// firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2119 120// firstprivate(s_arr)121 122// firstprivate(var)123 124 125 126 127 128 129// Skip global and bound tid vars130// Skip temp vars for loop131 132// param copy133 134 135// T_VAR and preparation variables136 137// firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2138 139// firstprivate(s_arr)140 141// firstprivate(var)142 143 144#endif145// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init146// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {147// CHECK1-NEXT: entry:148// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)149// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]150// CHECK1-NEXT: ret void151//152//153// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev154// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {155// CHECK1-NEXT: entry:156// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8157// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8158// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8159// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])160// CHECK1-NEXT: ret void161//162//163// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev164// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {165// CHECK1-NEXT: entry:166// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8167// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8168// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8169// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]170// CHECK1-NEXT: ret void171//172//173// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev174// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {175// CHECK1-NEXT: entry:176// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8177// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8178// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8179// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0180// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4181// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float182// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4183// CHECK1-NEXT: ret void184//185//186// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev187// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {188// CHECK1-NEXT: entry:189// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8190// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8191// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8192// CHECK1-NEXT: ret void193//194//195// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1196// CHECK1-SAME: () #[[ATTR0]] {197// CHECK1-NEXT: entry:198// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)199// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)200// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]201// CHECK1-NEXT: ret void202//203//204// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef205// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {206// CHECK1-NEXT: entry:207// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8208// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4209// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8210// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4211// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8212// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4213// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])214// CHECK1-NEXT: ret void215//216//217// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor218// CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {219// CHECK1-NEXT: entry:220// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8221// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8222// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]223// CHECK1: arraydestroy.body:224// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]225// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1226// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]227// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr228// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]229// CHECK1: arraydestroy.done1:230// CHECK1-NEXT: ret void231//232//233// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef234// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {235// CHECK1-NEXT: entry:236// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8237// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4238// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8239// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4240// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8241// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0242// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4243// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4244// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float245// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]246// CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4247// CHECK1-NEXT: ret void248//249//250// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2251// CHECK1-SAME: () #[[ATTR0]] {252// CHECK1-NEXT: entry:253// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)254// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]255// CHECK1-NEXT: ret void256//257//258// CHECK1-LABEL: define {{[^@]+}}@main259// CHECK1-SAME: () #[[ATTR3:[0-9]+]] {260// CHECK1-NEXT: entry:261// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4262// CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8263// CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8264// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8265// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8266// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8267// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4268// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8269// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4270// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr @t_var, align 4271// CHECK1-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4272// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8273// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4274// CHECK1-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4275// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8276// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0277// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP4]], align 8278// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0279// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8280// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0281// CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8282// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1283// CHECK1-NEXT: store ptr @vec, ptr [[TMP7]], align 8284// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1285// CHECK1-NEXT: store ptr @vec, ptr [[TMP8]], align 8286// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1287// CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8288// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2289// CHECK1-NEXT: store ptr @s_arr, ptr [[TMP10]], align 8290// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2291// CHECK1-NEXT: store ptr @s_arr, ptr [[TMP11]], align 8292// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2293// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8294// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3295// CHECK1-NEXT: store ptr @var, ptr [[TMP13]], align 8296// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3297// CHECK1-NEXT: store ptr @var, ptr [[TMP14]], align 8298// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3299// CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8300// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4301// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP16]], align 8302// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4303// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP17]], align 8304// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4305// CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8306// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0307// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0308// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0309// CHECK1-NEXT: store i32 3, ptr [[TMP21]], align 4310// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1311// CHECK1-NEXT: store i32 5, ptr [[TMP22]], align 4312// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2313// CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8314// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3315// CHECK1-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 8316// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4317// CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP25]], align 8318// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5319// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 8320// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6321// CHECK1-NEXT: store ptr null, ptr [[TMP27]], align 8322// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7323// CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8324// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8325// CHECK1-NEXT: store i64 2, ptr [[TMP29]], align 8326// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9327// CHECK1-NEXT: store i64 0, ptr [[TMP30]], align 8328// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10329// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4330// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11331// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP32]], align 4332// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12333// CHECK1-NEXT: store i32 0, ptr [[TMP33]], align 4334// CHECK1-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, ptr [[KERNEL_ARGS]])335// CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0336// CHECK1-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]337// CHECK1: omp_offload.failed:338// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i64 [[TMP1]], ptr @vec, ptr @s_arr, ptr @var, i64 [[TMP3]]) #[[ATTR2]]339// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]340// CHECK1: omp_offload.cont:341// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()342// CHECK1-NEXT: ret i32 [[CALL]]343//344//345// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94346// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {347// CHECK1-NEXT: entry:348// CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8349// CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8350// CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8351// CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8352// CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8353// CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8354// CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8355// CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8356// CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8357// CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8358// CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8359// CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8360// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]]361// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]362// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]363// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4364// CHECK1-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4365// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8366// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4367// CHECK1-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4368// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8369// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i64 [[TMP6]])370// CHECK1-NEXT: ret void371//372//373// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined374// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] {375// CHECK1-NEXT: entry:376// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8377// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8378// CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8379// CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8380// CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8381// CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8382// CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8383// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4384// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4385// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4386// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4387// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4388// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4389// CHECK1-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4390// CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4391// CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4392// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4393// CHECK1-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4394// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4395// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8396// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8397// CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8398// CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8399// CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8400// CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8401// CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8402// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]403// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]404// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]405// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4406// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4407// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4408// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4409// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false)410// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0411// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2412// CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]413// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]414// CHECK1: omp.arraycpy.body:415// CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]416// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]417// CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])418// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])419// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]420// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1421// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1422// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]423// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]424// CHECK1: omp.arraycpy.done3:425// CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]])426// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]])427// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]428// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8429// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4430// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)431// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4432// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1433// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]434// CHECK1: cond.true:435// CHECK1-NEXT: br label [[COND_END:%.*]]436// CHECK1: cond.false:437// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4438// CHECK1-NEXT: br label [[COND_END]]439// CHECK1: cond.end:440// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]441// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4442// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4443// CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4444// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]445// CHECK1: omp.inner.for.cond:446// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]]447// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]]448// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]449// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]450// CHECK1: omp.inner.for.cond.cleanup:451// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]452// CHECK1: omp.inner.for.body:453// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]454// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1455// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]456// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]457// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP9]]458// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]459// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64460// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 [[IDXPROM]]461// CHECK1-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]]462// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]463// CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64464// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i64 0, i64 [[IDXPROM7]]465// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[VAR4]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]]466// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]467// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP9]]468// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]469// CHECK1-NEXT: store i32 [[ADD9]], ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP9]]470// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]471// CHECK1: omp.body.continue:472// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]473// CHECK1: omp.inner.for.inc:474// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]475// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP17]], 1476// CHECK1-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]477// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]478// CHECK1: omp.inner.for.end:479// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]480// CHECK1: omp.loop.exit:481// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8482// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4483// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]])484// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4485// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0486// CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]487// CHECK1: .omp.final.then:488// CHECK1-NEXT: store i32 2, ptr [[I]], align 4489// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]490// CHECK1: .omp.final.done:491// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]492// CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0493// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2494// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]495// CHECK1: arraydestroy.body:496// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]497// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1498// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]499// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]500// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]501// CHECK1: arraydestroy.done12:502// CHECK1-NEXT: ret void503//504//505// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev506// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {507// CHECK1-NEXT: entry:508// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8509// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8510// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8511// CHECK1-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])512// CHECK1-NEXT: ret void513//514//515// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St516// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {517// CHECK1-NEXT: entry:518// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8519// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8520// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8521// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8522// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8523// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8524// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8525// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8526// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])527// CHECK1-NEXT: ret void528//529//530// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev531// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {532// CHECK1-NEXT: entry:533// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8534// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8535// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8536// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]537// CHECK1-NEXT: ret void538//539//540// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v541// CHECK1-SAME: () #[[ATTR1]] comdat {542// CHECK1-NEXT: entry:543// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4544// CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4545// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4546// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4547// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4548// CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8549// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8550// CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8551// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8552// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8553// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8554// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4555// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8556// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])557// CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4558// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)559// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1)560// CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1561// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)562// CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8563// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META7]], !align [[META8]]564// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8565// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4566// CHECK1-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4567// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8568// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]569// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]570// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]571// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0572// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP6]], align 8573// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0574// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP7]], align 8575// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0576// CHECK1-NEXT: store ptr null, ptr [[TMP8]], align 8577// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1578// CHECK1-NEXT: store ptr [[VEC]], ptr [[TMP9]], align 8579// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1580// CHECK1-NEXT: store ptr [[VEC]], ptr [[TMP10]], align 8581// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1582// CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8583// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2584// CHECK1-NEXT: store ptr [[S_ARR]], ptr [[TMP12]], align 8585// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2586// CHECK1-NEXT: store ptr [[S_ARR]], ptr [[TMP13]], align 8587// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2588// CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8589// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3590// CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP15]], align 8591// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3592// CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 8593// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3594// CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8595// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0596// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0597// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0598// CHECK1-NEXT: store i32 3, ptr [[TMP20]], align 4599// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1600// CHECK1-NEXT: store i32 4, ptr [[TMP21]], align 4601// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2602// CHECK1-NEXT: store ptr [[TMP18]], ptr [[TMP22]], align 8603// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3604// CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8605// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4606// CHECK1-NEXT: store ptr @.offload_sizes.3, ptr [[TMP24]], align 8607// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5608// CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP25]], align 8609// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6610// CHECK1-NEXT: store ptr null, ptr [[TMP26]], align 8611// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7612// CHECK1-NEXT: store ptr null, ptr [[TMP27]], align 8613// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8614// CHECK1-NEXT: store i64 2, ptr [[TMP28]], align 8615// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9616// CHECK1-NEXT: store i64 0, ptr [[TMP29]], align 8617// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10618// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP30]], align 4619// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11620// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4621// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12622// CHECK1-NEXT: store i32 0, ptr [[TMP32]], align 4623// CHECK1-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])624// CHECK1-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0625// CHECK1-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]626// CHECK1: omp_offload.failed:627// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i64 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]]628// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]629// CHECK1: omp_offload.cont:630// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4631// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0632// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2633// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]634// CHECK1: arraydestroy.body:635// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]636// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1637// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]638// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]639// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]640// CHECK1: arraydestroy.done2:641// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]642// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4643// CHECK1-NEXT: ret i32 [[TMP36]]644//645//646// CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev647// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {648// CHECK1-NEXT: entry:649// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8650// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8651// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8652// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0653// CHECK1-NEXT: store i32 0, ptr [[A]], align 4654// CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1655// CHECK1-NEXT: store i32 0, ptr [[B]], align 4656// CHECK1-NEXT: ret void657//658//659// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St660// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {661// CHECK1-NEXT: entry:662// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8663// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8664// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8665// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8666// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8667// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8668// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8669// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0670// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]671// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0672// CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4673// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0674// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4675// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float676// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]677// CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4678// CHECK1-NEXT: ret void679//680//681// CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev682// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {683// CHECK1-NEXT: entry:684// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8685// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8686// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8687// CHECK1-NEXT: ret void688//689//690// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev691// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {692// CHECK1-NEXT: entry:693// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8694// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8695// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8696// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])697// CHECK1-NEXT: ret void698//699//700// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei701// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {702// CHECK1-NEXT: entry:703// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8704// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4705// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8706// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4707// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8708// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4709// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])710// CHECK1-NEXT: ret void711//712//713// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56714// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {715// CHECK1-NEXT: entry:716// CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8717// CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8718// CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8719// CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8720// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8721// CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8722// CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8723// CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8724// CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8725// CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8726// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]727// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]728// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]729// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8730// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4731// CHECK1-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4732// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8733// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]734// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]])735// CHECK1-NEXT: ret void736//737//738// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined739// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {740// CHECK1-NEXT: entry:741// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8742// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8743// CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8744// CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8745// CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8746// CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8747// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8748// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4749// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4750// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4751// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4752// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4753// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4754// CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4755// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4756// CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4757// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4758// CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4759// CHECK1-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8760// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4761// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8762// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8763// CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8764// CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8765// CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8766// CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8767// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]768// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]769// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]770// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8771// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4772// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4773// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4774// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4775// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false)776// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0777// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2778// CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]779// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]780// CHECK1: omp.arraycpy.body:781// CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]782// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]783// CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])784// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])785// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]786// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1787// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1788// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]789// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]790// CHECK1: omp.arraycpy.done4:791// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]792// CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])793// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]])794// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]795// CHECK1-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 8796// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8797// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4798// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)799// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4800// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1801// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]802// CHECK1: cond.true:803// CHECK1-NEXT: br label [[COND_END:%.*]]804// CHECK1: cond.false:805// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4806// CHECK1-NEXT: br label [[COND_END]]807// CHECK1: cond.end:808// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]809// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4810// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4811// CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4812// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]813// CHECK1: omp.inner.for.cond:814// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]]815// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP15]]816// CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]817// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]818// CHECK1: omp.inner.for.cond.cleanup:819// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]820// CHECK1: omp.inner.for.body:821// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]822// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1823// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]824// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]]825// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP15]]826// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]]827// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64828// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]]829// CHECK1-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]]830// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP15]]831// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]]832// CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP16]] to i64833// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM9]]834// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group [[ACC_GRP15]]835// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]836// CHECK1: omp.body.continue:837// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]838// CHECK1: omp.inner.for.inc:839// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]840// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1841// CHECK1-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]842// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]843// CHECK1: omp.inner.for.end:844// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]845// CHECK1: omp.loop.exit:846// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8847// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4848// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]])849// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4850// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0851// CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]852// CHECK1: .omp.final.then:853// CHECK1-NEXT: store i32 2, ptr [[I]], align 4854// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]855// CHECK1: .omp.final.done:856// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]857// CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0858// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2859// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]860// CHECK1: arraydestroy.body:861// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]862// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1863// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]864// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]865// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]866// CHECK1: arraydestroy.done13:867// CHECK1-NEXT: ret void868//869//870// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St871// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {872// CHECK1-NEXT: entry:873// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8874// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8875// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8876// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8877// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8878// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8879// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8880// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8881// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])882// CHECK1-NEXT: ret void883//884//885// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev886// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {887// CHECK1-NEXT: entry:888// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8889// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8890// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8891// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]892// CHECK1-NEXT: ret void893//894//895// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev896// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {897// CHECK1-NEXT: entry:898// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8899// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8900// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8901// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0902// CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4903// CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4904// CHECK1-NEXT: ret void905//906//907// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei908// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {909// CHECK1-NEXT: entry:910// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8911// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4912// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8913// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4914// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8915// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0916// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4917// CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4918// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]919// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4920// CHECK1-NEXT: ret void921//922//923// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St924// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {925// CHECK1-NEXT: entry:926// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8927// CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8928// CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8929// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8930// CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8931// CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8932// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8933// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0934// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]935// CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0936// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4937// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0938// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4939// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]940// CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4941// CHECK1-NEXT: ret void942//943//944// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev945// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {946// CHECK1-NEXT: entry:947// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8948// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8949// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8950// CHECK1-NEXT: ret void951//952//953// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp954// CHECK1-SAME: () #[[ATTR0]] {955// CHECK1-NEXT: entry:956// CHECK1-NEXT: call void @__cxx_global_var_init()957// CHECK1-NEXT: call void @__cxx_global_var_init.1()958// CHECK1-NEXT: call void @__cxx_global_var_init.2()959// CHECK1-NEXT: ret void960//961//962// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init963// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {964// CHECK3-NEXT: entry:965// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)966// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]967// CHECK3-NEXT: ret void968//969//970// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev971// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {972// CHECK3-NEXT: entry:973// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4974// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4975// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4976// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])977// CHECK3-NEXT: ret void978//979//980// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev981// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {982// CHECK3-NEXT: entry:983// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4984// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4985// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4986// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]987// CHECK3-NEXT: ret void988//989//990// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev991// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {992// CHECK3-NEXT: entry:993// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4994// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4995// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4996// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0997// CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4998// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float999// CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 41000// CHECK3-NEXT: ret void1001//1002//1003// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev1004// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1005// CHECK3-NEXT: entry:1006// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41007// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41008// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41009// CHECK3-NEXT: ret void1010//1011//1012// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.11013// CHECK3-SAME: () #[[ATTR0]] {1014// CHECK3-NEXT: entry:1015// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)1016// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00)1017// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]1018// CHECK3-NEXT: ret void1019//1020//1021// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef1022// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1023// CHECK3-NEXT: entry:1024// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41025// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 41026// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41027// CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 41028// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41029// CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41030// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])1031// CHECK3-NEXT: ret void1032//1033//1034// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor1035// CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {1036// CHECK3-NEXT: entry:1037// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 41038// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 41039// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1040// CHECK3: arraydestroy.body:1041// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1042// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11043// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1044// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr1045// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]1046// CHECK3: arraydestroy.done1:1047// CHECK3-NEXT: ret void1048//1049//1050// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef1051// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1052// CHECK3-NEXT: entry:1053// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41054// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 41055// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41056// CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 41057// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41058// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01059// CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41060// CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 41061// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float1062// CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]1063// CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 41064// CHECK3-NEXT: ret void1065//1066//1067// CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.21068// CHECK3-SAME: () #[[ATTR0]] {1069// CHECK3-NEXT: entry:1070// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)1071// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]1072// CHECK3-NEXT: ret void1073//1074//1075// CHECK3-LABEL: define {{[^@]+}}@main1076// CHECK3-SAME: () #[[ATTR3:[0-9]+]] {1077// CHECK3-NEXT: entry:1078// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 41079// CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 41080// CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 41081// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 41082// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 41083// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 41084// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 41085// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81086// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 41087// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr @t_var, align 41088// CHECK3-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 41089// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41090// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 41091// CHECK3-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 41092// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 41093// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01094// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP4]], align 41095// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01096// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 41097// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 01098// CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 41099// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11100// CHECK3-NEXT: store ptr @vec, ptr [[TMP7]], align 41101// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11102// CHECK3-NEXT: store ptr @vec, ptr [[TMP8]], align 41103// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 11104// CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 41105// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21106// CHECK3-NEXT: store ptr @s_arr, ptr [[TMP10]], align 41107// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21108// CHECK3-NEXT: store ptr @s_arr, ptr [[TMP11]], align 41109// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 21110// CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 41111// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31112// CHECK3-NEXT: store ptr @var, ptr [[TMP13]], align 41113// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31114// CHECK3-NEXT: store ptr @var, ptr [[TMP14]], align 41115// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 31116// CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 41117// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 41118// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP16]], align 41119// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 41120// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP17]], align 41121// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 41122// CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 41123// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01124// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01125// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01126// CHECK3-NEXT: store i32 3, ptr [[TMP21]], align 41127// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11128// CHECK3-NEXT: store i32 5, ptr [[TMP22]], align 41129// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21130// CHECK3-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 41131// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31132// CHECK3-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 41133// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41134// CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP25]], align 41135// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51136// CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 41137// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61138// CHECK3-NEXT: store ptr null, ptr [[TMP27]], align 41139// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71140// CHECK3-NEXT: store ptr null, ptr [[TMP28]], align 41141// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81142// CHECK3-NEXT: store i64 2, ptr [[TMP29]], align 81143// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91144// CHECK3-NEXT: store i64 0, ptr [[TMP30]], align 81145// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101146// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 41147// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111148// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP32]], align 41149// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121150// CHECK3-NEXT: store i32 0, ptr [[TMP33]], align 41151// CHECK3-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, ptr [[KERNEL_ARGS]])1152// CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 01153// CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1154// CHECK3: omp_offload.failed:1155// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i32 [[TMP1]], ptr @vec, ptr @s_arr, ptr @var, i32 [[TMP3]]) #[[ATTR2]]1156// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]1157// CHECK3: omp_offload.cont:1158// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()1159// CHECK3-NEXT: ret i32 [[CALL]]1160//1161//1162// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l941163// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {1164// CHECK3-NEXT: entry:1165// CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 41166// CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 41167// CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 41168// CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 41169// CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 41170// CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 41171// CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 41172// CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41173// CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 41174// CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41175// CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 41176// CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 41177// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]]1178// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1179// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1180// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 41181// CHECK3-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 41182// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41183// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 41184// CHECK3-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 41185// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 41186// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i32 [[TMP6]])1187// CHECK3-NEXT: ret void1188//1189//1190// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined1191// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] {1192// CHECK3-NEXT: entry:1193// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41194// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41195// CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 41196// CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 41197// CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 41198// CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 41199// CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 41200// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41201// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 41202// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41203// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41204// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41205// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41206// CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 41207// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 41208// CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 41209// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 41210// CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 41211// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 41212// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41213// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41214// CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 41215// CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41216// CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41217// CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 41218// CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 41219// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1220// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1221// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1222// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41223// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 41224// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41225// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41226// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false)1227// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 01228// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 21229// CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]1230// CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1231// CHECK3: omp.arraycpy.body:1232// CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1233// CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1234// CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])1235// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])1236// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]1237// CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11238// CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11239// CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]1240// CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]1241// CHECK3: omp.arraycpy.done3:1242// CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]])1243// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]])1244// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]1245// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41246// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 41247// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1248// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41249// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 11250// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1251// CHECK3: cond.true:1252// CHECK3-NEXT: br label [[COND_END:%.*]]1253// CHECK3: cond.false:1254// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41255// CHECK3-NEXT: br label [[COND_END]]1256// CHECK3: cond.end:1257// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]1258// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41259// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41260// CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 41261// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1262// CHECK3: omp.inner.for.cond:1263// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]]1264// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]]1265// CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]1266// CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1267// CHECK3: omp.inner.for.cond.cleanup:1268// CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]1269// CHECK3: omp.inner.for.body:1270// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]1271// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 11272// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1273// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]1274// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]]1275// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]1276// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP13]]1277// CHECK3-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]]1278// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]1279// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP14]]1280// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]]1281// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]1282// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]]1283// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]1284// CHECK3-NEXT: store i32 [[ADD8]], ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]]1285// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1286// CHECK3: omp.body.continue:1287// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1288// CHECK3: omp.inner.for.inc:1289// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]1290// CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP17]], 11291// CHECK3-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]1292// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]1293// CHECK3: omp.inner.for.end:1294// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1295// CHECK3: omp.loop.exit:1296// CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41297// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 41298// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]])1299// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41300// CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 01301// CHECK3-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1302// CHECK3: .omp.final.then:1303// CHECK3-NEXT: store i32 2, ptr [[I]], align 41304// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]1305// CHECK3: .omp.final.done:1306// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]1307// CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 01308// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 21309// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1310// CHECK3: arraydestroy.body:1311// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1312// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11313// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1314// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]1315// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]1316// CHECK3: arraydestroy.done11:1317// CHECK3-NEXT: ret void1318//1319//1320// CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev1321// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1322// CHECK3-NEXT: entry:1323// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41324// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41325// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41326// CHECK3-NEXT: call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])1327// CHECK3-NEXT: ret void1328//1329//1330// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St1331// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1332// CHECK3-NEXT: entry:1333// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41334// CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 41335// CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 41336// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41337// CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 41338// CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 41339// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41340// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 41341// CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])1342// CHECK3-NEXT: ret void1343//1344//1345// CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev1346// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1347// CHECK3-NEXT: entry:1348// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41349// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41350// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41351// CHECK3-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]1352// CHECK3-NEXT: ret void1353//1354//1355// CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v1356// CHECK3-SAME: () #[[ATTR1]] comdat {1357// CHECK3-NEXT: entry:1358// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 41359// CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41360// CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 41361// CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 41362// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 41363// CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 41364// CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 41365// CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 41366// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 41367// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 41368// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 41369// CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 41370// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 81371// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])1372// CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 41373// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)1374// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)1375// CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 11376// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)1377// CHECK3-NEXT: store ptr [[TEST]], ptr [[VAR]], align 41378// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META8]], !align [[META9]]1379// CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 41380// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 41381// CHECK3-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 41382// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41383// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1384// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1385// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1386// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01387// CHECK3-NEXT: store i32 [[TMP2]], ptr [[TMP6]], align 41388// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01389// CHECK3-NEXT: store i32 [[TMP2]], ptr [[TMP7]], align 41390// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 01391// CHECK3-NEXT: store ptr null, ptr [[TMP8]], align 41392// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 11393// CHECK3-NEXT: store ptr [[VEC]], ptr [[TMP9]], align 41394// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 11395// CHECK3-NEXT: store ptr [[VEC]], ptr [[TMP10]], align 41396// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 11397// CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 41398// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 21399// CHECK3-NEXT: store ptr [[S_ARR]], ptr [[TMP12]], align 41400// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 21401// CHECK3-NEXT: store ptr [[S_ARR]], ptr [[TMP13]], align 41402// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 21403// CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 41404// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 31405// CHECK3-NEXT: store ptr [[TMP4]], ptr [[TMP15]], align 41406// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 31407// CHECK3-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 41408// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 31409// CHECK3-NEXT: store ptr null, ptr [[TMP17]], align 41410// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 01411// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 01412// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 01413// CHECK3-NEXT: store i32 3, ptr [[TMP20]], align 41414// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11415// CHECK3-NEXT: store i32 4, ptr [[TMP21]], align 41416// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 21417// CHECK3-NEXT: store ptr [[TMP18]], ptr [[TMP22]], align 41418// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 31419// CHECK3-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 41420// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 41421// CHECK3-NEXT: store ptr @.offload_sizes.3, ptr [[TMP24]], align 41422// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 51423// CHECK3-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP25]], align 41424// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 61425// CHECK3-NEXT: store ptr null, ptr [[TMP26]], align 41426// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 71427// CHECK3-NEXT: store ptr null, ptr [[TMP27]], align 41428// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 81429// CHECK3-NEXT: store i64 2, ptr [[TMP28]], align 81430// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 91431// CHECK3-NEXT: store i64 0, ptr [[TMP29]], align 81432// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 101433// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP30]], align 41434// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 111435// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 41436// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 121437// CHECK3-NEXT: store i32 0, ptr [[TMP32]], align 41438// CHECK3-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])1439// CHECK3-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 01440// CHECK3-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]1441// CHECK3: omp_offload.failed:1442// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i32 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]]1443// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]1444// CHECK3: omp_offload.cont:1445// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 41446// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01447// CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 21448// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1449// CHECK3: arraydestroy.body:1450// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1451// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11452// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1453// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]1454// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]1455// CHECK3: arraydestroy.done2:1456// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]1457// CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 41458// CHECK3-NEXT: ret i32 [[TMP36]]1459//1460//1461// CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev1462// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1463// CHECK3-NEXT: entry:1464// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41465// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41466// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41467// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 01468// CHECK3-NEXT: store i32 0, ptr [[A]], align 41469// CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 11470// CHECK3-NEXT: store i32 0, ptr [[B]], align 41471// CHECK3-NEXT: ret void1472//1473//1474// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St1475// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1476// CHECK3-NEXT: entry:1477// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41478// CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 41479// CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 41480// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41481// CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 41482// CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 41483// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41484// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01485// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1486// CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 01487// CHECK3-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 41488// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 01489// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 41490// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float1491// CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]1492// CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 41493// CHECK3-NEXT: ret void1494//1495//1496// CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev1497// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1498// CHECK3-NEXT: entry:1499// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41500// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41501// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41502// CHECK3-NEXT: ret void1503//1504//1505// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev1506// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1507// CHECK3-NEXT: entry:1508// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41509// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41510// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41511// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1512// CHECK3-NEXT: ret void1513//1514//1515// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei1516// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1517// CHECK3-NEXT: entry:1518// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41519// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 41520// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41521// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 41522// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41523// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41524// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])1525// CHECK3-NEXT: ret void1526//1527//1528// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l561529// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {1530// CHECK3-NEXT: entry:1531// CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 41532// CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 41533// CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 41534// CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 41535// CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 41536// CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 41537// CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41538// CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 41539// CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41540// CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 41541// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1542// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1543// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1544// CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 41545// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 41546// CHECK3-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 41547// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 41548// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1549// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]])1550// CHECK3-NEXT: ret void1551//1552//1553// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined1554// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {1555// CHECK3-NEXT: entry:1556// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 41557// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 41558// CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 41559// CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 41560// CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 41561// CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 41562// CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 41563// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41564// CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 41565// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41566// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41567// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 41568// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 41569// CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 41570// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 41571// CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 41572// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41573// CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 41574// CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 41575// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 41576// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 41577// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 41578// CHECK3-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 41579// CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 41580// CHECK3-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 41581// CHECK3-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 41582// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1583// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1584// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1585// CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 41586// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41587// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 41588// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 41589// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 41590// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false)1591// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 01592// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 21593// CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]1594// CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]1595// CHECK3: omp.arraycpy.body:1596// CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1597// CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]1598// CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])1599// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])1600// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]1601// CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 11602// CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 11603// CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]1604// CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]1605// CHECK3: omp.arraycpy.done4:1606// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]1607// CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])1608// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]])1609// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]1610// CHECK3-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 41611// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41612// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 41613// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)1614// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41615// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 11616// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]1617// CHECK3: cond.true:1618// CHECK3-NEXT: br label [[COND_END:%.*]]1619// CHECK3: cond.false:1620// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 41621// CHECK3-NEXT: br label [[COND_END]]1622// CHECK3: cond.end:1623// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]1624// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 41625// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41626// CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 41627// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1628// CHECK3: omp.inner.for.cond:1629// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]]1630// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP16]]1631// CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]1632// CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]1633// CHECK3: omp.inner.for.cond.cleanup:1634// CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]1635// CHECK3: omp.inner.for.body:1636// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]]1637// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 11638// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1639// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]]1640// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP16]]1641// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]]1642// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP14]]1643// CHECK3-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]]1644// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP16]]1645// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]]1646// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP16]]1647// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group [[ACC_GRP16]]1648// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1649// CHECK3: omp.body.continue:1650// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1651// CHECK3: omp.inner.for.inc:1652// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]]1653// CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP17]], 11654// CHECK3-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP16]]1655// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]1656// CHECK3: omp.inner.for.end:1657// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]1658// CHECK3: omp.loop.exit:1659// CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 41660// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 41661// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]])1662// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 41663// CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 01664// CHECK3-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]1665// CHECK3: .omp.final.then:1666// CHECK3-NEXT: store i32 2, ptr [[I]], align 41667// CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]1668// CHECK3: .omp.final.done:1669// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]1670// CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 01671// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 21672// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1673// CHECK3: arraydestroy.body:1674// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1675// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -11676// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1677// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]1678// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]1679// CHECK3: arraydestroy.done12:1680// CHECK3-NEXT: ret void1681//1682//1683// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St1684// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1685// CHECK3-NEXT: entry:1686// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41687// CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 41688// CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 41689// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41690// CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 41691// CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 41692// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41693// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 41694// CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])1695// CHECK3-NEXT: ret void1696//1697//1698// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev1699// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1700// CHECK3-NEXT: entry:1701// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41702// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41703// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41704// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]1705// CHECK3-NEXT: ret void1706//1707//1708// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev1709// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1710// CHECK3-NEXT: entry:1711// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41712// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41713// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41714// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01715// CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 41716// CHECK3-NEXT: store i32 [[TMP0]], ptr [[F]], align 41717// CHECK3-NEXT: ret void1718//1719//1720// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei1721// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1722// CHECK3-NEXT: entry:1723// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41724// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 41725// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41726// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 41727// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41728// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01729// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 41730// CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 41731// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]1732// CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 41733// CHECK3-NEXT: ret void1734//1735//1736// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St1737// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1738// CHECK3-NEXT: entry:1739// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41740// CHECK3-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 41741// CHECK3-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 41742// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41743// CHECK3-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 41744// CHECK3-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 41745// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41746// CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 01747// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4, !nonnull [[META8]], !align [[META9]]1748// CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 01749// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 41750// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 01751// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 41752// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]1753// CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 41754// CHECK3-NEXT: ret void1755//1756//1757// CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev1758// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {1759// CHECK3-NEXT: entry:1760// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 41761// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 41762// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 41763// CHECK3-NEXT: ret void1764//1765//1766// CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp1767// CHECK3-SAME: () #[[ATTR0]] {1768// CHECK3-NEXT: entry:1769// CHECK3-NEXT: call void @__cxx_global_var_init()1770// CHECK3-NEXT: call void @__cxx_global_var_init.1()1771// CHECK3-NEXT: call void @__cxx_global_var_init.2()1772// CHECK3-NEXT: ret void1773//1774//1775// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init1776// CHECK5-SAME: () #[[ATTR0:[0-9]+]] {1777// CHECK5-NEXT: entry:1778// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)1779// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]1780// CHECK5-NEXT: ret void1781//1782//1783// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev1784// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {1785// CHECK5-NEXT: entry:1786// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81787// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81788// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81789// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])1790// CHECK5-NEXT: ret void1791//1792//1793// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev1794// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1795// CHECK5-NEXT: entry:1796// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81797// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81798// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81799// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]1800// CHECK5-NEXT: ret void1801//1802//1803// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.11804// CHECK5-SAME: () #[[ATTR0]] {1805// CHECK5-NEXT: entry:1806// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)1807// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)1808// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]1809// CHECK5-NEXT: ret void1810//1811//1812// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef1813// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {1814// CHECK5-NEXT: entry:1815// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81816// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 41817// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81818// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 41819// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81820// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 41821// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])1822// CHECK5-NEXT: ret void1823//1824//1825// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor1826// CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {1827// CHECK5-NEXT: entry:1828// CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 81829// CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 81830// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1831// CHECK5: arraydestroy.body:1832// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1833// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11834// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1835// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr1836// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]1837// CHECK5: arraydestroy.done1:1838// CHECK5-NEXT: ret void1839//1840//1841// CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.21842// CHECK5-SAME: () #[[ATTR0]] {1843// CHECK5-NEXT: entry:1844// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)1845// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]1846// CHECK5-NEXT: ret void1847//1848//1849// CHECK5-LABEL: define {{[^@]+}}@main1850// CHECK5-SAME: () #[[ATTR3:[0-9]+]] {1851// CHECK5-NEXT: entry:1852// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 41853// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 41854// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41855// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41856// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41857// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 41858// CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 41859// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41860// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 41861// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41862// CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 41863// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1864// CHECK5: omp.inner.for.cond:1865// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]1866// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]1867// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]1868// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1869// CHECK5: omp.inner.for.body:1870// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]1871// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 11872// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1873// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]1874// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr @t_var, align 4, !llvm.access.group [[ACC_GRP2]]1875// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]1876// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i641877// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, i64 0, i64 [[IDXPROM]]1878// CHECK5-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]]1879// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]1880// CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i641881// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i64 0, i64 [[IDXPROM1]]1882// CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 @var, i64 4, i1 false), !llvm.access.group [[ACC_GRP2]]1883// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]1884// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]]1885// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]]1886// CHECK5-NEXT: store i32 [[ADD3]], ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]]1887// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1888// CHECK5: omp.body.continue:1889// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1890// CHECK5: omp.inner.for.inc:1891// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]1892// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 11893// CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]1894// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]1895// CHECK5: omp.inner.for.end:1896// CHECK5-NEXT: store i32 2, ptr [[I]], align 41897// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()1898// CHECK5-NEXT: ret i32 [[CALL]]1899//1900//1901// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v1902// CHECK5-SAME: () #[[ATTR1]] comdat {1903// CHECK5-NEXT: entry:1904// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 41905// CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 41906// CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 41907// CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 41908// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 41909// CHECK5-NEXT: [[VAR:%.*]] = alloca ptr, align 81910// CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 81911// CHECK5-NEXT: [[_TMP1:%.*]] = alloca ptr, align 81912// CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 41913// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 41914// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 41915// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 41916// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 41917// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])1918// CHECK5-NEXT: store i32 0, ptr [[T_VAR]], align 41919// CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)1920// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1)1921// CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 11922// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)1923// CHECK5-NEXT: store ptr [[TEST]], ptr [[VAR]], align 81924// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]]1925// CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 81926// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META6]], !align [[META7]]1927// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META6]], !align [[META7]]1928// CHECK5-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 81929// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 41930// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 41931// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 41932// CHECK5-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 41933// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]1934// CHECK5: omp.inner.for.cond:1935// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]]1936// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]]1937// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]1938// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]1939// CHECK5: omp.inner.for.body:1940// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]1941// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 11942// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]1943// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]1944// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP8]]1945// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]1946// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP8]] to i641947// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]1948// CHECK5-NEXT: store i32 [[TMP7]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]]1949// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META6]], !align [[META7]], !llvm.access.group [[ACC_GRP8]]1950// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]1951// CHECK5-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP10]] to i641952// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]]1953// CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP9]], i64 4, i1 false), !llvm.access.group [[ACC_GRP8]]1954// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]1955// CHECK5: omp.body.continue:1956// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]1957// CHECK5: omp.inner.for.inc:1958// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]1959// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 11960// CHECK5-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]1961// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]1962// CHECK5: omp.inner.for.end:1963// CHECK5-NEXT: store i32 2, ptr [[I]], align 41964// CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 41965// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 01966// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 21967// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]1968// CHECK5: arraydestroy.body:1969// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]1970// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -11971// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]1972// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]1973// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]1974// CHECK5: arraydestroy.done6:1975// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]1976// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[RETVAL]], align 41977// CHECK5-NEXT: ret i32 [[TMP13]]1978//1979//1980// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev1981// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1982// CHECK5-NEXT: entry:1983// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81984// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81985// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81986// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 01987// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 41988// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float1989// CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 41990// CHECK5-NEXT: ret void1991//1992//1993// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev1994// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {1995// CHECK5-NEXT: entry:1996// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 81997// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 81998// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 81999// CHECK5-NEXT: ret void2000//2001//2002// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef2003// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2004// CHECK5-NEXT: entry:2005// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82006// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 42007// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82008// CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 42009// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82010// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02011// CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42012// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 42013// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float2014// CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]2015// CHECK5-NEXT: store float [[ADD]], ptr [[F]], align 42016// CHECK5-NEXT: ret void2017//2018//2019// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev2020// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2021// CHECK5-NEXT: entry:2022// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82023// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82024// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82025// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])2026// CHECK5-NEXT: ret void2027//2028//2029// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei2030// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2031// CHECK5-NEXT: entry:2032// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82033// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42034// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82035// CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42036// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82037// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42038// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])2039// CHECK5-NEXT: ret void2040//2041//2042// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev2043// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2044// CHECK5-NEXT: entry:2045// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82046// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82047// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82048// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]2049// CHECK5-NEXT: ret void2050//2051//2052// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev2053// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2054// CHECK5-NEXT: entry:2055// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82056// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82057// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82058// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 02059// CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 42060// CHECK5-NEXT: store i32 [[TMP0]], ptr [[F]], align 42061// CHECK5-NEXT: ret void2062//2063//2064// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei2065// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2066// CHECK5-NEXT: entry:2067// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82068// CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42069// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82070// CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42071// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82072// CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 02073// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42074// CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 42075// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]2076// CHECK5-NEXT: store i32 [[ADD]], ptr [[F]], align 42077// CHECK5-NEXT: ret void2078//2079//2080// CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev2081// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2082// CHECK5-NEXT: entry:2083// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82084// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82085// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82086// CHECK5-NEXT: ret void2087//2088//2089// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp2090// CHECK5-SAME: () #[[ATTR0]] {2091// CHECK5-NEXT: entry:2092// CHECK5-NEXT: call void @__cxx_global_var_init()2093// CHECK5-NEXT: call void @__cxx_global_var_init.1()2094// CHECK5-NEXT: call void @__cxx_global_var_init.2()2095// CHECK5-NEXT: ret void2096//2097//2098// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init2099// CHECK7-SAME: () #[[ATTR0:[0-9]+]] {2100// CHECK7-NEXT: entry:2101// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)2102// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]2103// CHECK7-NEXT: ret void2104//2105//2106// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev2107// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {2108// CHECK7-NEXT: entry:2109// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42110// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42111// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42112// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])2113// CHECK7-NEXT: ret void2114//2115//2116// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev2117// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2118// CHECK7-NEXT: entry:2119// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42120// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42121// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42122// CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]2123// CHECK7-NEXT: ret void2124//2125//2126// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.12127// CHECK7-SAME: () #[[ATTR0]] {2128// CHECK7-NEXT: entry:2129// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)2130// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00)2131// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]2132// CHECK7-NEXT: ret void2133//2134//2135// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef2136// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2137// CHECK7-NEXT: entry:2138// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42139// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 42140// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42141// CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 42142// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42143// CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42144// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])2145// CHECK7-NEXT: ret void2146//2147//2148// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor2149// CHECK7-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {2150// CHECK7-NEXT: entry:2151// CHECK7-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 42152// CHECK7-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 42153// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]2154// CHECK7: arraydestroy.body:2155// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2156// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -12157// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]2158// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr2159// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]2160// CHECK7: arraydestroy.done1:2161// CHECK7-NEXT: ret void2162//2163//2164// CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.22165// CHECK7-SAME: () #[[ATTR0]] {2166// CHECK7-NEXT: entry:2167// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)2168// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]2169// CHECK7-NEXT: ret void2170//2171//2172// CHECK7-LABEL: define {{[^@]+}}@main2173// CHECK7-SAME: () #[[ATTR3:[0-9]+]] {2174// CHECK7-NEXT: entry:2175// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 42176// CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 42177// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42178// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42179// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42180// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 42181// CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 42182// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42183// CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 42184// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42185// CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 42186// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2187// CHECK7: omp.inner.for.cond:2188// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]2189// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]]2190// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]2191// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2192// CHECK7: omp.inner.for.body:2193// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]2194// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 12195// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2196// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]2197// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr @t_var, align 4, !llvm.access.group [[ACC_GRP3]]2198// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]2199// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, i32 0, i32 [[TMP5]]2200// CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]]2201// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]2202// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i32 0, i32 [[TMP6]]2203// CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 @var, i32 4, i1 false), !llvm.access.group [[ACC_GRP3]]2204// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]2205// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP3]]2206// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], [[TMP7]]2207// CHECK7-NEXT: store i32 [[ADD2]], ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP3]]2208// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2209// CHECK7: omp.body.continue:2210// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2211// CHECK7: omp.inner.for.inc:2212// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]2213// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 12214// CHECK7-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]2215// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]2216// CHECK7: omp.inner.for.end:2217// CHECK7-NEXT: store i32 2, ptr [[I]], align 42218// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()2219// CHECK7-NEXT: ret i32 [[CALL]]2220//2221//2222// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v2223// CHECK7-SAME: () #[[ATTR1]] comdat {2224// CHECK7-NEXT: entry:2225// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 42226// CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 42227// CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 42228// CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 42229// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 42230// CHECK7-NEXT: [[VAR:%.*]] = alloca ptr, align 42231// CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 42232// CHECK7-NEXT: [[_TMP1:%.*]] = alloca ptr, align 42233// CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32, align 42234// CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42235// CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42236// CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42237// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 42238// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])2239// CHECK7-NEXT: store i32 0, ptr [[T_VAR]], align 42240// CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)2241// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)2242// CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 12243// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)2244// CHECK7-NEXT: store ptr [[TEST]], ptr [[VAR]], align 42245// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]]2246// CHECK7-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 42247// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META7]], !align [[META8]]2248// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META7]], !align [[META8]]2249// CHECK7-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 42250// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42251// CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 42252// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42253// CHECK7-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 42254// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2255// CHECK7: omp.inner.for.cond:2256// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]]2257// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]]2258// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]2259// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2260// CHECK7: omp.inner.for.body:2261// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]2262// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 12263// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2264// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]2265// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP9]]2266// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]2267// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP8]]2268// CHECK7-NEXT: store i32 [[TMP7]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]]2269// CHECK7-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP9]]2270// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]2271// CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP10]]2272// CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[TMP9]], i32 4, i1 false), !llvm.access.group [[ACC_GRP9]]2273// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2274// CHECK7: omp.body.continue:2275// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2276// CHECK7: omp.inner.for.inc:2277// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]2278// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 12279// CHECK7-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]2280// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]2281// CHECK7: omp.inner.for.end:2282// CHECK7-NEXT: store i32 2, ptr [[I]], align 42283// CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 42284// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 02285// CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 22286// CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]2287// CHECK7: arraydestroy.body:2288// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2289// CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -12290// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]2291// CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]2292// CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]2293// CHECK7: arraydestroy.done5:2294// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]2295// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[RETVAL]], align 42296// CHECK7-NEXT: ret i32 [[TMP13]]2297//2298//2299// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev2300// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2301// CHECK7-NEXT: entry:2302// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42303// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42304// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42305// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02306// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 42307// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float2308// CHECK7-NEXT: store float [[CONV]], ptr [[F]], align 42309// CHECK7-NEXT: ret void2310//2311//2312// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev2313// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2314// CHECK7-NEXT: entry:2315// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42316// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42317// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42318// CHECK7-NEXT: ret void2319//2320//2321// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef2322// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2323// CHECK7-NEXT: entry:2324// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42325// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 42326// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42327// CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 42328// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42329// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02330// CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42331// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 42332// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float2333// CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]2334// CHECK7-NEXT: store float [[ADD]], ptr [[F]], align 42335// CHECK7-NEXT: ret void2336//2337//2338// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev2339// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2340// CHECK7-NEXT: entry:2341// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42342// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42343// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42344// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])2345// CHECK7-NEXT: ret void2346//2347//2348// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei2349// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2350// CHECK7-NEXT: entry:2351// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42352// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42353// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42354// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42355// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42356// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42357// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])2358// CHECK7-NEXT: ret void2359//2360//2361// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev2362// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2363// CHECK7-NEXT: entry:2364// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42365// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42366// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42367// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]2368// CHECK7-NEXT: ret void2369//2370//2371// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev2372// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2373// CHECK7-NEXT: entry:2374// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42375// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42376// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42377// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 02378// CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 42379// CHECK7-NEXT: store i32 [[TMP0]], ptr [[F]], align 42380// CHECK7-NEXT: ret void2381//2382//2383// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei2384// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2385// CHECK7-NEXT: entry:2386// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42387// CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 42388// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42389// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 42390// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42391// CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 02392// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 42393// CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 42394// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]2395// CHECK7-NEXT: store i32 [[ADD]], ptr [[F]], align 42396// CHECK7-NEXT: ret void2397//2398//2399// CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev2400// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {2401// CHECK7-NEXT: entry:2402// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 42403// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 42404// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 42405// CHECK7-NEXT: ret void2406//2407//2408// CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp2409// CHECK7-SAME: () #[[ATTR0]] {2410// CHECK7-NEXT: entry:2411// CHECK7-NEXT: call void @__cxx_global_var_init()2412// CHECK7-NEXT: call void @__cxx_global_var_init.1()2413// CHECK7-NEXT: call void @__cxx_global_var_init.2()2414// CHECK7-NEXT: ret void2415//2416//2417// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init2418// CHECK9-SAME: () #[[ATTR0:[0-9]+]] {2419// CHECK9-NEXT: entry:2420// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)2421// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]2422// CHECK9-NEXT: ret void2423//2424//2425// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev2426// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {2427// CHECK9-NEXT: entry:2428// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82429// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82430// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82431// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])2432// CHECK9-NEXT: ret void2433//2434//2435// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev2436// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2437// CHECK9-NEXT: entry:2438// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82439// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82440// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82441// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]2442// CHECK9-NEXT: ret void2443//2444//2445// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev2446// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2447// CHECK9-NEXT: entry:2448// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82449// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82450// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82451// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02452// CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 42453// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float2454// CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 42455// CHECK9-NEXT: ret void2456//2457//2458// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev2459// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2460// CHECK9-NEXT: entry:2461// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82462// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82463// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82464// CHECK9-NEXT: ret void2465//2466//2467// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.12468// CHECK9-SAME: () #[[ATTR0]] {2469// CHECK9-NEXT: entry:2470// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)2471// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)2472// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]2473// CHECK9-NEXT: ret void2474//2475//2476// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef2477// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2478// CHECK9-NEXT: entry:2479// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82480// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 42481// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82482// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 42483// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82484// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42485// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])2486// CHECK9-NEXT: ret void2487//2488//2489// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor2490// CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {2491// CHECK9-NEXT: entry:2492// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 82493// CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 82494// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]2495// CHECK9: arraydestroy.body:2496// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2497// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -12498// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]2499// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr2500// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]2501// CHECK9: arraydestroy.done1:2502// CHECK9-NEXT: ret void2503//2504//2505// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef2506// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2507// CHECK9-NEXT: entry:2508// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82509// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 42510// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82511// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 42512// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82513// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02514// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42515// CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 42516// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float2517// CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]2518// CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 42519// CHECK9-NEXT: ret void2520//2521//2522// CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.22523// CHECK9-SAME: () #[[ATTR0]] {2524// CHECK9-NEXT: entry:2525// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)2526// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]2527// CHECK9-NEXT: ret void2528//2529//2530// CHECK9-LABEL: define {{[^@]+}}@main2531// CHECK9-SAME: () #[[ATTR3:[0-9]+]] {2532// CHECK9-NEXT: entry:2533// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 42534// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 12535// CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 42536// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])2537// CHECK9-NEXT: ret i32 02538//2539//2540// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l752541// CHECK9-SAME: (i64 noundef [[G:%.*]], i64 noundef [[SIVAR:%.*]], i64 noundef [[G1:%.*]]) #[[ATTR4:[0-9]+]] {2542// CHECK9-NEXT: entry:2543// CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 82544// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 82545// CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 82546// CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 82547// CHECK9-NEXT: [[G_CASTED:%.*]] = alloca i64, align 82548// CHECK9-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 82549// CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 82550// CHECK9-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 82551// CHECK9-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 82552// CHECK9-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 82553// CHECK9-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 82554// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[G_ADDR]], align 42555// CHECK9-NEXT: store i32 [[TMP0]], ptr [[G_CASTED]], align 42556// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 82557// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]2558// CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, ptr [[TMP2]], align 42559// CHECK9-NEXT: store i32 [[TMP3]], ptr [[G1_CASTED]], align 42560// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[G1_CASTED]], align 82561// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 42562// CHECK9-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 42563// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 82564// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined, i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])2565// CHECK9-NEXT: ret void2566//2567//2568// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined2569// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] {2570// CHECK9-NEXT: entry:2571// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 82572// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 82573// CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 82574// CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 82575// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 82576// CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 82577// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 42578// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 42579// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 42580// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 42581// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 42582// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 42583// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 42584// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 82585// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 82586// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 82587// CHECK9-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 82588// CHECK9-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 82589// CHECK9-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 82590// CHECK9-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 82591// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 42592// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 42593// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 42594// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 42595// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 82596// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 42597// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)2598// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42599// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 12600// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]2601// CHECK9: cond.true:2602// CHECK9-NEXT: br label [[COND_END:%.*]]2603// CHECK9: cond.false:2604// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 42605// CHECK9-NEXT: br label [[COND_END]]2606// CHECK9: cond.end:2607// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]2608// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 42609// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 42610// CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 42611// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]2612// CHECK9: omp.inner.for.cond:2613// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]2614// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]]2615// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]2616// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]2617// CHECK9: omp.inner.for.body:2618// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]2619// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 12620// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]2621// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]2622// CHECK9-NEXT: store i32 1, ptr [[G_ADDR]], align 4, !llvm.access.group [[ACC_GRP7]]2623// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]], !llvm.access.group [[ACC_GRP7]]2624// CHECK9-NEXT: store volatile i32 1, ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP7]]2625// CHECK9-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP7]]2626// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 02627// CHECK9-NEXT: store ptr [[G_ADDR]], ptr [[TMP9]], align 8, !llvm.access.group [[ACC_GRP7]]2628// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 12629// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]], !llvm.access.group [[ACC_GRP7]]2630// CHECK9-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP7]]2631// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 22632// CHECK9-NEXT: store ptr [[SIVAR_ADDR]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP7]]2633// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group [[ACC_GRP7]]2634// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]2635// CHECK9: omp.body.continue:2636// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]2637// CHECK9: omp.inner.for.inc:2638// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]2639// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP13]], 12640// CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]2641// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]2642// CHECK9: omp.inner.for.end:2643// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]2644// CHECK9: omp.loop.exit:2645// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])2646// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 42647// CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 02648// CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]2649// CHECK9: .omp.final.then:2650// CHECK9-NEXT: store i32 2, ptr [[I]], align 42651// CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]2652// CHECK9: .omp.final.done:2653// CHECK9-NEXT: ret void2654//2655//2656// CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp2657// CHECK9-SAME: () #[[ATTR0]] {2658// CHECK9-NEXT: entry:2659// CHECK9-NEXT: call void @__cxx_global_var_init()2660// CHECK9-NEXT: call void @__cxx_global_var_init.1()2661// CHECK9-NEXT: call void @__cxx_global_var_init.2()2662// CHECK9-NEXT: ret void2663//2664//2665// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init2666// CHECK11-SAME: () #[[ATTR0:[0-9]+]] {2667// CHECK11-NEXT: entry:2668// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)2669// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]2670// CHECK11-NEXT: ret void2671//2672//2673// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev2674// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {2675// CHECK11-NEXT: entry:2676// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82677// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82678// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82679// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])2680// CHECK11-NEXT: ret void2681//2682//2683// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev2684// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2685// CHECK11-NEXT: entry:2686// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82687// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82688// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82689// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]2690// CHECK11-NEXT: ret void2691//2692//2693// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.12694// CHECK11-SAME: () #[[ATTR0]] {2695// CHECK11-NEXT: entry:2696// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)2697// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)2698// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]2699// CHECK11-NEXT: ret void2700//2701//2702// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef2703// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2704// CHECK11-NEXT: entry:2705// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82706// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 42707// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82708// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 42709// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82710// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42711// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])2712// CHECK11-NEXT: ret void2713//2714//2715// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor2716// CHECK11-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {2717// CHECK11-NEXT: entry:2718// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 82719// CHECK11-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 82720// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]2721// CHECK11: arraydestroy.body:2722// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]2723// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -12724// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]2725// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr2726// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]2727// CHECK11: arraydestroy.done1:2728// CHECK11-NEXT: ret void2729//2730//2731// CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.22732// CHECK11-SAME: () #[[ATTR0]] {2733// CHECK11-NEXT: entry:2734// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)2735// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]2736// CHECK11-NEXT: ret void2737//2738//2739// CHECK11-LABEL: define {{[^@]+}}@main2740// CHECK11-SAME: () #[[ATTR3:[0-9]+]] {2741// CHECK11-NEXT: entry:2742// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 42743// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 12744// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 42745// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])2746// CHECK11-NEXT: ret i32 02747//2748//2749// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev2750// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2751// CHECK11-NEXT: entry:2752// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82753// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82754// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82755// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02756// CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 42757// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float2758// CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 42759// CHECK11-NEXT: ret void2760//2761//2762// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev2763// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {2764// CHECK11-NEXT: entry:2765// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82766// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82767// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82768// CHECK11-NEXT: ret void2769//2770//2771// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef2772// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {2773// CHECK11-NEXT: entry:2774// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 82775// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 42776// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 82777// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 42778// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 82779// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 02780// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 42781// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 42782// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float2783// CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]2784// CHECK11-NEXT: store float [[ADD]], ptr [[F]], align 42785// CHECK11-NEXT: ret void2786//2787//2788// CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp2789// CHECK11-SAME: () #[[ATTR0]] {2790// CHECK11-NEXT: entry:2791// CHECK11-NEXT: call void @__cxx_global_var_init()2792// CHECK11-NEXT: call void @__cxx_global_var_init.1()2793// CHECK11-NEXT: call void @__cxx_global_var_init.2()2794// CHECK11-NEXT: ret void2795//2796