131 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _2// RUN: %clang_cc1 -Wno-error=incompatible-pointer-types -verify -triple powerpc64le-unknown-linux-gnu -fopenmp -x c -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 4// RUN: %clang_cc1 -Wno-error=incompatible-pointer-types -verify -triple powerpc64le-unknown-linux-gnu -fopenmp-simd -x c -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"5 6int a;7 8void foo(void) {9 int(*b)[a];10 int *(**c)[a];11#pragma omp parallel if (0)12 b[0][0] = c[0][a][0][a];13}14 15 16void bar(int n, int *a) {17 // expected-warning@+1 {{incompatible pointer types initializing 'int (*)[n]' with an expression of type 'int **'}}18 int(*p)[n] = &a;19#pragma omp parallel if(0)20 // expected-warning@+1 {{comparison of distinct pointer types ('int (*)[n]' and 'int **')}}21 if (p == &a) {22 }23}24 25// CHECK1-LABEL: define {{[^@]+}}@foo26// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {27// CHECK1-NEXT: entry:28// CHECK1-NEXT: [[B:%.*]] = alloca ptr, align 829// CHECK1-NEXT: [[C:%.*]] = alloca ptr, align 830// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 431// CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 432// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])33// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 434// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i6435// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr @a, align 436// CHECK1-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i6437// CHECK1-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])38// CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 439// CHECK1-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 440// CHECK1-NEXT: call void @foo.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]], ptr [[B]], i64 [[TMP4]], ptr [[C]]) #[[ATTR2:[0-9]+]]41// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])42// CHECK1-NEXT: ret void43//44//45// CHECK1-LABEL: define {{[^@]+}}@foo.omp_outlined46// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1:[0-9]+]] {47// CHECK1-NEXT: entry:48// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 849// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 850// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 851// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 852// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 853// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 854// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 855// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 856// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 857// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 858// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 859// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 860// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 861// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 862// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 863// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 864// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 865// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP4]], i64 066// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[ARRAYIDX]], align 867// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr @a, align 468// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i6469// CHECK1-NEXT: [[TMP7:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP2]]70// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds ptr, ptr [[TMP5]], i64 [[TMP7]]71// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds ptr, ptr [[ARRAYIDX3]], i64 072// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYIDX4]], align 873// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr @a, align 474// CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i6475// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, ptr [[TMP8]], i64 [[IDXPROM5]]76// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX6]], align 477// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 878// CHECK1-NEXT: [[TMP12:%.*]] = mul nsw i64 0, [[TMP0]]79// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, ptr [[TMP11]], i64 [[TMP12]]80// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX7]], i64 081// CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX8]], align 482// CHECK1-NEXT: ret void83//84//85// CHECK1-LABEL: define {{[^@]+}}@bar86// CHECK1-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {87// CHECK1-NEXT: entry:88// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 489// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 890// CHECK1-NEXT: [[P:%.*]] = alloca ptr, align 891// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 492// CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 493// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])94// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 495// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 896// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 497// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i6498// CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[P]], align 899// CHECK1-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])100// CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4101// CHECK1-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4102// CHECK1-NEXT: call void @bar.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]], ptr [[P]], ptr [[A_ADDR]]) #[[ATTR2]]103// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])104// CHECK1-NEXT: ret void105//106//107// CHECK1-LABEL: define {{[^@]+}}@bar.omp_outlined108// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[P:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR1]] {109// CHECK1-NEXT: entry:110// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8111// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8112// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8113// CHECK1-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8114// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8115// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8116// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8117// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8118// CHECK1-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 8119// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8120// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8121// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[P_ADDR]], align 8122// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8123// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP1]], align 8124// CHECK1-NEXT: [[CMP:%.*]] = icmp eq ptr [[TMP3]], [[TMP2]]125// CHECK1-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]126// CHECK1: if.then:127// CHECK1-NEXT: br label [[IF_END]]128// CHECK1: if.end:129// CHECK1-NEXT: ret void130//131