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1// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \2// RUN: -target-feature +zve32x -target-feature +zfh \3// RUN: -disable-O0-optnone -o - -fsyntax-only %s -verify 4// REQUIRES: riscv-registered-target5#include <riscv_vector.h>6 7vint64m1_t foo() { /* expected-error {{RISC-V type 'vint64m1_t' (aka '__rvv_int64m1_t') requires the 'zve64x' extension}} */8 vint64m1_t i64m1; /* expected-error {{RISC-V type 'vint64m1_t' (aka '__rvv_int64m1_t') requires the 'zve64x' extension}} */9 10 (void)i64m1; /* expected-error {{RISC-V type 'vint64m1_t' (aka '__rvv_int64m1_t') requires the 'zve64x' extension}} */11 12 return i64m1; /* expected-error {{RISC-V type 'vint64m1_t' (aka '__rvv_int64m1_t') requires the 'zve64x' extension}} */13}14 15vint64m1x2_t bar() { /* expected-error {{RISC-V type 'vint64m1x2_t' (aka '__rvv_int64m1x2_t') requires the 'zve64x' extension}} */16 vint64m1x2_t i64m1x2; /* expected-error {{RISC-V type 'vint64m1x2_t' (aka '__rvv_int64m1x2_t') requires the 'zve64x' extension}} */17 18 (void)i64m1x2; /* expected-error {{RISC-V type 'vint64m1x2_t' (aka '__rvv_int64m1x2_t') requires the 'zve64x' extension}} */19 20 return i64m1x2; /* expected-error {{RISC-V type 'vint64m1x2_t' (aka '__rvv_int64m1x2_t') requires the 'zve64x' extension}} */21}22