36 lines · c
1// REQUIRES: riscv-registered-target2// RUN: %clang_cc1 -triple riscv64 -target-feature +zvknha %s -fsyntax-only -verify3 4#include <riscv_vector.h>5 6// expected-no-diagnostics7 8__attribute__((target("arch=+zvl128b")))9void test_zvk_features(vuint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) {10 __riscv_vsha2ch_vv_u32m1(vd, vs2, vs1, vl);11}12 13__attribute__((target("arch=+v,+zvkn")))14vuint32m4_t testcase1(vuint32m4_t pt, vuint32m1_t rk, size_t vl)15{16 return __riscv_vaesz_vs_u32m1_u32m4(pt, rk, vl);17}18 19__attribute__((target("arch=+v,+zvknc")))20vuint32m4_t testcase2(vuint32m4_t pt, vuint32m1_t rk, size_t vl)21{22 return __riscv_vaesz_vs_u32m1_u32m4(pt, rk, vl);23}24 25__attribute__((target("arch=+v,+zvkned")))26vuint32m4_t testcase3(vuint32m4_t pt, vuint32m1_t rk, size_t vl)27{28 return __riscv_vaesz_vs_u32m1_u32m4(pt, rk, vl);29}30 31__attribute__((target("arch=+v,+zvkng")))32vuint32m4_t testcase4(vuint32m4_t pt, vuint32m1_t rk, size_t vl)33{34 return __riscv_vaesz_vs_u32m1_u32m4(pt, rk, vl);35}36