1429 lines · cpp
1//===- unittest/Format/FormatTestVerilog.cpp ------------------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#include "FormatTestBase.h"10 11#define DEBUG_TYPE "format-test"12 13namespace clang {14namespace format {15namespace test {16namespace {17class FormatTestVerilog : public test::FormatTestBase {18protected:19 FormatStyle getDefaultStyle() const override {20 return getLLVMStyle(FormatStyle::LK_Verilog);21 }22 std::string messUp(StringRef Code) const override {23 return test::messUp(Code, /*HandleHash=*/false);24 }25};26 27TEST_F(FormatTestVerilog, Align) {28 FormatStyle Style = getDefaultStyle();29 Style.AlignConsecutiveAssignments.Enabled = true;30 verifyFormat("x <= x;\n"31 "sfdbddfbdfbb <= x;\n"32 "x = x;",33 Style);34 verifyFormat("x = x;\n"35 "sfdbddfbdfbb = x;\n"36 "x = x;",37 Style);38 // Compound assignments are not aligned by default. '<=' is not a compound39 // assignment.40 verifyFormat("x <= x;\n"41 "sfdbddfbdfbb <= x;",42 Style);43 verifyFormat("x += x;\n"44 "sfdbddfbdfbb <= x;",45 Style);46 verifyFormat("x <<= x;\n"47 "sfdbddfbdfbb <= x;",48 Style);49 verifyFormat("x <<<= x;\n"50 "sfdbddfbdfbb <= x;",51 Style);52 verifyFormat("x >>= x;\n"53 "sfdbddfbdfbb <= x;",54 Style);55 verifyFormat("x >>>= x;\n"56 "sfdbddfbdfbb <= x;",57 Style);58 Style.AlignConsecutiveAssignments.AlignCompound = true;59 verifyFormat("x <= x;\n"60 "sfdbddfbdfbb <= x;",61 Style);62 verifyFormat("x += x;\n"63 "sfdbddfbdfbb <= x;",64 Style);65 verifyFormat("x <<= x;\n"66 "sfdbddfbdfbb <= x;",67 Style);68 verifyFormat("x <<<= x;\n"69 "sfdbddfbdfbb <= x;",70 Style);71 verifyFormat("x >>= x;\n"72 "sfdbddfbdfbb <= x;",73 Style);74 verifyFormat("x >>>= x;\n"75 "sfdbddfbdfbb <= x;",76 Style);77}78 79TEST_F(FormatTestVerilog, Assign) {80 verifyFormat("assign mynet = enable;");81 verifyFormat("assign (strong1, pull0) #1 mynet = enable;");82 verifyFormat("assign #1 mynet = enable;");83 verifyFormat("assign mynet = enable;");84 // Test that assignments are on separate lines.85 verifyFormat("assign mynet = enable,\n"86 " mynet1 = enable1;");87 // Test that `<=` and `,` don't confuse it.88 verifyFormat("assign mynet = enable1 <= enable2;");89 verifyFormat("assign mynet = enable1 <= enable2,\n"90 " mynet1 = enable3;");91 verifyFormat("assign mynet = enable,\n"92 " mynet1 = enable2 <= enable3;");93 verifyFormat("assign mynet = enable(enable1, enable2);");94}95 96TEST_F(FormatTestVerilog, BasedLiteral) {97 verifyFormat("x = '0;");98 verifyFormat("x = '1;");99 verifyFormat("x = 'X;");100 verifyFormat("x = 'x;");101 verifyFormat("x = 'Z;");102 verifyFormat("x = 'z;");103 verifyFormat("x = 659;");104 verifyFormat("x = 'h837ff;");105 verifyFormat("x = 'o7460;");106 verifyFormat("x = 4'b1001;");107 verifyFormat("x = 5'D3;");108 verifyFormat("x = 3'b01x;");109 verifyFormat("x = 12'hx;");110 verifyFormat("x = 16'hz;");111 verifyFormat("x = -8'd6;");112 verifyFormat("x = 4'shf;");113 verifyFormat("x = -4'sd15;");114 verifyFormat("x = 16'sd?;");115}116 117TEST_F(FormatTestVerilog, Block) {118 verifyFormat("begin\n"119 " x = x;\n"120 "end");121 verifyFormat("begin : x\n"122 " x = x;\n"123 "end : x");124 verifyFormat("begin\n"125 " x = x;\n"126 " x = x;\n"127 "end");128 verifyFormat("fork\n"129 " x = x;\n"130 "join");131 verifyFormat("fork\n"132 " x = x;\n"133 "join_any");134 verifyFormat("fork\n"135 " x = x;\n"136 "join_none");137 verifyFormat("generate\n"138 " x = x;\n"139 "endgenerate");140 verifyFormat("generate : x\n"141 " x = x;\n"142 "endgenerate : x");143 // Nested blocks.144 verifyFormat("begin\n"145 " begin\n"146 " end\n"147 "end");148 verifyFormat("begin : x\n"149 " begin\n"150 " end\n"151 "end : x");152 verifyFormat("begin : x\n"153 " begin : x\n"154 " end : x\n"155 "end : x");156 verifyFormat("begin\n"157 " begin : x\n"158 " end : x\n"159 "end");160 // Test that 'disable fork' and 'rand join' don't get mistaken as blocks.161 verifyFormat("disable fork;\n"162 "x = x;");163 verifyFormat("wait fork;\n"164 "x = x;");165 verifyFormat("rand join x x;\n"166 "x = x;");167 // The begin keyword should not be indented if it is too long to fit on the168 // same line.169 verifyFormat("while (true) //\n"170 "begin\n"171 " while (true) //\n"172 " begin\n"173 " end\n"174 "end");175 verifyFormat("while (true) //\n"176 "begin : x\n"177 " while (true) //\n"178 " begin : x\n"179 " end : x\n"180 "end : x");181 verifyFormat("while (true) //\n"182 "fork\n"183 " while (true) //\n"184 " fork\n"185 " join\n"186 "join");187 auto Style = getDefaultStyle();188 Style.ColumnLimit = 17;189 verifyFormat("while (true)\n"190 "begin\n"191 " while (true)\n"192 " begin\n"193 " end\n"194 "end",195 "while (true) begin\n"196 " while (true) begin"197 " end\n"198 "end",199 Style);200}201 202TEST_F(FormatTestVerilog, Case) {203 verifyFormat("case (data)\n"204 "endcase");205 verifyFormat("casex (data)\n"206 "endcase");207 verifyFormat("casez (data)\n"208 "endcase");209 verifyFormat("case (data) inside\n"210 "endcase");211 verifyFormat("case (data)\n"212 " 16'd0:\n"213 " result = 10'b0111111111;\n"214 "endcase");215 verifyFormat("case (data)\n"216 " xxxxxxxx:\n"217 " result = 10'b0111111111;\n"218 "endcase");219 // Test labels with multiple options.220 verifyFormat("case (data)\n"221 " 16'd0, 16'd1:\n"222 " result = 10'b0111111111;\n"223 "endcase");224 verifyFormat("case (data)\n"225 " 16'd0, //\n"226 " 16'd1:\n"227 " result = 10'b0111111111;\n"228 "endcase");229 // Test that blocks following labels are indented.230 verifyFormat("case (data)\n"231 " 16'd1: fork\n"232 " result = 10'b1011111111;\n"233 " join\n"234 "endcase");235 verifyFormat("case (data)\n"236 " 16'd1: fork : x\n"237 " result = 10'b1011111111;\n"238 " join : x\n"239 "endcase");240 // Test default.241 verifyFormat("case (data)\n"242 " default\n"243 " result = 10'b1011111111;\n"244 "endcase");245 verifyFormat("case (data)\n"246 " default:\n"247 " result = 10'b1011111111;\n"248 "endcase");249 // Test that question marks and colons don't get mistaken as labels.250 verifyFormat("case (data)\n"251 " 8'b1???????:\n"252 " instruction1(ir);\n"253 "endcase");254 verifyFormat("case (data)\n"255 " x ? 8'b1??????? : 1:\n"256 " instruction3(ir);\n"257 "endcase");258 // Test indention options.259 auto Style = getDefaultStyle();260 Style.IndentCaseLabels = false;261 verifyFormat("case (data)\n"262 "16'd0:\n"263 " result = 10'b0111111111;\n"264 "endcase",265 Style);266 verifyFormat("case (data)\n"267 "16'd0: begin\n"268 " result = 10'b0111111111;\n"269 "end\n"270 "endcase",271 Style);272 Style.IndentCaseLabels = true;273 verifyFormat("case (data)\n"274 " 16'd0:\n"275 " result = 10'b0111111111;\n"276 "endcase",277 Style);278 verifyFormat("case (data)\n"279 " 16'd0: begin\n"280 " result = 10'b0111111111;\n"281 " end\n"282 "endcase",283 Style);284 // Other colons should not be mistaken as case colons.285 Style = getDefaultStyle();286 Style.BitFieldColonSpacing = FormatStyle::BFCS_None;287 verifyFormat("case (x[1:0])\n"288 "endcase",289 Style);290 verifyFormat("default:\n"291 " x[1:0] = x[1:0];",292 Style);293 Style.BitFieldColonSpacing = FormatStyle::BFCS_Both;294 verifyFormat("case (x[1 : 0])\n"295 "endcase",296 Style);297 verifyFormat("default:\n"298 " x[1 : 0] = x[1 : 0];",299 Style);300 Style = getDefaultStyle();301 Style.SpacesInContainerLiterals = true;302 verifyFormat("case ('{x : x, default : 9})\n"303 "endcase",304 Style);305 verifyFormat("x = '{x : x, default : 9};", Style);306 verifyFormat("default:\n"307 " x = '{x : x, default : 9};",308 Style);309 Style.SpacesInContainerLiterals = false;310 verifyFormat("case ('{x: x, default: 9})\n"311 "endcase",312 Style);313 verifyFormat("x = '{x: x, default: 9};", Style);314 verifyFormat("default:\n"315 " x = '{x: x, default: 9};",316 Style);317 // When the line following the case label needs to be broken, the continuation318 // should be indented correctly.319 verifyFormat("case (data)\n"320 " 16'd0:\n"321 " result = //\n"322 " 10'b0111111111;\n"323 "endcase");324 verifyFormat("case (data)\n"325 " 16'd0, //\n"326 " 16'd1:\n"327 " result = //\n"328 " 10'b0111111111;\n"329 "endcase");330 verifyFormat("case (data)\n"331 " 16'd0:\n"332 " result = (10'b0111111111 + //\n"333 " 10'b0111111111 + //\n"334 " 10'b0111111111);\n"335 "endcase");336 verifyFormat("case (data)\n"337 " 16'd0:\n"338 " result = //\n"339 " (10'b0111111111 + //\n"340 " 10'b0111111111 + //\n"341 " 10'b0111111111);\n"342 "endcase");343 verifyFormat("case (data)\n"344 " 16'd0:\n"345 " result = //\n"346 " longfunction( //\n"347 " arg);\n"348 "endcase");349 verifyFormat("case (data)\n"350 " 16'd0:\n"351 " //\n"352 " result = //\n"353 " 10'b0111111111;\n"354 "endcase");355 verifyFormat("case (data)\n"356 " 16'd0:\n"357 " //\n"358 "\n"359 " //\n"360 " result = //\n"361 " 10'b0111111111;\n"362 "endcase");363 Style = getDefaultStyle();364 Style.ContinuationIndentWidth = 1;365 verifyFormat("case (data)\n"366 " 16'd0:\n"367 " result = //\n"368 " 10'b0111111111;\n"369 "endcase",370 Style);371 verifyFormat("case (data)\n"372 " 16'd0:\n"373 " result = //\n"374 " longfunction( //\n"375 " arg);\n"376 "endcase",377 Style);378 379 verifyFormat("case (v) matches\n"380 " tagged Valid .n:\n"381 " ;\n"382 "endcase");383}384 385TEST_F(FormatTestVerilog, Coverage) {386 verifyFormat("covergroup x\n"387 " @@(begin x);\n"388 "endgroup");389}390 391TEST_F(FormatTestVerilog, Declaration) {392 verifyFormat("wire mynet;");393 verifyFormat("wire mynet, mynet1;");394 verifyFormat("wire mynet, //\n"395 " mynet1;");396 verifyFormat("wire #0 mynet, mynet1;");397 verifyFormat("wire logic #0 mynet, mynet1;");398 verifyFormat("wire #(1, 2, 3) mynet, mynet1;");399 verifyFormat("wire #0 mynet, //\n"400 " mynet1;");401 verifyFormat("wire logic #0 mynet, //\n"402 " mynet1;");403 verifyFormat("wire #(1, 2, 3) mynet, //\n"404 " mynet1;");405 verifyFormat("wire mynet = enable;");406 verifyFormat("wire mynet = enable, mynet1;");407 verifyFormat("wire mynet = enable, //\n"408 " mynet1;");409 verifyFormat("wire mynet, mynet1 = enable;");410 verifyFormat("wire mynet, //\n"411 " mynet1 = enable;");412 verifyFormat("wire mynet = enable, mynet1 = enable;");413 verifyFormat("wire mynet = enable, //\n"414 " mynet1 = enable;");415 verifyFormat("wire (strong1, pull0) mynet;");416 verifyFormat("wire (strong1, pull0) mynet, mynet1;");417 verifyFormat("wire (strong1, pull0) mynet, //\n"418 " mynet1;");419 verifyFormat("wire (strong1, pull0) mynet = enable;");420 verifyFormat("wire (strong1, pull0) mynet = enable, mynet1;");421 verifyFormat("wire (strong1, pull0) mynet = enable, //\n"422 " mynet1;");423 verifyFormat("wire (strong1, pull0) mynet, mynet1 = enable;");424 verifyFormat("wire (strong1, pull0) mynet, //\n"425 " mynet1 = enable;");426}427 428TEST_F(FormatTestVerilog, Delay) {429 // Delay by the default unit.430 verifyFormat("#0;");431 verifyFormat("#1;");432 verifyFormat("#10;");433 verifyFormat("#1.5;");434 // Explicit unit.435 verifyFormat("#1fs;");436 verifyFormat("#1.5fs;");437 verifyFormat("#1ns;");438 verifyFormat("#1.5ns;");439 verifyFormat("#1us;");440 verifyFormat("#1.5us;");441 verifyFormat("#1ms;");442 verifyFormat("#1.5ms;");443 verifyFormat("#1s;");444 verifyFormat("#1.5s;");445 // The following expression should be on the same line.446 verifyFormat("#1 x = x;");447 verifyFormat("#1 x = x;", "#1\n"448 "x = x;");449}450 451TEST_F(FormatTestVerilog, Enum) {452 verifyFormat("enum { x } x;");453 verifyFormat("typedef enum { x } x;");454 verifyFormat("enum { red, yellow, green } x;");455 verifyFormat("typedef enum { red, yellow, green } x;");456 verifyFormat("enum integer { x } x;");457 verifyFormat("typedef enum { x = 0 } x;");458 verifyFormat("typedef enum { red = 0, yellow = 1, green = 2 } x;");459 verifyFormat("typedef enum integer { x } x;");460 verifyFormat("typedef enum bit [0 : 1] { x } x;");461 verifyFormat("typedef enum { add = 10, sub[5], jmp[6 : 8] } E1;");462 verifyFormat("typedef enum { add = 10, sub[5] = 0, jmp[6 : 8] = 1 } E1;");463}464 465TEST_F(FormatTestVerilog, Headers) {466 // Test headers with multiple ports.467 verifyFormat("module mh1\n"468 " (input var int in1,\n"469 " input var shortreal in2,\n"470 " output tagged_st out);\n"471 "endmodule");472 // There should be a space following the type but not the variable name.473 verifyFormat("module test\n"474 " (input wire [7 : 0] a,\n"475 " input wire b[7 : 0],\n"476 " input wire [7 : 0] c[7 : 0]);\n"477 "endmodule");478 // Ports should be grouped by types.479 verifyFormat("module test\n"480 " (input [7 : 0] a,\n"481 " input signed [7 : 0] b, c, d);\n"482 "endmodule");483 verifyFormat("module test\n"484 " (input [7 : 0] a,\n"485 " (* x = x *) input signed [7 : 0] b, c, d);\n"486 "endmodule");487 verifyFormat("module test\n"488 " (input [7 : 0] a = 0,\n"489 " input signed [7 : 0] b = 0, c = 0, d = 0);\n"490 "endmodule");491 verifyFormat("module test\n"492 " #(parameter x)\n"493 " (input [7 : 0] a,\n"494 " input signed [7 : 0] b, c, d);\n"495 "endmodule");496 // When a line needs to be broken, ports of the same type should be aligned to497 // the same column.498 verifyFormat("module test\n"499 " (input signed [7 : 0] b, c, //\n"500 " d);\n"501 "endmodule");502 verifyFormat("module test\n"503 " ((* x = x *) input signed [7 : 0] b, c, //\n"504 " d);\n"505 "endmodule");506 verifyFormat("module test\n"507 " (input signed [7 : 0] b = 0, c, //\n"508 " d);\n"509 "endmodule");510 verifyFormat("module test\n"511 " (input signed [7 : 0] b, c = 0, //\n"512 " d);\n"513 "endmodule");514 verifyFormat("module test\n"515 " (input signed [7 : 0] b, c, //\n"516 " d = 0);\n"517 "endmodule");518 verifyFormat("module test\n"519 " (input wire logic signed [7 : 0][0 : 1] b, c, //\n"520 " d);\n"521 "endmodule");522 verifyFormat("module test\n"523 " (input signed [7 : 0] b, //\n"524 " c, //\n"525 " d);\n"526 "endmodule");527 verifyFormat("module test\n"528 " (input [7 : 0] a,\n"529 " input signed [7 : 0] b, //\n"530 " c, //\n"531 " d);\n"532 "endmodule");533 verifyFormat("module test\n"534 " (input signed [7 : 0] b, //\n"535 " c, //\n"536 " d,\n"537 " output signed [7 : 0] h);\n"538 "endmodule");539 // With a modport.540 verifyFormat("module m\n"541 " (i2.master i);\n"542 "endmodule");543 verifyFormat("module m\n"544 " (i2.master i, ii);\n"545 "endmodule");546 verifyFormat("module m\n"547 " (i2.master i, //\n"548 " ii);\n"549 "endmodule");550 verifyFormat("module m\n"551 " (i2.master i,\n"552 " input ii);\n"553 "endmodule");554 verifyFormat("module m\n"555 " (i2::i2.master i);\n"556 "endmodule");557 verifyFormat("module m\n"558 " (i2::i2.master i, ii);\n"559 "endmodule");560 verifyFormat("module m\n"561 " (i2::i2.master i, //\n"562 " ii);\n"563 "endmodule");564 verifyFormat("module m\n"565 " (i2::i2.master i,\n"566 " input ii);\n"567 "endmodule");568 verifyFormat("module m\n"569 " (i2::i2 i);\n"570 "endmodule");571 verifyFormat("module m\n"572 " (i2::i2 i, ii);\n"573 "endmodule");574 verifyFormat("module m\n"575 " (i2::i2 i, //\n"576 " ii);\n"577 "endmodule");578 verifyFormat("module m\n"579 " (i2::i2 i,\n"580 " input ii);\n"581 "endmodule");582 // With a macro in the names.583 verifyFormat("module m\n"584 " (input var `x a, b);\n"585 "endmodule");586 verifyFormat("module m\n"587 " (input var `x a, //\n"588 " b);\n"589 "endmodule");590 verifyFormat("module m\n"591 " (input var x `a, b);\n"592 "endmodule");593 verifyFormat("module m\n"594 " (input var x `a, //\n"595 " b);\n"596 "endmodule");597 // A line comment shouldn't disrupt the indentation of the port list.598 verifyFormat("extern module x\n"599 " (//\n"600 " output y);");601 verifyFormat("extern module x\n"602 " #(//\n"603 " parameter x)\n"604 " (//\n"605 " output y);");606 // With a concatenation in the names.607 auto Style = getDefaultStyle();608 Style.ColumnLimit = 40;609 verifyFormat("`define X(x) \\\n"610 " module test \\\n"611 " (input var x``x a, b);",612 Style);613 verifyFormat("`define X(x) \\\n"614 " module test \\\n"615 " (input var x``x aaaaaaaaaaaaaaa, \\\n"616 " b);",617 Style);618 verifyFormat("`define X(x) \\\n"619 " module test \\\n"620 " (input var x a``x, b);",621 Style);622 verifyFormat("`define X(x) \\\n"623 " module test \\\n"624 " (input var x aaaaaaaaaaaaaaa``x, \\\n"625 " b);",626 Style);627 // When the ports line is not to be formatted, following lines should not take628 // on its indentation.629 verifyFormat("module x\n"630 " (output x);\n"631 " assign x = 0;\n"632 "endmodule",633 "module x\n"634 " (output x);\n"635 " assign x = 0;\n"636 "endmodule",637 getDefaultStyle(), {tooling::Range(25, 18)});638}639 640TEST_F(FormatTestVerilog, Hierarchy) {641 verifyFormat("module x;\n"642 "endmodule");643 // Test that the end label is on the same line as the end keyword.644 verifyFormat("module x;\n"645 "endmodule : x");646 // Test that things inside are indented.647 verifyFormat("module x;\n"648 " generate\n"649 " endgenerate\n"650 "endmodule");651 verifyFormat("program x;\n"652 " generate\n"653 " endgenerate\n"654 "endprogram");655 verifyFormat("interface x;\n"656 " generate\n"657 " endgenerate\n"658 "endinterface");659 verifyFormat("task x;\n"660 " generate\n"661 " endgenerate\n"662 "endtask");663 verifyFormat("function x;\n"664 " generate\n"665 " endgenerate\n"666 "endfunction");667 verifyFormat("class x;\n"668 " generate\n"669 " endgenerate\n"670 "endclass");671 // Test that they nest.672 verifyFormat("module x;\n"673 " program x;\n"674 " program x;\n"675 " endprogram\n"676 " endprogram\n"677 "endmodule");678 // Test that an extern declaration doesn't change the indentation.679 verifyFormat("import \"DPI-C\" context MyCFunc = function integer MapID\n"680 " (int portID);\n"681 "x = x;");682 verifyFormat("export \"DPI-C\" function exported_sv_func;\n"683 "x = x;");684 verifyFormat("import \"DPI-C\" function void f1\n"685 " (input int i1,\n"686 " pair i2,\n"687 " output logic [63 : 0] o3);\n"688 "x = x;");689 verifyFormat("extern module x;\n"690 "x = x;");691 // Test complex headers692 verifyFormat("extern module x\n"693 " import x.x::x::*;\n"694 " import x;\n"695 " #(parameter x)\n"696 " (output x);");697 verifyFormat("module x\n"698 " import x.x::x::*;\n"699 " import x;\n"700 " #(parameter x)\n"701 " (output x);\n"702 " generate\n"703 " endgenerate\n"704 "endmodule : x");705 verifyFormat("virtual class x\n"706 " (x)\n"707 " extends x(x)\n"708 " implements x, x, x;\n"709 " generate\n"710 " endgenerate\n"711 "endclass : x");712 verifyFormat("function automatic logic [1 : 0] x\n"713 " (input x);\n"714 " generate\n"715 " endgenerate\n"716 "endfunction : x");717 // Type names with '::' should be recognized.718 verifyFormat("function automatic x::x x\n"719 " (input x);\n"720 "endfunction : x");721 // Names having to do macros should be recognized.722 verifyFormat("function automatic x::x x``x\n"723 " (input x);\n"724 "endfunction : x");725 verifyFormat("function automatic x::x `x\n"726 " (input x);\n"727 "endfunction : x");728 verifyNoCrash("x x(x x, x x);");729}730 731TEST_F(FormatTestVerilog, Identifiers) {732 // Escaped identifiers should not be split.733 verifyFormat("\\busa+index");734 verifyFormat("\\-clock");735 verifyFormat("\\***error-condition***");736 verifyFormat("\\net1\\/net2");737 verifyFormat("\\{a,b}");738 verifyFormat("\\a*(b+c)");739 // Escaped identifiers can't be joined with the next token. Extra space740 // should be removed.741 verifyFormat("\\busa+index ;", "\\busa+index\n"742 ";");743 verifyFormat("\\busa+index ;", "\\busa+index\r\n"744 ";");745 verifyFormat("\\busa+index ;", "\\busa+index ;");746 verifyFormat("\\busa+index ;", "\\busa+index\n"747 " ;");748 verifyFormat("\\busa+index ;");749 verifyFormat("(\\busa+index );");750 verifyFormat("\\busa+index \\busa+index ;");751}752 753TEST_F(FormatTestVerilog, If) {754 verifyFormat("if (x)\n"755 " x = x;");756 verifyFormat("unique if (x)\n"757 " x = x;");758 verifyFormat("unique0 if (x)\n"759 " x = x;");760 verifyFormat("priority if (x)\n"761 " x = x;");762 verifyFormat("if (x)\n"763 " x = x;\n"764 "x = x;");765 766 // Test else767 verifyFormat("if (x)\n"768 " x = x;\n"769 "else if (x)\n"770 " x = x;\n"771 "else\n"772 " x = x;");773 verifyFormat("if (x) begin\n"774 " x = x;\n"775 "end else if (x) begin\n"776 " x = x;\n"777 "end else begin\n"778 " x = x;\n"779 "end");780 verifyFormat("if (x) begin : x\n"781 " x = x;\n"782 "end : x else if (x) begin : x\n"783 " x = x;\n"784 "end : x else begin : x\n"785 " x = x;\n"786 "end : x");787 788 // Test block keywords.789 verifyFormat("if (x) begin\n"790 " x = x;\n"791 "end");792 verifyFormat("if (x) begin : x\n"793 " x = x;\n"794 "end : x");795 verifyFormat("if (x) begin\n"796 " x = x;\n"797 " x = x;\n"798 "end");799 verifyFormat("if (x) fork\n"800 " x = x;\n"801 "join");802 verifyFormat("if (x) fork\n"803 " x = x;\n"804 "join_any");805 verifyFormat("if (x) fork\n"806 " x = x;\n"807 "join_none");808 verifyFormat("if (x) generate\n"809 " x = x;\n"810 "endgenerate");811 verifyFormat("if (x) generate : x\n"812 " x = x;\n"813 "endgenerate : x");814 815 // Test that concatenation braces don't get regarded as blocks.816 verifyFormat("if (x)\n"817 " {x} = x;");818 verifyFormat("if (x)\n"819 " x = {x};");820 verifyFormat("if (x)\n"821 " x = {x};\n"822 "else\n"823 " {x} = {x};");824 825 // With attributes.826 verifyFormat("(* x *) if (x)\n"827 " x = x;");828 verifyFormat("(* x = \"x\" *) if (x)\n"829 " x = x;");830 verifyFormat("(* x, x = \"x\" *) if (x)\n"831 " x = x;");832 833 // Assert are treated similar to if. But the else parts should not be834 // chained.835 verifyFormat("assert (x);");836 verifyFormat("assert (x)\n"837 " $info();");838 verifyFormat("assert (x)\n"839 " $info();\n"840 "else\n"841 " $error();");842 verifyFormat("assert (x)\n"843 "else\n"844 " $error();");845 verifyFormat("assert (x)\n"846 "else begin\n"847 "end");848 verifyFormat("assert (x)\n"849 "else\n"850 " if (x)\n"851 " $error();");852 verifyFormat("assert (x)\n"853 " $info();\n"854 "else\n"855 " if (x)\n"856 " $error();");857 verifyFormat("assert (x)\n"858 " $info();\n"859 "else\n"860 " if (x)\n"861 " $error();\n"862 " else\n"863 " $error();");864 verifyFormat("assert (x)\n"865 " $info();\n"866 "else\n"867 " if (x)\n"868 " $error();\n"869 " else if (x)\n"870 " $error();\n"871 " else\n"872 " $error();");873 // The body is optional for asserts. The next line should not be indented if874 // the statement already ended with a semicolon.875 verifyFormat("assert (x);\n"876 "x = x;");877 verifyFormat("if (x)\n"878 " assert (x);\n"879 "else if (x) begin\n"880 "end else begin\n"881 "end");882 verifyFormat("if (x)\n"883 " assert (x);\n"884 "else begin\n"885 "end");886 verifyFormat("if (x)\n"887 " assert (x)\n"888 " else begin\n"889 " end");890 // Other keywords.891 verifyFormat("assume (x)\n"892 " $info();");893 verifyFormat("cover (x)\n"894 " $info();");895 verifyFormat("restrict (x)\n"896 " $info();");897 verifyFormat("assert #0 (x)\n"898 " $info();");899 verifyFormat("assert final (x)\n"900 " $info();");901 verifyFormat("cover #0 (x)\n"902 " $info();");903 verifyFormat("cover final (x)\n"904 " $info();");905 906 // The space around parentheses options should work.907 auto Style = getDefaultStyle();908 verifyFormat("if (x)\n"909 " x = x;\n"910 "else if (x)\n"911 " x = x;",912 Style);913 verifyFormat("assert (x);", Style);914 verifyFormat("assert #0 (x);", Style);915 verifyFormat("assert (x)\n"916 "else\n"917 " if (x)\n"918 " x = x;",919 Style);920 Style.SpacesInParens = FormatStyle::SIPO_Custom;921 Style.SpacesInParensOptions.InConditionalStatements = true;922 verifyFormat("if ( x )\n"923 " x = x;\n"924 "else if ( x )\n"925 " x = x;",926 Style);927 verifyFormat("assert ( x );", Style);928 verifyFormat("assert #0 ( x );", Style);929 verifyFormat("assert ( x )\n"930 "else\n"931 " if ( x )\n"932 " x = x;",933 Style);934}935 936TEST_F(FormatTestVerilog, Instantiation) {937 // Without ports.938 verifyFormat("ffnand ff1;");939 // With named ports.940 verifyFormat("ffnand ff1(.qbar(out1),\n"941 " .clear(in1),\n"942 " .preset(in2));");943 // With wildcard.944 verifyFormat("ffnand ff1(.qbar(out1),\n"945 " .clear(in1),\n"946 " .preset(in2),\n"947 " .*);");948 verifyFormat("ffnand ff1(.*,\n"949 " .qbar(out1),\n"950 " .clear(in1),\n"951 " .preset(in2));");952 // With unconnected ports.953 verifyFormat("ffnand ff1(.q(),\n"954 " .qbar(out1),\n"955 " .clear(in1),\n"956 " .preset(in2));");957 verifyFormat("ffnand ff1(.q(),\n"958 " .qbar(),\n"959 " .clear(),\n"960 " .preset());");961 verifyFormat("ffnand ff1(,\n"962 " .qbar(out1),\n"963 " .clear(in1),\n"964 " .preset(in2));");965 // With positional ports.966 verifyFormat("ffnand ff1(out1,\n"967 " in1,\n"968 " in2);");969 verifyFormat("ffnand ff1(,\n"970 " out1,\n"971 " in1,\n"972 " in2);");973 // Multiple instantiations.974 verifyFormat("ffnand ff1(.q(),\n"975 " .qbar(out1),\n"976 " .clear(in1),\n"977 " .preset(in2)),\n"978 " ff1(.q(),\n"979 " .qbar(out1),\n"980 " .clear(in1),\n"981 " .preset(in2));");982 verifyFormat("ffnand //\n"983 " ff1(.q(),\n"984 " .qbar(out1),\n"985 " .clear(in1),\n"986 " .preset(in2)),\n"987 " ff1(.q(),\n"988 " .qbar(out1),\n"989 " .clear(in1),\n"990 " .preset(in2));");991 verifyNoCrash(", ff1();");992 // With breaking between instance ports disabled.993 auto Style = getDefaultStyle();994 Style.VerilogBreakBetweenInstancePorts = false;995 verifyFormat("ffnand ff1;", Style);996 verifyFormat("ffnand ff1(.qbar(out1), .clear(in1), .preset(in2), .*);",997 Style);998 verifyFormat("ffnand ff1(out1, in1, in2);", Style);999 verifyFormat("ffnand ff1(.q(), .qbar(out1), .clear(in1), .preset(in2)),\n"1000 " ff1(.q(), .qbar(out1), .clear(in1), .preset(in2));",1001 Style);1002 verifyFormat("ffnand //\n"1003 " ff1(.q(), .qbar(out1), .clear(in1), .preset(in2)),\n"1004 " ff1(.q(), .qbar(out1), .clear(in1), .preset(in2));",1005 Style);1006}1007 1008TEST_F(FormatTestVerilog, Loop) {1009 verifyFormat("foreach (x[x])\n"1010 " x = x;");1011 verifyFormat("repeat (x)\n"1012 " x = x;");1013 verifyFormat("foreach (x[x]) begin\n"1014 "end");1015 verifyFormat("repeat (x) begin\n"1016 "end");1017 auto Style = getDefaultStyle();1018 Style.SpacesInParens = FormatStyle::SIPO_Custom;1019 Style.SpacesInParensOptions.InConditionalStatements = true;1020 verifyFormat("foreach ( x[x] )\n"1021 " x = x;",1022 Style);1023 verifyFormat("repeat ( x )\n"1024 " x = x;",1025 Style);1026}1027 1028TEST_F(FormatTestVerilog, Operators) {1029 // Test that unary operators are not followed by space.1030 verifyFormat("x = +x;");1031 verifyFormat("x = -x;");1032 verifyFormat("x = !x;");1033 verifyFormat("x = ~x;");1034 verifyFormat("x = &x;");1035 verifyFormat("x = ~&x;");1036 verifyFormat("x = |x;");1037 verifyFormat("x = ~|x;");1038 verifyFormat("x = ^x;");1039 verifyFormat("x = ~^x;");1040 verifyFormat("x = ^~x;");1041 verifyFormat("x = ++x;");1042 verifyFormat("x = --x;");1043 1044 // Test that `*` and `*>` are binary.1045 verifyFormat("x = x * x;");1046 verifyFormat("x = (x * x);");1047 verifyFormat("(opcode *> o1) = 6.1;");1048 verifyFormat("(C, D *> Q) = 18;");1049 // The wildcard import is not a binary operator.1050 verifyFormat("import p::*;");1051 1052 // Test that operators don't get split.1053 verifyFormat("x = x++;");1054 verifyFormat("x = x--;");1055 verifyFormat("x = x ** x;");1056 verifyFormat("x = x << x;");1057 verifyFormat("x = x >> x;");1058 verifyFormat("x = x <<< x;");1059 verifyFormat("x = x >>> x;");1060 verifyFormat("x = x <= x;");1061 verifyFormat("x = x >= x;");1062 verifyFormat("x = x == x;");1063 verifyFormat("x = x != x;");1064 verifyFormat("x = x === x;");1065 verifyFormat("x = x !== x;");1066 verifyFormat("x = x ==? x;");1067 verifyFormat("x = x !=? x;");1068 verifyFormat("x = x ~^ x;");1069 verifyFormat("x = x ^~ x;");1070 verifyFormat("x = x && x;");1071 verifyFormat("x = x || x;");1072 verifyFormat("x = x -> x;");1073 verifyFormat("x = x <-> x;");1074 verifyFormat("x += x;");1075 verifyFormat("x -= x;");1076 verifyFormat("x *= x;");1077 verifyFormat("x /= x;");1078 verifyFormat("x %= x;");1079 verifyFormat("x &= x;");1080 verifyFormat("x ^= x;");1081 verifyFormat("x |= x;");1082 verifyFormat("x <<= x;");1083 verifyFormat("x >>= x;");1084 verifyFormat("x <<<= x;");1085 verifyFormat("x >>>= x;");1086 verifyFormat("x <= x;");1087 1088 // Test that space is added between operators.1089 verifyFormat("x = x < -x;", "x=x<-x;");1090 verifyFormat("x = x << -x;", "x=x<<-x;");1091 verifyFormat("x = x <<< -x;", "x=x<<<-x;");1092 1093 // Test that operators that are C++ identifiers get treated as operators.1094 verifyFormat("solve s before d;"); // before1095 verifyFormat("binsof(i) intersect {0};"); // intersect1096 verifyFormat("req dist {1};"); // dist1097 verifyFormat("a inside {b, c};"); // inside1098 verifyFormat("bus.randomize() with { atype == low; };"); // with1099}1100 1101TEST_F(FormatTestVerilog, Preprocessor) {1102 auto Style = getDefaultStyle();1103 Style.ColumnLimit = 20;1104 1105 // Macro definitions.1106 verifyFormat("`define X \\\n"1107 " if (x) \\\n"1108 " x = x;",1109 "`define X if(x)x=x;", Style);1110 verifyFormat("`define X(x) \\\n"1111 " if (x) \\\n"1112 " x = x;",1113 "`define X(x) if(x)x=x;", Style);1114 verifyFormat("`define X \\\n"1115 " x = x; \\\n"1116 " x = x;",1117 "`define X x=x;x=x;", Style);1118 // Macro definitions with invocations inside.1119 verifyFormat("`define LIST \\\n"1120 " `ENTRY \\\n"1121 " `ENTRY",1122 "`define LIST \\\n"1123 "`ENTRY \\\n"1124 "`ENTRY",1125 Style);1126 verifyFormat("`define LIST \\\n"1127 " `x = `x; \\\n"1128 " `x = `x;",1129 "`define LIST \\\n"1130 "`x = `x; \\\n"1131 "`x = `x;",1132 Style);1133 verifyFormat("`define LIST \\\n"1134 " `x = `x; \\\n"1135 " `x = `x;",1136 "`define LIST `x=`x;`x=`x;", Style);1137 // Macro invocations.1138 verifyFormat("`x = (`x1 + `x2 + x);");1139 // Lines starting with a preprocessor directive should not be indented.1140 std::string Directives[] = {1141 "begin_keywords",1142 "celldefine",1143 "default_nettype",1144 "define",1145 "else",1146 "elsif",1147 "end_keywords",1148 "endcelldefine",1149 "endif",1150 "ifdef",1151 "ifndef",1152 "include",1153 "line",1154 "nounconnected_drive",1155 "pragma",1156 "resetall",1157 "timescale",1158 "unconnected_drive",1159 "undef",1160 "undefineall",1161 };1162 for (auto &Name : Directives) {1163 verifyFormat("if (x)\n"1164 "`" +1165 Name +1166 "\n"1167 " ;",1168 "if (x)\n"1169 "`" +1170 Name +1171 "\n"1172 ";",1173 Style);1174 }1175 // Lines starting with a regular macro invocation should be indented as a1176 // normal line.1177 verifyFormat("if (x)\n"1178 " `x = `x;\n"1179 "`timescale 1ns / 1ps",1180 "if (x)\n"1181 "`x = `x;\n"1182 "`timescale 1ns / 1ps",1183 Style);1184 verifyFormat("if (x)\n"1185 "`timescale 1ns / 1ps\n"1186 " `x = `x;",1187 "if (x)\n"1188 "`timescale 1ns / 1ps\n"1189 "`x = `x;",1190 Style);1191 std::string NonDirectives[] = {1192 // For `__FILE__` and `__LINE__`, although the standard classifies them as1193 // preprocessor directives, they are used like regular macros.1194 "__FILE__", "__LINE__", "elif", "foo", "x",1195 };1196 for (auto &Name : NonDirectives) {1197 verifyFormat("if (x)\n"1198 " `" +1199 Name + ";",1200 "if (x)\n"1201 "`" +1202 Name +1203 "\n"1204 ";",1205 Style);1206 }1207}1208 1209TEST_F(FormatTestVerilog, Primitive) {1210 verifyFormat("primitive multiplexer\n"1211 " (mux, control, dataA, dataB);\n"1212 " output mux;\n"1213 " input control, dataA, dataB;\n"1214 " table\n"1215 " 0 1 ? : 1;\n"1216 " 0 0 ? : 0;\n"1217 " 1 ? 1 : 1;\n"1218 " 1 ? 0 : 0;\n"1219 " x 0 0 : 0;\n"1220 " x 1 1 : 1;\n"1221 " endtable\n"1222 "endprimitive");1223 verifyFormat("primitive latch\n"1224 " (q, ena_, data);\n"1225 " output q;\n"1226 " reg q;\n"1227 " input ena_, data;\n"1228 " table\n"1229 " 0 1 : ? : 1;\n"1230 " 0 0 : ? : 0;\n"1231 " 1 ? : ? : -;\n"1232 " ? * : ? : -;\n"1233 " endtable\n"1234 "endprimitive");1235 verifyFormat("primitive d\n"1236 " (q, clock, data);\n"1237 " output q;\n"1238 " reg q;\n"1239 " input clock, data;\n"1240 " table\n"1241 " (01) 0 : ? : 0;\n"1242 " (01) 1 : ? : 1;\n"1243 " (0?) 1 : 1 : 1;\n"1244 " (0?) 0 : 0 : 0;\n"1245 " (?0) ? : ? : -;\n"1246 " (?\?) ? : ? : -;\n"1247 " endtable\n"1248 "endprimitive");1249}1250 1251TEST_F(FormatTestVerilog, Streaming) {1252 verifyFormat("x = {>>{j}};");1253 verifyFormat("x = {>>byte{j}};");1254 verifyFormat("x = {<<{j}};");1255 verifyFormat("x = {<<byte{j}};");1256 verifyFormat("x = {<<16{j}};");1257 verifyFormat("x = {<<{8'b0011_0101}};");1258 verifyFormat("x = {<<4{6'b11_0101}};");1259 verifyFormat("x = {>>4{6'b11_0101}};");1260 verifyFormat("x = {<<2{{<<{4'b1101}}}};");1261 verifyFormat("bit [96 : 1] y = {>>{a, b, c}};");1262 verifyFormat("int j = {>>{a, b, c}};");1263 verifyFormat("{>>{a, b, c}} = 23'b1;");1264 verifyFormat("{>>{a, b, c}} = x;");1265 verifyFormat("{>>{j}} = x;");1266 verifyFormat("{>>byte{j}} = x;");1267 verifyFormat("{<<{j}} = x;");1268 verifyFormat("{<<byte{j}} = x;");1269}1270 1271TEST_F(FormatTestVerilog, StringLiteral) {1272 // Long strings should be broken.1273 verifyFormat(R"(x({"xxxxxxxxxxxxxxxx ",1274 "xxxx"});)",1275 R"(x({"xxxxxxxxxxxxxxxx xxxx"});)",1276 getStyleWithColumns(getDefaultStyle(), 23));1277 verifyFormat(R"(x({"xxxxxxxxxxxxxxxx",1278 " xxxx"});)",1279 R"(x({"xxxxxxxxxxxxxxxx xxxx"});)",1280 getStyleWithColumns(getDefaultStyle(), 22));1281 // Braces should be added when they don't already exist.1282 verifyFormat(R"(x({"xxxxxxxxxxxxxxxx ",1283 "xxxx"});)",1284 R"(x("xxxxxxxxxxxxxxxx xxxx");)",1285 getStyleWithColumns(getDefaultStyle(), 23));1286 verifyFormat(R"(x({"xxxxxxxxxxxxxxxx",1287 " xxxx"});)",1288 R"(x("xxxxxxxxxxxxxxxx xxxx");)",1289 getStyleWithColumns(getDefaultStyle(), 22));1290 verifyFormat(R"(x({{"xxxxxxxxxxxxxxxx ",1291 "xxxx"} == x});)",1292 R"(x({"xxxxxxxxxxxxxxxx xxxx" == x});)",1293 getStyleWithColumns(getDefaultStyle(), 24));1294 verifyFormat(R"(string x = {"xxxxxxxxxxxxxxxx ",1295 "xxxxxxxx"};)",1296 R"(string x = "xxxxxxxxxxxxxxxx xxxxxxxx";)",1297 getStyleWithColumns(getDefaultStyle(), 32));1298 // Space around braces should be correct.1299 auto Style = getStyleWithColumns(getDefaultStyle(), 24);1300 Style.Cpp11BracedListStyle = FormatStyle::BLS_Block;1301 verifyFormat(R"(x({ "xxxxxxxxxxxxxxxx ",1302 "xxxx" });)",1303 R"(x("xxxxxxxxxxxxxxxx xxxx");)", Style);1304 // Braces should not be added twice.1305 verifyFormat(R"(x({"xxxxxxxx",1306 "xxxxxxxx",1307 "xxxxxx"});)",1308 R"(x("xxxxxxxxxxxxxxxxxxxxxx");)",1309 getStyleWithColumns(getDefaultStyle(), 14));1310 verifyFormat(R"(x({"xxxxxxxxxxxxxxxx ",1311 "xxxxxxxxxxxxxxxx ",1312 "xxxx"});)",1313 R"(x("xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxx");)",1314 getStyleWithColumns(getDefaultStyle(), 23));1315 verifyFormat(R"(x({"xxxxxxxxxxxxxxxx ",1316 "xxxxxxxxxxxxxxxx ",1317 "xxxx"});)",1318 R"(x({"xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx ", "xxxx"});)",1319 getStyleWithColumns(getDefaultStyle(), 23));1320 // import/export "DPI"/"DPI-C" cannot be split.1321 verifyFormat(R"(import1322 "DPI-C" function void foo1323 ();)",1324 R"(import "DPI-C" function void foo();)",1325 getStyleWithColumns(getDefaultStyle(), 23));1326 verifyFormat(R"(export "DPI-C" function foo;)",1327 R"(export "DPI-C" function foo;)",1328 getStyleWithColumns(getDefaultStyle(), 23));1329 // These kinds of strings don't exist in Verilog.1330 verifyNoCrash(R"(x(@"xxxxxxxxxxxxxxxx xxxx");)",1331 getStyleWithColumns(getDefaultStyle(), 23));1332 verifyNoCrash(R"(x(u"xxxxxxxxxxxxxxxx xxxx");)",1333 getStyleWithColumns(getDefaultStyle(), 23));1334 verifyNoCrash(R"(x(u8"xxxxxxxxxxxxxxxx xxxx");)",1335 getStyleWithColumns(getDefaultStyle(), 23));1336 verifyNoCrash(R"(x(_T("xxxxxxxxxxxxxxxx xxxx"));)",1337 getStyleWithColumns(getDefaultStyle(), 23));1338}1339 1340TEST_F(FormatTestVerilog, StructLiteral) {1341 verifyFormat("c = '{0, 0.0};");1342 verifyFormat("c = '{'{1, 1.0}, '{2, 2.0}};");1343 verifyFormat("c = '{a: 0, b: 0.0};");1344 verifyFormat("c = '{a: 0, b: 0.0, default: 0};");1345 verifyFormat("d = {int: 1, shortreal: 1.0};");1346 verifyFormat("c = '{default: 0};");1347 1348 // The identifier before the quote can be either a tag or a type case. There1349 // should be a space between the tag and the quote.1350 verifyFormat("c = ab'{a: 0, b: 0.0};");1351 verifyFormat("c = ab'{cd: cd'{1, 1.0}, ef: ef'{2, 2.0}};");1352 verifyFormat("c = ab'{cd'{1, 1.0}, ef'{2, 2.0}};");1353 verifyFormat("d = ab'{int: 1, shortreal: 1.0};");1354 verifyFormat("x = tagged Add '{e1, 4, ed};");1355 1356 auto Style = getDefaultStyle();1357 Style.SpacesInContainerLiterals = true;1358 verifyFormat("c = '{a : 0, b : 0.0};", Style);1359 verifyFormat("c = '{a : 0, b : 0.0, default : 0};", Style);1360 verifyFormat("c = ab'{a : 0, b : 0.0};", Style);1361 verifyFormat("c = ab'{cd : cd'{1, 1.0}, ef : ef'{2, 2.0}};", Style);1362 1363 // It should be indented correctly when the line has to break.1364 verifyFormat("c = //\n"1365 " '{default: 0};");1366 Style = getDefaultStyle();1367 Style.ContinuationIndentWidth = 2;1368 verifyFormat("c = //\n"1369 " '{default: 0};",1370 Style);1371}1372 1373TEST_F(FormatTestVerilog, StructuredProcedure) {1374 // Blocks should be indented correctly.1375 verifyFormat("initial begin\n"1376 "end");1377 verifyFormat("initial begin\n"1378 " x <= x;\n"1379 " x <= x;\n"1380 "end");1381 verifyFormat("initial\n"1382 " x <= x;\n"1383 "x <= x;");1384 verifyFormat("always @(x) begin\n"1385 "end");1386 verifyFormat("always @(x) begin\n"1387 " x <= x;\n"1388 " x <= x;\n"1389 "end");1390 verifyFormat("always @(x)\n"1391 " x <= x;\n"1392 "x <= x;");1393 // Various keywords.1394 verifyFormat("always @(x)\n"1395 " x <= x;");1396 verifyFormat("always @(posedge x)\n"1397 " x <= x;");1398 verifyFormat("always @(posedge x or posedge y)\n"1399 " x <= x;");1400 verifyFormat("always @(posedge x, posedge y)\n"1401 " x <= x;");1402 verifyFormat("always @(negedge x, negedge y)\n"1403 " x <= x;");1404 verifyFormat("always @(edge x, edge y)\n"1405 " x <= x;");1406 verifyFormat("always\n"1407 " x <= x;");1408 verifyFormat("always @*\n"1409 " x <= x;");1410 verifyFormat("always @(*)\n"1411 " x <= x;");1412 verifyFormat("always_comb\n"1413 " x <= x;");1414 verifyFormat("always_latch @(x)\n"1415 " x <= x;");1416 verifyFormat("always_ff @(posedge x)\n"1417 " x <= x;");1418 verifyFormat("initial\n"1419 " x <= x;");1420 verifyFormat("final\n"1421 " x <= x;");1422 verifyFormat("forever\n"1423 " x <= x;");1424}1425} // namespace1426} // namespace test1427} // namespace format1428} // namespace clang1429