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1//===-- cpu_model/x86.c - Support for __cpu_model builtin --------*- C -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file is based on LLVM's lib/Support/Host.cpp.10// It implements the operating system Host concept and builtin11// __cpu_model for the compiler_rt library for x86.12//13//===----------------------------------------------------------------------===//14 15#include "cpu_model.h"16 17#if !(defined(__i386__) || defined(_M_IX86) || defined(__x86_64__) || \18 defined(_M_X64))19#error This file is intended only for x86-based targets20#endif21 22#if defined(__GNUC__) || defined(__clang__) || defined(_MSC_VER)23 24#if __STDC_HOSTED__25#include <assert.h>26#endif // __STDC_HOSTED__27 28#if (defined(__GNUC__) || defined(__clang__)) && !defined(_MSC_VER)29#include <cpuid.h>30#endif31 32#ifdef _MSC_VER33#include <intrin.h>34#endif35 36enum VendorSignatures {37 SIG_INTEL = 0x756e6547, // Genu38 SIG_AMD = 0x68747541, // Auth39};40 41enum ProcessorVendors {42 VENDOR_INTEL = 1,43 VENDOR_AMD,44 VENDOR_OTHER,45 VENDOR_MAX46};47 48enum ProcessorTypes {49 INTEL_BONNELL = 1,50 INTEL_CORE2,51 INTEL_COREI7,52 AMDFAM10H,53 AMDFAM15H,54 INTEL_SILVERMONT,55 INTEL_KNL,56 AMD_BTVER1,57 AMD_BTVER2,58 AMDFAM17H,59 INTEL_KNM,60 INTEL_GOLDMONT,61 INTEL_GOLDMONT_PLUS,62 INTEL_TREMONT,63 AMDFAM19H,64 ZHAOXIN_FAM7H,65 INTEL_SIERRAFOREST,66 INTEL_GRANDRIDGE,67 INTEL_CLEARWATERFOREST,68 AMDFAM1AH,69 CPU_TYPE_MAX70};71 72enum ProcessorSubtypes {73 INTEL_COREI7_NEHALEM = 1,74 INTEL_COREI7_WESTMERE,75 INTEL_COREI7_SANDYBRIDGE,76 AMDFAM10H_BARCELONA,77 AMDFAM10H_SHANGHAI,78 AMDFAM10H_ISTANBUL,79 AMDFAM15H_BDVER1,80 AMDFAM15H_BDVER2,81 AMDFAM15H_BDVER3,82 AMDFAM15H_BDVER4,83 AMDFAM17H_ZNVER1,84 INTEL_COREI7_IVYBRIDGE,85 INTEL_COREI7_HASWELL,86 INTEL_COREI7_BROADWELL,87 INTEL_COREI7_SKYLAKE,88 INTEL_COREI7_SKYLAKE_AVX512,89 INTEL_COREI7_CANNONLAKE,90 INTEL_COREI7_ICELAKE_CLIENT,91 INTEL_COREI7_ICELAKE_SERVER,92 AMDFAM17H_ZNVER2,93 INTEL_COREI7_CASCADELAKE,94 INTEL_COREI7_TIGERLAKE,95 INTEL_COREI7_COOPERLAKE,96 INTEL_COREI7_SAPPHIRERAPIDS,97 INTEL_COREI7_ALDERLAKE,98 AMDFAM19H_ZNVER3,99 INTEL_COREI7_ROCKETLAKE,100 ZHAOXIN_FAM7H_LUJIAZUI,101 AMDFAM19H_ZNVER4,102 INTEL_COREI7_GRANITERAPIDS,103 INTEL_COREI7_GRANITERAPIDS_D,104 INTEL_COREI7_ARROWLAKE,105 INTEL_COREI7_ARROWLAKE_S,106 INTEL_COREI7_PANTHERLAKE,107 AMDFAM1AH_ZNVER5,108 INTEL_COREI7_DIAMONDRAPIDS,109 INTEL_COREI7_NOVALAKE,110 CPU_SUBTYPE_MAX111};112 113enum ProcessorFeatures {114 FEATURE_CMOV = 0,115 FEATURE_MMX,116 FEATURE_POPCNT,117 FEATURE_SSE,118 FEATURE_SSE2,119 FEATURE_SSE3,120 FEATURE_SSSE3,121 FEATURE_SSE4_1,122 FEATURE_SSE4_2,123 FEATURE_AVX,124 FEATURE_AVX2,125 FEATURE_SSE4_A,126 FEATURE_FMA4,127 FEATURE_XOP,128 FEATURE_FMA,129 FEATURE_AVX512F,130 FEATURE_BMI,131 FEATURE_BMI2,132 FEATURE_AES,133 FEATURE_PCLMUL,134 FEATURE_AVX512VL,135 FEATURE_AVX512BW,136 FEATURE_AVX512DQ,137 FEATURE_AVX512CD,138 FEATURE_AVX512VBMI = 26,139 FEATURE_AVX512IFMA,140 FEATURE_AVX512VPOPCNTDQ = 30,141 FEATURE_AVX512VBMI2,142 FEATURE_GFNI,143 FEATURE_VPCLMULQDQ,144 FEATURE_AVX512VNNI,145 FEATURE_AVX512BITALG,146 FEATURE_AVX512BF16,147 FEATURE_AVX512VP2INTERSECT,148 // FIXME: Below Features has some missings comparing to gcc, it's because gcc149 // has some not one-to-one mapped in llvm.150 // FEATURE_3DNOW,151 // FEATURE_3DNOWP,152 FEATURE_ADX = 40,153 // FEATURE_ABM,154 FEATURE_CLDEMOTE = 42,155 FEATURE_CLFLUSHOPT,156 FEATURE_CLWB,157 FEATURE_CLZERO,158 FEATURE_CMPXCHG16B,159 // FIXME: Not adding FEATURE_CMPXCHG8B is a workaround to make 'generic' as160 // a cpu string with no X86_FEATURE_COMPAT features, which is required in161 // current implementantion of cpu_specific/cpu_dispatch FMV feature.162 // FEATURE_CMPXCHG8B,163 FEATURE_ENQCMD = 48,164 FEATURE_F16C,165 FEATURE_FSGSBASE,166 // FEATURE_FXSAVE,167 // FEATURE_HLE,168 // FEATURE_IBT,169 FEATURE_LAHF_LM = 54,170 FEATURE_LM,171 FEATURE_LWP,172 FEATURE_LZCNT,173 FEATURE_MOVBE,174 FEATURE_MOVDIR64B,175 FEATURE_MOVDIRI,176 FEATURE_MWAITX,177 // FEATURE_OSXSAVE,178 FEATURE_PCONFIG = 63,179 FEATURE_PKU,180 FEATURE_PRFCHW = 66,181 FEATURE_PTWRITE,182 FEATURE_RDPID,183 FEATURE_RDRND,184 FEATURE_RDSEED,185 FEATURE_RTM,186 FEATURE_SERIALIZE,187 FEATURE_SGX,188 FEATURE_SHA,189 FEATURE_SHSTK,190 FEATURE_TBM,191 FEATURE_TSXLDTRK,192 FEATURE_VAES,193 FEATURE_WAITPKG,194 FEATURE_WBNOINVD,195 FEATURE_XSAVE,196 FEATURE_XSAVEC,197 FEATURE_XSAVEOPT,198 FEATURE_XSAVES,199 FEATURE_AMX_TILE,200 FEATURE_AMX_INT8,201 FEATURE_AMX_BF16,202 FEATURE_UINTR,203 FEATURE_HRESET,204 FEATURE_KL,205 // FEATURE_AESKLE,206 FEATURE_WIDEKL = 92,207 FEATURE_AVXVNNI,208 FEATURE_AVX512FP16,209 FEATURE_X86_64_BASELINE,210 FEATURE_X86_64_V2,211 FEATURE_X86_64_V3,212 FEATURE_X86_64_V4,213 FEATURE_AVXIFMA,214 FEATURE_AVXVNNIINT8,215 FEATURE_AVXNECONVERT,216 FEATURE_CMPCCXADD,217 FEATURE_AMX_FP16,218 FEATURE_PREFETCHI,219 FEATURE_RAOINT,220 FEATURE_AMX_COMPLEX,221 FEATURE_AVXVNNIINT16,222 FEATURE_SM3,223 FEATURE_SHA512,224 FEATURE_SM4,225 FEATURE_APXF,226 FEATURE_USERMSR,227 FEATURE_AVX10_1 = 114,228 FEATURE_AVX10_2 = 116,229 FEATURE_AMX_AVX512,230 FEATURE_AMX_TF32,231 FEATURE_AMX_FP8 = 120,232 FEATURE_MOVRS,233 FEATURE_AMX_MOVRS,234 CPU_FEATURE_MAX235};236 237#ifndef _WIN32238__attribute__((visibility("hidden")))239#endif240struct __processor_model {241 unsigned int __cpu_vendor;242 unsigned int __cpu_type;243 unsigned int __cpu_subtype;244 unsigned int __cpu_features[1];245} __cpu_model = {0, 0, 0, {0}};246 247_Static_assert(sizeof(__cpu_model) == 16,248 "Wrong size of __cpu_model will result in ABI break");249 250// This code is copied from lib/Support/Host.cpp.251// Changes to either file should be mirrored in the other.252 253/// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in254/// the specified arguments. If we can't run cpuid on the host, return true.255static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,256 unsigned *rECX, unsigned *rEDX) {257#if (defined(__GNUC__) || defined(__clang__)) && !defined(_MSC_VER)258 return !__get_cpuid(value, rEAX, rEBX, rECX, rEDX);259#elif defined(_MSC_VER)260 // The MSVC intrinsic is portable across x86 and x64.261 int registers[4];262 __cpuid(registers, value);263 *rEAX = registers[0];264 *rEBX = registers[1];265 *rECX = registers[2];266 *rEDX = registers[3];267 return false;268#else269 return true;270#endif271}272 273/// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return274/// the 4 values in the specified arguments. If we can't run cpuid on the host,275/// return true.276static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,277 unsigned *rEAX, unsigned *rEBX, unsigned *rECX,278 unsigned *rEDX) {279 // TODO(boomanaiden154): When the minimum toolchain versions for gcc and clang280 // are such that __cpuidex is defined within cpuid.h for both, we can remove281 // the __get_cpuid_count function and share the MSVC implementation between282 // all three.283#if (defined(__GNUC__) || defined(__clang__)) && !defined(_MSC_VER)284 return !__get_cpuid_count(value, subleaf, rEAX, rEBX, rECX, rEDX);285#elif defined(_MSC_VER)286 int registers[4];287 __cpuidex(registers, value, subleaf);288 *rEAX = registers[0];289 *rEBX = registers[1];290 *rECX = registers[2];291 *rEDX = registers[3];292 return false;293#else294 return true;295#endif296}297 298// Read control register 0 (XCR0). Used to detect features such as AVX.299static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) {300 // TODO(boomanaiden154): When the minimum toolchain versions for gcc and clang301 // are such that _xgetbv is supported by both, we can unify the implementation302 // with MSVC and remove all inline assembly.303#if defined(__GNUC__) || defined(__clang__)304 // Check xgetbv; this uses a .byte sequence instead of the instruction305 // directly because older assemblers do not include support for xgetbv and306 // there is no easy way to conditionally compile based on the assembler used.307 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));308 return false;309#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)310 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);311 *rEAX = Result;312 *rEDX = Result >> 32;313 return false;314#else315 return true;316#endif317}318 319static void detectX86FamilyModel(unsigned EAX, unsigned *Family,320 unsigned *Model) {321 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11322 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7323 if (*Family == 6 || *Family == 0xf) {324 if (*Family == 0xf)325 // Examine extended family ID if family ID is F.326 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27327 // Examine extended model ID if family ID is 6 or F.328 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19329 }330}331 332#define testFeature(F) (Features[F / 32] & (1 << (F % 32))) != 0333 334static const char *335getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,336 const unsigned *Features,337 struct __processor_model *CpuModel) {338 // We select CPU strings to match the code in Host.cpp, but we don't use them339 // in compiler-rt.340 const char *CPU = 0;341 342 enum ProcessorTypes Type = CPU_TYPE_MAX;343 enum ProcessorSubtypes Subtype = CPU_SUBTYPE_MAX;344 345 switch (Family) {346 case 0x6:347 switch (Model) {348 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile349 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad350 // mobile processor, Intel Core 2 Extreme processor, Intel351 // Pentium Dual-Core processor, Intel Xeon processor, model352 // 0Fh. All processors are manufactured using the 65 nm process.353 case 0x16: // Intel Celeron processor model 16h. All processors are354 // manufactured using the 65 nm process355 CPU = "core2";356 Type = INTEL_CORE2;357 break;358 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model359 // 17h. All processors are manufactured using the 45 nm process.360 //361 // 45nm: Penryn , Wolfdale, Yorkfield (XE)362 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using363 // the 45 nm process.364 CPU = "penryn";365 Type = INTEL_CORE2;366 break;367 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All368 // processors are manufactured using the 45 nm process.369 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.370 // As found in a Summer 2010 model iMac.371 case 0x1f:372 case 0x2e: // Nehalem EX373 CPU = "nehalem";374 Type = INTEL_COREI7;375 Subtype = INTEL_COREI7_NEHALEM;376 break;377 case 0x25: // Intel Core i7, laptop version.378 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All379 // processors are manufactured using the 32 nm process.380 case 0x2f: // Westmere EX381 CPU = "westmere";382 Type = INTEL_COREI7;383 Subtype = INTEL_COREI7_WESTMERE;384 break;385 case 0x2a: // Intel Core i7 processor. All processors are manufactured386 // using the 32 nm process.387 case 0x2d:388 CPU = "sandybridge";389 Type = INTEL_COREI7;390 Subtype = INTEL_COREI7_SANDYBRIDGE;391 break;392 case 0x3a:393 case 0x3e: // Ivy Bridge EP394 CPU = "ivybridge";395 Type = INTEL_COREI7;396 Subtype = INTEL_COREI7_IVYBRIDGE;397 break;398 399 // Haswell:400 case 0x3c:401 case 0x3f:402 case 0x45:403 case 0x46:404 CPU = "haswell";405 Type = INTEL_COREI7;406 Subtype = INTEL_COREI7_HASWELL;407 break;408 409 // Broadwell:410 case 0x3d:411 case 0x47:412 case 0x4f:413 case 0x56:414 CPU = "broadwell";415 Type = INTEL_COREI7;416 Subtype = INTEL_COREI7_BROADWELL;417 break;418 419 // Skylake:420 case 0x4e: // Skylake mobile421 case 0x5e: // Skylake desktop422 case 0x8e: // Kaby Lake mobile423 case 0x9e: // Kaby Lake desktop424 case 0xa5: // Comet Lake-H/S425 case 0xa6: // Comet Lake-U426 CPU = "skylake";427 Type = INTEL_COREI7;428 Subtype = INTEL_COREI7_SKYLAKE;429 break;430 431 // Rocketlake:432 case 0xa7:433 CPU = "rocketlake";434 Type = INTEL_COREI7;435 Subtype = INTEL_COREI7_ROCKETLAKE;436 break;437 438 // Skylake Xeon:439 case 0x55:440 Type = INTEL_COREI7;441 if (testFeature(FEATURE_AVX512BF16)) {442 CPU = "cooperlake";443 Subtype = INTEL_COREI7_COOPERLAKE;444 } else if (testFeature(FEATURE_AVX512VNNI)) {445 CPU = "cascadelake";446 Subtype = INTEL_COREI7_CASCADELAKE;447 } else {448 CPU = "skylake-avx512";449 Subtype = INTEL_COREI7_SKYLAKE_AVX512;450 }451 break;452 453 // Cannonlake:454 case 0x66:455 CPU = "cannonlake";456 Type = INTEL_COREI7;457 Subtype = INTEL_COREI7_CANNONLAKE;458 break;459 460 // Icelake:461 case 0x7d:462 case 0x7e:463 CPU = "icelake-client";464 Type = INTEL_COREI7;465 Subtype = INTEL_COREI7_ICELAKE_CLIENT;466 break;467 468 // Tigerlake:469 case 0x8c:470 case 0x8d:471 CPU = "tigerlake";472 Type = INTEL_COREI7;473 Subtype = INTEL_COREI7_TIGERLAKE;474 break;475 476 // Alderlake:477 case 0x97:478 case 0x9a:479 CPU = "alderlake";480 Type = INTEL_COREI7;481 Subtype = INTEL_COREI7_ALDERLAKE;482 break;483 484 // Raptorlake:485 case 0xb7:486 case 0xba:487 case 0xbf:488 CPU = "raptorlake";489 Type = INTEL_COREI7;490 Subtype = INTEL_COREI7_ALDERLAKE;491 break;492 493 // Meteorlake:494 case 0xaa:495 case 0xac:496 CPU = "meteorlake";497 Type = INTEL_COREI7;498 Subtype = INTEL_COREI7_ALDERLAKE;499 break;500 501 // Gracemont:502 case 0xbe:503 CPU = "gracemont";504 Type = INTEL_COREI7;505 Subtype = INTEL_COREI7_ALDERLAKE;506 break;507 508 // Arrowlake:509 case 0xc5:510 // Arrowlake U:511 case 0xb5:512 CPU = "arrowlake";513 Type = INTEL_COREI7;514 Subtype = INTEL_COREI7_ARROWLAKE;515 break;516 517 // Arrowlake S:518 case 0xc6:519 CPU = "arrowlake-s";520 Type = INTEL_COREI7;521 Subtype = INTEL_COREI7_ARROWLAKE_S;522 break;523 524 // Lunarlake:525 case 0xbd:526 CPU = "lunarlake";527 Type = INTEL_COREI7;528 Subtype = INTEL_COREI7_ARROWLAKE_S;529 break;530 531 // Pantherlake:532 case 0xcc:533 CPU = "pantherlake";534 Type = INTEL_COREI7;535 Subtype = INTEL_COREI7_PANTHERLAKE;536 break;537 538 // Wildcatlake:539 case 0xd5:540 CPU = "wildcatlake";541 Type = INTEL_COREI7;542 Subtype = INTEL_COREI7_PANTHERLAKE;543 break;544 545 // Icelake Xeon:546 case 0x6a:547 case 0x6c:548 CPU = "icelake-server";549 Type = INTEL_COREI7;550 Subtype = INTEL_COREI7_ICELAKE_SERVER;551 break;552 553 // Emerald Rapids:554 case 0xcf:555 CPU = "emeraldrapids";556 Type = INTEL_COREI7;557 Subtype = INTEL_COREI7_SAPPHIRERAPIDS;558 break;559 560 // Sapphire Rapids:561 case 0x8f:562 CPU = "sapphirerapids";563 Type = INTEL_COREI7;564 Subtype = INTEL_COREI7_SAPPHIRERAPIDS;565 break;566 567 // Granite Rapids:568 case 0xad:569 CPU = "graniterapids";570 Type = INTEL_COREI7;571 Subtype = INTEL_COREI7_GRANITERAPIDS;572 break;573 574 // Granite Rapids D:575 case 0xae:576 CPU = "graniterapids-d";577 Type = INTEL_COREI7;578 Subtype = INTEL_COREI7_GRANITERAPIDS_D;579 break;580 581 case 0x1c: // Most 45 nm Intel Atom processors582 case 0x26: // 45 nm Atom Lincroft583 case 0x27: // 32 nm Atom Medfield584 case 0x35: // 32 nm Atom Midview585 case 0x36: // 32 nm Atom Midview586 CPU = "bonnell";587 Type = INTEL_BONNELL;588 break;589 590 // Atom Silvermont codes from the Intel software optimization guide.591 case 0x37:592 case 0x4a:593 case 0x4d:594 case 0x5a:595 case 0x5d:596 case 0x4c: // really airmont597 CPU = "silvermont";598 Type = INTEL_SILVERMONT;599 break;600 // Goldmont:601 case 0x5c: // Apollo Lake602 case 0x5f: // Denverton603 CPU = "goldmont";604 Type = INTEL_GOLDMONT;605 break; // "goldmont"606 case 0x7a:607 CPU = "goldmont-plus";608 Type = INTEL_GOLDMONT_PLUS;609 break;610 case 0x86:611 case 0x8a: // Lakefield612 case 0x96: // Elkhart Lake613 case 0x9c: // Jasper Lake614 CPU = "tremont";615 Type = INTEL_TREMONT;616 break;617 618 // Sierraforest:619 case 0xaf:620 CPU = "sierraforest";621 Type = INTEL_SIERRAFOREST;622 break;623 624 // Grandridge:625 case 0xb6:626 CPU = "grandridge";627 Type = INTEL_GRANDRIDGE;628 break;629 630 // Clearwaterforest:631 case 0xdd:632 CPU = "clearwaterforest";633 Type = INTEL_CLEARWATERFOREST;634 break;635 636 case 0x57:637 CPU = "knl";638 Type = INTEL_KNL;639 break;640 641 case 0x85:642 CPU = "knm";643 Type = INTEL_KNM;644 break;645 646 default: // Unknown family 6 CPU.647 break;648 }649 break;650 case 0x13:651 switch (Model) {652 // Diamond Rapids:653 case 0x01:654 CPU = "diamondrapids";655 Type = INTEL_COREI7;656 Subtype = INTEL_COREI7_DIAMONDRAPIDS;657 break;658 659 default: // Unknown family 19 CPU.660 break;661 }662 break;663 case 0x12:664 switch (Model) {665 case 0x1:666 case 0x3:667 CPU = "novalake";668 Type = INTEL_COREI7;669 Subtype = INTEL_COREI7_NOVALAKE;670 break;671 default: // Unknown family 0x12 CPU.672 break;673 }674 break;675 676 default:677 break; // Unknown.678 }679 680 if (Type != CPU_TYPE_MAX)681 CpuModel->__cpu_type = Type;682 if (Subtype != CPU_SUBTYPE_MAX)683 CpuModel->__cpu_subtype = Subtype;684 685 return CPU;686}687 688static const char *689getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,690 const unsigned *Features,691 struct __processor_model *CpuModel) {692 const char *CPU = 0;693 694 enum ProcessorTypes Type = CPU_TYPE_MAX;695 enum ProcessorSubtypes Subtype = CPU_SUBTYPE_MAX;696 697 switch (Family) {698 case 4:699 CPU = "i486";700 break;701 case 5:702 CPU = "pentium";703 switch (Model) {704 case 6:705 case 7:706 CPU = "k6";707 break;708 case 8:709 CPU = "k6-2";710 break;711 case 9:712 case 13:713 CPU = "k6-3";714 break;715 case 10:716 CPU = "geode";717 break;718 }719 break;720 case 6:721 if (testFeature(FEATURE_SSE)) {722 CPU = "athlon-xp";723 break;724 }725 CPU = "athlon";726 break;727 case 15:728 if (testFeature(FEATURE_SSE3)) {729 CPU = "k8-sse3";730 break;731 }732 CPU = "k8";733 break;734 case 16:735 case 18:736 CPU = "amdfam10";737 Type = AMDFAM10H; // "amdfam10"738 switch (Model) {739 case 2:740 Subtype = AMDFAM10H_BARCELONA;741 break;742 case 4:743 Subtype = AMDFAM10H_SHANGHAI;744 break;745 case 8:746 Subtype = AMDFAM10H_ISTANBUL;747 break;748 }749 break;750 case 20:751 CPU = "btver1";752 Type = AMD_BTVER1;753 break;754 case 21:755 CPU = "bdver1";756 Type = AMDFAM15H;757 if (Model >= 0x60 && Model <= 0x7f) {758 CPU = "bdver4";759 Subtype = AMDFAM15H_BDVER4;760 break; // 60h-7Fh: Excavator761 }762 if (Model >= 0x30 && Model <= 0x3f) {763 CPU = "bdver3";764 Subtype = AMDFAM15H_BDVER3;765 break; // 30h-3Fh: Steamroller766 }767 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) {768 CPU = "bdver2";769 Subtype = AMDFAM15H_BDVER2;770 break; // 02h, 10h-1Fh: Piledriver771 }772 if (Model <= 0x0f) {773 Subtype = AMDFAM15H_BDVER1;774 break; // 00h-0Fh: Bulldozer775 }776 break;777 case 22:778 CPU = "btver2";779 Type = AMD_BTVER2;780 break;781 case 23:782 CPU = "znver1";783 Type = AMDFAM17H;784 if ((Model >= 0x30 && Model <= 0x3f) || (Model == 0x47) ||785 (Model >= 0x60 && Model <= 0x67) || (Model >= 0x68 && Model <= 0x6f) ||786 (Model >= 0x70 && Model <= 0x7f) || (Model >= 0x84 && Model <= 0x87) ||787 (Model >= 0x90 && Model <= 0x97) || (Model >= 0x98 && Model <= 0x9f) ||788 (Model >= 0xa0 && Model <= 0xaf)) {789 // Family 17h Models 30h-3Fh (Starship) Zen 2790 // Family 17h Models 47h (Cardinal) Zen 2791 // Family 17h Models 60h-67h (Renoir) Zen 2792 // Family 17h Models 68h-6Fh (Lucienne) Zen 2793 // Family 17h Models 70h-7Fh (Matisse) Zen 2794 // Family 17h Models 84h-87h (ProjectX) Zen 2795 // Family 17h Models 90h-97h (VanGogh) Zen 2796 // Family 17h Models 98h-9Fh (Mero) Zen 2797 // Family 17h Models A0h-AFh (Mendocino) Zen 2798 CPU = "znver2";799 Subtype = AMDFAM17H_ZNVER2;800 break;801 }802 if ((Model >= 0x10 && Model <= 0x1f) || (Model >= 0x20 && Model <= 0x2f)) {803 // Family 17h Models 10h-1Fh (Raven1) Zen804 // Family 17h Models 10h-1Fh (Picasso) Zen+805 // Family 17h Models 20h-2Fh (Raven2 x86) Zen806 Subtype = AMDFAM17H_ZNVER1;807 break;808 }809 break;810 case 25:811 CPU = "znver3";812 Type = AMDFAM19H;813 if (Model <= 0x0f || (Model >= 0x20 && Model <= 0x2f) ||814 (Model >= 0x30 && Model <= 0x3f) || (Model >= 0x40 && Model <= 0x4f) ||815 (Model >= 0x50 && Model <= 0x5f)) {816 // Family 19h Models 00h-0Fh (Genesis, Chagall) Zen 3817 // Family 19h Models 20h-2Fh (Vermeer) Zen 3818 // Family 19h Models 30h-3Fh (Badami) Zen 3819 // Family 19h Models 40h-4Fh (Rembrandt) Zen 3+820 // Family 19h Models 50h-5Fh (Cezanne) Zen 3821 Subtype = AMDFAM19H_ZNVER3;822 break;823 }824 if ((Model >= 0x10 && Model <= 0x1f) || (Model >= 0x60 && Model <= 0x6f) ||825 (Model >= 0x70 && Model <= 0x77) || (Model >= 0x78 && Model <= 0x7f) ||826 (Model >= 0xa0 && Model <= 0xaf)) {827 // Family 19h Models 10h-1Fh (Stones; Storm Peak) Zen 4828 // Family 19h Models 60h-6Fh (Raphael) Zen 4829 // Family 19h Models 70h-77h (Phoenix, Hawkpoint1) Zen 4830 // Family 19h Models 78h-7Fh (Phoenix 2, Hawkpoint2) Zen 4831 // Family 19h Models A0h-AFh (Stones-Dense) Zen 4832 CPU = "znver4";833 Subtype = AMDFAM19H_ZNVER4;834 break; // "znver4"835 }836 break; // family 19h837 case 26:838 CPU = "znver5";839 Type = AMDFAM1AH;840 if (Model <= 0x77) {841 // Models 00h-0Fh (Breithorn).842 // Models 10h-1Fh (Breithorn-Dense).843 // Models 20h-2Fh (Strix 1).844 // Models 30h-37h (Strix 2).845 // Models 38h-3Fh (Strix 3).846 // Models 40h-4Fh (Granite Ridge).847 // Models 50h-5Fh (Weisshorn).848 // Models 60h-6Fh (Krackan1).849 // Models 70h-77h (Sarlak).850 CPU = "znver5";851 Subtype = AMDFAM1AH_ZNVER5;852 break; // "znver5"853 }854 break;855 default:856 break; // Unknown AMD CPU.857 }858 859 if (Type != CPU_TYPE_MAX)860 CpuModel->__cpu_type = Type;861 if (Subtype != CPU_SUBTYPE_MAX)862 CpuModel->__cpu_subtype = Subtype;863 864 return CPU;865}866 867#undef testFeature868 869static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,870 unsigned *Features) {871 unsigned EAX = 0, EBX = 0;872 873#define hasFeature(F) ((Features[F / 32] >> (F % 32)) & 1)874#define setFeature(F) Features[F / 32] |= 1U << (F % 32)875 876 if ((EDX >> 15) & 1)877 setFeature(FEATURE_CMOV);878 if ((EDX >> 23) & 1)879 setFeature(FEATURE_MMX);880 if ((EDX >> 25) & 1)881 setFeature(FEATURE_SSE);882 if ((EDX >> 26) & 1)883 setFeature(FEATURE_SSE2);884 885 if ((ECX >> 0) & 1)886 setFeature(FEATURE_SSE3);887 if ((ECX >> 1) & 1)888 setFeature(FEATURE_PCLMUL);889 if ((ECX >> 9) & 1)890 setFeature(FEATURE_SSSE3);891 if ((ECX >> 12) & 1)892 setFeature(FEATURE_FMA);893 if ((ECX >> 13) & 1)894 setFeature(FEATURE_CMPXCHG16B);895 if ((ECX >> 19) & 1)896 setFeature(FEATURE_SSE4_1);897 if ((ECX >> 20) & 1)898 setFeature(FEATURE_SSE4_2);899 if ((ECX >> 22) & 1)900 setFeature(FEATURE_MOVBE);901 if ((ECX >> 23) & 1)902 setFeature(FEATURE_POPCNT);903 if ((ECX >> 25) & 1)904 setFeature(FEATURE_AES);905 if ((ECX >> 29) & 1)906 setFeature(FEATURE_F16C);907 if ((ECX >> 30) & 1)908 setFeature(FEATURE_RDRND);909 910 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV911 // indicates that the AVX registers will be saved and restored on context912 // switch, then we have full AVX support.913 const unsigned AVXBits = (1 << 27) | (1 << 28);914 bool HasAVXSave = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&915 ((EAX & 0x6) == 0x6);916#if defined(__APPLE__)917 // Darwin lazily saves the AVX512 context on first use: trust that the OS will918 // save the AVX512 context if we use AVX512 instructions, even the bit is not919 // set right now.920 bool HasAVX512Save = true;921#else922 // AVX512 requires additional context to be saved by the OS.923 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);924#endif925 // AMX requires additional context to be saved by the OS.926 const unsigned AMXBits = (1 << 17) | (1 << 18);927 bool HasXSave = ((ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX);928 bool HasAMXSave = HasXSave && ((EAX & AMXBits) == AMXBits);929 930 if (HasAVXSave)931 setFeature(FEATURE_AVX);932 933 if (((ECX >> 26) & 1) && HasAVXSave)934 setFeature(FEATURE_XSAVE);935 936 bool HasLeaf7 =937 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);938 939 if (HasLeaf7 && ((EBX >> 0) & 1))940 setFeature(FEATURE_FSGSBASE);941 if (HasLeaf7 && ((EBX >> 2) & 1))942 setFeature(FEATURE_SGX);943 if (HasLeaf7 && ((EBX >> 3) & 1))944 setFeature(FEATURE_BMI);945 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave)946 setFeature(FEATURE_AVX2);947 if (HasLeaf7 && ((EBX >> 8) & 1))948 setFeature(FEATURE_BMI2);949 if (HasLeaf7 && ((EBX >> 11) & 1))950 setFeature(FEATURE_RTM);951 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save)952 setFeature(FEATURE_AVX512F);953 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)954 setFeature(FEATURE_AVX512DQ);955 if (HasLeaf7 && ((EBX >> 18) & 1))956 setFeature(FEATURE_RDSEED);957 if (HasLeaf7 && ((EBX >> 19) & 1))958 setFeature(FEATURE_ADX);959 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)960 setFeature(FEATURE_AVX512IFMA);961 if (HasLeaf7 && ((EBX >> 23) & 1))962 setFeature(FEATURE_CLFLUSHOPT);963 if (HasLeaf7 && ((EBX >> 24) & 1))964 setFeature(FEATURE_CLWB);965 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)966 setFeature(FEATURE_AVX512CD);967 if (HasLeaf7 && ((EBX >> 29) & 1))968 setFeature(FEATURE_SHA);969 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)970 setFeature(FEATURE_AVX512BW);971 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)972 setFeature(FEATURE_AVX512VL);973 974 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)975 setFeature(FEATURE_AVX512VBMI);976 if (HasLeaf7 && ((ECX >> 4) & 1))977 setFeature(FEATURE_PKU);978 if (HasLeaf7 && ((ECX >> 5) & 1))979 setFeature(FEATURE_WAITPKG);980 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save)981 setFeature(FEATURE_AVX512VBMI2);982 if (HasLeaf7 && ((ECX >> 7) & 1))983 setFeature(FEATURE_SHSTK);984 if (HasLeaf7 && ((ECX >> 8) & 1))985 setFeature(FEATURE_GFNI);986 if (HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave)987 setFeature(FEATURE_VAES);988 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave)989 setFeature(FEATURE_VPCLMULQDQ);990 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save)991 setFeature(FEATURE_AVX512VNNI);992 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)993 setFeature(FEATURE_AVX512BITALG);994 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)995 setFeature(FEATURE_AVX512VPOPCNTDQ);996 if (HasLeaf7 && ((ECX >> 22) & 1))997 setFeature(FEATURE_RDPID);998 if (HasLeaf7 && ((ECX >> 23) & 1))999 setFeature(FEATURE_KL);1000 if (HasLeaf7 && ((ECX >> 25) & 1))1001 setFeature(FEATURE_CLDEMOTE);1002 if (HasLeaf7 && ((ECX >> 27) & 1))1003 setFeature(FEATURE_MOVDIRI);1004 if (HasLeaf7 && ((ECX >> 28) & 1))1005 setFeature(FEATURE_MOVDIR64B);1006 if (HasLeaf7 && ((ECX >> 29) & 1))1007 setFeature(FEATURE_ENQCMD);1008 1009 if (HasLeaf7 && ((EDX >> 5) & 1))1010 setFeature(FEATURE_UINTR);1011 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save)1012 setFeature(FEATURE_AVX512VP2INTERSECT);1013 if (HasLeaf7 && ((EDX >> 14) & 1))1014 setFeature(FEATURE_SERIALIZE);1015 if (HasLeaf7 && ((EDX >> 16) & 1))1016 setFeature(FEATURE_TSXLDTRK);1017 if (HasLeaf7 && ((EDX >> 18) & 1))1018 setFeature(FEATURE_PCONFIG);1019 if (HasLeaf7 && ((EDX >> 22) & 1) && HasAMXSave)1020 setFeature(FEATURE_AMX_BF16);1021 if (HasLeaf7 && ((EDX >> 23) & 1) && HasAVX512Save)1022 setFeature(FEATURE_AVX512FP16);1023 if (HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave)1024 setFeature(FEATURE_AMX_TILE);1025 if (HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave)1026 setFeature(FEATURE_AMX_INT8);1027 1028 // EAX from subleaf 0 is the maximum subleaf supported. Some CPUs don't1029 // return all 0s for invalid subleaves so check the limit.1030 bool HasLeaf7Subleaf1 =1031 HasLeaf7 && EAX >= 1 &&1032 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);1033 if (HasLeaf7Subleaf1 && ((EAX >> 0) & 1))1034 setFeature(FEATURE_SHA512);1035 if (HasLeaf7Subleaf1 && ((EAX >> 1) & 1))1036 setFeature(FEATURE_SM3);1037 if (HasLeaf7Subleaf1 && ((EAX >> 2) & 1))1038 setFeature(FEATURE_SM4);1039 if (HasLeaf7Subleaf1 && ((EAX >> 3) & 1))1040 setFeature(FEATURE_RAOINT);1041 if (HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave)1042 setFeature(FEATURE_AVXVNNI);1043 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save)1044 setFeature(FEATURE_AVX512BF16);1045 if (HasLeaf7Subleaf1 && ((EAX >> 7) & 1))1046 setFeature(FEATURE_CMPCCXADD);1047 if (HasLeaf7Subleaf1 && ((EAX >> 21) & 1) && HasAMXSave)1048 setFeature(FEATURE_AMX_FP16);1049 if (HasLeaf7Subleaf1 && ((EAX >> 22) & 1))1050 setFeature(FEATURE_HRESET);1051 if (HasLeaf7Subleaf1 && ((EAX >> 23) & 1) && HasAVXSave)1052 setFeature(FEATURE_AVXIFMA);1053 if (HasLeaf7Subleaf1 && ((EAX >> 31) & 1))1054 setFeature(FEATURE_MOVRS);1055 1056 if (HasLeaf7Subleaf1 && ((EDX >> 4) & 1) && HasAVXSave)1057 setFeature(FEATURE_AVXVNNIINT8);1058 if (HasLeaf7Subleaf1 && ((EDX >> 5) & 1) && HasAVXSave)1059 setFeature(FEATURE_AVXNECONVERT);1060 if (HasLeaf7Subleaf1 && ((EDX >> 8) & 1) && HasAMXSave)1061 setFeature(FEATURE_AMX_COMPLEX);1062 if (HasLeaf7Subleaf1 && ((EDX >> 10) & 1) && HasAVXSave)1063 setFeature(FEATURE_AVXVNNIINT16);1064 if (HasLeaf7Subleaf1 && ((EDX >> 14) & 1))1065 setFeature(FEATURE_PREFETCHI);1066 if (HasLeaf7Subleaf1 && ((EDX >> 15) & 1))1067 setFeature(FEATURE_USERMSR);1068 if (HasLeaf7Subleaf1 && ((EDX >> 21) & 1))1069 setFeature(FEATURE_APXF);1070 1071 unsigned MaxLevel = 0;1072 getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX);1073 bool HasLeafD = MaxLevel >= 0xd &&1074 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);1075 if (HasLeafD && ((EAX >> 0) & 1) && HasAVXSave)1076 setFeature(FEATURE_XSAVEOPT);1077 if (HasLeafD && ((EAX >> 1) & 1) && HasAVXSave)1078 setFeature(FEATURE_XSAVEC);1079 if (HasLeafD && ((EAX >> 3) & 1) && HasAVXSave)1080 setFeature(FEATURE_XSAVES);1081 1082 bool HasLeaf1E = MaxLevel >= 0x1e &&1083 !getX86CpuIDAndInfoEx(0x1e, 0x1, &EAX, &EBX, &ECX, &EDX);1084 if (HasLeaf1E && (EAX & 0x10))1085 setFeature(FEATURE_AMX_FP8);1086 if (HasLeaf1E && (EAX & 0x40))1087 setFeature(FEATURE_AMX_TF32);1088 if (HasLeaf1E && (EAX & 0x80))1089 setFeature(FEATURE_AMX_AVX512);1090 if (HasLeaf1E && (EAX & 0x100))1091 setFeature(FEATURE_AMX_MOVRS);1092 1093 bool HasLeaf24 =1094 MaxLevel >= 0x24 && !getX86CpuIDAndInfo(0x24, &EAX, &EBX, &ECX, &EDX);1095 if (HasLeaf7Subleaf1 && ((EDX >> 19) & 1) && HasLeaf24) {1096 int AVX10Ver = EBX & 0xff;1097 if (AVX10Ver >= 1)1098 setFeature(FEATURE_AVX10_1);1099 if (AVX10Ver >= 2)1100 setFeature(FEATURE_AVX10_2);1101 }1102 1103 unsigned MaxExtLevel = 0;1104 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);1105 1106 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&1107 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);1108 if (HasExtLeaf1) {1109 if (ECX & 1)1110 setFeature(FEATURE_LAHF_LM);1111 if ((ECX >> 5) & 1)1112 setFeature(FEATURE_LZCNT);1113 if (((ECX >> 6) & 1))1114 setFeature(FEATURE_SSE4_A);1115 if (((ECX >> 8) & 1))1116 setFeature(FEATURE_PRFCHW);1117 if (((ECX >> 11) & 1))1118 setFeature(FEATURE_XOP);1119 if (((ECX >> 15) & 1))1120 setFeature(FEATURE_LWP);1121 if (((ECX >> 16) & 1))1122 setFeature(FEATURE_FMA4);1123 if (((ECX >> 21) & 1))1124 setFeature(FEATURE_TBM);1125 if (((ECX >> 29) & 1))1126 setFeature(FEATURE_MWAITX);1127 1128 if (((EDX >> 29) & 1))1129 setFeature(FEATURE_LM);1130 }1131 1132 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&1133 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);1134 if (HasExtLeaf8 && ((EBX >> 0) & 1))1135 setFeature(FEATURE_CLZERO);1136 if (HasExtLeaf8 && ((EBX >> 9) & 1))1137 setFeature(FEATURE_WBNOINVD);1138 1139 bool HasExtLeaf21 = MaxExtLevel >= 0x80000021 &&1140 !getX86CpuIDAndInfo(0x80000021, &EAX, &EBX, &ECX, &EDX);1141 // AMD cpuid bit for prefetchi is different from Intel1142 if (HasExtLeaf21 && ((EAX >> 20) & 1))1143 setFeature(FEATURE_PREFETCHI);1144 1145 bool HasLeaf14 = MaxLevel >= 0x14 &&1146 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);1147 if (HasLeaf14 && ((EBX >> 4) & 1))1148 setFeature(FEATURE_PTWRITE);1149 1150 bool HasLeaf19 =1151 MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX);1152 if (HasLeaf7 && HasLeaf19 && ((EBX >> 2) & 1))1153 setFeature(FEATURE_WIDEKL);1154 1155 if (hasFeature(FEATURE_LM) && hasFeature(FEATURE_SSE2)) {1156 setFeature(FEATURE_X86_64_BASELINE);1157 if (hasFeature(FEATURE_CMPXCHG16B) && hasFeature(FEATURE_POPCNT) &&1158 hasFeature(FEATURE_LAHF_LM) && hasFeature(FEATURE_SSE4_2)) {1159 setFeature(FEATURE_X86_64_V2);1160 if (hasFeature(FEATURE_AVX2) && hasFeature(FEATURE_BMI) &&1161 hasFeature(FEATURE_BMI2) && hasFeature(FEATURE_F16C) &&1162 hasFeature(FEATURE_FMA) && hasFeature(FEATURE_LZCNT) &&1163 hasFeature(FEATURE_MOVBE)) {1164 setFeature(FEATURE_X86_64_V3);1165 if (hasFeature(FEATURE_AVX512BW) && hasFeature(FEATURE_AVX512CD) &&1166 hasFeature(FEATURE_AVX512DQ) && hasFeature(FEATURE_AVX512VL))1167 setFeature(FEATURE_X86_64_V4);1168 }1169 }1170 }1171 1172#undef hasFeature1173#undef setFeature1174}1175 1176#ifndef _WIN321177__attribute__((visibility("hidden")))1178#endif1179int __cpu_indicator_init(void) CONSTRUCTOR_ATTRIBUTE;1180 1181#ifndef _WIN321182__attribute__((visibility("hidden")))1183#endif1184unsigned __cpu_features2[(CPU_FEATURE_MAX - 1) / 32];1185 1186// A constructor function that is sets __cpu_model and __cpu_features2 with1187// the right values. This needs to run only once. This constructor is1188// given the highest priority and it should run before constructors without1189// the priority set. However, it still runs after ifunc initializers and1190// needs to be called explicitly there.1191 1192int CONSTRUCTOR_ATTRIBUTE __cpu_indicator_init(void) {1193 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;1194 unsigned MaxLeaf = 5;1195 unsigned Vendor;1196 unsigned Model, Family;1197 unsigned Features[(CPU_FEATURE_MAX + 31) / 32] = {0};1198 _Static_assert(sizeof(Features) / sizeof(Features[0]) == 4, "");1199 _Static_assert(sizeof(__cpu_features2) / sizeof(__cpu_features2[0]) == 3, "");1200 1201 // This function needs to run just once.1202 if (__cpu_model.__cpu_vendor)1203 return 0;1204 1205 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) {1206 __cpu_model.__cpu_vendor = VENDOR_OTHER;1207 return -1;1208 }1209 1210 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);1211 detectX86FamilyModel(EAX, &Family, &Model);1212 1213 // Find available features.1214 getAvailableFeatures(ECX, EDX, MaxLeaf, &Features[0]);1215 1216 __cpu_model.__cpu_features[0] = Features[0];1217 __cpu_features2[0] = Features[1];1218 __cpu_features2[1] = Features[2];1219 __cpu_features2[2] = Features[3];1220 1221 if (Vendor == SIG_INTEL) {1222 // Get CPU type.1223 getIntelProcessorTypeAndSubtype(Family, Model, &Features[0], &__cpu_model);1224 __cpu_model.__cpu_vendor = VENDOR_INTEL;1225 } else if (Vendor == SIG_AMD) {1226 // Get CPU type.1227 getAMDProcessorTypeAndSubtype(Family, Model, &Features[0], &__cpu_model);1228 __cpu_model.__cpu_vendor = VENDOR_AMD;1229 } else1230 __cpu_model.__cpu_vendor = VENDOR_OTHER;1231 1232#if __STDC_HOSTED__1233 assert(__cpu_model.__cpu_vendor < VENDOR_MAX);1234 assert(__cpu_model.__cpu_type < CPU_TYPE_MAX);1235 assert(__cpu_model.__cpu_subtype < CPU_SUBTYPE_MAX);1236#endif // __STDC_HOSTED__1237 1238 return 0;1239}1240#endif // defined(__GNUC__) || defined(__clang__) || defined(_MSC_VER)1241