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1//===----------------------Hexagon builtin routine ------------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9 .macro FUNCTION_BEGIN name10 .text11 .p2align 512 .globl \name13 .type \name, @function14\name:15 .endm16 17 .macro FUNCTION_END name18 .size \name, . - \name19 .endm20 21 22FUNCTION_BEGIN __hexagon_divdi323 {24 p2 = tstbit(r1,#31)25 p3 = tstbit(r3,#31)26 }27 {28 r1:0 = abs(r1:0)29 r3:2 = abs(r3:2)30 }31 {32 r6 = cl0(r1:0) // count leading 0's of dividend (numerator)33 r7 = cl0(r3:2) // count leading 0's of divisor (denominator)34 r5:4 = r3:2 // divisor moved into working registers35 r3:2 = r1:0 // dividend is the initial remainder, r3:2 contains remainder36 }37 {38 p3 = xor(p2,p3)39 r10 = sub(r7,r6) // left shift count for bit & divisor40 r1:0 = #0 // initialize quotient to 041 r15:14 = #1 // initialize bit to 142 }43 {44 r11 = add(r10,#1) // loop count is 1 more than shift count45 r13:12 = lsl(r5:4,r10) // shift divisor msb into same bit position as dividend msb46 r15:14 = lsl(r15:14,r10) // shift the bit left by same amount as divisor47 }48 {49 p0 = cmp.gtu(r5:4,r3:2) // check if divisor > dividend50 loop0(1f,r11) // register loop51 }52 {53 if (p0) jump .hexagon_divdi3_return // if divisor > dividend, we're done, so return54 }55 .falign561:57 {58 p0 = cmp.gtu(r13:12,r3:2) // set predicate reg if shifted divisor > current remainder59 }60 {61 r7:6 = sub(r3:2, r13:12) // subtract shifted divisor from current remainder62 r9:8 = add(r1:0, r15:14) // save current quotient to temp (r9:8)63 }64 {65 r1:0 = vmux(p0, r1:0, r9:8) // choose either current quotient or new quotient (r9:8)66 r3:2 = vmux(p0, r3:2, r7:6) // choose either current remainder or new remainder (r7:6)67 }68 {69 r15:14 = lsr(r15:14, #1) // shift bit right by 1 for next iteration70 r13:12 = lsr(r13:12, #1) // shift "shifted divisor" right by 1 for next iteration71 }:endloop072 73.hexagon_divdi3_return:74 {75 r3:2 = neg(r1:0)76 }77 {78 r1:0 = vmux(p3,r3:2,r1:0)79 jumpr r3180 }81FUNCTION_END __hexagon_divdi382 83 .globl __qdsp_divdi384 .set __qdsp_divdi3, __hexagon_divdi385