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1//===----------------------Hexagon builtin routine ------------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9 10 .macro FUNCTION_BEGIN name11 .text12 .p2align 513 .globl \name14 .type \name, @function15\name:16 .endm17 18 .macro FUNCTION_END name19 .size \name, . - \name20 .endm21 22 23FUNCTION_BEGIN __hexagon_udivdi324 {25 r6 = cl0(r1:0) // count leading 0's of dividend (numerator)26 r7 = cl0(r3:2) // count leading 0's of divisor (denominator)27 r5:4 = r3:2 // divisor moved into working registers28 r3:2 = r1:0 // dividend is the initial remainder, r3:2 contains remainder29 }30 {31 r10 = sub(r7,r6) // left shift count for bit & divisor32 r1:0 = #0 // initialize quotient to 033 r15:14 = #1 // initialize bit to 134 }35 {36 r11 = add(r10,#1) // loop count is 1 more than shift count37 r13:12 = lsl(r5:4,r10) // shift divisor msb into same bit position as dividend msb38 r15:14 = lsl(r15:14,r10) // shift the bit left by same amount as divisor39 }40 {41 p0 = cmp.gtu(r5:4,r3:2) // check if divisor > dividend42 loop0(1f,r11) // register loop43 }44 {45 if (p0) jumpr r31 // if divisor > dividend, we're done, so return46 }47 .falign481:49 {50 p0 = cmp.gtu(r13:12,r3:2) // set predicate reg if shifted divisor > current remainder51 }52 {53 r7:6 = sub(r3:2, r13:12) // subtract shifted divisor from current remainder54 r9:8 = add(r1:0, r15:14) // save current quotient to temp (r9:8)55 }56 {57 r1:0 = vmux(p0, r1:0, r9:8) // choose either current quotient or new quotient (r9:8)58 r3:2 = vmux(p0, r3:2, r7:6) // choose either current remainder or new remainder (r7:6)59 }60 {61 r15:14 = lsr(r15:14, #1) // shift bit right by 1 for next iteration62 r13:12 = lsr(r13:12, #1) // shift "shifted divisor" right by 1 for next iteration63 }:endloop064 {65 jumpr r31 // return66 }67FUNCTION_END __hexagon_udivdi368 69 .globl __qdsp_udivdi370 .set __qdsp_udivdi3, __hexagon_udivdi371