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1//===-- restore.S - restore up to 12 callee-save registers ----------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// Multiple entry points depending on number of registers to restore10//11//===----------------------------------------------------------------------===//12 13// All of the entry points are in the same section since we rely on many of14// them falling through into each other and don't want the linker to15// accidentally split them up, garbage collect, or reorder them.16//17// For the conventional ABIs, entry points are grouped up into 2s for rv64 and18// 4s for rv32 since this is the minimum grouping which will maintain the19// required 16-byte stack alignment.20//21// For the ilp32e/lp64e abis, entry points are grouped into 1s, since this is22// the minimum grouping which will maintain the required 4-byte stack alignment.23 24 .text25 26#if __riscv_xlen == 3227 28#ifndef __riscv_abi_rve29 30 .globl __riscv_restore_1231 .type __riscv_restore_12,@function32__riscv_restore_12:33 lw s11, 12(sp)34 addi sp, sp, 1635 // fallthrough into __riscv_restore_11/10/9/836 37 .globl __riscv_restore_1138 .type __riscv_restore_11,@function39 .globl __riscv_restore_1040 .type __riscv_restore_10,@function41 .globl __riscv_restore_942 .type __riscv_restore_9,@function43 .globl __riscv_restore_844 .type __riscv_restore_8,@function45__riscv_restore_11:46__riscv_restore_10:47__riscv_restore_9:48__riscv_restore_8:49 lw s10, 0(sp)50 lw s9, 4(sp)51 lw s8, 8(sp)52 lw s7, 12(sp)53 addi sp, sp, 1654 // fallthrough into __riscv_restore_7/6/5/455 56 .globl __riscv_restore_757 .type __riscv_restore_7,@function58 .globl __riscv_restore_659 .type __riscv_restore_6,@function60 .globl __riscv_restore_561 .type __riscv_restore_5,@function62 .globl __riscv_restore_463 .type __riscv_restore_4,@function64__riscv_restore_7:65__riscv_restore_6:66__riscv_restore_5:67__riscv_restore_4:68 lw s6, 0(sp)69 lw s5, 4(sp)70 lw s4, 8(sp)71 lw s3, 12(sp)72 addi sp, sp, 1673 // fallthrough into __riscv_restore_3/2/1/074 75 .globl __riscv_restore_376 .type __riscv_restore_3,@function77 .globl __riscv_restore_278 .type __riscv_restore_2,@function79 .globl __riscv_restore_180 .type __riscv_restore_1,@function81 .globl __riscv_restore_082 .type __riscv_restore_0,@function83__riscv_restore_3:84__riscv_restore_2:85__riscv_restore_1:86__riscv_restore_0:87 lw s2, 0(sp)88 lw s1, 4(sp)89 lw s0, 8(sp)90 lw ra, 12(sp)91 addi sp, sp, 1692 ret93 94#else95 96 .globl __riscv_restore_297 .type __riscv_restore_2,@function98__riscv_restore_2:99 lw s1, 0(sp)100 addi sp, sp, 4101 // fallthrough into __riscv_restore_1/0102 103 .globl __riscv_restore_1104 .type __riscv_restore_1,@function105__riscv_restore_1:106 lw s0, 0(sp)107 addi sp, sp, 4108 // fallthrough into __riscv_restore_0109 110 .globl __riscv_restore_0111 .type __riscv_restore_0,@function112__riscv_restore_0:113 lw ra, 0(sp)114 addi sp, sp, 4115 ret116 117#endif118 119#elif __riscv_xlen == 64120 121#ifndef __riscv_abi_rve122 123 .globl __riscv_restore_12124 .type __riscv_restore_12,@function125__riscv_restore_12:126 ld s11, 8(sp)127 addi sp, sp, 16128 // fallthrough into __riscv_restore_11/10129 130 .globl __riscv_restore_11131 .type __riscv_restore_11,@function132 .globl __riscv_restore_10133 .type __riscv_restore_10,@function134__riscv_restore_11:135__riscv_restore_10:136 ld s10, 0(sp)137 ld s9, 8(sp)138 addi sp, sp, 16139 // fallthrough into __riscv_restore_9/8140 141 .globl __riscv_restore_9142 .type __riscv_restore_9,@function143 .globl __riscv_restore_8144 .type __riscv_restore_8,@function145__riscv_restore_9:146__riscv_restore_8:147 ld s8, 0(sp)148 ld s7, 8(sp)149 addi sp, sp, 16150 // fallthrough into __riscv_restore_7/6151 152 .globl __riscv_restore_7153 .type __riscv_restore_7,@function154 .globl __riscv_restore_6155 .type __riscv_restore_6,@function156__riscv_restore_7:157__riscv_restore_6:158 ld s6, 0(sp)159 ld s5, 8(sp)160 addi sp, sp, 16161 // fallthrough into __riscv_restore_5/4162 163 .globl __riscv_restore_5164 .type __riscv_restore_5,@function165 .globl __riscv_restore_4166 .type __riscv_restore_4,@function167__riscv_restore_5:168__riscv_restore_4:169 ld s4, 0(sp)170 ld s3, 8(sp)171 addi sp, sp, 16172 // fallthrough into __riscv_restore_3/2173 174 .globl __riscv_restore_3175 .type __riscv_restore_3,@function176 .globl __riscv_restore_2177 .type __riscv_restore_2,@function178__riscv_restore_3:179__riscv_restore_2:180 ld s2, 0(sp)181 ld s1, 8(sp)182 addi sp, sp, 16183 // fallthrough into __riscv_restore_1/0184 185 .globl __riscv_restore_1186 .type __riscv_restore_1,@function187 .globl __riscv_restore_0188 .type __riscv_restore_0,@function189__riscv_restore_1:190__riscv_restore_0:191 ld s0, 0(sp)192 ld ra, 8(sp)193 addi sp, sp, 16194 ret195 196#else197 198 .globl __riscv_restore_2199 .type __riscv_restore_2,@function200__riscv_restore_2:201 ld s1, 0(sp)202 addi sp, sp, 8203 // fallthrough into __riscv_restore_1/0204 205 .globl __riscv_restore_1206 .type __riscv_restore_1,@function207__riscv_restore_1:208 ld s0, 0(sp)209 addi sp, sp, 8210 // fallthrough into __riscv_restore_0211 212 .globl __riscv_restore_0213 .type __riscv_restore_0,@function214__riscv_restore_0:215 ld ra, 0(sp)216 addi sp, sp, 8217 ret218 219#endif220 221#else222# error "xlen must be 32 or 64 for save-restore implementation223#endif224