218 lines · plain
1! RUN: bbc -emit-hlfir -o - %s | FileCheck %s2 3! CHECK-LABEL: c.func @_QQmain4program p5 use ieee_arithmetic, only: ieee_real6 7 ! CHECK: %[[V_0:[0-9]+]] = fir.alloca i16 {bindc_name = "j2", uniq_name = "_QFEj2"}8 ! CHECK: %[[V_1:[0-9]+]]:2 = hlfir.declare %[[V_0]] {uniq_name = "_QFEj2"} : (!fir.ref<i16>) -> (!fir.ref<i16>, !fir.ref<i16>)9 ! CHECK: %[[V_2:[0-9]+]] = fir.alloca i64 {bindc_name = "j8", uniq_name = "_QFEj8"}10 ! CHECK: %[[V_3:[0-9]+]]:2 = hlfir.declare %[[V_2]] {uniq_name = "_QFEj8"} : (!fir.ref<i64>) -> (!fir.ref<i64>, !fir.ref<i64>)11 ! CHECK: %[[V_4:[0-9]+]] = fir.alloca f16 {bindc_name = "x2", uniq_name = "_QFEx2"}12 ! CHECK: %[[V_5:[0-9]+]]:2 = hlfir.declare %[[V_4]] {uniq_name = "_QFEx2"} : (!fir.ref<f16>) -> (!fir.ref<f16>, !fir.ref<f16>)13 ! CHECK: %[[V_6:[0-9]+]] = fir.alloca f32 {bindc_name = "x4", uniq_name = "_QFEx4"}14 ! CHECK: %[[V_7:[0-9]+]]:2 = hlfir.declare %[[V_6]] {uniq_name = "_QFEx4"} : (!fir.ref<f32>) -> (!fir.ref<f32>, !fir.ref<f32>)15 ! CHECK: %[[V_8:[0-9]+]] = fir.alloca f64 {bindc_name = "x8", uniq_name = "_QFEx8"}16 ! CHECK: %[[V_9:[0-9]+]]:2 = hlfir.declare %[[V_8]] {uniq_name = "_QFEx8"} : (!fir.ref<f64>) -> (!fir.ref<f64>, !fir.ref<f64>)17 integer(2) :: j218 integer(8) :: j819 real(2) :: x220 real(4) :: x421 real(8) :: x822 23 ! CHECK: hlfir.assign %c-32768{{.*}} to %[[V_1]]#0 : i16, !fir.ref<i16>24 j2 = -huge(j2) - 125 26 ! CHECK: %[[V_10:[0-9]+]] = fir.load %[[V_1]]#0 : !fir.ref<i16>27 ! CHECK: %[[V_11:[0-9]+]] = fir.convert %[[V_10]] : (i16) -> f3228 ! CHECK: hlfir.assign %[[V_11]] to %[[V_7]]#0 : f32, !fir.ref<f32>29 x4 = ieee_real(j2,4) ! exact30! print*, j2, ' -> ', x431 32 ! CHECK: hlfir.assign %c33{{.*}} to %[[V_3]]#0 : i64, !fir.ref<i64>33 j8 = 3334 35 ! CHECK: %[[V_12:[0-9]+]] = fir.load %[[V_3]]#0 : !fir.ref<i64>36 ! CHECK: %[[V_13:[0-9]+]] = fir.convert %[[V_12]] : (i64) -> f3237 ! CHECK: %[[V_14:[0-9]+]] = fir.convert %[[V_13]] : (f32) -> i6438 ! CHECK: %[[V_15:[0-9]+]] = arith.cmpi eq, %[[V_12]], %[[V_14]] : i6439 ! CHECK: %[[V_16:[0-9]+]] = fir.if %[[V_15]] -> (f32) {40 ! CHECK: fir.result %[[V_13]] : f3241 ! CHECK: } else {42 ! CHECK: %[[V_27:[0-9]+]] = fir.call @llvm.get.rounding() fastmath<contract> : () -> i3243 ! CHECK-DAG: %[[V_28:[0-9]+]] = arith.cmpi slt, %[[V_12]], %c0{{.*}} : i6444 ! CHECK-DAG: %[[V_29:[0-9]+]] = arith.cmpi sgt, %[[V_12]], %c0{{.*}} : i6445 ! CHECK-DAG: %[[V_30:[0-9]+]] = arith.bitcast %[[V_13]] : f32 to i3246 ! CHECK-DAG: %[[V_31:[0-9]+]] = arith.andi %[[V_30]], %c1{{.*}} : i3247 ! CHECK-DAG: %[[V_32:[0-9]+]] = fir.convert %[[V_31]] : (i32) -> i148 ! CHECK-DAG: %[[V_33:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c5{{.*}} : i3249 ! CHECK-DAG: %[[V_34:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c1{{.*}} : i3250 ! CHECK-DAG: %[[V_35:[0-9]+]] = arith.ori %[[V_34]], %[[V_33]] : i151 ! CHECK-DAG: %[[V_36:[0-9]+]] = arith.andi %[[V_35]], %[[V_32]] : i152 ! CHECK-DAG: %[[V_37:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c0{{.*}} : i3253 ! CHECK-DAG: %[[V_38:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c4{{.*}} : i3254 ! CHECK-DAG: %[[V_39:[0-9]+]] = arith.cmpi slt, %[[V_12]], %[[V_14]] : i6455 ! CHECK-DAG: %[[V_40:[0-9]+]] = arith.addi %[[V_30]], %c1{{.*}} : i3256 ! CHECK-DAG: %[[V_41:[0-9]+]] = arith.subi %[[V_30]], %c1{{.*}} : i3257 ! CHECK: %[[V_42:[0-9]+]] = fir.if %[[V_39]] -> (f32) {58 ! CHECK-DAG: %[[V_44:[0-9]+]] = arith.andi %[[V_37]], %[[V_29]] : i159 ! CHECK-DAG: %[[V_45:[0-9]+]] = arith.andi %[[V_38]], %[[V_28]] : i160 ! CHECK-DAG: %[[V_46:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c3{{.*}} : i3261 ! CHECK-DAG: %[[V_47:[0-9]+]] = arith.ori %[[V_36]], %[[V_44]] : i162 ! CHECK-DAG: %[[V_48:[0-9]+]] = arith.ori %[[V_47]], %[[V_45]] : i163 ! CHECK-DAG: %[[V_49:[0-9]+]] = arith.ori %[[V_48]], %[[V_46]] : i164 ! CHECK: %[[V_50:[0-9]+]] = fir.if %[[V_49]] -> (f32) {65 ! CHECK: %[[V_51:[0-9]+]] = arith.select %[[V_28]], %[[V_40]], %[[V_41]] : i3266 ! CHECK: %[[V_52:[0-9]+]] = arith.bitcast %[[V_51]] : i32 to f3267 ! CHECK: fir.result %[[V_52]] : f3268 ! CHECK: } else {69 ! CHECK: fir.result %[[V_13]] : f3270 ! CHECK: }71 ! CHECK: fir.result %[[V_50]] : f3272 ! CHECK: } else {73 ! CHECK-DAG: %[[V_44:[0-9]+]] = arith.andi %[[V_37]], %[[V_28]] : i174 ! CHECK-DAG: %[[V_45:[0-9]+]] = arith.andi %[[V_38]], %[[V_29]] : i175 ! CHECK-DAG: %[[V_46:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c2{{.*}} : i3276 ! CHECK-DAG: %[[V_47:[0-9]+]] = arith.ori %[[V_36]], %[[V_44]] : i177 ! CHECK-DAG: %[[V_48:[0-9]+]] = arith.ori %[[V_47]], %[[V_45]] : i178 ! CHECK-DAG: %[[V_49:[0-9]+]] = arith.ori %[[V_48]], %[[V_46]] : i179 ! CHECK: %[[V_50:[0-9]+]] = fir.if %[[V_49]] -> (f32) {80 ! CHECK: %[[V_51:[0-9]+]] = arith.select %[[V_29]], %[[V_40]], %[[V_41]] : i3281 ! CHECK: %[[V_52:[0-9]+]] = arith.bitcast %[[V_51]] : i32 to f3282 ! CHECK: fir.result %[[V_52]] : f3283 ! CHECK: } else {84 ! CHECK: fir.result %[[V_13]] : f3285 ! CHECK: }86 ! CHECK: fir.result %[[V_50]] : f3287 ! CHECK: }88 ! CHECK: %[[V_43:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_42]]) <{bit = 516 : i32}> : (f32) -> i189 ! CHECK: fir.if %[[V_43]] {90 ! CHECK: %[[V_44:[0-9]+]] = fir.call @_FortranAMapException(%c40{{.*}}) fastmath<contract> : (i32) -> i3291 ! CHECK: fir.call {{.*}}feraiseexcept(%[[V_44]]) fastmath<contract> : (i32)92 ! CHECK: } else {93 ! CHECK: %[[V_44:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_42]]) <{bit = 240 : i32}> : (f32) -> i194 ! CHECK: fir.if %[[V_44]] {95 ! CHECK: %[[V_45:[0-9]+]] = fir.call @_FortranAMapException(%c48{{.*}}) fastmath<contract> : (i32) -> i3296 ! CHECK: fir.call {{.*}}feraiseexcept(%[[V_45]]) fastmath<contract> : (i32)97 ! CHECK: } else {98 ! CHECK: %[[V_45:[0-9]+]] = fir.call @_FortranAMapException(%c32{{.*}}) fastmath<contract> : (i32) -> i3299 ! CHECK: fir.call {{.*}}feraiseexcept(%[[V_45]]) fastmath<contract> : (i32)100 ! CHECK: }101 ! CHECK: }102 ! CHECK: fir.result %[[V_42]] : f32103 ! CHECK: }104 ! CHECK: hlfir.assign %[[V_16]] to %[[V_7]]#0 : f32, !fir.ref<f32>105 x4 = ieee_real(j8,4)106! print*, j8, ' -> ', x4107 108 ! CHECK: hlfir.assign %cst{{[_0-9]*}} to %[[V_5]]#0 : f16, !fir.ref<f16>109 x2 = 3.33110 111 ! CHECK: %[[V_17:[0-9]+]] = fir.load %[[V_5]]#0 : !fir.ref<f16>112 ! CHECK: %[[V_18:[0-9]+]] = fir.convert %[[V_17]] : (f16) -> f32113 ! CHECK: %[[V_19:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_18]]) <{bit = 1 : i32}> : (f32) -> i1114 ! CHECK: %[[V_20:[0-9]+]] = fir.if %[[V_19]] -> (f32) {115 ! CHECK: %[[V_27:[0-9]+]] = fir.call @_FortranAMapException(%c1{{.*}}) fastmath<contract> : (i32) -> i32116 ! CHECK: fir.call {{.*}}feraiseexcept(%[[V_27]]) fastmath<contract> : (i32)117 ! CHECK: %[[V_29:[0-9]+]] = fir.address_of(@_FortranAIeeeValueTable_4) : !fir.ref<!fir.array<12xi32>>118 ! CHECK: %[[V_30:[0-9]+]] = fir.coordinate_of %[[V_29]], %c2{{.*}} : (!fir.ref<!fir.array<12xi32>>, i8) -> !fir.ref<i32>119 ! CHECK: %[[V_31:[0-9]+]] = fir.load %[[V_30]] : !fir.ref<i32>120 ! CHECK: %[[V_32:[0-9]+]] = arith.bitcast %[[V_31]] : i32 to f32121 ! CHECK: fir.result %[[V_32]] : f32122 ! CHECK: } else {123 ! CHECK: fir.result %[[V_18]] : f32124 ! CHECK: }125 ! CHECK: %[[V_21:[0-9]+]] = fir.convert %[[V_20]] : (f32) -> f16126 ! CHECK: hlfir.assign %[[V_21]] to %[[V_5]]#0 : f16, !fir.ref<f16>127 x2 = ieee_real(x2,4) ! exact128! print*, x2, ' -> ', x2129 130 ! CHECK: hlfir.assign %cst{{[_0-9]*}} to %[[V_9]]#0 : f64, !fir.ref<f64>131 x8 = -0.132 133 ! CHECK: %[[V_22:[0-9]+]] = fir.load %[[V_9]]#0 : !fir.ref<f64>134 ! CHECK: %[[V_23:[0-9]+]] = fir.convert %[[V_22]] : (f64) -> f32135 ! CHECK: %[[V_24:[0-9]+]] = fir.convert %[[V_23]] : (f32) -> f64136 ! CHECK: %[[V_25:[0-9]+]] = arith.cmpf ueq, %[[V_22]], %[[V_24]] fastmath<contract> : f64137 ! CHECK: %[[V_26:[0-9]+]] = fir.if %[[V_25]] -> (f32) {138 ! CHECK: %[[V_27:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_23]]) <{bit = 1 : i32}> : (f32) -> i1139 ! CHECK: %[[V_28:[0-9]+]] = fir.if %[[V_27]] -> (f32) {140 ! CHECK: %[[V_29:[0-9]+]] = fir.call @_FortranAMapException(%c1{{.*}}) fastmath<contract> : (i32) -> i32141 ! CHECK: fir.call {{.*}}feraiseexcept(%[[V_29]]) fastmath<contract> : (i32)142 ! CHECK: %[[V_31:[0-9]+]] = fir.address_of(@_FortranAIeeeValueTable_4) : !fir.ref<!fir.array<12xi32>>143 ! CHECK: %[[V_32:[0-9]+]] = fir.coordinate_of %[[V_31]], %c2{{.*}} : (!fir.ref<!fir.array<12xi32>>, i8) -> !fir.ref<i32>144 ! CHECK: %[[V_33:[0-9]+]] = fir.load %[[V_32]] : !fir.ref<i32>145 ! CHECK: %[[V_34:[0-9]+]] = arith.bitcast %[[V_33]] : i32 to f32146 ! CHECK: fir.result %[[V_34]] : f32147 ! CHECK: } else {148 ! CHECK: fir.result %[[V_23]] : f32149 ! CHECK: }150 ! CHECK: fir.result %[[V_28]] : f32151 ! CHECK: } else {152 ! CHECK-DAG: %[[V_27:[0-9]+]] = fir.call @llvm.get.rounding() fastmath<contract> : () -> i32153 ! CHECK-DAG: %[[V_28:[0-9]+]] = arith.cmpf olt, %[[V_22]], %cst{{[_0-9]*}} fastmath<contract> : f64154 ! CHECK-DAG: %[[V_29:[0-9]+]] = arith.cmpf ogt, %[[V_22]], %cst{{[_0-9]*}} fastmath<contract> : f64155 ! CHECK-DAG: %[[V_30:[0-9]+]] = arith.bitcast %[[V_23]] : f32 to i32156 ! CHECK-DAG: %[[V_31:[0-9]+]] = arith.andi %[[V_30]], %c1{{.*}} : i32157 ! CHECK-DAG: %[[V_32:[0-9]+]] = fir.convert %[[V_31]] : (i32) -> i1158 ! CHECK-DAG: %[[V_33:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c5{{.*}} : i32159 ! CHECK-DAG: %[[V_34:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c1{{.*}} : i32160 ! CHECK-DAG: %[[V_35:[0-9]+]] = arith.ori %[[V_34]], %[[V_33]] : i1161 ! CHECK-DAG: %[[V_36:[0-9]+]] = arith.andi %[[V_35]], %[[V_32]] : i1162 ! CHECK-DAG: %[[V_37:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c0{{.*}} : i32163 ! CHECK-DAG: %[[V_38:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c4{{.*}} : i32164 ! CHECK-DAG: %[[V_39:[0-9]+]] = arith.cmpf olt, %[[V_22]], %[[V_24]] fastmath<contract> : f64165 ! CHECK-DAG: %[[V_40:[0-9]+]] = arith.addi %[[V_30]], %c1{{.*}} : i32166 ! CHECK-DAG: %[[V_41:[0-9]+]] = arith.subi %[[V_30]], %c1{{.*}} : i32167 ! CHECK: %[[V_42:[0-9]+]] = fir.if %[[V_39]] -> (f32) {168 ! CHECK-DAG: %[[V_44:[0-9]+]] = arith.andi %[[V_37]], %[[V_29]] : i1169 ! CHECK-DAG: %[[V_45:[0-9]+]] = arith.andi %[[V_38]], %[[V_28]] : i1170 ! CHECK-DAG: %[[V_46:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c3{{.*}} : i32171 ! CHECK-DAG: %[[V_47:[0-9]+]] = arith.ori %[[V_36]], %[[V_44]] : i1172 ! CHECK-DAG: %[[V_48:[0-9]+]] = arith.ori %[[V_47]], %[[V_45]] : i1173 ! CHECK-DAG: %[[V_49:[0-9]+]] = arith.ori %[[V_48]], %[[V_46]] : i1174 ! CHECK: %[[V_50:[0-9]+]] = fir.if %[[V_49]] -> (f32) {175 ! CHECK: %[[V_51:[0-9]+]] = arith.select %[[V_28]], %[[V_40]], %[[V_41]] : i32176 ! CHECK: %[[V_52:[0-9]+]] = arith.bitcast %[[V_51]] : i32 to f32177 ! CHECK: fir.result %[[V_52]] : f32178 ! CHECK: } else {179 ! CHECK: fir.result %[[V_23]] : f32180 ! CHECK: }181 ! CHECK: fir.result %[[V_50]] : f32182 ! CHECK: } else {183 ! CHECK-DAG: %[[V_44:[0-9]+]] = arith.andi %[[V_37]], %[[V_28]] : i1184 ! CHECK-DAG: %[[V_45:[0-9]+]] = arith.andi %[[V_38]], %[[V_29]] : i1185 ! CHECK-DAG: %[[V_46:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c2{{.*}} : i32186 ! CHECK-DAG: %[[V_47:[0-9]+]] = arith.ori %[[V_36]], %[[V_44]] : i1187 ! CHECK-DAG: %[[V_48:[0-9]+]] = arith.ori %[[V_47]], %[[V_45]] : i1188 ! CHECK-DAG: %[[V_49:[0-9]+]] = arith.ori %[[V_48]], %[[V_46]] : i1189 ! CHECK: %[[V_50:[0-9]+]] = fir.if %[[V_49]] -> (f32) {190 ! CHECK: %[[V_51:[0-9]+]] = arith.select %[[V_29]], %[[V_40]], %[[V_41]] : i32191 ! CHECK: %[[V_52:[0-9]+]] = arith.bitcast %[[V_51]] : i32 to f32192 ! CHECK: fir.result %[[V_52]] : f32193 ! CHECK: } else {194 ! CHECK: fir.result %[[V_23]] : f32195 ! CHECK: }196 ! CHECK: fir.result %[[V_50]] : f32197 ! CHECK: }198 ! CHECK: %[[V_43:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_42]]) <{bit = 516 : i32}> : (f32) -> i1199 ! CHECK: fir.if %[[V_43]] {200 ! CHECK: %[[V_44:[0-9]+]] = fir.call @_FortranAMapException(%c40{{.*}}) fastmath<contract> : (i32) -> i32201 ! CHECK: fir.call {{.*}}feraiseexcept(%[[V_44]]) fastmath<contract> : (i32)202 ! CHECK: } else {203 ! CHECK: %[[V_44:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_42]]) <{bit = 240 : i32}> : (f32) -> i1204 ! CHECK: fir.if %[[V_44]] {205 ! CHECK: %[[V_45:[0-9]+]] = fir.call @_FortranAMapException(%c48{{.*}}) fastmath<contract> : (i32) -> i32206 ! CHECK: fir.call {{.*}}feraiseexcept(%[[V_45]]) fastmath<contract> : (i32)207 ! CHECK: } else {208 ! CHECK: %[[V_45:[0-9]+]] = fir.call @_FortranAMapException(%c32{{.*}}) fastmath<contract> : (i32) -> i32209 ! CHECK: fir.call {{.*}}feraiseexcept(%[[V_45]]) fastmath<contract> : (i32)210 ! CHECK: }211 ! CHECK: }212 ! CHECK: fir.result %[[V_42]] : f32213 ! CHECK: }214 ! CHECK: hlfir.assign %[[V_26]] to %[[V_7]]#0 : f32, !fir.ref<f32>215 x4 = ieee_real(x8,4)216! print*, x8, ' -> ', x4217end218