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1! RUN: %flang_fc1 -flang-experimental-hlfir -emit-llvm %s -fno-ppc-native-vector-element-order -triple ppc64le-unknown-linux -o - | FileCheck --check-prefixes="LLVMIR" %s2! REQUIRES: target=powerpc{{.*}}3 4!-------------------5! vec_ld6!-------------------7 8! CHECK-LABEL: @vec_ld_testi89subroutine vec_ld_testi8(arg1, arg2, res)10 integer(1) :: arg111 vector(integer(1)) :: arg2, res12 res = vec_ld(arg1, arg2)13 14! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 115! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]]16! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr %[[addr]])17! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[ld]] to <16 x i8>18! LLVMIR: %[[shflv:.*]] = shufflevector <16 x i8> %[[bc]], <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>19! LLVMIR: store <16 x i8> %[[shflv]], ptr %2, align 1620end subroutine vec_ld_testi821 22! CHECK-LABEL: @vec_ld_testi1623subroutine vec_ld_testi16(arg1, arg2, res)24 integer(2) :: arg125 vector(integer(2)) :: arg2, res26 res = vec_ld(arg1, arg2)27 28! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 229! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]]30! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr %[[addr]])31! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[ld]] to <8 x i16>32! LLVMIR: %[[shflv:.*]] = shufflevector <8 x i16> %[[bc]], <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>33! LLVMIR: store <8 x i16> %[[shflv]], ptr %2, align 1634end subroutine vec_ld_testi1635 36! CHECK-LABEL: @vec_ld_testi3237subroutine vec_ld_testi32(arg1, arg2, res)38 integer(4) :: arg139 vector(integer(4)) :: arg2, res40 res = vec_ld(arg1, arg2)41 42! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 443! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]]44! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr %[[addr]])45! LLVMIR: %[[shflv:.*]] = shufflevector <4 x i32> %[[ld]], <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>46! LLVMIR: store <4 x i32> %[[shflv]], ptr %2, align 1647end subroutine vec_ld_testi3248 49! CHECK-LABEL: @vec_ld_testf3250subroutine vec_ld_testf32(arg1, arg2, res)51 integer(8) :: arg152 vector(real(4)) :: arg2, res53 res = vec_ld(arg1, arg2)54 55! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 856! LLVMIR: %[[i4:.*]] = trunc i64 %[[arg1]] to i3257! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[i4]]58! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr %[[addr]])59! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[ld]] to <4 x float>60! LLVMIR: %[[shflv:.*]] = shufflevector <4 x float> %[[bc]], <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>61! LLVMIR: store <4 x float> %[[shflv]], ptr %2, align 1662end subroutine vec_ld_testf3263 64! CHECK-LABEL: @vec_ld_testu3265subroutine vec_ld_testu32(arg1, arg2, res)66 integer(1) :: arg167 vector(unsigned(4)) :: arg2, res68 res = vec_ld(arg1, arg2)69 70! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 171! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]]72! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr %[[addr]])73! LLVMIR: %[[shflv:.*]] = shufflevector <4 x i32> %[[ld]], <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>74! LLVMIR: store <4 x i32> %[[shflv]], ptr %2, align 1675end subroutine vec_ld_testu3276 77! CHECK-LABEL: @vec_ld_testi32a78subroutine vec_ld_testi32a(arg1, arg2, res)79 integer(4) :: arg180 integer(4) :: arg2(10)81 vector(integer(4)) :: res82 res = vec_ld(arg1, arg2)83 84! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 485! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]]86! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr %[[addr]])87! LLVMIR: %[[shflv:.*]] = shufflevector <4 x i32> %[[ld]], <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>88! LLVMIR: store <4 x i32> %[[shflv]], ptr %2, align 1689end subroutine vec_ld_testi32a90 91! CHECK-LABEL: @vec_ld_testf32av92subroutine vec_ld_testf32av(arg1, arg2, res)93 integer(8) :: arg194 vector(real(4)) :: arg2(2, 4, 8)95 vector(real(4)) :: res96 res = vec_ld(arg1, arg2)97 98! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 899! LLVMIR: %[[i4:.*]] = trunc i64 %[[arg1]] to i32100! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[i4]]101! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr %[[addr]])102! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[ld]] to <4 x float>103! LLVMIR: %[[shflv:.*]] = shufflevector <4 x float> %[[bc]], <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>104! LLVMIR: store <4 x float> %[[shflv]], ptr %2, align 16105end subroutine vec_ld_testf32av106 107! CHECK-LABEL: @vec_ld_testi32s108subroutine vec_ld_testi32s(arg1, arg2, res)109 integer(4) :: arg1110 real(4) :: arg2111 vector(real(4)) :: res112 res = vec_ld(arg1, arg2)113 114! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4115! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]]116! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr %[[addr]])117! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[ld]] to <4 x float>118! LLVMIR: %[[shflv:.*]] = shufflevector <4 x float> %[[bc]], <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>119! LLVMIR: store <4 x float> %[[shflv]], ptr %2, align 16120end subroutine vec_ld_testi32s121 122!-------------------123! vec_lde124!-------------------125 126! CHECK-LABEL: @vec_lde_testi8s127subroutine vec_lde_testi8s(arg1, arg2, res)128 integer(1) :: arg1129 integer(1) :: arg2130 vector(integer(1)) :: res131 res = vec_lde(arg1, arg2)132 133! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 1134! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]]135! LLVMIR: %[[ld:.*]] = call <16 x i8> @llvm.ppc.altivec.lvebx(ptr %[[addr]])136! LLVMIR: %[[shflv:.*]] = shufflevector <16 x i8> %[[ld]], <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>137! LLVMIR: store <16 x i8> %[[shflv]], ptr %2, align 16138end subroutine vec_lde_testi8s139 140! CHECK-LABEL: @vec_lde_testi16a141subroutine vec_lde_testi16a(arg1, arg2, res)142 integer(2) :: arg1143 integer(2) :: arg2(2, 11, 7)144 vector(integer(2)) :: res145 res = vec_lde(arg1, arg2)146 147! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2148! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]]149! LLVMIR: %[[ld:.*]] = call <8 x i16> @llvm.ppc.altivec.lvehx(ptr %[[addr]])150! LLVMIR: %[[shflv:.*]] = shufflevector <8 x i16> %[[ld]], <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>151! LLVMIR: store <8 x i16> %[[shflv]], ptr %2, align 16152end subroutine vec_lde_testi16a153 154! CHECK-LABEL: @vec_lde_testi32a155subroutine vec_lde_testi32a(arg1, arg2, res)156 integer(4) :: arg1157 integer(4) :: arg2(5)158 vector(integer(4)) :: res159 res = vec_lde(arg1, arg2)160 161! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4162! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]]163! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.altivec.lvewx(ptr %[[addr]])164! LLVMIR: %[[shflv:.*]] = shufflevector <4 x i32> %[[ld]], <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>165! LLVMIR: store <4 x i32> %[[shflv]], ptr %2, align 16166end subroutine vec_lde_testi32a167 168! CHECK-LABEL: @vec_lde_testf32a169subroutine vec_lde_testf32a(arg1, arg2, res)170 integer(8) :: arg1171 real(4) :: arg2(11)172 vector(real(4)) :: res173 res = vec_lde(arg1, arg2)174 175! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8176! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]]177! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.altivec.lvewx(ptr %[[addr]])178! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[ld]] to <4 x float>179! LLVMIR: %[[shflv:.*]] = shufflevector <4 x float> %[[bc]], <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>180! LLVMIR: store <4 x float> %[[shflv]], ptr %2, align 16181end subroutine vec_lde_testf32a182 183!-------------------184! vec_lvsl185!-------------------186 187! CHECK-LABEL: @vec_lvsl_testi8s188subroutine vec_lvsl_testi8s(arg1, arg2, res)189 integer(1) :: arg1190 integer(1) :: arg2191 vector(unsigned(1)) :: res192 res = vec_lvsl(arg1, arg2)193 194! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 1195! LLVMIR: %[[iext:.*]] = sext i8 %[[arg1]] to i64196! LLVMIR: %[[lshft:.*]] = shl i64 %[[iext]], 56197! LLVMIR: %[[rshft:.*]] = ashr i64 %[[lshft]], 56198! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[rshft]]199! LLVMIR: %[[ld:.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr %[[addr]])200! LLVMIR: store <16 x i8> %[[ld]], ptr %2, align 16201end subroutine vec_lvsl_testi8s202 203! CHECK-LABEL: @vec_lvsl_testi16a204subroutine vec_lvsl_testi16a(arg1, arg2, res)205 integer(2) :: arg1206 integer(2) :: arg2(4)207 vector(unsigned(1)) :: res208 res = vec_lvsl(arg1, arg2)209 210! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2211! LLVMIR: %[[iext:.*]] = sext i16 %[[arg1]] to i64212! LLVMIR: %[[lshft:.*]] = shl i64 %[[iext]], 56213! LLVMIR: %[[rshft:.*]] = ashr i64 %[[lshft]], 56214! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[rshft]]215! LLVMIR: %[[ld:.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr %[[addr]])216! LLVMIR: store <16 x i8> %[[ld]], ptr %2, align 16217end subroutine vec_lvsl_testi16a218 219! CHECK-LABEL: @vec_lvsl_testi32a220subroutine vec_lvsl_testi32a(arg1, arg2, res)221 integer(4) :: arg1222 integer(4) :: arg2(11, 3, 4)223 vector(unsigned(1)) :: res224 res = vec_lvsl(arg1, arg2)225 226! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4227! LLVMIR: %[[iext:.*]] = sext i32 %[[arg1]] to i64228! LLVMIR: %[[lshft:.*]] = shl i64 %[[iext]], 56229! LLVMIR: %[[rshft:.*]] = ashr i64 %[[lshft]], 56230! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[rshft]]231! LLVMIR: %[[ld:.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr %[[addr]])232! LLVMIR: store <16 x i8> %[[ld]], ptr %2, align 16233end subroutine vec_lvsl_testi32a234 235! CHECK-LABEL: @vec_lvsl_testf32a236subroutine vec_lvsl_testf32a(arg1, arg2, res)237 integer(8) :: arg1238 real(4) :: arg2(51)239 vector(unsigned(1)) :: res240 res = vec_lvsl(arg1, arg2)241 242! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8243! LLVMIR: %[[lshft:.*]] = shl i64 %[[arg1]], 56244! LLVMIR: %[[rshft:.*]] = ashr i64 %[[lshft]], 56245! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[rshft]]246! LLVMIR: %[[ld:.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr %[[addr]])247! LLVMIR: store <16 x i8> %[[ld]], ptr %2, align 16248end subroutine vec_lvsl_testf32a249 250!-------------------251! vec_lvsr252!-------------------253 254! CHECK-LABEL: @vec_lvsr_testi8s255subroutine vec_lvsr_testi8s(arg1, arg2, res)256 integer(1) :: arg1257 integer(1) :: arg2258 vector(unsigned(1)) :: res259 res = vec_lvsr(arg1, arg2)260 261! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 1262! LLVMIR: %[[iext:.*]] = sext i8 %[[arg1]] to i64263! LLVMIR: %[[lshft:.*]] = shl i64 %[[iext]], 56264! LLVMIR: %[[rshft:.*]] = ashr i64 %[[lshft]], 56265! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[rshft]]266! LLVMIR: %[[ld:.*]] = call <16 x i8> @llvm.ppc.altivec.lvsr(ptr %[[addr]])267! LLVMIR: store <16 x i8> %[[ld]], ptr %2, align 16268end subroutine vec_lvsr_testi8s269 270! CHECK-LABEL: @vec_lvsr_testi16a271subroutine vec_lvsr_testi16a(arg1, arg2, res)272 integer(2) :: arg1273 integer(2) :: arg2(41)274 vector(unsigned(1)) :: res275 res = vec_lvsr(arg1, arg2)276 277! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2278! LLVMIR: %[[iext:.*]] = sext i16 %[[arg1]] to i64279! LLVMIR: %[[lshft:.*]] = shl i64 %[[iext]], 56280! LLVMIR: %[[rshft:.*]] = ashr i64 %[[lshft]], 56281! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[rshft]]282! LLVMIR: %[[ld:.*]] = call <16 x i8> @llvm.ppc.altivec.lvsr(ptr %[[addr]])283! LLVMIR: store <16 x i8> %[[ld]], ptr %2, align 16284end subroutine vec_lvsr_testi16a285 286! CHECK-LABEL: @vec_lvsr_testi32a287subroutine vec_lvsr_testi32a(arg1, arg2, res)288 integer(4) :: arg1289 integer(4) :: arg2(23, 31, 47)290 vector(unsigned(1)) :: res291 res = vec_lvsr(arg1, arg2)292 293! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4294! LLVMIR: %[[iext:.*]] = sext i32 %[[arg1]] to i64295! LLVMIR: %[[lshft:.*]] = shl i64 %[[iext]], 56296! LLVMIR: %[[rshft:.*]] = ashr i64 %[[lshft]], 56297! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[rshft]]298! LLVMIR: %[[ld:.*]] = call <16 x i8> @llvm.ppc.altivec.lvsr(ptr %[[addr]])299! LLVMIR: store <16 x i8> %[[ld]], ptr %2, align 16300end subroutine vec_lvsr_testi32a301 302! CHECK-LABEL: @vec_lvsr_testf32a303subroutine vec_lvsr_testf32a(arg1, arg2, res)304 integer(8) :: arg1305 real(4) :: arg2306 vector(unsigned(1)) :: res307 res = vec_lvsr(arg1, arg2)308 309! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8310! LLVMIR: %[[lshft:.*]] = shl i64 %[[arg1]], 56311! LLVMIR: %[[rshft:.*]] = ashr i64 %[[lshft]], 56312! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[rshft]]313! LLVMIR: %[[ld:.*]] = call <16 x i8> @llvm.ppc.altivec.lvsr(ptr %[[addr]])314! LLVMIR: store <16 x i8> %[[ld]], ptr %2, align 16315end subroutine vec_lvsr_testf32a316 317!-------------------318! vec_lxv319!-------------------320 321! CHECK-LABEL: @vec_lxv_testi8a322subroutine vec_lxv_testi8a(arg1, arg2, res)323 integer(1) :: arg1324 integer(1) :: arg2(4)325 vector(integer(1)) :: res326 res = vec_lxv(arg1, arg2)327 328! LLVMIR: %[[offset:.*]] = load i8, ptr %0, align 1329! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[offset]]330! LLVMIR: %[[res:.*]] = load <16 x i8>, ptr %[[addr]], align 1331! LLVMIR: store <16 x i8> %[[res]], ptr %2, align 16332end subroutine vec_lxv_testi8a333 334! CHECK-LABEL: @vec_lxv_testi16a335subroutine vec_lxv_testi16a(arg1, arg2, res)336 integer(2) :: arg1337 integer(2) :: arg2(2, 4, 8)338 vector(integer(2)) :: res339 res = vec_lxv(arg1, arg2)340 341! LLVMIR: %[[offset:.*]] = load i16, ptr %0, align 2342! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[offset]]343! LLVMIR: %[[res:.*]] = load <8 x i16>, ptr %[[addr]], align 1344! LLVMIR: store <8 x i16> %[[res]], ptr %2, align 16345end subroutine vec_lxv_testi16a346 347! CHECK-LABEL: @vec_lxv_testi32a348subroutine vec_lxv_testi32a(arg1, arg2, res)349 integer(4) :: arg1350 integer(4) :: arg2(2, 4, 8)351 vector(integer(4)) :: res352 res = vec_lxv(arg1, arg2)353 354! LLVMIR: %[[offset:.*]] = load i32, ptr %0, align 4355! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[offset]]356! LLVMIR: %[[res:.*]] = load <4 x i32>, ptr %[[addr]], align 1357! LLVMIR: store <4 x i32> %[[res]], ptr %2, align 16358end subroutine vec_lxv_testi32a359 360! CHECK-LABEL: @vec_lxv_testf32a361subroutine vec_lxv_testf32a(arg1, arg2, res)362 integer(2) :: arg1363 real(4) :: arg2(4)364 vector(real(4)) :: res365 res = vec_lxv(arg1, arg2)366 367! LLVMIR: %[[offset:.*]] = load i16, ptr %0, align 2368! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[offset]]369! LLVMIR: %[[res:.*]] = load <4 x float>, ptr %[[addr]], align 1370! LLVMIR: store <4 x float> %[[res]], ptr %2, align 16371end subroutine vec_lxv_testf32a372 373! CHECK-LABEL: @vec_lxv_testf64a374subroutine vec_lxv_testf64a(arg1, arg2, res)375 integer(8) :: arg1376 real(8) :: arg2(4)377 vector(real(8)) :: res378 res = vec_lxv(arg1, arg2)379 380! LLVMIR: %[[offset:.*]] = load i64, ptr %0, align 8381! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[offset]]382! LLVMIR: %[[res:.*]] = load <2 x double>, ptr %[[addr]], align 1383! LLVMIR: store <2 x double> %[[res]], ptr %2, align 16384end subroutine vec_lxv_testf64a385 386!-------------------387! vec_xl388!-------------------389 390! CHECK-LABEL: @vec_xl_testi8a391subroutine vec_xl_testi8a(arg1, arg2, res)392 integer(1) :: arg1393 integer(1) :: arg2394 vector(integer(1)) :: res395 res = vec_xl(arg1, arg2)396 397 398! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 1399! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]]400! LLVMIR: %[[ld:.*]] = load <16 x i8>, ptr %[[addr]], align 1401! LLVMIR: %[[shflv:.*]] = shufflevector <16 x i8> %[[ld]], <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>402! LLVMIR: store <16 x i8> %[[shflv]], ptr %2, align 16403end subroutine vec_xl_testi8a404 405! CHECK-LABEL: @vec_xl_testi16a406subroutine vec_xl_testi16a(arg1, arg2, res)407 integer(2) :: arg1408 integer(2) :: arg2(2, 8)409 vector(integer(2)) :: res410 res = vec_xl(arg1, arg2)411 412! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2413! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]]414! LLVMIR: %[[ld:.*]] = load <8 x i16>, ptr %[[addr]], align 1415! LLVMIR: %[[shflv:.*]] = shufflevector <8 x i16> %[[ld]], <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>416! LLVMIR: store <8 x i16> %[[shflv]], ptr %2, align 16417end subroutine vec_xl_testi16a418 419! CHECK-LABEL: @vec_xl_testi32a420subroutine vec_xl_testi32a(arg1, arg2, res)421 integer(4) :: arg1422 integer(4) :: arg2(2, 4, 8)423 vector(integer(4)) :: res424 res = vec_xl(arg1, arg2)425 426! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4427! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]]428! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(ptr %[[addr]])429! LLVMIR: store <4 x i32> %[[ld]], ptr %2, align 16430end subroutine vec_xl_testi32a431 432! CHECK-LABEL: @vec_xl_testi64a433subroutine vec_xl_testi64a(arg1, arg2, res)434 integer(8) :: arg1435 integer(8) :: arg2(2, 4, 1)436 vector(integer(8)) :: res437 res = vec_xl(arg1, arg2)438 439! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8440! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]]441! LLVMIR: %[[ld:.*]] = call contract <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %[[addr]])442! LLVMIR: %[[bc:.*]] = bitcast <2 x double> %[[ld]] to <2 x i64>443! LLVMIR: store <2 x i64> %[[bc]], ptr %2, align 16444end subroutine vec_xl_testi64a445 446! CHECK-LABEL: @vec_xl_testf32a447subroutine vec_xl_testf32a(arg1, arg2, res)448 integer(2) :: arg1449 real(4) :: arg2(4)450 vector(real(4)) :: res451 res = vec_xl(arg1, arg2)452 453! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2454! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]]455! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(ptr %[[addr]])456! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[ld]] to <4 x float>457! LLVMIR: store <4 x float> %[[bc]], ptr %2, align 16458end subroutine vec_xl_testf32a459 460! CHECK-LABEL: @vec_xl_testf64a461subroutine vec_xl_testf64a(arg1, arg2, res)462 integer(8) :: arg1463 real(8) :: arg2(2)464 vector(real(8)) :: res465 res = vec_xl(arg1, arg2)466 467! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8468! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]]469! LLVMIR: %[[ld:.*]] = call contract <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %[[addr]])470! LLVMIR: store <2 x double> %[[ld]], ptr %2, align 16471end subroutine vec_xl_testf64a472 473!-------------------474! vec_xl_be475!-------------------476 477! CHECK-LABEL: @vec_xl_be_testi8a478subroutine vec_xl_be_testi8a(arg1, arg2, res)479 integer(1) :: arg1480 integer(1) :: arg2(2, 4, 8)481 vector(integer(1)) :: res482 res = vec_xl_be(arg1, arg2)483 484 485! LLVMIR: %4 = load i8, ptr %0, align 1486! LLVMIR: %5 = getelementptr i8, ptr %1, i8 %4487! LLVMIR: %6 = load <16 x i8>, ptr %5, align 1488! LLVMIR: %7 = shufflevector <16 x i8> %6, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>489! LLVMIR: store <16 x i8> %7, ptr %2, align 16490end subroutine vec_xl_be_testi8a491 492! CHECK-LABEL: @vec_xl_be_testi16a493subroutine vec_xl_be_testi16a(arg1, arg2, res)494 integer(2) :: arg1495 integer(2) :: arg2(8,2)496 vector(integer(2)) :: res497 res = vec_xl_be(arg1, arg2)498 499! LLVMIR: %4 = load i16, ptr %0, align 2500! LLVMIR: %5 = getelementptr i8, ptr %1, i16 %4501! LLVMIR: %6 = load <8 x i16>, ptr %5, align 1502! LLVMIR: %7 = shufflevector <8 x i16> %6, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>503! LLVMIR: store <8 x i16> %7, ptr %2, align 16504end subroutine vec_xl_be_testi16a505 506! CHECK-LABEL: @vec_xl_be_testi32a507subroutine vec_xl_be_testi32a(arg1, arg2, res)508 integer(4) :: arg1509 integer(4) :: arg2(2, 4)510 vector(integer(4)) :: res511 res = vec_xl_be(arg1, arg2)512 513! LLVMIR: %4 = load i32, ptr %0, align 4514! LLVMIR: %5 = getelementptr i8, ptr %1, i32 %4515! LLVMIR: %6 = load <4 x i32>, ptr %5, align 1516! LLVMIR: %7 = shufflevector <4 x i32> %6, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>517! LLVMIR: store <4 x i32> %7, ptr %2, align 16518end subroutine vec_xl_be_testi32a519 520! CHECK-LABEL: @vec_xl_be_testi64a521subroutine vec_xl_be_testi64a(arg1, arg2, res)522 integer(8) :: arg1523 integer(8) :: arg2(2, 4, 8)524 vector(integer(8)) :: res525 res = vec_xl_be(arg1, arg2)526 527! LLVMIR: %4 = load i64, ptr %0, align 8528! LLVMIR: %5 = getelementptr i8, ptr %1, i64 %4529! LLVMIR: %6 = load <2 x i64>, ptr %5, align 1530! LLVMIR: %7 = shufflevector <2 x i64> %6, <2 x i64> undef, <2 x i32> <i32 1, i32 0>531! LLVMIR: store <2 x i64> %7, ptr %2, align 16532end subroutine vec_xl_be_testi64a533 534! CHECK-LABEL: @vec_xl_be_testf32a535subroutine vec_xl_be_testf32a(arg1, arg2, res)536 integer(2) :: arg1537 real(4) :: arg2(4)538 vector(real(4)) :: res539 res = vec_xl_be(arg1, arg2)540 541! LLVMIR: %4 = load i16, ptr %0, align 2542! LLVMIR: %5 = getelementptr i8, ptr %1, i16 %4543! LLVMIR: %6 = load <4 x float>, ptr %5, align 1544! LLVMIR: %7 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>545! LLVMIR: store <4 x float> %7, ptr %2, align 16546end subroutine vec_xl_be_testf32a547 548! CHECK-LABEL: @vec_xl_be_testf64a549subroutine vec_xl_be_testf64a(arg1, arg2, res)550 integer(8) :: arg1551 real(8) :: arg2(4)552 vector(real(8)) :: res553 res = vec_xl_be(arg1, arg2)554 555! LLVMIR: %4 = load i64, ptr %0, align 8556! LLVMIR: %5 = getelementptr i8, ptr %1, i64 %4557! LLVMIR: %6 = load <2 x double>, ptr %5, align 1558! LLVMIR: %7 = shufflevector <2 x double> %6, <2 x double> undef, <2 x i32> <i32 1, i32 0>559! LLVMIR: store <2 x double> %7, ptr %2, align 16560end subroutine vec_xl_be_testf64a561 562!-------------------563! vec_xld2564!-------------------565 566! CHECK-LABEL: @vec_xld2_testi8a567subroutine vec_xld2_testi8a(arg1, arg2, res)568 integer(1) :: arg1569 vector(integer(1)) :: arg2(4)570 vector(integer(1)) :: res571 res = vec_xld2(arg1, arg2)572 573! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 1574! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]]575! LLVMIR: %[[ld:.*]] = call contract <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %[[addr]])576! LLVMIR: %[[bc:.*]] = bitcast <2 x double> %[[ld]] to <16 x i8>577! LLVMIR: store <16 x i8> %[[bc]], ptr %2, align 16578end subroutine vec_xld2_testi8a579 580! CHECK-LABEL: @vec_xld2_testi16a581subroutine vec_xld2_testi16a(arg1, arg2, res)582 integer(2) :: arg1583 vector(integer(2)) :: arg2(4)584 vector(integer(2)) :: res585 res = vec_xld2(arg1, arg2)586 587! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2588! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]]589! LLVMIR: %[[ld:.*]] = call contract <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %[[addr]])590! LLVMIR: %[[bc:.*]] = bitcast <2 x double> %[[ld]] to <8 x i16>591! LLVMIR: store <8 x i16> %[[bc]], ptr %2, align 16592end subroutine vec_xld2_testi16a593 594! CHECK-LABEL: @vec_xld2_testi32a595subroutine vec_xld2_testi32a(arg1, arg2, res)596 integer(4) :: arg1597 vector(integer(4)) :: arg2(11)598 vector(integer(4)) :: res599 res = vec_xld2(arg1, arg2)600 601! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4602! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]]603! LLVMIR: %[[ld:.*]] = call contract <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %[[addr]])604! LLVMIR: %[[bc:.*]] = bitcast <2 x double> %[[ld]] to <4 x i32>605! LLVMIR: store <4 x i32> %[[bc]], ptr %2, align 16606end subroutine vec_xld2_testi32a607 608! CHECK-LABEL: @vec_xld2_testi64a609subroutine vec_xld2_testi64a(arg1, arg2, res)610 integer(8) :: arg1611 vector(integer(8)) :: arg2(31,7)612 vector(integer(8)) :: res613 res = vec_xld2(arg1, arg2)614 615! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8616! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]]617! LLVMIR: %[[ld:.*]] = call contract <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %[[addr]])618! LLVMIR: %[[bc:.*]] = bitcast <2 x double> %[[ld]] to <2 x i64>619! LLVMIR: store <2 x i64> %[[bc]], ptr %2, align 16620end subroutine vec_xld2_testi64a621 622! CHECK-LABEL: @vec_xld2_testf32a623subroutine vec_xld2_testf32a(arg1, arg2, res)624 integer(2) :: arg1625 vector(real(4)) :: arg2(5)626 vector(real(4)) :: res627 res = vec_xld2(arg1, arg2)628 629! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2630! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]]631! LLVMIR: %[[ld:.*]] = call contract <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %[[addr]])632! LLVMIR: %[[bc:.*]] = bitcast <2 x double> %[[ld]] to <4 x float>633! LLVMIR: store <4 x float> %[[bc]], ptr %2, align 16634end subroutine vec_xld2_testf32a635 636! CHECK-LABEL: @vec_xld2_testf64a637subroutine vec_xld2_testf64a(arg1, arg2, res)638 integer(8) :: arg1639 vector(real(8)) :: arg2(4)640 vector(real(8)) :: res641 res = vec_xld2(arg1, arg2)642 643! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8644! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]]645! LLVMIR: %[[ld:.*]] = call contract <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %[[addr]])646! LLVMIR: store <2 x double> %[[ld]], ptr %2, align 16647end subroutine vec_xld2_testf64a648 649!-------------------650! vec_xlw4651!-------------------652 653! CHECK-LABEL: @vec_xlw4_testi8a654subroutine vec_xlw4_testi8a(arg1, arg2, res)655 integer(1) :: arg1656 vector(integer(1)) :: arg2(2, 11, 37)657 vector(integer(1)) :: res658 res = vec_xlw4(arg1, arg2)659 660! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 1661! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]]662! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(ptr %[[addr]])663! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[ld]] to <16 x i8>664! LLVMIR: store <16 x i8> %[[bc]], ptr %2, align 16665end subroutine vec_xlw4_testi8a666 667! CHECK-LABEL: @vec_xlw4_testi16a668subroutine vec_xlw4_testi16a(arg1, arg2, res)669 integer(2) :: arg1670 vector(integer(2)) :: arg2(2, 8)671 vector(integer(2)) :: res672 res = vec_xlw4(arg1, arg2)673 674! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2675! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]]676! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(ptr %[[addr]])677! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[ld]] to <8 x i16>678! LLVMIR: store <8 x i16> %[[bc]], ptr %2, align 16679end subroutine vec_xlw4_testi16a680 681! CHECK-LABEL: @vec_xlw4_testu32a682subroutine vec_xlw4_testu32a(arg1, arg2, res)683 integer(4) :: arg1684 vector(unsigned(4)) :: arg2(8, 4)685 vector(unsigned(4)) :: res686 res = vec_xlw4(arg1, arg2)687 688! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4689! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]]690! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(ptr %[[addr]])691! LLVMIR: store <4 x i32> %[[ld]], ptr %2, align 16692end subroutine vec_xlw4_testu32a693 694! CHECK-LABEL: @vec_xlw4_testf32a695subroutine vec_xlw4_testf32a(arg1, arg2, res)696 integer(2) :: arg1697 vector(real(4)) :: arg2698 vector(real(4)) :: res699 res = vec_xlw4(arg1, arg2)700 701! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2702! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]]703! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(ptr %[[addr]])704! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[ld]] to <4 x float>705! LLVMIR: store <4 x float> %[[bc]], ptr %2, align 16706end subroutine vec_xlw4_testf32a707 708!-------------------709! vec_xlds710!-------------------711 712! CHECK-LABEL: @vec_xlds_testi64a713subroutine vec_xlds_testi64a(arg1, arg2, res)714 integer(8) :: arg1715 vector(integer(8)) :: arg2(4)716 vector(integer(8)) :: res717 res = vec_xlds(arg1, arg2)718 719! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8720! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]]721! LLVMIR: %[[ld:.*]] = load i64, ptr %[[addr]], align 8722! LLVMIR: %[[insrt:.*]] = insertelement <2 x i64> poison, i64 %[[ld]], i32 0723! LLVMIR: %[[shflv:.*]] = shufflevector <2 x i64> %[[insrt]], <2 x i64> poison, <2 x i32> zeroinitializer724! LLVMIR: store <2 x i64> %[[shflv]], ptr %2, align 16725end subroutine vec_xlds_testi64a726 727! CHECK-LABEL: @vec_xlds_testf64a728subroutine vec_xlds_testf64a(arg1, arg2, res)729 integer(8) :: arg1730 vector(real(8)) :: arg2(4)731 vector(real(8)) :: res732 res = vec_xlds(arg1, arg2)733 734! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8735! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]]736! LLVMIR: %[[ld:.*]] = load i64, ptr %[[addr]], align 8737! LLVMIR: %[[insrt:.*]] = insertelement <2 x i64> poison, i64 %[[ld]], i32 0738! LLVMIR: %[[shflv:.*]] = shufflevector <2 x i64> %[[insrt]], <2 x i64> poison, <2 x i32> zeroinitializer739! LLVMIR: %[[bc:.*]] = bitcast <2 x i64> %[[shflv]] to <2 x double>740! LLVMIR: store <2 x double> %[[bc]], ptr %2, align 16741end subroutine vec_xlds_testf64a742