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1! RUN: %flang_fc1 -flang-experimental-hlfir -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR","LLVMIR-LE","LLVM" %s2! RUN: %flang_fc1 -triple powerpc64le-unknown-unknown -target-cpu pwr9 -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR","LLVMIR_P9","LLVM" %s3! RUN: %flang_fc1 -flang-experimental-hlfir -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR","LLVMIR-BE","LLVM" %s4! REQUIRES: target=powerpc{{.*}}5 6!----------------------7! vec_ld8!----------------------9 10! LLVM-LABEL: @vec_ld_testi811subroutine vec_ld_testi8(arg1, arg2, res)12 integer(1) :: arg113 vector(integer(1)) :: arg2, res14 res = vec_ld(arg1, arg2)15 16! LLVMIR: %[[arg1:.*]] = load i8, ptr %{{.*}}, align 117! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]]18! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr %[[addr]])19! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[call]] to <16 x i8>20! LLVMIR: store <16 x i8> %[[bc]], ptr %2, align 1621end subroutine vec_ld_testi822 23! LLVM-LABEL: @vec_ld_testi1624subroutine vec_ld_testi16(arg1, arg2, res)25 integer(2) :: arg126 vector(integer(2)) :: arg2, res27 res = vec_ld(arg1, arg2)28 29! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 230! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]]31! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr %[[addr]])32! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[call]] to <8 x i16>33! LLVMIR: store <8 x i16> %[[bc]], ptr %2, align 1634end subroutine vec_ld_testi1635 36! LLVM-LABEL: @vec_ld_testi3237subroutine vec_ld_testi32(arg1, arg2, res)38 integer(4) :: arg139 vector(integer(4)) :: arg2, res40 res = vec_ld(arg1, arg2)41 42! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 443! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]]44! LLVMIR: %[[bc:.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr %[[addr]])45! LLVMIR: store <4 x i32> %[[bc]], ptr %2, align 1646end subroutine vec_ld_testi3247 48! LLVM-LABEL: @vec_ld_testf3249subroutine vec_ld_testf32(arg1, arg2, res)50 integer(8) :: arg151 vector(real(4)) :: arg2, res52 res = vec_ld(arg1, arg2)53 54! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 855! LLVMIR: %[[arg1i32:.*]] = trunc i64 %[[arg1]] to i3256! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1i32]]57! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr %[[addr]])58! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[call]] to <4 x float>59! LLVMIR: store <4 x float> %[[bc]], ptr %2, align 1660end subroutine vec_ld_testf3261 62! LLVM-LABEL: @vec_ld_testu3263subroutine vec_ld_testu32(arg1, arg2, res)64 integer(1) :: arg165 vector(unsigned(4)) :: arg2, res66 res = vec_ld(arg1, arg2)67 68! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 169! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]]70! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr %[[addr]])71! LLVMIR: store <4 x i32> %[[call]], ptr %2, align 1672end subroutine vec_ld_testu3273 74! LLVM-LABEL: @vec_ld_testi32a75subroutine vec_ld_testi32a(arg1, arg2, res)76 integer(4) :: arg177 integer(4) :: arg2(10)78 vector(integer(4)) :: res79 res = vec_ld(arg1, arg2)80 81! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 482! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]]83! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr %[[addr]])84! LLVMIR: store <4 x i32> %[[call]], ptr %2, align 1685end subroutine vec_ld_testi32a86 87! LLVM-LABEL: @vec_ld_testf32av88subroutine vec_ld_testf32av(arg1, arg2, res)89 integer(8) :: arg190 vector(real(4)) :: arg2(2, 4, 8)91 vector(real(4)) :: res92 res = vec_ld(arg1, arg2)93 94! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 895! LLVMIR: %[[arg1i32:.*]] = trunc i64 %[[arg1]] to i3296! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1i32]]97! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr %[[addr]])98! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[call]] to <4 x float>99! LLVMIR: store <4 x float> %[[bc]], ptr %2, align 16100end subroutine vec_ld_testf32av101 102! LLVM-LABEL: @vec_ld_testi32s103subroutine vec_ld_testi32s(arg1, arg2, res)104 integer(4) :: arg1105 real(4) :: arg2106 vector(real(4)) :: res107 res = vec_ld(arg1, arg2)108 109! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4110! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]]111! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvx(ptr %[[addr]])112! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[call]] to <4 x float>113! LLVMIR: store <4 x float> %[[bc]], ptr %2, align 16114end subroutine vec_ld_testi32s115 116!----------------------117! vec_lde118!----------------------119 120! LLVM-LABEL: @vec_lde_testi8s121subroutine vec_lde_testi8s(arg1, arg2, res)122 integer(1) :: arg1123 integer(1) :: arg2124 vector(integer(1)) :: res125 res = vec_lde(arg1, arg2)126 127! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 1128! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]]129! LLVMIR: %[[call:.*]] = call <16 x i8> @llvm.ppc.altivec.lvebx(ptr %[[addr]])130! LLVMIR: store <16 x i8> %[[call]], ptr %2, align 16131end subroutine vec_lde_testi8s132 133! LLVM-LABEL: @vec_lde_testi16a134subroutine vec_lde_testi16a(arg1, arg2, res)135 integer(2) :: arg1136 integer(2) :: arg2(2, 4, 8)137 vector(integer(2)) :: res138 res = vec_lde(arg1, arg2)139 140! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2141! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]]142! LLVMIR: %[[call:.*]] = call <8 x i16> @llvm.ppc.altivec.lvehx(ptr %[[addr]])143! LLVMIR: store <8 x i16> %[[call]], ptr %2, align 16144end subroutine vec_lde_testi16a145 146! LLVM-LABEL: @vec_lde_testi32a147subroutine vec_lde_testi32a(arg1, arg2, res)148 integer(4) :: arg1149 integer(4) :: arg2(4)150 vector(integer(4)) :: res151 res = vec_lde(arg1, arg2)152 153! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4154! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]]155! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvewx(ptr %[[addr]])156! LLVMIR: store <4 x i32> %[[call]], ptr %2, align 16157end subroutine vec_lde_testi32a158 159! LLVM-LABEL: @vec_lde_testf32a160subroutine vec_lde_testf32a(arg1, arg2, res)161 integer(8) :: arg1162 real(4) :: arg2(4)163 vector(real(4)) :: res164 res = vec_lde(arg1, arg2)165 166! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8167! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]]168! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvewx(ptr %[[addr]])169! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[call]] to <4 x float>170! LLVMIR: store <4 x float> %[[bc]], ptr %2, align 16171end subroutine vec_lde_testf32a172 173!----------------------174! vec_ldl175!----------------------176 177! LLVM-LABEL: @vec_ldl_testi8178subroutine vec_ldl_testi8(arg1, arg2, res)179 integer(1) :: arg1180 vector(integer(1)) :: arg2, res181 res = vec_ldl(arg1, arg2)182 183! LLVMIR: %[[arg1:.*]] = load i8, ptr %{{.*}}, align 1184! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]]185! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvxl(ptr %[[addr]])186! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[call]] to <16 x i8>187! LLVMIR: store <16 x i8> %[[bc]], ptr %2, align 16188end subroutine vec_ldl_testi8189 190! LLVM-LABEL: @vec_ldl_testi16191subroutine vec_ldl_testi16(arg1, arg2, res)192 integer(2) :: arg1193 vector(integer(2)) :: arg2, res194 res = vec_ldl(arg1, arg2)195 196! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2197! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]]198! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvxl(ptr %[[addr]])199! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[call]] to <8 x i16>200! LLVMIR: store <8 x i16> %[[bc]], ptr %2, align 16201end subroutine vec_ldl_testi16202 203! LLVM-LABEL: @vec_ldl_testi32204subroutine vec_ldl_testi32(arg1, arg2, res)205 integer(4) :: arg1206 vector(integer(4)) :: arg2, res207 res = vec_ldl(arg1, arg2)208 209! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4210! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]]211! LLVMIR: %[[bc:.*]] = call <4 x i32> @llvm.ppc.altivec.lvxl(ptr %[[addr]])212! LLVMIR: store <4 x i32> %[[bc]], ptr %2, align 16213end subroutine vec_ldl_testi32214 215! LLVM-LABEL: @vec_ldl_testf32216subroutine vec_ldl_testf32(arg1, arg2, res)217 integer(8) :: arg1218 vector(real(4)) :: arg2, res219 res = vec_ldl(arg1, arg2)220 221 222! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8223! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]]224! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvxl(ptr %[[addr]])225! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[call]] to <4 x float>226! LLVMIR: store <4 x float> %[[bc]], ptr %2, align 16227end subroutine vec_ldl_testf32228 229! LLVM-LABEL: @vec_ldl_testu32230subroutine vec_ldl_testu32(arg1, arg2, res)231 integer(1) :: arg1232 vector(unsigned(4)) :: arg2, res233 res = vec_ldl(arg1, arg2)234 235! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 1236! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]]237! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvxl(ptr %[[addr]])238! LLVMIR: store <4 x i32> %[[call]], ptr %2, align 16239end subroutine vec_ldl_testu32240 241! LLVM-LABEL: @vec_ldl_testi32a242subroutine vec_ldl_testi32a(arg1, arg2, res)243 integer(4) :: arg1244 integer(4) :: arg2(10)245 vector(integer(4)) :: res246 res = vec_ldl(arg1, arg2)247 248! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4249! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]]250! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvxl(ptr %[[addr]])251! LLVMIR: store <4 x i32> %[[call]], ptr %2, align 16252end subroutine vec_ldl_testi32a253 254! LLVM-LABEL: @vec_ldl_testf32av255subroutine vec_ldl_testf32av(arg1, arg2, res)256 integer(8) :: arg1257 vector(real(4)) :: arg2(2, 4, 8)258 vector(real(4)) :: res259 res = vec_ldl(arg1, arg2)260 261! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8262! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]]263! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvxl(ptr %[[addr]])264! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[call]] to <4 x float>265! LLVMIR: store <4 x float> %[[bc]], ptr %2, align 16266end subroutine vec_ldl_testf32av267 268! LLVM-LABEL: @vec_ldl_testi32s269subroutine vec_ldl_testi32s(arg1, arg2, res)270 integer(4) :: arg1271 real(4) :: arg2272 vector(real(4)) :: res273 res = vec_ldl(arg1, arg2)274 275! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4276! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]]277! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.lvxl(ptr %[[addr]])278! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[call]] to <4 x float>279! LLVMIR: store <4 x float> %[[bc]], ptr %2, align 16280end subroutine vec_ldl_testi32s281 282!----------------------283! vec_lvsl284!----------------------285 286! LLVM-LABEL: @vec_lvsl_testi8s287subroutine vec_lvsl_testi8s(arg1, arg2, res)288 integer(1) :: arg1289 integer(1) :: arg2290 vector(unsigned(1)) :: res291 res = vec_lvsl(arg1, arg2)292 293! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 1294! LLVMIR: %[[ext:.*]] = sext i8 %[[arg1]] to i64295! LLVMIR: %[[lshft:.*]] = shl i64 %[[ext]], 56296! LLVMIR: %[[rshft:.*]] = ashr i64 %[[lshft]], 56297! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[rshft]]298! LLVMIR: %[[ld:.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr %[[addr]])299! LLVMIR-LE: %[[sv:.*]] = shufflevector <16 x i8> %[[ld]], <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>300! LLVMIR-LE: store <16 x i8> %[[sv]], ptr %2, align 16301! LLVMIR-BE: store <16 x i8> %[[ld]], ptr %2, align 16302end subroutine vec_lvsl_testi8s303 304! LLVM-LABEL: @vec_lvsl_testi16a305subroutine vec_lvsl_testi16a(arg1, arg2, res)306 integer(2) :: arg1307 integer(2) :: arg2(4)308 vector(unsigned(1)) :: res309 res = vec_lvsl(arg1, arg2)310 311! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2312! LLVMIR: %[[ext:.*]] = sext i16 %[[arg1]] to i64313! LLVMIR: %[[lshft:.*]] = shl i64 %[[ext]], 56314! LLVMIR: %[[rshft:.*]] = ashr i64 %[[lshft]], 56315! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[rshft]]316! LLVMIR: %[[ld:.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr %[[addr]])317! LLVMIR-LE: %[[sv:.*]] = shufflevector <16 x i8> %[[ld]], <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>318! LLVMIR-LE: store <16 x i8> %[[sv]], ptr %2, align 16319! LLVMIR-BE: store <16 x i8> %[[ld]], ptr %2, align 16320end subroutine vec_lvsl_testi16a321 322! LLVM-LABEL: @vec_lvsl_testi32a323subroutine vec_lvsl_testi32a(arg1, arg2, res)324 integer(4) :: arg1325 integer(4) :: arg2(2, 3, 4)326 vector(unsigned(1)) :: res327 res = vec_lvsl(arg1, arg2)328 329! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4330! LLVMIR: %[[ext:.*]] = sext i32 %[[arg1]] to i64331! LLVMIR: %[[lshft:.*]] = shl i64 %[[ext]], 56332! LLVMIR: %[[rshft:.*]] = ashr i64 %[[lshft]], 56333! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[rshft]]334! LLVMIR: %[[ld:.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr %[[addr]])335! LLVMIR-LE: %[[sv:.*]] = shufflevector <16 x i8> %[[ld]], <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>336! LLVMIR-LE: store <16 x i8> %[[sv]], ptr %2, align 16337! LLVMIR-BE: store <16 x i8> %[[ld]], ptr %2, align 16338end subroutine vec_lvsl_testi32a339 340! LLVM-LABEL: @vec_lvsl_testf32a341subroutine vec_lvsl_testf32a(arg1, arg2, res)342 integer(8) :: arg1343 real(4) :: arg2(4)344 vector(unsigned(1)) :: res345 res = vec_lvsl(arg1, arg2)346 347! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8348! LLVMIR: %[[lshft:.*]] = shl i64 %[[arg1]], 56349! LLVMIR: %[[rshft:.*]] = ashr i64 %[[lshft]], 56350! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[rshft]]351! LLVMIR: %[[ld:.*]] = call <16 x i8> @llvm.ppc.altivec.lvsl(ptr %[[addr]])352! LLVMIR-LE: %[[sv:.*]] = shufflevector <16 x i8> %[[ld]], <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>353! LLVMIR-LE: store <16 x i8> %[[sv]], ptr %2, align 16354! LLVMIR-BE: store <16 x i8> %[[ld]], ptr %2, align 16355end subroutine vec_lvsl_testf32a356 357!----------------------358! vec_lvsr359!----------------------360 361! LLVM-LABEL: @vec_lvsr_testi8s362subroutine vec_lvsr_testi8s(arg1, arg2, res)363 integer(1) :: arg1364 integer(1) :: arg2365 vector(unsigned(1)) :: res366 res = vec_lvsr(arg1, arg2)367 368! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 1369! LLVMIR: %[[ext:.*]] = sext i8 %[[arg1]] to i64370! LLVMIR: %[[lshft:.*]] = shl i64 %[[ext]], 56371! LLVMIR: %[[rshft:.*]] = ashr i64 %[[lshft]], 56372! LLVMIR: %[[ld:.*]] = getelementptr i8, ptr %1, i64 %[[rshft]]373! LLVMIR: %[[addr:.*]] = call <16 x i8> @llvm.ppc.altivec.lvsr(ptr %[[ld]])374! LLVMIR-LE: %[[sv:.*]] = shufflevector <16 x i8> %[[addr]], <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>375! LLVMIR-LE: store <16 x i8> %[[sv]], ptr %2, align 16376! LLVMIR-BE: store <16 x i8> %[[addr]], ptr %2, align 16377end subroutine vec_lvsr_testi8s378 379! LLVM-LABEL: @vec_lvsr_testi16a380subroutine vec_lvsr_testi16a(arg1, arg2, res)381 integer(2) :: arg1382 integer(2) :: arg2(4)383 vector(unsigned(1)) :: res384 res = vec_lvsr(arg1, arg2)385 386! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2387! LLVMIR: %[[ext:.*]] = sext i16 %[[arg1]] to i64388! LLVMIR: %[[lshft:.*]] = shl i64 %[[ext]], 56389! LLVMIR: %[[rshft:.*]] = ashr i64 %[[lshft]], 56390! LLVMIR: %[[ld:.*]] = getelementptr i8, ptr %1, i64 %[[rshft]]391! LLVMIR: %[[addr:.*]] = call <16 x i8> @llvm.ppc.altivec.lvsr(ptr %[[ld]])392! LLVMIR-LE: %[[sv:.*]] = shufflevector <16 x i8> %[[addr]], <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>393! LLVMIR-LE: store <16 x i8> %[[sv]], ptr %2, align 16394! LLVMIR-BE: store <16 x i8> %[[addr]], ptr %2, align 16395end subroutine vec_lvsr_testi16a396 397! LLVM-LABEL: @vec_lvsr_testi32a398subroutine vec_lvsr_testi32a(arg1, arg2, res)399 integer(4) :: arg1400 integer(4) :: arg2(2, 3, 4)401 vector(unsigned(1)) :: res402 res = vec_lvsr(arg1, arg2)403 404! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4405! LLVMIR: %[[ext:.*]] = sext i32 %[[arg1]] to i64406! LLVMIR: %[[lshft:.*]] = shl i64 %[[ext]], 56407! LLVMIR: %[[rshft:.*]] = ashr i64 %[[lshft]], 56408! LLVMIR: %[[ld:.*]] = getelementptr i8, ptr %1, i64 %[[rshft]]409! LLVMIR: %[[addr:.*]] = call <16 x i8> @llvm.ppc.altivec.lvsr(ptr %[[ld]])410! LLVMIR-LE: %[[sv:.*]] = shufflevector <16 x i8> %[[addr]], <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>411! LLVMIR-LE: store <16 x i8> %[[sv]], ptr %2, align 16412! LLVMIR-BE: store <16 x i8> %[[addr]], ptr %2, align 16413end subroutine vec_lvsr_testi32a414 415! LLVM-LABEL: @vec_lvsr_testf32a416subroutine vec_lvsr_testf32a(arg1, arg2, res)417 integer(8) :: arg1418 real(4) :: arg2(4)419 vector(unsigned(1)) :: res420 res = vec_lvsr(arg1, arg2)421 422! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8423! LLVMIR: %[[lshft:.*]] = shl i64 %[[arg1]], 56424! LLVMIR: %[[rshft:.*]] = ashr i64 %[[lshft]], 56425! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[rshft]]426! LLVMIR: %[[ld:.*]] = call <16 x i8> @llvm.ppc.altivec.lvsr(ptr %[[addr]])427! LLVMIR-LE: %[[sv:.*]] = shufflevector <16 x i8> %[[ld]], <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>428! LLVMIR-LE: store <16 x i8> %[[sv]], ptr %2, align 16429! LLVMIR-BE: store <16 x i8> %[[ld]], ptr %2, align 16430end subroutine vec_lvsr_testf32a431 432!----------------------433! vec_lxv434!----------------------435 436! LLVM-LABEL: @vec_lxv_testi8a437subroutine vec_lxv_testi8a(arg1, arg2, res)438 integer(1) :: arg1439 integer(1) :: arg2(4)440 vector(integer(1)) :: res441 res = vec_lxv(arg1, arg2)442 443! LLVMIR_P9: %[[arg1:.*]] = load i8, ptr %0, align 1444! LLVMIR_P9: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]]445! LLVMIR_P9: %[[ld:.*]] = load <16 x i8>, ptr %[[addr]], align 1446! LLVMIR_P9: store <16 x i8> %[[ld]], ptr %2, align 16447end subroutine vec_lxv_testi8a448 449! LLVM-LABEL: @vec_lxv_testi16a450subroutine vec_lxv_testi16a(arg1, arg2, res)451 integer(2) :: arg1452 integer(2) :: arg2(2, 4, 8)453 vector(integer(2)) :: res454 res = vec_lxv(arg1, arg2)455 456! LLVMIR_P9: %[[arg1:.*]] = load i16, ptr %0, align 2457! LLVMIR_P9: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]]458! LLVMIR_P9: %[[ld:.*]] = load <8 x i16>, ptr %[[addr]], align 1459! LLVMIR_P9: store <8 x i16> %[[ld]], ptr %2, align 16460end subroutine vec_lxv_testi16a461 462! LLVM-LABEL: @vec_lxv_testi32a463subroutine vec_lxv_testi32a(arg1, arg2, res)464 integer(4) :: arg1465 integer(4) :: arg2(2, 4, 8)466 vector(integer(4)) :: res467 res = vec_lxv(arg1, arg2)468 469! LLVMIR_P9: %[[arg1:.*]] = load i32, ptr %0, align 4470! LLVMIR_P9: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]]471! LLVMIR_P9: %[[ld:.*]] = load <4 x i32>, ptr %[[addr]], align 1472! LLVMIR_P9: store <4 x i32> %[[ld]], ptr %2, align 16473end subroutine vec_lxv_testi32a474 475! LLVM-LABEL: @vec_lxv_testf32a476subroutine vec_lxv_testf32a(arg1, arg2, res)477 integer(2) :: arg1478 real(4) :: arg2(4)479 vector(real(4)) :: res480 res = vec_lxv(arg1, arg2)481 482! LLVMIR_P9: %[[arg1:.*]] = load i16, ptr %0, align 2483! LLVMIR_P9: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]]484! LLVMIR_P9: %[[ld:.*]] = load <4 x float>, ptr %[[addr]], align 1485! LLVMIR_P9: store <4 x float> %[[ld]], ptr %2, align 16486end subroutine vec_lxv_testf32a487 488! LLVM-LABEL: @vec_lxv_testf64a489subroutine vec_lxv_testf64a(arg1, arg2, res)490 integer(8) :: arg1491 real(8) :: arg2(4)492 vector(real(8)) :: res493 res = vec_lxv(arg1, arg2)494 495! LLVMIR_P9: %[[arg1:.*]] = load i64, ptr %0, align 8496! LLVMIR_P9: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]]497! LLVMIR_P9: %[[ld:.*]] = load <2 x double>, ptr %[[addr]], align 1498! LLVMIR_P9: store <2 x double> %[[ld]], ptr %2, align 16499end subroutine vec_lxv_testf64a500 501!----------------------502! vec_xld2503!----------------------504 505! LLVM-LABEL: @vec_xld2_testi8a506subroutine vec_xld2_testi8a(arg1, arg2, res)507 integer(1) :: arg1508 vector(integer(1)) :: arg2(4)509 vector(integer(1)) :: res510 res = vec_xld2(arg1, arg2)511 512! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 1513! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]]514! LLVMIR: %[[ld:.*]] = call contract <2 x double> @llvm.ppc.vsx.lxvd2x(ptr %[[addr]])515! LLVMIR: %[[bc:.*]] = bitcast <2 x double> %[[ld]] to <16 x i8>516! LLVMIR: store <16 x i8> %[[bc]], ptr %2, align 16517end subroutine vec_xld2_testi8a518 519! LLVM-LABEL: @vec_xld2_testi16520subroutine vec_xld2_testi16(arg1, arg2, res)521 integer :: arg1522 vector(integer(2)) :: arg2523 vector(integer(2)) :: res524 res = vec_xld2(arg1, arg2)525 526! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4527! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]]528! LLVMIR: %[[ld:.*]] = call contract <2 x double> @llvm.ppc.vsx.lxvd2x(ptr %[[addr]])529! LLVMIR: %[[bc:.*]] = bitcast <2 x double> %[[ld]] to <8 x i16>530! LLVMIR: store <8 x i16> %[[bc]], ptr %2, align 16531end subroutine vec_xld2_testi16532 533! LLVM-LABEL: @vec_xld2_testi32a534subroutine vec_xld2_testi32a(arg1, arg2, res)535 integer(4) :: arg1536 vector(integer(4)) :: arg2(41)537 vector(integer(4)) :: res538 res = vec_xld2(arg1, arg2)539 540! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4541! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]]542! LLVMIR: %[[ld:.*]] = call contract <2 x double> @llvm.ppc.vsx.lxvd2x(ptr %[[addr]])543! LLVMIR: %[[bc:.*]] = bitcast <2 x double> %[[ld]] to <4 x i32>544! LLVMIR: store <4 x i32> %[[bc]], ptr %2, align 16545end subroutine vec_xld2_testi32a546 547! LLVM-LABEL: @vec_xld2_testi64a548subroutine vec_xld2_testi64a(arg1, arg2, res)549 integer(8) :: arg1550 vector(integer(8)) :: arg2(4)551 vector(integer(8)) :: res552 res = vec_xld2(arg1, arg2)553 554! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8555! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]]556! LLVMIR: %[[ld:.*]] = call contract <2 x double> @llvm.ppc.vsx.lxvd2x(ptr %[[addr]])557! LLVMIR: %[[bc:.*]] = bitcast <2 x double> %[[ld]] to <2 x i64>558! LLVMIR: store <2 x i64> %[[bc]], ptr %2, align 16559end subroutine vec_xld2_testi64a560 561! LLVM-LABEL: @vec_xld2_testf32a562subroutine vec_xld2_testf32a(arg1, arg2, res)563 integer(2) :: arg1564 vector(real(4)) :: arg2(4)565 vector(real(4)) :: res566 res = vec_xld2(arg1, arg2)567 568! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2569! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]]570! LLVMIR: %[[ld:.*]] = call contract <2 x double> @llvm.ppc.vsx.lxvd2x(ptr %[[addr]])571! LLVMIR: %[[bc:.*]] = bitcast <2 x double> %[[ld]] to <4 x float>572! LLVMIR: store <4 x float> %[[bc]], ptr %2, align 16573end subroutine vec_xld2_testf32a574 575! LLVM-LABEL: @vec_xld2_testf64a576subroutine vec_xld2_testf64a(arg1, arg2, res)577 integer(8) :: arg1578 vector(real(8)) :: arg2(4)579 vector(real(8)) :: res580 res = vec_xld2(arg1, arg2)581 582! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8583! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]]584! LLVMIR: %[[ld:.*]] = call contract <2 x double> @llvm.ppc.vsx.lxvd2x(ptr %[[addr]])585! LLVMIR: store <2 x double> %[[ld]], ptr %2, align 16586end subroutine vec_xld2_testf64a587 588!----------------------589! vec_xl590!----------------------591 592! LLVM-LABEL: @vec_xl_testi8a593subroutine vec_xl_testi8a(arg1, arg2, res)594 integer(1) :: arg1595 integer(1) :: arg2(4)596 vector(integer(1)) :: res597 res = vec_xl(arg1, arg2)598 599! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 1600! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]]601! LLVMIR: %[[ld:.*]] = load <16 x i8>, ptr %[[addr]], align 1602! LLVMIR: store <16 x i8> %[[ld]], ptr %2, align 16603end subroutine vec_xl_testi8a604 605! LLVM-LABEL: @vec_xl_testi16a606subroutine vec_xl_testi16a(arg1, arg2, res)607 integer(2) :: arg1608 integer(2) :: arg2(2, 4, 8)609 vector(integer(2)) :: res610 res = vec_xl(arg1, arg2)611 612! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2613! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]]614! LLVMIR: %[[ld:.*]] = load <8 x i16>, ptr %[[addr]], align 1615! LLVMIR: store <8 x i16> %[[ld]], ptr %2, align 16616end subroutine vec_xl_testi16a617 618! LLVM-LABEL: @vec_xl_testi32a619subroutine vec_xl_testi32a(arg1, arg2, res)620 integer(4) :: arg1621 integer(4) :: arg2(2, 4, 8)622 vector(integer(4)) :: res623 res = vec_xl(arg1, arg2)624 625! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4626! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]]627! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.vsx.lxvw4x(ptr %[[addr]])628! LLVMIR: store <4 x i32> %[[ld]], ptr %2, align 16629end subroutine vec_xl_testi32a630 631! LLVM-LABEL: @vec_xl_testi64a632subroutine vec_xl_testi64a(arg1, arg2, res)633 integer(8) :: arg1634 integer(8) :: arg2(2, 4, 8)635 vector(integer(8)) :: res636 res = vec_xl(arg1, arg2)637 638! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8639! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]]640! LLVMIR: %[[ld:.*]] = call contract <2 x double> @llvm.ppc.vsx.lxvd2x(ptr %[[addr]])641! LLVMIR: %[[bc:.*]] = bitcast <2 x double> %[[ld]] to <2 x i64>642! LLVMIR: store <2 x i64> %[[bc]], ptr %2, align 16643end subroutine vec_xl_testi64a644 645! LLVM-LABEL: @vec_xl_testf32a646subroutine vec_xl_testf32a(arg1, arg2, res)647 integer(2) :: arg1648 real(4) :: arg2(4)649 vector(real(4)) :: res650 res = vec_xl(arg1, arg2)651 652! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2653! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]]654! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.vsx.lxvw4x(ptr %[[addr]])655! LLVMIR: %[[bc:.*]] = bitcast <4 x i32> %[[ld]] to <4 x float>656! LLVMIR: store <4 x float> %[[bc]], ptr %2, align 16657end subroutine vec_xl_testf32a658 659! LLVM-LABEL: @vec_xl_testf64a660subroutine vec_xl_testf64a(arg1, arg2, res)661 integer(8) :: arg1662 real(8) :: arg2663 vector(real(8)) :: res664 res = vec_xl(arg1, arg2)665 666! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8667! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]]668! LLVMIR: %[[ld:.*]] = call contract <2 x double> @llvm.ppc.vsx.lxvd2x(ptr %[[addr]])669! LLVMIR: store <2 x double> %[[ld]], ptr %2, align 16670end subroutine vec_xl_testf64a671 672!----------------------673! vec_xlds674!----------------------675 676! LLVM-LABEL: @vec_xlds_testi64a677subroutine vec_xlds_testi64a(arg1, arg2, res)678 integer(8) :: arg1679 vector(integer(8)) :: arg2(4)680 vector(integer(8)) :: res681 res = vec_xlds(arg1, arg2)682 683! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8684! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]]685! LLVMIR: %[[ld:.*]] = load i64, ptr %[[addr]], align 8686! LLVMIR: %[[insrt:.*]] = insertelement <2 x i64> poison, i64 %[[ld]], i32 0687! LLVMIR: %[[shfl:.*]] = shufflevector <2 x i64> %[[insrt]], <2 x i64> poison, <2 x i32> zeroinitializer688! LLVMIR: store <2 x i64> %[[shfl]], ptr %2, align 16689end subroutine vec_xlds_testi64a690 691! LLVM-LABEL: @vec_xlds_testf64a692subroutine vec_xlds_testf64a(arg1, arg2, res)693 integer(8) :: arg1694 vector(real(8)) :: arg2(4)695 vector(real(8)) :: res696 res = vec_xlds(arg1, arg2)697 698! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8699! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]]700! LLVMIR: %[[ld:.*]] = load i64, ptr %[[addr]], align 8701! LLVMIR: %[[insrt:.*]] = insertelement <2 x i64> poison, i64 %[[ld]], i32 0702! LLVMIR: %[[shfl:.*]] = shufflevector <2 x i64> %[[insrt]], <2 x i64> poison, <2 x i32> zeroinitializer703! LLVMIR: %[[bc:.*]] = bitcast <2 x i64> %[[shfl]] to <2 x double>704! LLVMIR: store <2 x double> %[[bc]], ptr %2, align 16705end subroutine vec_xlds_testf64a706 707!----------------------708! vec_xl_be709!----------------------710 711! LLVM-LABEL: @vec_xl_be_testi8a712subroutine vec_xl_be_testi8a(arg1, arg2, res)713 integer(1) :: arg1714 integer(1) :: arg2(2, 4, 8)715 vector(integer(1)) :: res716 res = vec_xl_be(arg1, arg2)717 718! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 1719! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]]720! LLVMIR: %[[ld:.*]] = load <16 x i8>, ptr %[[addr]], align 1721! LLVMIR-LE: %[[shff:.*]] = shufflevector <16 x i8> %[[ld]], <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>722! LLVMIR-LE: store <16 x i8> %[[shff]], ptr %2, align 16723! LLVMIR-BE: store <16 x i8> %[[ld]], ptr %2, align 16724end subroutine vec_xl_be_testi8a725 726! LLVM-LABEL: @vec_xl_be_testi16a727subroutine vec_xl_be_testi16a(arg1, arg2, res)728 integer(2) :: arg1729 integer(2) :: arg2(2, 4, 8)730 vector(integer(2)) :: res731 res = vec_xl_be(arg1, arg2)732 733! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2734! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]]735! LLVMIR: %[[ld:.*]] = load <8 x i16>, ptr %[[addr]], align 1736! LLVMIR-LE: %[[shff:.*]] = shufflevector <8 x i16> %[[ld]], <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>737! LLVMIR-LE: store <8 x i16> %[[shff]], ptr %2, align 16738! LLVMIR-BE: store <8 x i16> %[[ld]], ptr %2, align 16739end subroutine vec_xl_be_testi16a740 741! LLVM-LABEL: @vec_xl_be_testi32a742subroutine vec_xl_be_testi32a(arg1, arg2, res)743 integer(4) :: arg1744 integer(4) :: arg2(2, 4, 8)745 vector(integer(4)) :: res746 res = vec_xl_be(arg1, arg2)747 748! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4749! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]]750! LLVMIR: %[[ld:.*]] = load <4 x i32>, ptr %[[addr]], align 1751! LLVMIR-LE: %[[shff:.*]] = shufflevector <4 x i32> %[[ld]], <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>752! LLVMIR-LE: store <4 x i32> %[[shff]], ptr %2, align 16753! LLVMIR-BE: store <4 x i32> %[[ld]], ptr %2, align 16754end subroutine vec_xl_be_testi32a755 756! LLVM-LABEL: @vec_xl_be_testi64a757subroutine vec_xl_be_testi64a(arg1, arg2, res)758 integer(8) :: arg1759 integer(8) :: arg2(2, 4, 8)760 vector(integer(8)) :: res761 res = vec_xl_be(arg1, arg2)762 763! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8764! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]]765! LLVMIR: %[[ld:.*]] = load <2 x i64>, ptr %[[addr]], align 1766! LLVMIR-LE: %[[shff:.*]] = shufflevector <2 x i64> %[[ld]], <2 x i64> undef, <2 x i32> <i32 1, i32 0>767! LLVMIR-LE: store <2 x i64> %[[shff]], ptr %2, align 16768! LLVMIR-BE: store <2 x i64> %[[ld]], ptr %2, align 16769end subroutine vec_xl_be_testi64a770 771! LLVM-LABEL: @vec_xl_be_testf32a772subroutine vec_xl_be_testf32a(arg1, arg2, res)773 integer(2) :: arg1774 real(4) :: arg2(4)775 vector(real(4)) :: res776 res = vec_xl_be(arg1, arg2)777 778! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2779! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]]780! LLVMIR: %[[ld:.*]] = load <4 x float>, ptr %[[addr]], align 1781! LLVMIR-LE: %[[shff:.*]] = shufflevector <4 x float> %[[ld]], <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>782! LLVMIR-LE: store <4 x float> %[[shff]], ptr %2, align 16783! LLVMIR-BE: store <4 x float> %[[ld]], ptr %2, align 16784end subroutine vec_xl_be_testf32a785 786! LLVM-LABEL: @vec_xl_be_testf64a787subroutine vec_xl_be_testf64a(arg1, arg2, res)788 integer(8) :: arg1789 real(8) :: arg2(7)790 vector(real(8)) :: res791 res = vec_xl_be(arg1, arg2)792 793! LLVMIR: %[[arg1:.*]] = load i64, ptr %0, align 8794! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i64 %[[arg1]]795! LLVMIR: %[[ld:.*]] = load <2 x double>, ptr %[[addr]], align 1796! LLVMIR-LE: %[[shff:.*]] = shufflevector <2 x double> %[[ld]], <2 x double> undef, <2 x i32> <i32 1, i32 0>797! LLVMIR-LE: store <2 x double> %[[shff]], ptr %2, align 16798! LLVMIR-BE: store <2 x double> %[[ld]], ptr %2, align 16799end subroutine vec_xl_be_testf64a800 801!----------------------802! vec_xlw4803!----------------------804 805! LLVM-LABEL: @vec_xlw4_testi8a806subroutine vec_xlw4_testi8a(arg1, arg2, res)807 integer(1) :: arg1808 vector(integer(1)) :: arg2(2, 4, 8)809 vector(integer(1)) :: res810 res = vec_xlw4(arg1, arg2)811 812! LLVMIR: %[[arg1:.*]] = load i8, ptr %0, align 1813! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i8 %[[arg1]]814! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.vsx.lxvw4x(ptr %[[addr]])815! LLVMIR: %[[res:.*]] = bitcast <4 x i32> %[[ld]] to <16 x i8>816! LLVMIR: store <16 x i8> %[[res]], ptr %2, align 16817end subroutine vec_xlw4_testi8a818 819! LLVM-LABEL: @vec_xlw4_testi16a820subroutine vec_xlw4_testi16a(arg1, arg2, res)821 integer(2) :: arg1822 vector(integer(2)) :: arg2(2, 4, 8)823 vector(integer(2)) :: res824 res = vec_xlw4(arg1, arg2)825 826! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2827! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]]828! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.vsx.lxvw4x(ptr %[[addr]])829! LLVMIR: %[[res:.*]] = bitcast <4 x i32> %[[ld]] to <8 x i16>830! LLVMIR: store <8 x i16> %[[res]], ptr %2, align 16831end subroutine vec_xlw4_testi16a832 833! LLVM-LABEL: @vec_xlw4_testu32a834subroutine vec_xlw4_testu32a(arg1, arg2, res)835 integer(4) :: arg1836 vector(unsigned(4)) :: arg2(2, 4, 8)837 vector(unsigned(4)) :: res838 res = vec_xlw4(arg1, arg2)839 840! LLVMIR: %[[arg1:.*]] = load i32, ptr %0, align 4841! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i32 %[[arg1]]842! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.vsx.lxvw4x(ptr %[[addr]])843! LLVMIR: store <4 x i32> %[[ld]], ptr %2, align 16844end subroutine vec_xlw4_testu32a845 846! LLVM-LABEL: @vec_xlw4_testf32a847subroutine vec_xlw4_testf32a(arg1, arg2, res)848 integer(2) :: arg1849 vector(real(4)) :: arg2(4)850 vector(real(4)) :: res851 res = vec_xlw4(arg1, arg2)852 853! LLVMIR: %[[arg1:.*]] = load i16, ptr %0, align 2854! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %1, i16 %[[arg1]]855! LLVMIR: %[[ld:.*]] = call <4 x i32> @llvm.ppc.vsx.lxvw4x(ptr %[[addr]])856! LLVMIR: %[[res:.*]] = bitcast <4 x i32> %[[ld]] to <4 x float>857! LLVMIR: store <4 x float> %[[res]], ptr %2, align 16858end subroutine vec_xlw4_testf32a859