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1! RUN: %flang_fc1 -flang-experimental-hlfir -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR" %s2! RUN: %flang_fc1 -flang-experimental-hlfir -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR" %s3! REQUIRES: target=powerpc{{.*}}4 5!----------------------6! vec_sl7!----------------------8 9! CHECK-LABEL: vec_sl_i110subroutine vec_sl_i1(arg1, arg2)11 vector(integer(1)) :: arg1, r12 vector(unsigned(1)) :: arg213 r = vec_sl(arg1, arg2)14 15! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 1616! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 1617! LLVMIR: %[[msk:.*]] = urem <16 x i8> %[[arg2]], splat (i8 8)18! LLVMIR: %7 = shl <16 x i8> %[[arg1]], %[[msk]]19end subroutine vec_sl_i120 21! CHECK-LABEL: vec_sl_i222subroutine vec_sl_i2(arg1, arg2)23 vector(integer(2)) :: arg1, r24 vector(unsigned(2)) :: arg225 r = vec_sl(arg1, arg2)26 27! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 1628! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 1629! LLVMIR: %[[msk:.*]] = urem <8 x i16> %[[arg2]], splat (i16 16)30! LLVMIR: %7 = shl <8 x i16> %[[arg1]], %[[msk]]31end subroutine vec_sl_i232 33! CHECK-LABEL: vec_sl_i434subroutine vec_sl_i4(arg1, arg2)35 vector(integer(4)) :: arg1, r36 vector(unsigned(4)) :: arg237 r = vec_sl(arg1, arg2)38 39! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 1640! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 1641! LLVMIR: %[[msk:.*]] = urem <4 x i32> %[[arg2]], splat (i32 32)42! LLVMIR: %7 = shl <4 x i32> %[[arg1]], %[[msk]]43end subroutine vec_sl_i444 45! CHECK-LABEL: vec_sl_i846subroutine vec_sl_i8(arg1, arg2)47 vector(integer(8)) :: arg1, r48 vector(unsigned(8)) :: arg249 r = vec_sl(arg1, arg2)50 51! LLVMIR: %[[arg1:.*]] = load <2 x i64>, ptr %{{.*}}, align 1652! LLVMIR: %[[arg2:.*]] = load <2 x i64>, ptr %{{.*}}, align 1653! LLVMIR: %[[msk:.*]] = urem <2 x i64> %[[arg2]], splat (i64 64)54! LLVMIR: %7 = shl <2 x i64> %[[arg1]], %[[msk]]55end subroutine vec_sl_i856 57! CHECK-LABEL: vec_sl_u158subroutine vec_sl_u1(arg1, arg2)59 vector(unsigned(1)) :: arg1, r60 vector(unsigned(1)) :: arg261 r = vec_sl(arg1, arg2)62 63! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 1664! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 1665! LLVMIR: %[[msk:.*]] = urem <16 x i8> %[[arg2]], splat (i8 8)66! LLVMIR: %7 = shl <16 x i8> %[[arg1]], %[[msk]]67end subroutine vec_sl_u168 69! CHECK-LABEL: vec_sl_u270subroutine vec_sl_u2(arg1, arg2)71 vector(unsigned(2)) :: arg1, r72 vector(unsigned(2)) :: arg273 r = vec_sl(arg1, arg2)74 75! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 1676! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 1677! LLVMIR: %[[msk:.*]] = urem <8 x i16> %[[arg2]], splat (i16 16)78! LLVMIR: %7 = shl <8 x i16> %[[arg1]], %[[msk]]79end subroutine vec_sl_u280 81! CHECK-LABEL: vec_sl_u482subroutine vec_sl_u4(arg1, arg2)83 vector(unsigned(4)) :: arg1, r84 vector(unsigned(4)) :: arg285 r = vec_sl(arg1, arg2)86 87! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 1688! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 1689! LLVMIR: %[[msk:.*]] = urem <4 x i32> %[[arg2]], splat (i32 32)90! LLVMIR: %7 = shl <4 x i32> %[[arg1]], %[[msk]]91end subroutine vec_sl_u492 93! CHECK-LABEL: vec_sl_u894subroutine vec_sl_u8(arg1, arg2)95 vector(unsigned(8)) :: arg1, r96 vector(unsigned(8)) :: arg297 r = vec_sl(arg1, arg2)98 99! LLVMIR: %[[arg1:.*]] = load <2 x i64>, ptr %{{.*}}, align 16100! LLVMIR: %[[arg2:.*]] = load <2 x i64>, ptr %{{.*}}, align 16101! LLVMIR: %[[msk:.*]] = urem <2 x i64> %[[arg2]], splat (i64 64)102! LLVMIR: %{{[0-9]+}} = shl <2 x i64> %[[arg1]], %[[msk]]103end subroutine vec_sl_u8104 105!----------------------106! vec_sll107!----------------------108! CHECK-LABEL: vec_sll_i1u1109subroutine vec_sll_i1u1(arg1, arg2)110 vector(integer(1)) :: arg1, r111 vector(unsigned(1)) :: arg2112 r = vec_sll(arg1, arg2)113 114! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16115! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16116! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32>117! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>118! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])119! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8>120end subroutine vec_sll_i1u1121 122! CHECK-LABEL: vec_sll_i2u1123subroutine vec_sll_i2u1(arg1, arg2)124 vector(integer(2)) :: arg1, r125 vector(unsigned(1)) :: arg2126 r = vec_sll(arg1, arg2)127 128! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16129! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16130! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32>131! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>132! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])133! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16>134end subroutine vec_sll_i2u1135 136! CHECK-LABEL: vec_sll_i4u1137subroutine vec_sll_i4u1(arg1, arg2)138 vector(integer(4)) :: arg1, r139 vector(unsigned(1)) :: arg2140 r = vec_sll(arg1, arg2)141 142! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16143! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16144! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>145! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]])146end subroutine vec_sll_i4u1147 148! CHECK-LABEL: vec_sll_i1u2149subroutine vec_sll_i1u2(arg1, arg2)150 vector(integer(1)) :: arg1, r151 vector(unsigned(2)) :: arg2152 r = vec_sll(arg1, arg2)153 154! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16155! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16156! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32>157! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>158! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])159! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8>160end subroutine vec_sll_i1u2161 162! CHECK-LABEL: vec_sll_i2u2163subroutine vec_sll_i2u2(arg1, arg2)164 vector(integer(2)) :: arg1, r165 vector(unsigned(2)) :: arg2166 r = vec_sll(arg1, arg2)167 168! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16169! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16170! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32>171! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>172! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])173! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16>174end subroutine vec_sll_i2u2175 176! CHECK-LABEL: vec_sll_i4u2177subroutine vec_sll_i4u2(arg1, arg2)178 vector(integer(4)) :: arg1, r179 vector(unsigned(2)) :: arg2180 r = vec_sll(arg1, arg2)181 182! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16183! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16184! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>185! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]])186end subroutine vec_sll_i4u2187 188! CHECK-LABEL: vec_sll_i1u4189subroutine vec_sll_i1u4(arg1, arg2)190 vector(integer(1)) :: arg1, r191 vector(unsigned(4)) :: arg2192 r = vec_sll(arg1, arg2)193 194! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16195! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16196! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32>197! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[varg1]], <4 x i32> %[[arg2]])198! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8>199end subroutine vec_sll_i1u4200 201! CHECK-LABEL: vec_sll_i2u4202subroutine vec_sll_i2u4(arg1, arg2)203 vector(integer(2)) :: arg1, r204 vector(unsigned(4)) :: arg2205 r = vec_sll(arg1, arg2)206 207! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16208! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16209! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32>210! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[varg1]], <4 x i32> %[[arg2]])211! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16>212end subroutine vec_sll_i2u4213 214! CHECK-LABEL: vec_sll_i4u4215subroutine vec_sll_i4u4(arg1, arg2)216 vector(integer(4)) :: arg1, r217 vector(unsigned(4)) :: arg2218 r = vec_sll(arg1, arg2)219 220! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16221! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16222! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[arg1]], <4 x i32> %[[arg2]])223end subroutine vec_sll_i4u4224 225! CHECK-LABEL: vec_sll_u1u1226subroutine vec_sll_u1u1(arg1, arg2)227 vector(unsigned(1)) :: arg1, r228 vector(unsigned(1)) :: arg2229 r = vec_sll(arg1, arg2)230 231! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16232! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16233! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32>234! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>235! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])236! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8>237end subroutine vec_sll_u1u1238 239! CHECK-LABEL: vec_sll_u2u1240subroutine vec_sll_u2u1(arg1, arg2)241 vector(unsigned(2)) :: arg1, r242 vector(unsigned(1)) :: arg2243 r = vec_sll(arg1, arg2)244 245! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16246! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16247! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32>248! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>249! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])250! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16>251end subroutine vec_sll_u2u1252 253! CHECK-LABEL: vec_sll_u4u1254subroutine vec_sll_u4u1(arg1, arg2)255 vector(unsigned(4)) :: arg1, r256 vector(unsigned(1)) :: arg2257 r = vec_sll(arg1, arg2)258 259! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16260! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16261! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>262! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]])263end subroutine vec_sll_u4u1264 265! CHECK-LABEL: vec_sll_u1u2266subroutine vec_sll_u1u2(arg1, arg2)267 vector(unsigned(1)) :: arg1, r268 vector(unsigned(2)) :: arg2269 r = vec_sll(arg1, arg2)270 271! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16272! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16273! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32>274! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>275! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])276! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8>277end subroutine vec_sll_u1u2278 279! CHECK-LABEL: vec_sll_u2u2280subroutine vec_sll_u2u2(arg1, arg2)281 vector(unsigned(2)) :: arg1, r282 vector(unsigned(2)) :: arg2283 r = vec_sll(arg1, arg2)284 285! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16286! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16287! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32>288! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>289! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])290! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16>291end subroutine vec_sll_u2u2292 293! CHECK-LABEL: vec_sll_u4u2294subroutine vec_sll_u4u2(arg1, arg2)295 vector(unsigned(4)) :: arg1, r296 vector(unsigned(2)) :: arg2297 r = vec_sll(arg1, arg2)298 299! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16300! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16301! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>302! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]])303end subroutine vec_sll_u4u2304 305! CHECK-LABEL: vec_sll_u1u4306subroutine vec_sll_u1u4(arg1, arg2)307 vector(unsigned(1)) :: arg1, r308 vector(unsigned(4)) :: arg2309 r = vec_sll(arg1, arg2)310 311! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16312! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16313! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32>314! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[varg1]], <4 x i32> %[[arg2]])315! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8>316end subroutine vec_sll_u1u4317 318! CHECK-LABEL: vec_sll_u2u4319subroutine vec_sll_u2u4(arg1, arg2)320 vector(unsigned(2)) :: arg1, r321 vector(unsigned(4)) :: arg2322 r = vec_sll(arg1, arg2)323 324! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16325! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16326! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32>327! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[varg1]], <4 x i32> %[[arg2]])328! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16>329end subroutine vec_sll_u2u4330 331! CHECK-LABEL: vec_sll_u4u4332subroutine vec_sll_u4u4(arg1, arg2)333 vector(unsigned(4)) :: arg1, r334 vector(unsigned(4)) :: arg2335 r = vec_sll(arg1, arg2)336 337! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16338! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16339! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[arg1]], <4 x i32> %[[arg2]])340end subroutine vec_sll_u4u4341 342!----------------------343! vec_slo344!----------------------345 346! CHECK-LABEL: vec_slo_i1u1347subroutine vec_slo_i1u1(arg1, arg2)348 vector(integer(1)) :: arg1, r349 vector(unsigned(1)) :: arg2350 r = vec_slo(arg1, arg2)351 352! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16353! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16354! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32>355! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>356! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])357! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8>358end subroutine vec_slo_i1u1359 360! CHECK-LABEL: vec_slo_i2u1361subroutine vec_slo_i2u1(arg1, arg2)362 vector(integer(2)) :: arg1, r363 vector(unsigned(1)) :: arg2364 r = vec_slo(arg1, arg2)365 366! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16367! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16368! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32>369! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>370! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])371! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16>372end subroutine vec_slo_i2u1373 374! CHECK-LABEL: vec_slo_i4u1375subroutine vec_slo_i4u1(arg1, arg2)376 vector(integer(4)) :: arg1, r377 vector(unsigned(1)) :: arg2378 r = vec_slo(arg1, arg2)379 380! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16381! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16382! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>383! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]])384end subroutine vec_slo_i4u1385 386! CHECK-LABEL: vec_slo_u1u1387subroutine vec_slo_u1u1(arg1, arg2)388 vector(unsigned(1)) :: arg1, r389 vector(unsigned(1)) :: arg2390 r = vec_slo(arg1, arg2)391 392! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16393! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16394! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32>395! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>396! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])397! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8>398end subroutine vec_slo_u1u1399 400! CHECK-LABEL: vec_slo_u2u1401subroutine vec_slo_u2u1(arg1, arg2)402 vector(unsigned(2)) :: arg1, r403 vector(unsigned(1)) :: arg2404 r = vec_slo(arg1, arg2)405 406! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16407! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16408! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32>409! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>410! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])411! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16>412end subroutine vec_slo_u2u1413 414! CHECK-LABEL: vec_slo_u4u1415subroutine vec_slo_u4u1(arg1, arg2)416 vector(unsigned(4)) :: arg1, r417 vector(unsigned(1)) :: arg2418 r = vec_slo(arg1, arg2)419 420! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16421! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16422! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>423! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]])424end subroutine vec_slo_u4u1425 426! CHECK-LABEL: vec_slo_r4u1427subroutine vec_slo_r4u1(arg1, arg2)428 vector(real(4)) :: arg1, r429 vector(unsigned(1)) :: arg2430 r = vec_slo(arg1, arg2)431 432! LLVMIR: %[[arg1:.*]] = load <4 x float>, ptr %{{.*}}, align 16433! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16434! LLVMIR: %[[varg1:.*]] = bitcast <4 x float> %[[arg1]] to <4 x i32>435! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>436! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])437! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <4 x float>438end subroutine vec_slo_r4u1439 440! CHECK-LABEL: vec_slo_i1u2441subroutine vec_slo_i1u2(arg1, arg2)442 vector(integer(1)) :: arg1, r443 vector(unsigned(2)) :: arg2444 r = vec_slo(arg1, arg2)445 446! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16447! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16448! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32>449! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>450! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])451! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8>452end subroutine vec_slo_i1u2453 454! CHECK-LABEL: vec_slo_i2u2455subroutine vec_slo_i2u2(arg1, arg2)456 vector(integer(2)) :: arg1, r457 vector(unsigned(2)) :: arg2458 r = vec_slo(arg1, arg2)459 460! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16461! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16462! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32>463! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>464! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])465! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16>466end subroutine vec_slo_i2u2467 468! CHECK-LABEL: vec_slo_i4u2469subroutine vec_slo_i4u2(arg1, arg2)470 vector(integer(4)) :: arg1, r471 vector(unsigned(2)) :: arg2472 r = vec_slo(arg1, arg2)473 474! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16475! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16476! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>477! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]])478end subroutine vec_slo_i4u2479 480! CHECK-LABEL: vec_slo_u1u2481subroutine vec_slo_u1u2(arg1, arg2)482 vector(unsigned(1)) :: arg1, r483 vector(unsigned(2)) :: arg2484 r = vec_slo(arg1, arg2)485 486! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16487! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16488! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32>489! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>490! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])491! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8>492end subroutine vec_slo_u1u2493 494! CHECK-LABEL: vec_slo_u2u2495subroutine vec_slo_u2u2(arg1, arg2)496 vector(unsigned(2)) :: arg1, r497 vector(unsigned(2)) :: arg2498 r = vec_slo(arg1, arg2)499 500! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16501! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16502! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32>503! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>504! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])505! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16>506 507end subroutine vec_slo_u2u2508 509! CHECK-LABEL: vec_slo_u4u2510subroutine vec_slo_u4u2(arg1, arg2)511 vector(unsigned(4)) :: arg1, r512 vector(unsigned(2)) :: arg2513 r = vec_slo(arg1, arg2)514 515! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16516! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16517! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>518! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]])519end subroutine vec_slo_u4u2520 521! CHECK-LABEL: vec_slo_r4u2522subroutine vec_slo_r4u2(arg1, arg2)523 vector(real(4)) :: arg1, r524 vector(unsigned(2)) :: arg2525 r = vec_slo(arg1, arg2)526 527! LLVMIR: %[[arg1:.*]] = load <4 x float>, ptr %{{.*}}, align 16528! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16529! LLVMIR: %[[varg1:.*]] = bitcast <4 x float> %[[arg1]] to <4 x i32>530! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>531! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])532! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <4 x float>533end subroutine vec_slo_r4u2534 535!----------------------536! vec_sr537!----------------------538! CHECK-LABEL: vec_sr_i1539subroutine vec_sr_i1(arg1, arg2)540 vector(integer(1)) :: arg1, r541 vector(unsigned(1)) :: arg2542 r = vec_sr(arg1, arg2)543 544! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16545! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16546! LLVMIR: %[[msk:.*]] = urem <16 x i8> %[[arg2]], splat (i8 8)547! LLVMIR: %7 = lshr <16 x i8> %[[arg1]], %[[msk]]548end subroutine vec_sr_i1549 550! CHECK-LABEL: vec_sr_i2551subroutine vec_sr_i2(arg1, arg2)552 vector(integer(2)) :: arg1, r553 vector(unsigned(2)) :: arg2554 r = vec_sr(arg1, arg2)555 556! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16557! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16558! LLVMIR: %[[msk:.*]] = urem <8 x i16> %[[arg2]], splat (i16 16)559! LLVMIR: %7 = lshr <8 x i16> %[[arg1]], %[[msk]]560end subroutine vec_sr_i2561 562! CHECK-LABEL: vec_sr_i4563subroutine vec_sr_i4(arg1, arg2)564 vector(integer(4)) :: arg1, r565 vector(unsigned(4)) :: arg2566 r = vec_sr(arg1, arg2)567 568! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16569! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16570! LLVMIR: %[[msk:.*]] = urem <4 x i32> %[[arg2]], splat (i32 32)571! LLVMIR: %7 = lshr <4 x i32> %[[arg1]], %[[msk]]572end subroutine vec_sr_i4573 574! CHECK-LABEL: vec_sr_i8575subroutine vec_sr_i8(arg1, arg2)576 vector(integer(8)) :: arg1, r577 vector(unsigned(8)) :: arg2578 r = vec_sr(arg1, arg2)579 580! LLVMIR: %[[arg1:.*]] = load <2 x i64>, ptr %{{.*}}, align 16581! LLVMIR: %[[arg2:.*]] = load <2 x i64>, ptr %{{.*}}, align 16582! LLVMIR: %[[msk:.*]] = urem <2 x i64> %[[arg2]], splat (i64 64)583! LLVMIR: %7 = lshr <2 x i64> %[[arg1]], %[[msk]]584end subroutine vec_sr_i8585 586! CHECK-LABEL: vec_sr_u1587subroutine vec_sr_u1(arg1, arg2)588 vector(unsigned(1)) :: arg1, r589 vector(unsigned(1)) :: arg2590 r = vec_sr(arg1, arg2)591 592! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16593! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16594! LLVMIR: %[[msk:.*]] = urem <16 x i8> %[[arg2]], splat (i8 8)595! LLVMIR: %7 = lshr <16 x i8> %[[arg1]], %[[msk]]596end subroutine vec_sr_u1597 598! CHECK-LABEL: vec_sr_u2599subroutine vec_sr_u2(arg1, arg2)600 vector(unsigned(2)) :: arg1, r601 vector(unsigned(2)) :: arg2602 r = vec_sr(arg1, arg2)603 604! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16605! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16606! LLVMIR: %[[msk:.*]] = urem <8 x i16> %[[arg2]], splat (i16 16)607! LLVMIR: %7 = lshr <8 x i16> %[[arg1]], %[[msk]]608end subroutine vec_sr_u2609 610! CHECK-LABEL: vec_sr_u4611subroutine vec_sr_u4(arg1, arg2)612 vector(unsigned(4)) :: arg1, r613 vector(unsigned(4)) :: arg2614 r = vec_sr(arg1, arg2)615 616! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16617! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16618! LLVMIR: %[[msk:.*]] = urem <4 x i32> %[[arg2]], splat (i32 32)619! LLVMIR: %7 = lshr <4 x i32> %[[arg1]], %[[msk]]620end subroutine vec_sr_u4621 622! CHECK-LABEL: vec_sr_u8623subroutine vec_sr_u8(arg1, arg2)624 vector(unsigned(8)) :: arg1, r625 vector(unsigned(8)) :: arg2626 r = vec_sr(arg1, arg2)627 628! LLVMIR: %[[arg1:.*]] = load <2 x i64>, ptr %{{.*}}, align 16629! LLVMIR: %[[arg2:.*]] = load <2 x i64>, ptr %{{.*}}, align 16630! LLVMIR: %[[msk:.*]] = urem <2 x i64> %[[arg2]], splat (i64 64)631! LLVMIR: %7 = lshr <2 x i64> %[[arg1]], %[[msk]]632end subroutine vec_sr_u8633 634!----------------------635! vec_srl636!----------------------637! CHECK-LABEL: vec_srl_i1u1638subroutine vec_srl_i1u1(arg1, arg2)639 vector(integer(1)) :: arg1, r640 vector(unsigned(1)) :: arg2641 r = vec_srl(arg1, arg2)642 643! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16644! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16645! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32>646! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>647! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])648! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8>649end subroutine vec_srl_i1u1650 651! CHECK-LABEL: vec_srl_i2u1652subroutine vec_srl_i2u1(arg1, arg2)653 vector(integer(2)) :: arg1, r654 vector(unsigned(1)) :: arg2655 r = vec_srl(arg1, arg2)656 657! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16658! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16659! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32>660! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>661! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])662! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16>663end subroutine vec_srl_i2u1664 665! CHECK-LABEL: vec_srl_i4u1666subroutine vec_srl_i4u1(arg1, arg2)667 vector(integer(4)) :: arg1, r668 vector(unsigned(1)) :: arg2669 r = vec_srl(arg1, arg2)670 671! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16672! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16673! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>674! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]])675end subroutine vec_srl_i4u1676 677! CHECK-LABEL: vec_srl_i1u2678subroutine vec_srl_i1u2(arg1, arg2)679 vector(integer(1)) :: arg1, r680 vector(unsigned(2)) :: arg2681 r = vec_srl(arg1, arg2)682 683! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16684! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16685! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32>686! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>687! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])688! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8>689end subroutine vec_srl_i1u2690 691! CHECK-LABEL: vec_srl_i2u2692subroutine vec_srl_i2u2(arg1, arg2)693 vector(integer(2)) :: arg1, r694 vector(unsigned(2)) :: arg2695 r = vec_srl(arg1, arg2)696 697! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16698! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16699! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32>700! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>701! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])702! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16>703end subroutine vec_srl_i2u2704 705! CHECK-LABEL: vec_srl_i4u2706subroutine vec_srl_i4u2(arg1, arg2)707 vector(integer(4)) :: arg1, r708 vector(unsigned(2)) :: arg2709 r = vec_srl(arg1, arg2)710 711! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16712! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16713! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>714! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]])715end subroutine vec_srl_i4u2716 717! CHECK-LABEL: vec_srl_i1u4718subroutine vec_srl_i1u4(arg1, arg2)719 vector(integer(1)) :: arg1, r720 vector(unsigned(4)) :: arg2721 r = vec_srl(arg1, arg2)722 723! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16724! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16725! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32>726! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[varg1]], <4 x i32> %[[arg2]])727! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8>728end subroutine vec_srl_i1u4729 730! CHECK-LABEL: vec_srl_i2u4731subroutine vec_srl_i2u4(arg1, arg2)732 vector(integer(2)) :: arg1, r733 vector(unsigned(4)) :: arg2734 r = vec_srl(arg1, arg2)735 736! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16737! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16738! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32>739! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[varg1]], <4 x i32> %[[arg2]])740! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16>741end subroutine vec_srl_i2u4742 743! CHECK-LABEL: vec_srl_i4u4744subroutine vec_srl_i4u4(arg1, arg2)745 vector(integer(4)) :: arg1, r746 vector(unsigned(4)) :: arg2747 r = vec_srl(arg1, arg2)748 749! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16750! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16751! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[arg1]], <4 x i32> %[[arg2]])752end subroutine vec_srl_i4u4753 754! CHECK-LABEL: vec_srl_u1u1755subroutine vec_srl_u1u1(arg1, arg2)756 vector(unsigned(1)) :: arg1, r757 vector(unsigned(1)) :: arg2758 r = vec_srl(arg1, arg2)759 760! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16761! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16762! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32>763! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>764! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])765! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8>766end subroutine vec_srl_u1u1767 768! CHECK-LABEL: vec_srl_u2u1769subroutine vec_srl_u2u1(arg1, arg2)770 vector(unsigned(2)) :: arg1, r771 vector(unsigned(1)) :: arg2772 r = vec_srl(arg1, arg2)773 774! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16775! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16776! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32>777! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>778! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])779! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16>780end subroutine vec_srl_u2u1781 782! CHECK-LABEL: vec_srl_u4u1783subroutine vec_srl_u4u1(arg1, arg2)784 vector(unsigned(4)) :: arg1, r785 vector(unsigned(1)) :: arg2786 r = vec_srl(arg1, arg2)787 788! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16789! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16790! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>791! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]])792end subroutine vec_srl_u4u1793 794! CHECK-LABEL: vec_srl_u1u2795subroutine vec_srl_u1u2(arg1, arg2)796 vector(unsigned(1)) :: arg1, r797 vector(unsigned(2)) :: arg2798 r = vec_srl(arg1, arg2)799 800! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16801! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16802! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32>803! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>804! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])805! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8>806end subroutine vec_srl_u1u2807 808! CHECK-LABEL: vec_srl_u2u2809subroutine vec_srl_u2u2(arg1, arg2)810 vector(unsigned(2)) :: arg1, r811 vector(unsigned(2)) :: arg2812 r = vec_srl(arg1, arg2)813 814! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16815! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16816! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32>817! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>818! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])819! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16>820end subroutine vec_srl_u2u2821 822! CHECK-LABEL: vec_srl_u4u2823subroutine vec_srl_u4u2(arg1, arg2)824 vector(unsigned(4)) :: arg1, r825 vector(unsigned(2)) :: arg2826 r = vec_srl(arg1, arg2)827 828! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16829! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16830! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>831! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]])832end subroutine vec_srl_u4u2833 834! CHECK-LABEL: vec_srl_u1u4835subroutine vec_srl_u1u4(arg1, arg2)836 vector(unsigned(1)) :: arg1, r837 vector(unsigned(4)) :: arg2838 r = vec_srl(arg1, arg2)839 840! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16841! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16842! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32>843! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[varg1]], <4 x i32> %[[arg2]])844! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8>845end subroutine vec_srl_u1u4846 847! CHECK-LABEL: vec_srl_u2u4848subroutine vec_srl_u2u4(arg1, arg2)849 vector(unsigned(2)) :: arg1, r850 vector(unsigned(4)) :: arg2851 r = vec_srl(arg1, arg2)852 853! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16854! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16855! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32>856! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[varg1]], <4 x i32> %[[arg2]])857! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16>858end subroutine vec_srl_u2u4859 860! CHECK-LABEL: vec_srl_u4u4861subroutine vec_srl_u4u4(arg1, arg2)862 vector(unsigned(4)) :: arg1, r863 vector(unsigned(4)) :: arg2864 r = vec_srl(arg1, arg2)865 866! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16867! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16868! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[arg1]], <4 x i32> %[[arg2]])869end subroutine vec_srl_u4u4870 871!----------------------872! vec_sro873!----------------------874 875! CHECK-LABEL: vec_sro_i1u1876subroutine vec_sro_i1u1(arg1, arg2)877 vector(integer(1)) :: arg1, r878 vector(unsigned(1)) :: arg2879 r = vec_sro(arg1, arg2)880 881! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16882! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16883! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32>884! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>885! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])886! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8>887end subroutine vec_sro_i1u1888 889! CHECK-LABEL: vec_sro_i2u1890subroutine vec_sro_i2u1(arg1, arg2)891 vector(integer(2)) :: arg1, r892 vector(unsigned(1)) :: arg2893 r = vec_sro(arg1, arg2)894 895! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16896! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16897! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32>898! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>899! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])900! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16>901end subroutine vec_sro_i2u1902 903! CHECK-LABEL: vec_sro_i4u1904subroutine vec_sro_i4u1(arg1, arg2)905 vector(integer(4)) :: arg1, r906 vector(unsigned(1)) :: arg2907 r = vec_sro(arg1, arg2)908 909! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16910! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16911! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>912! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]])913end subroutine vec_sro_i4u1914 915! CHECK-LABEL: vec_sro_u1u1916subroutine vec_sro_u1u1(arg1, arg2)917 vector(unsigned(1)) :: arg1, r918 vector(unsigned(1)) :: arg2919 r = vec_sro(arg1, arg2)920 921! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16922! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16923! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32>924! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>925! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])926! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8>927end subroutine vec_sro_u1u1928 929! CHECK-LABEL: vec_sro_u2u1930subroutine vec_sro_u2u1(arg1, arg2)931 vector(unsigned(2)) :: arg1, r932 vector(unsigned(1)) :: arg2933 r = vec_sro(arg1, arg2)934 935! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16936! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16937! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32>938! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>939! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])940! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16>941end subroutine vec_sro_u2u1942 943! CHECK-LABEL: vec_sro_u4u1944subroutine vec_sro_u4u1(arg1, arg2)945 vector(unsigned(4)) :: arg1, r946 vector(unsigned(1)) :: arg2947 r = vec_sro(arg1, arg2)948 949! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16950! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16951! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>952! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]])953end subroutine vec_sro_u4u1954 955! CHECK-LABEL: vec_sro_r4u1956subroutine vec_sro_r4u1(arg1, arg2)957 vector(real(4)) :: arg1, r958 vector(unsigned(1)) :: arg2959 r = vec_sro(arg1, arg2)960 961! LLVMIR: %[[arg1:.*]] = load <4 x float>, ptr %{{.*}}, align 16962! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16963! LLVMIR: %[[varg1:.*]] = bitcast <4 x float> %[[arg1]] to <4 x i32>964! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>965! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])966! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <4 x float>967end subroutine vec_sro_r4u1968 969!-------------------------------------970 971! CHECK-LABEL: vec_sro_i1u2972subroutine vec_sro_i1u2(arg1, arg2)973 vector(integer(1)) :: arg1, r974 vector(unsigned(2)) :: arg2975 r = vec_sro(arg1, arg2)976 977! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16978! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16979! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32>980! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>981! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])982! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8>983end subroutine vec_sro_i1u2984 985! CHECK-LABEL: vec_sro_i2u2986subroutine vec_sro_i2u2(arg1, arg2)987 vector(integer(2)) :: arg1, r988 vector(unsigned(2)) :: arg2989 r = vec_sro(arg1, arg2)990 991! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16992! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16993! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32>994! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>995! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])996! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16>997end subroutine vec_sro_i2u2998 999! CHECK-LABEL: vec_sro_i4u21000subroutine vec_sro_i4u2(arg1, arg2)1001 vector(integer(4)) :: arg1, r1002 vector(unsigned(2)) :: arg21003 r = vec_sro(arg1, arg2)1004 1005! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 161006! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 161007! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>1008! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]])1009end subroutine vec_sro_i4u21010 1011! CHECK-LABEL: vec_sro_u1u21012subroutine vec_sro_u1u2(arg1, arg2)1013 vector(unsigned(1)) :: arg1, r1014 vector(unsigned(2)) :: arg21015 r = vec_sro(arg1, arg2)1016 1017! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 161018! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 161019! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32>1020! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>1021! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])1022! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8>1023end subroutine vec_sro_u1u21024 1025! CHECK-LABEL: vec_sro_u2u21026subroutine vec_sro_u2u2(arg1, arg2)1027 vector(unsigned(2)) :: arg1, r1028 vector(unsigned(2)) :: arg21029 r = vec_sro(arg1, arg2)1030 1031! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 161032! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 161033! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32>1034! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>1035! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])1036! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16>1037 1038end subroutine vec_sro_u2u21039 1040! CHECK-LABEL: vec_sro_u4u21041subroutine vec_sro_u4u2(arg1, arg2)1042 vector(unsigned(4)) :: arg1, r1043 vector(unsigned(2)) :: arg21044 r = vec_sro(arg1, arg2)1045 1046! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 161047! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 161048! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>1049! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]])1050end subroutine vec_sro_u4u21051 1052! CHECK-LABEL: vec_sro_r4u21053subroutine vec_sro_r4u2(arg1, arg2)1054 vector(real(4)) :: arg1, r1055 vector(unsigned(2)) :: arg21056 r = vec_sro(arg1, arg2)1057 1058! LLVMIR: %[[arg1:.*]] = load <4 x float>, ptr %{{.*}}, align 161059! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 161060! LLVMIR: %[[varg1:.*]] = bitcast <4 x float> %[[arg1]] to <4 x i32>1061! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32>1062! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]])1063! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <4 x float>1064end subroutine vec_sro_r4u21065