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1//===-- riscv floating point env manipulation functions ---------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_FENVIMPL_H10#define LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_FENVIMPL_H11 12#include "hdr/fenv_macros.h"13#include "hdr/stdint_proxy.h"14#include "hdr/types/fenv_t.h"15#include "src/__support/FPUtil/FPBits.h"16#include "src/__support/macros/attributes.h" // For LIBC_INLINE_ASM17#include "src/__support/macros/config.h" // For LIBC_INLINE18 19namespace LIBC_NAMESPACE_DECL {20namespace fputil {21 22struct FEnv {23 // We will ignore RMM and DYN rounding modes.24 static constexpr uint32_t TONEAREST = 0x0;25 static constexpr uint32_t TOWARDZERO = 0x1;26 static constexpr uint32_t DOWNWARD = 0x2;27 static constexpr uint32_t UPWARD = 0x3;28 29 // These are the bit locations of the corresponding exceptions in fcsr.30 static constexpr uint32_t INEXACT = 0x1;31 static constexpr uint32_t UNDERFLOW = 0x2;32 static constexpr uint32_t OVERFLOW = 0x4;33 static constexpr uint32_t DIVBYZERO = 0x8;34 static constexpr uint32_t INVALID = 0x10;35 36 LIBC_INLINE static uint32_t get_frm() {37 unsigned int rm;38 LIBC_INLINE_ASM("frrm %0\n\t" : "=r"(rm));39 return rm;40 }41 42 LIBC_INLINE static void set_frm(uint32_t rm) {43 LIBC_INLINE_ASM("fsrm %0, %0\n\t" : "+r"(rm));44 }45 46 LIBC_INLINE static uint32_t get_fflags() {47 unsigned int flags;48 LIBC_INLINE_ASM("frflags %0\n\t" : "=r"(flags));49 return flags;50 }51 52 LIBC_INLINE static void set_fflags(uint32_t flags) {53 LIBC_INLINE_ASM("fsflags %0, %0\n\t" : "+r"(flags));54 }55 56 LIBC_INLINE static uint32_t get_fcsr() {57 unsigned int fcsr;58 LIBC_INLINE_ASM("frcsr %0\n\t" : "=r"(fcsr));59 return fcsr;60 }61 62 LIBC_INLINE static void set_fcsr(uint32_t fcsr) {63 LIBC_INLINE_ASM("fscsr %0, %0\n\t" : "+r"(fcsr));64 }65 66 LIBC_INLINE static int exception_bits_to_macro(uint32_t status) {67 return ((status & INVALID) ? FE_INVALID : 0) |68 ((status & DIVBYZERO) ? FE_DIVBYZERO : 0) |69 ((status & OVERFLOW) ? FE_OVERFLOW : 0) |70 ((status & UNDERFLOW) ? FE_UNDERFLOW : 0) |71 ((status & INEXACT) ? FE_INEXACT : 0);72 }73 74 LIBC_INLINE static uint32_t exception_macro_to_bits(int except) {75 return ((except & FE_INVALID) ? INVALID : 0) |76 ((except & FE_DIVBYZERO) ? DIVBYZERO : 0) |77 ((except & FE_OVERFLOW) ? OVERFLOW : 0) |78 ((except & FE_UNDERFLOW) ? UNDERFLOW : 0) |79 ((except & FE_INEXACT) ? INEXACT : 0);80 }81};82 83// Since RISCV does not have exception enable bits, we will just return84// the failure indicator.85LIBC_INLINE int enable_except(int) { return -1; }86 87// Always succeed.88LIBC_INLINE int disable_except(int) { return 0; }89 90// Always return "no exceptions enabled".91LIBC_INLINE int get_except() { return 0; }92 93LIBC_INLINE int clear_except(int excepts) {94 uint32_t flags = FEnv::get_fflags();95 uint32_t to_clear = FEnv::exception_macro_to_bits(excepts);96 flags &= ~to_clear;97 FEnv::set_fflags(flags);98 return 0;99}100 101LIBC_INLINE int test_except(int excepts) {102 uint32_t to_test = FEnv::exception_macro_to_bits(excepts);103 uint32_t flags = FEnv::get_fflags();104 return FEnv::exception_bits_to_macro(flags & to_test);105}106 107LIBC_INLINE int set_except(int excepts) {108 uint32_t flags = FEnv::get_fflags();109 FEnv::set_fflags(flags | FEnv::exception_macro_to_bits(excepts));110 return 0;111}112 113LIBC_INLINE int raise_except(int excepts) {114 // Since there are no traps, we just set the exception flags.115 uint32_t flags = FEnv::get_fflags();116 FEnv::set_fflags(flags | FEnv::exception_macro_to_bits(excepts));117 return 0;118}119 120LIBC_INLINE int get_round() {121 uint32_t rm = FEnv::get_frm();122 switch (rm) {123 case FEnv::TONEAREST:124 return FE_TONEAREST;125 case FEnv::DOWNWARD:126 return FE_DOWNWARD;127 case FEnv::UPWARD:128 return FE_UPWARD;129 case FEnv::TOWARDZERO:130 return FE_TOWARDZERO;131 default:132 return -1; // Error value.133 }134 return 0;135}136 137LIBC_INLINE int set_round(int mode) {138 uint32_t rm;139 switch (mode) {140 case FE_TONEAREST:141 rm = FEnv::TONEAREST;142 break;143 case FE_DOWNWARD:144 rm = FEnv::DOWNWARD;145 break;146 case FE_UPWARD:147 rm = FEnv::UPWARD;148 break;149 case FE_TOWARDZERO:150 rm = FEnv::TOWARDZERO;151 break;152 default:153 return -1; // To indicate failure154 }155 FEnv::set_frm(rm);156 return 0;157}158 159LIBC_INLINE int get_env(fenv_t *envp) {160 uint32_t *state = reinterpret_cast<uint32_t *>(envp);161 *state = FEnv::get_fcsr();162 return 0;163}164 165LIBC_INLINE int set_env(const fenv_t *envp) {166 if (envp == FE_DFL_ENV) {167 FEnv::set_frm(FEnv::TONEAREST);168 FEnv::set_fflags(0);169 return 0;170 }171 uint32_t status = *reinterpret_cast<const uint32_t *>(envp);172 // We have to do the masking to preserve the reserved bits.173 FEnv::set_fcsr((status & 0xFF) | (FEnv::get_fcsr() & 0xFFFFFF00));174 return 0;175}176 177} // namespace fputil178} // namespace LIBC_NAMESPACE_DECL179 180#endif // LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_FENVIMPL_H181