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1//===-- Compile time cpu feature detection ----------------------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8// This file lists target cpu features by introspecting compiler enabled9// preprocessor definitions.10//===----------------------------------------------------------------------===//11 12#ifndef LLVM_LIBC_SRC___SUPPORT_MACROS_PROPERTIES_CPU_FEATURES_H13#define LLVM_LIBC_SRC___SUPPORT_MACROS_PROPERTIES_CPU_FEATURES_H14 15#include "architectures.h"16 17#if defined(__ARM_FEATURE_FP16_SCALAR_ARITHMETIC)18#define LIBC_TARGET_CPU_HAS_FULLFP1619#endif20 21#if defined(__ARM_FEATURE_SVE)22#define LIBC_TARGET_CPU_HAS_SVE23#endif24 25#if defined(__ARM_FEATURE_SVE2)26#define LIBC_TARGET_CPU_HAS_SVE227#endif28 29#if defined(__ARM_FEATURE_MOPS)30#define LIBC_TARGET_CPU_HAS_MOPS31#endif32 33#if defined(__SSE2__)34#define LIBC_TARGET_CPU_HAS_SSE235#define LIBC_TARGET_CPU_HAS_FPU_FLOAT36#define LIBC_TARGET_CPU_HAS_FPU_DOUBLE37#endif38 39#if defined(__SSE4_2__)40#define LIBC_TARGET_CPU_HAS_SSE4_241#endif42 43#if defined(__AVX__)44#define LIBC_TARGET_CPU_HAS_AVX45#endif46 47#if defined(__AVX2__)48#define LIBC_TARGET_CPU_HAS_AVX249#endif50 51#if defined(__AVX512F__)52#define LIBC_TARGET_CPU_HAS_AVX512F53#endif54 55#if defined(__AVX512BW__)56#define LIBC_TARGET_CPU_HAS_AVX512BW57#endif58 59#if defined(__ARM_FP)60#if (__ARM_FP & 0x2)61#define LIBC_TARGET_CPU_HAS_ARM_FPU_HALF62#define LIBC_TARGET_CPU_HAS_FPU_HALF63#endif // LIBC_TARGET_CPU_HAS_ARM_FPU_HALF64#if (__ARM_FP & 0x4)65#define LIBC_TARGET_CPU_HAS_ARM_FPU_FLOAT66#define LIBC_TARGET_CPU_HAS_FPU_FLOAT67#endif // LIBC_TARGET_CPU_HAS_ARM_FPU_FLOAT68#if (__ARM_FP & 0x8)69#define LIBC_TARGET_CPU_HAS_ARM_FPU_DOUBLE70#define LIBC_TARGET_CPU_HAS_FPU_DOUBLE71#endif // LIBC_TARGET_CPU_HAS_ARM_FPU_DOUBLE72#endif // __ARM_FP73 74#if defined(__ARM_NEON)75#define LIBC_TARGET_CPU_HAS_ARM_NEON76#endif77 78#if defined(__riscv_flen)79// https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc80#if defined(__riscv_zfhmin)81#define LIBC_TARGET_CPU_HAS_RISCV_FPU_HALF82#define LIBC_TARGET_CPU_HAS_FPU_HALF83#endif // LIBC_TARGET_CPU_HAS_RISCV_FPU_HALF84#if (__riscv_flen >= 32)85#define LIBC_TARGET_CPU_HAS_RISCV_FPU_FLOAT86#define LIBC_TARGET_CPU_HAS_FPU_FLOAT87#endif // LIBC_TARGET_CPU_HAS_RISCV_FPU_FLOAT88#if (__riscv_flen >= 64)89#define LIBC_TARGET_CPU_HAS_RISCV_FPU_DOUBLE90#define LIBC_TARGET_CPU_HAS_FPU_DOUBLE91#endif // LIBC_TARGET_CPU_HAS_RISCV_FPU_DOUBLE92#endif // __riscv_flen93 94#if defined(__NVPTX__) || defined(__AMDGPU__)95#define LIBC_TARGET_CPU_HAS_FPU_FLOAT96#define LIBC_TARGET_CPU_HAS_FPU_DOUBLE97#endif98 99#if defined(__ARM_FEATURE_FMA) || (defined(__AVX2__) && defined(__FMA__)) || \100 defined(__NVPTX__) || defined(__AMDGPU__) || defined(__riscv_flen)101#define LIBC_TARGET_CPU_HAS_FMA102// Provide a more fine-grained control of FMA instruction for ARM targets.103#if defined(LIBC_TARGET_CPU_HAS_FPU_HALF)104#define LIBC_TARGET_CPU_HAS_FMA_HALF105#endif // LIBC_TARGET_CPU_HAS_FMA_HALF106#if defined(LIBC_TARGET_CPU_HAS_FPU_FLOAT)107#define LIBC_TARGET_CPU_HAS_FMA_FLOAT108#endif // LIBC_TARGET_CPU_HAS_FMA_FLOAT109#if defined(LIBC_TARGET_CPU_HAS_FPU_DOUBLE)110#define LIBC_TARGET_CPU_HAS_FMA_DOUBLE111#endif // LIBC_TARGET_CPU_HAS_FMA_DOUBLE112#endif113 114#if defined(LIBC_TARGET_ARCH_IS_AARCH64) || \115 (defined(LIBC_TARGET_ARCH_IS_X86_64) && \116 defined(LIBC_TARGET_CPU_HAS_SSE4_2))117#define LIBC_TARGET_CPU_HAS_NEAREST_INT118#endif119 120#if defined(LIBC_TARGET_ARCH_IS_AARCH64) || defined(LIBC_TARGET_ARCH_IS_GPU)121#define LIBC_TARGET_CPU_HAS_FAST_FLOAT16_OPS122#endif123 124#endif // LLVM_LIBC_SRC___SUPPORT_MACROS_PROPERTIES_CPU_FEATURES_H125