1410 lines · c
1//===----------------------------------------------------------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//8// Compatible with libunwind API documented at:9// http://www.nongnu.org/libunwind/man/libunwind(3).html10//11//===----------------------------------------------------------------------===//12 13#ifndef __LIBUNWIND__14#define __LIBUNWIND__15 16#include <__libunwind_config.h>17 18#include <stdint.h>19#include <stddef.h>20 21#ifdef __APPLE__22 #if __clang__23 #if __has_include(<Availability.h>)24 #include <Availability.h>25 #endif26 #elif __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ >= 105027 #include <Availability.h>28 #endif29 30 #ifdef __arm__31 #define LIBUNWIND_AVAIL __attribute__((unavailable))32 #elif defined(__OSX_AVAILABLE_STARTING)33 #define LIBUNWIND_AVAIL __OSX_AVAILABLE_STARTING(__MAC_10_6, __IPHONE_5_0)34 #else35 #include <AvailabilityMacros.h>36 #ifdef AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER37 #define LIBUNWIND_AVAIL AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER38 #else39 #define LIBUNWIND_AVAIL __attribute__((unavailable))40 #endif41 #endif42#else43 #define LIBUNWIND_AVAIL44#endif45 46#if defined(_LIBUNWIND_TARGET_AARCH64_AUTHENTICATED_UNWINDING)47 48 #include <ptrauth.h>49 50 // `__ptrauth_restricted_intptr` is a feature of apple clang that predates51 // support for direct application of `__ptrauth` to integer types. This52 // guard is necessary to support compilation with those compiler.53 #if __has_extension(ptrauth_restricted_intptr_qualifier)54 #define __unwind_ptrauth_restricted_intptr(...) \55 __ptrauth_restricted_intptr(__VA_ARGS__)56 #else57 #define __unwind_ptrauth_restricted_intptr(...) \58 __ptrauth(__VA_ARGS__)59 #endif60 61 // ptrauth_string_discriminator("unw_proc_info_t::handler") == 0x740562 #define __ptrauth_unwind_upi_handler_disc 0x740563 64 #define __ptrauth_unwind_upi_handler \65 __ptrauth(ptrauth_key_function_pointer, 1, __ptrauth_unwind_upi_handler_disc)66 67 #define __ptrauth_unwind_upi_handler_intptr \68 __unwind_ptrauth_restricted_intptr(ptrauth_key_function_pointer, 1,\69 __ptrauth_unwind_upi_handler_disc)70 71 // ptrauth_string_discriminator("unw_proc_info_t::start_ip") == 0xCA2C72 #define __ptrauth_unwind_upi_startip \73 __unwind_ptrauth_restricted_intptr(ptrauth_key_process_independent_code, 1, 0xCA2C)74 75 // ptrauth_string_discriminator("unw_proc_info_t::end_ip") == 0xE18376 #define __ptrauth_unwind_upi_endip \77 __unwind_ptrauth_restricted_intptr(ptrauth_key_process_independent_code, 1, 0xE183)78 79 // ptrauth_string_discriminator("unw_proc_info_t::lsda") == 0x83DE80 #define __ptrauth_unwind_upi_lsda \81 __unwind_ptrauth_restricted_intptr(ptrauth_key_process_dependent_data, 1, 0x83DE)82 83 // ptrauth_string_discriminator("unw_proc_info_t::flags") == 0x79A184 #define __ptrauth_unwind_upi_flags \85 __unwind_ptrauth_restricted_intptr(ptrauth_key_process_dependent_data, 1, 0x79A1)86 87 // ptrauth_string_discriminator("unw_proc_info_t::unwind_info") == 0xC20C88 #define __ptrauth_unwind_upi_info \89 __unwind_ptrauth_restricted_intptr(ptrauth_key_process_dependent_data, 1, 0xC20C)90 91 // ptrauth_string_discriminator("unw_proc_info_t::extra") == 0x03DF92 #define __ptrauth_unwind_upi_extra \93 __unwind_ptrauth_restricted_intptr(ptrauth_key_process_dependent_data, 1, 0x03DF)94 95 // ptrauth_string_discriminator("Registers_arm64::link_reg_t") == 0x830196 #define __ptrauth_unwind_registers_arm64_link_reg \97 __unwind_ptrauth_restricted_intptr(ptrauth_key_process_dependent_code, 1, 0x8301)98 99 // ptrauth_string_discriminator("UnwindInfoSections::dso_base") == 0x4FF5100 #define __ptrauth_unwind_uis_dso_base \101 __unwind_ptrauth_restricted_intptr(ptrauth_key_process_dependent_data, 1, 0x4FF5)102 103 // ptrauth_string_discriminator("UnwindInfoSections::dwarf_section") == 0x4974104 #define __ptrauth_unwind_uis_dwarf_section \105 __unwind_ptrauth_restricted_intptr(ptrauth_key_process_dependent_data, 1, 0x4974)106 107 // ptrauth_string_discriminator("UnwindInfoSections::dwarf_section_length") == 0x2A9A108 #define __ptrauth_unwind_uis_dwarf_section_length \109 __unwind_ptrauth_restricted_intptr(ptrauth_key_process_dependent_data, 1, 0x2A9A)110 111 // ptrauth_string_discriminator("UnwindInfoSections::compact_unwind_section") == 0xA27B112 #define __ptrauth_unwind_uis_compact_unwind_section \113 __unwind_ptrauth_restricted_intptr(ptrauth_key_process_dependent_data, 1, 0xA27B)114 115 // ptrauth_string_discriminator("UnwindInfoSections::compact_unwind_section_length") == 0x5D0A116 #define __ptrauth_unwind_uis_compact_unwind_section_length \117 __unwind_ptrauth_restricted_intptr(ptrauth_key_process_dependent_data, 1, 0x5D0A)118 119 // ptrauth_string_discriminator("CIE_Info::personality") == 0x6A40120 #define __ptrauth_unwind_cie_info_personality_disc 0x6A40121 #define __ptrauth_unwind_cie_info_personality \122 __unwind_ptrauth_restricted_intptr(ptrauth_key_function_pointer, 1, \123 __ptrauth_unwind_cie_info_personality_disc)124 125 // ptrauth_string_discriminator("personality") == 0x7EAD)126 #define __ptrauth_unwind_pauthtest_personality_disc 0x7EAD127 128#else129 130 #define __unwind_ptrauth_restricted_intptr(...)131 #define __ptrauth_unwind_upi_handler132 #define __ptrauth_unwind_upi_handler_intptr133 #define __ptrauth_unwind_upi_startip134 #define __ptrauth_unwind_upi_endip135 #define __ptrauth_unwind_upi_lsda136 #define __ptrauth_unwind_upi_flags137 #define __ptrauth_unwind_upi_info138 #define __ptrauth_unwind_upi_extra139 #define __ptrauth_unwind_registers_arm64_link_reg140 #define __ptrauth_unwind_uis_dso_base141 #define __ptrauth_unwind_uis_dwarf_section142 #define __ptrauth_unwind_uis_dwarf_section_length143 #define __ptrauth_unwind_uis_compact_unwind_section144 #define __ptrauth_unwind_uis_compact_unwind_section_length145 #define __ptrauth_unwind_cie_info_personality146 147#endif148 149#if defined(_WIN32) && defined(__SEH__)150 #define LIBUNWIND_CURSOR_ALIGNMENT_ATTR __attribute__((__aligned__(16)))151#else152 #define LIBUNWIND_CURSOR_ALIGNMENT_ATTR153#endif154 155/* error codes */156enum {157 UNW_ESUCCESS = 0, /* no error */158 UNW_EUNSPEC = -6540, /* unspecified (general) error */159 UNW_ENOMEM = -6541, /* out of memory */160 UNW_EBADREG = -6542, /* bad register number */161 UNW_EREADONLYREG = -6543, /* attempt to write read-only register */162 UNW_ESTOPUNWIND = -6544, /* stop unwinding */163 UNW_EINVALIDIP = -6545, /* invalid IP */164 UNW_EBADFRAME = -6546, /* bad frame */165 UNW_EINVAL = -6547, /* unsupported operation or bad value */166 UNW_EBADVERSION = -6548, /* unwind info has unsupported version */167 UNW_ENOINFO = -6549 /* no unwind info found */168#if defined(_LIBUNWIND_TARGET_AARCH64) && !defined(_LIBUNWIND_IS_NATIVE_ONLY)169 , UNW_ECROSSRASIGNING = -6550 /* cross unwind with return address signing */170#endif171};172 173struct unw_context_t {174 uint64_t data[_LIBUNWIND_CONTEXT_SIZE];175};176typedef struct unw_context_t unw_context_t;177 178struct unw_cursor_t {179 uint64_t data[_LIBUNWIND_CURSOR_SIZE];180} LIBUNWIND_CURSOR_ALIGNMENT_ATTR;181typedef struct unw_cursor_t unw_cursor_t;182 183typedef struct unw_addr_space *unw_addr_space_t;184 185typedef int unw_regnum_t;186typedef uintptr_t unw_word_t;187#if defined(__arm__) && !defined(__ARM_DWARF_EH__) && !defined(__SEH__)188typedef uint64_t unw_fpreg_t;189#else190typedef double unw_fpreg_t;191#endif192 193struct unw_proc_info_t {194 unw_word_t __ptrauth_unwind_upi_startip start_ip; /* start address of function */195 unw_word_t __ptrauth_unwind_upi_endip end_ip; /* address after end of function */196 unw_word_t __ptrauth_unwind_upi_lsda lsda; /* address of language specific data area, */197 /* or zero if not used */198 199 unw_word_t __ptrauth_unwind_upi_handler_intptr handler;200 unw_word_t gp; /* not used */201 unw_word_t __ptrauth_unwind_upi_flags flags; /* not used */202 uint32_t format; /* compact unwind encoding, or zero if none */203 uint32_t unwind_info_size; /* size of DWARF unwind info, or zero if none */204 unw_word_t __ptrauth_unwind_upi_info unwind_info; /* address of DWARF unwind info, or zero */205 unw_word_t __ptrauth_unwind_upi_extra extra; /* mach_header of mach-o image containing func */206};207typedef struct unw_proc_info_t unw_proc_info_t;208 209#ifdef __cplusplus210extern "C" {211#endif212 213extern int unw_getcontext(unw_context_t *) LIBUNWIND_AVAIL;214extern int unw_init_local(unw_cursor_t *, unw_context_t *) LIBUNWIND_AVAIL;215extern int unw_step(unw_cursor_t *) LIBUNWIND_AVAIL;216extern int unw_get_reg(unw_cursor_t *, unw_regnum_t, unw_word_t *) LIBUNWIND_AVAIL;217extern int unw_get_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t *) LIBUNWIND_AVAIL;218extern int unw_set_reg(unw_cursor_t *, unw_regnum_t, unw_word_t) LIBUNWIND_AVAIL;219extern int unw_set_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t) LIBUNWIND_AVAIL;220extern int unw_resume(unw_cursor_t *) LIBUNWIND_AVAIL;221 222#ifdef __arm__223/* Save VFP registers in FSTMX format (instead of FSTMD). */224extern void unw_save_vfp_as_X(unw_cursor_t *) LIBUNWIND_AVAIL;225#endif226 227#ifdef _AIX228extern uintptr_t unw_get_data_rel_base(unw_cursor_t *) LIBUNWIND_AVAIL;229#endif230 231extern const char *unw_regname(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL;232extern int unw_get_proc_info(unw_cursor_t *, unw_proc_info_t *) LIBUNWIND_AVAIL;233extern int unw_is_fpreg(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL;234extern int unw_is_signal_frame(unw_cursor_t *) LIBUNWIND_AVAIL;235extern int unw_get_proc_name(unw_cursor_t *, char *, size_t, unw_word_t *) LIBUNWIND_AVAIL;236//extern int unw_get_save_loc(unw_cursor_t*, int, unw_save_loc_t*);237extern const char *unw_strerror(int) LIBUNWIND_AVAIL;238 239extern unw_addr_space_t unw_local_addr_space;240 241#ifdef __cplusplus242}243#endif244 245// architecture independent register numbers246enum {247 UNW_REG_IP = -1, // instruction pointer248 UNW_REG_SP = -2, // stack pointer249};250 251// 32-bit x86 registers252enum {253 UNW_X86_EAX = 0,254 UNW_X86_ECX = 1,255 UNW_X86_EDX = 2,256 UNW_X86_EBX = 3,257 UNW_X86_EBP = 4,258 UNW_X86_ESP = 5,259 UNW_X86_ESI = 6,260 UNW_X86_EDI = 7261};262 263// 64-bit x86_64 registers264enum {265 UNW_X86_64_RAX = 0,266 UNW_X86_64_RDX = 1,267 UNW_X86_64_RCX = 2,268 UNW_X86_64_RBX = 3,269 UNW_X86_64_RSI = 4,270 UNW_X86_64_RDI = 5,271 UNW_X86_64_RBP = 6,272 UNW_X86_64_RSP = 7,273 UNW_X86_64_R8 = 8,274 UNW_X86_64_R9 = 9,275 UNW_X86_64_R10 = 10,276 UNW_X86_64_R11 = 11,277 UNW_X86_64_R12 = 12,278 UNW_X86_64_R13 = 13,279 UNW_X86_64_R14 = 14,280 UNW_X86_64_R15 = 15,281 UNW_X86_64_RIP = 16,282 UNW_X86_64_XMM0 = 17,283 UNW_X86_64_XMM1 = 18,284 UNW_X86_64_XMM2 = 19,285 UNW_X86_64_XMM3 = 20,286 UNW_X86_64_XMM4 = 21,287 UNW_X86_64_XMM5 = 22,288 UNW_X86_64_XMM6 = 23,289 UNW_X86_64_XMM7 = 24,290 UNW_X86_64_XMM8 = 25,291 UNW_X86_64_XMM9 = 26,292 UNW_X86_64_XMM10 = 27,293 UNW_X86_64_XMM11 = 28,294 UNW_X86_64_XMM12 = 29,295 UNW_X86_64_XMM13 = 30,296 UNW_X86_64_XMM14 = 31,297 UNW_X86_64_XMM15 = 32,298};299 300 301// 32-bit ppc register numbers302enum {303 UNW_PPC_R0 = 0,304 UNW_PPC_R1 = 1,305 UNW_PPC_R2 = 2,306 UNW_PPC_R3 = 3,307 UNW_PPC_R4 = 4,308 UNW_PPC_R5 = 5,309 UNW_PPC_R6 = 6,310 UNW_PPC_R7 = 7,311 UNW_PPC_R8 = 8,312 UNW_PPC_R9 = 9,313 UNW_PPC_R10 = 10,314 UNW_PPC_R11 = 11,315 UNW_PPC_R12 = 12,316 UNW_PPC_R13 = 13,317 UNW_PPC_R14 = 14,318 UNW_PPC_R15 = 15,319 UNW_PPC_R16 = 16,320 UNW_PPC_R17 = 17,321 UNW_PPC_R18 = 18,322 UNW_PPC_R19 = 19,323 UNW_PPC_R20 = 20,324 UNW_PPC_R21 = 21,325 UNW_PPC_R22 = 22,326 UNW_PPC_R23 = 23,327 UNW_PPC_R24 = 24,328 UNW_PPC_R25 = 25,329 UNW_PPC_R26 = 26,330 UNW_PPC_R27 = 27,331 UNW_PPC_R28 = 28,332 UNW_PPC_R29 = 29,333 UNW_PPC_R30 = 30,334 UNW_PPC_R31 = 31,335 UNW_PPC_F0 = 32,336 UNW_PPC_F1 = 33,337 UNW_PPC_F2 = 34,338 UNW_PPC_F3 = 35,339 UNW_PPC_F4 = 36,340 UNW_PPC_F5 = 37,341 UNW_PPC_F6 = 38,342 UNW_PPC_F7 = 39,343 UNW_PPC_F8 = 40,344 UNW_PPC_F9 = 41,345 UNW_PPC_F10 = 42,346 UNW_PPC_F11 = 43,347 UNW_PPC_F12 = 44,348 UNW_PPC_F13 = 45,349 UNW_PPC_F14 = 46,350 UNW_PPC_F15 = 47,351 UNW_PPC_F16 = 48,352 UNW_PPC_F17 = 49,353 UNW_PPC_F18 = 50,354 UNW_PPC_F19 = 51,355 UNW_PPC_F20 = 52,356 UNW_PPC_F21 = 53,357 UNW_PPC_F22 = 54,358 UNW_PPC_F23 = 55,359 UNW_PPC_F24 = 56,360 UNW_PPC_F25 = 57,361 UNW_PPC_F26 = 58,362 UNW_PPC_F27 = 59,363 UNW_PPC_F28 = 60,364 UNW_PPC_F29 = 61,365 UNW_PPC_F30 = 62,366 UNW_PPC_F31 = 63,367 UNW_PPC_MQ = 64,368 UNW_PPC_LR = 65,369 UNW_PPC_CTR = 66,370 UNW_PPC_AP = 67,371 UNW_PPC_CR0 = 68,372 UNW_PPC_CR1 = 69,373 UNW_PPC_CR2 = 70,374 UNW_PPC_CR3 = 71,375 UNW_PPC_CR4 = 72,376 UNW_PPC_CR5 = 73,377 UNW_PPC_CR6 = 74,378 UNW_PPC_CR7 = 75,379 UNW_PPC_XER = 76,380 UNW_PPC_V0 = 77,381 UNW_PPC_V1 = 78,382 UNW_PPC_V2 = 79,383 UNW_PPC_V3 = 80,384 UNW_PPC_V4 = 81,385 UNW_PPC_V5 = 82,386 UNW_PPC_V6 = 83,387 UNW_PPC_V7 = 84,388 UNW_PPC_V8 = 85,389 UNW_PPC_V9 = 86,390 UNW_PPC_V10 = 87,391 UNW_PPC_V11 = 88,392 UNW_PPC_V12 = 89,393 UNW_PPC_V13 = 90,394 UNW_PPC_V14 = 91,395 UNW_PPC_V15 = 92,396 UNW_PPC_V16 = 93,397 UNW_PPC_V17 = 94,398 UNW_PPC_V18 = 95,399 UNW_PPC_V19 = 96,400 UNW_PPC_V20 = 97,401 UNW_PPC_V21 = 98,402 UNW_PPC_V22 = 99,403 UNW_PPC_V23 = 100,404 UNW_PPC_V24 = 101,405 UNW_PPC_V25 = 102,406 UNW_PPC_V26 = 103,407 UNW_PPC_V27 = 104,408 UNW_PPC_V28 = 105,409 UNW_PPC_V29 = 106,410 UNW_PPC_V30 = 107,411 UNW_PPC_V31 = 108,412 UNW_PPC_VRSAVE = 109,413 UNW_PPC_VSCR = 110,414 UNW_PPC_SPE_ACC = 111,415 UNW_PPC_SPEFSCR = 112416};417 418// 64-bit ppc register numbers419enum {420 UNW_PPC64_R0 = 0,421 UNW_PPC64_R1 = 1,422 UNW_PPC64_R2 = 2,423 UNW_PPC64_R3 = 3,424 UNW_PPC64_R4 = 4,425 UNW_PPC64_R5 = 5,426 UNW_PPC64_R6 = 6,427 UNW_PPC64_R7 = 7,428 UNW_PPC64_R8 = 8,429 UNW_PPC64_R9 = 9,430 UNW_PPC64_R10 = 10,431 UNW_PPC64_R11 = 11,432 UNW_PPC64_R12 = 12,433 UNW_PPC64_R13 = 13,434 UNW_PPC64_R14 = 14,435 UNW_PPC64_R15 = 15,436 UNW_PPC64_R16 = 16,437 UNW_PPC64_R17 = 17,438 UNW_PPC64_R18 = 18,439 UNW_PPC64_R19 = 19,440 UNW_PPC64_R20 = 20,441 UNW_PPC64_R21 = 21,442 UNW_PPC64_R22 = 22,443 UNW_PPC64_R23 = 23,444 UNW_PPC64_R24 = 24,445 UNW_PPC64_R25 = 25,446 UNW_PPC64_R26 = 26,447 UNW_PPC64_R27 = 27,448 UNW_PPC64_R28 = 28,449 UNW_PPC64_R29 = 29,450 UNW_PPC64_R30 = 30,451 UNW_PPC64_R31 = 31,452 UNW_PPC64_F0 = 32,453 UNW_PPC64_F1 = 33,454 UNW_PPC64_F2 = 34,455 UNW_PPC64_F3 = 35,456 UNW_PPC64_F4 = 36,457 UNW_PPC64_F5 = 37,458 UNW_PPC64_F6 = 38,459 UNW_PPC64_F7 = 39,460 UNW_PPC64_F8 = 40,461 UNW_PPC64_F9 = 41,462 UNW_PPC64_F10 = 42,463 UNW_PPC64_F11 = 43,464 UNW_PPC64_F12 = 44,465 UNW_PPC64_F13 = 45,466 UNW_PPC64_F14 = 46,467 UNW_PPC64_F15 = 47,468 UNW_PPC64_F16 = 48,469 UNW_PPC64_F17 = 49,470 UNW_PPC64_F18 = 50,471 UNW_PPC64_F19 = 51,472 UNW_PPC64_F20 = 52,473 UNW_PPC64_F21 = 53,474 UNW_PPC64_F22 = 54,475 UNW_PPC64_F23 = 55,476 UNW_PPC64_F24 = 56,477 UNW_PPC64_F25 = 57,478 UNW_PPC64_F26 = 58,479 UNW_PPC64_F27 = 59,480 UNW_PPC64_F28 = 60,481 UNW_PPC64_F29 = 61,482 UNW_PPC64_F30 = 62,483 UNW_PPC64_F31 = 63,484 // 64: reserved485 UNW_PPC64_LR = 65,486 UNW_PPC64_CTR = 66,487 // 67: reserved488 UNW_PPC64_CR0 = 68,489 UNW_PPC64_CR1 = 69,490 UNW_PPC64_CR2 = 70,491 UNW_PPC64_CR3 = 71,492 UNW_PPC64_CR4 = 72,493 UNW_PPC64_CR5 = 73,494 UNW_PPC64_CR6 = 74,495 UNW_PPC64_CR7 = 75,496 UNW_PPC64_XER = 76,497 UNW_PPC64_V0 = 77,498 UNW_PPC64_V1 = 78,499 UNW_PPC64_V2 = 79,500 UNW_PPC64_V3 = 80,501 UNW_PPC64_V4 = 81,502 UNW_PPC64_V5 = 82,503 UNW_PPC64_V6 = 83,504 UNW_PPC64_V7 = 84,505 UNW_PPC64_V8 = 85,506 UNW_PPC64_V9 = 86,507 UNW_PPC64_V10 = 87,508 UNW_PPC64_V11 = 88,509 UNW_PPC64_V12 = 89,510 UNW_PPC64_V13 = 90,511 UNW_PPC64_V14 = 91,512 UNW_PPC64_V15 = 92,513 UNW_PPC64_V16 = 93,514 UNW_PPC64_V17 = 94,515 UNW_PPC64_V18 = 95,516 UNW_PPC64_V19 = 96,517 UNW_PPC64_V20 = 97,518 UNW_PPC64_V21 = 98,519 UNW_PPC64_V22 = 99,520 UNW_PPC64_V23 = 100,521 UNW_PPC64_V24 = 101,522 UNW_PPC64_V25 = 102,523 UNW_PPC64_V26 = 103,524 UNW_PPC64_V27 = 104,525 UNW_PPC64_V28 = 105,526 UNW_PPC64_V29 = 106,527 UNW_PPC64_V30 = 107,528 UNW_PPC64_V31 = 108,529 // 109, 111-113: OpenPOWER ELF V2 ABI: reserved530 // Borrowing VRSAVE number from PPC32.531 UNW_PPC64_VRSAVE = 109,532 UNW_PPC64_VSCR = 110,533 UNW_PPC64_TFHAR = 114,534 UNW_PPC64_TFIAR = 115,535 UNW_PPC64_TEXASR = 116,536 UNW_PPC64_VS0 = UNW_PPC64_F0,537 UNW_PPC64_VS1 = UNW_PPC64_F1,538 UNW_PPC64_VS2 = UNW_PPC64_F2,539 UNW_PPC64_VS3 = UNW_PPC64_F3,540 UNW_PPC64_VS4 = UNW_PPC64_F4,541 UNW_PPC64_VS5 = UNW_PPC64_F5,542 UNW_PPC64_VS6 = UNW_PPC64_F6,543 UNW_PPC64_VS7 = UNW_PPC64_F7,544 UNW_PPC64_VS8 = UNW_PPC64_F8,545 UNW_PPC64_VS9 = UNW_PPC64_F9,546 UNW_PPC64_VS10 = UNW_PPC64_F10,547 UNW_PPC64_VS11 = UNW_PPC64_F11,548 UNW_PPC64_VS12 = UNW_PPC64_F12,549 UNW_PPC64_VS13 = UNW_PPC64_F13,550 UNW_PPC64_VS14 = UNW_PPC64_F14,551 UNW_PPC64_VS15 = UNW_PPC64_F15,552 UNW_PPC64_VS16 = UNW_PPC64_F16,553 UNW_PPC64_VS17 = UNW_PPC64_F17,554 UNW_PPC64_VS18 = UNW_PPC64_F18,555 UNW_PPC64_VS19 = UNW_PPC64_F19,556 UNW_PPC64_VS20 = UNW_PPC64_F20,557 UNW_PPC64_VS21 = UNW_PPC64_F21,558 UNW_PPC64_VS22 = UNW_PPC64_F22,559 UNW_PPC64_VS23 = UNW_PPC64_F23,560 UNW_PPC64_VS24 = UNW_PPC64_F24,561 UNW_PPC64_VS25 = UNW_PPC64_F25,562 UNW_PPC64_VS26 = UNW_PPC64_F26,563 UNW_PPC64_VS27 = UNW_PPC64_F27,564 UNW_PPC64_VS28 = UNW_PPC64_F28,565 UNW_PPC64_VS29 = UNW_PPC64_F29,566 UNW_PPC64_VS30 = UNW_PPC64_F30,567 UNW_PPC64_VS31 = UNW_PPC64_F31,568 UNW_PPC64_VS32 = UNW_PPC64_V0,569 UNW_PPC64_VS33 = UNW_PPC64_V1,570 UNW_PPC64_VS34 = UNW_PPC64_V2,571 UNW_PPC64_VS35 = UNW_PPC64_V3,572 UNW_PPC64_VS36 = UNW_PPC64_V4,573 UNW_PPC64_VS37 = UNW_PPC64_V5,574 UNW_PPC64_VS38 = UNW_PPC64_V6,575 UNW_PPC64_VS39 = UNW_PPC64_V7,576 UNW_PPC64_VS40 = UNW_PPC64_V8,577 UNW_PPC64_VS41 = UNW_PPC64_V9,578 UNW_PPC64_VS42 = UNW_PPC64_V10,579 UNW_PPC64_VS43 = UNW_PPC64_V11,580 UNW_PPC64_VS44 = UNW_PPC64_V12,581 UNW_PPC64_VS45 = UNW_PPC64_V13,582 UNW_PPC64_VS46 = UNW_PPC64_V14,583 UNW_PPC64_VS47 = UNW_PPC64_V15,584 UNW_PPC64_VS48 = UNW_PPC64_V16,585 UNW_PPC64_VS49 = UNW_PPC64_V17,586 UNW_PPC64_VS50 = UNW_PPC64_V18,587 UNW_PPC64_VS51 = UNW_PPC64_V19,588 UNW_PPC64_VS52 = UNW_PPC64_V20,589 UNW_PPC64_VS53 = UNW_PPC64_V21,590 UNW_PPC64_VS54 = UNW_PPC64_V22,591 UNW_PPC64_VS55 = UNW_PPC64_V23,592 UNW_PPC64_VS56 = UNW_PPC64_V24,593 UNW_PPC64_VS57 = UNW_PPC64_V25,594 UNW_PPC64_VS58 = UNW_PPC64_V26,595 UNW_PPC64_VS59 = UNW_PPC64_V27,596 UNW_PPC64_VS60 = UNW_PPC64_V28,597 UNW_PPC64_VS61 = UNW_PPC64_V29,598 UNW_PPC64_VS62 = UNW_PPC64_V30,599 UNW_PPC64_VS63 = UNW_PPC64_V31600};601 602// 64-bit ARM64 registers603enum {604 UNW_AARCH64_X0 = 0,605 UNW_AARCH64_X1 = 1,606 UNW_AARCH64_X2 = 2,607 UNW_AARCH64_X3 = 3,608 UNW_AARCH64_X4 = 4,609 UNW_AARCH64_X5 = 5,610 UNW_AARCH64_X6 = 6,611 UNW_AARCH64_X7 = 7,612 UNW_AARCH64_X8 = 8,613 UNW_AARCH64_X9 = 9,614 UNW_AARCH64_X10 = 10,615 UNW_AARCH64_X11 = 11,616 UNW_AARCH64_X12 = 12,617 UNW_AARCH64_X13 = 13,618 UNW_AARCH64_X14 = 14,619 UNW_AARCH64_X15 = 15,620 UNW_AARCH64_X16 = 16,621 UNW_AARCH64_X17 = 17,622 UNW_AARCH64_X18 = 18,623 UNW_AARCH64_X19 = 19,624 UNW_AARCH64_X20 = 20,625 UNW_AARCH64_X21 = 21,626 UNW_AARCH64_X22 = 22,627 UNW_AARCH64_X23 = 23,628 UNW_AARCH64_X24 = 24,629 UNW_AARCH64_X25 = 25,630 UNW_AARCH64_X26 = 26,631 UNW_AARCH64_X27 = 27,632 UNW_AARCH64_X28 = 28,633 UNW_AARCH64_X29 = 29,634 UNW_AARCH64_FP = 29,635 UNW_AARCH64_X30 = 30,636 UNW_AARCH64_LR = 30,637 UNW_AARCH64_X31 = 31,638 UNW_AARCH64_SP = 31,639 UNW_AARCH64_PC = 32,640 UNW_AARCH64_VG = 46,641 642 // reserved block643 UNW_AARCH64_RA_SIGN_STATE = 34,644 645 // FP/vector registers646 UNW_AARCH64_V0 = 64,647 UNW_AARCH64_V1 = 65,648 UNW_AARCH64_V2 = 66,649 UNW_AARCH64_V3 = 67,650 UNW_AARCH64_V4 = 68,651 UNW_AARCH64_V5 = 69,652 UNW_AARCH64_V6 = 70,653 UNW_AARCH64_V7 = 71,654 UNW_AARCH64_V8 = 72,655 UNW_AARCH64_V9 = 73,656 UNW_AARCH64_V10 = 74,657 UNW_AARCH64_V11 = 75,658 UNW_AARCH64_V12 = 76,659 UNW_AARCH64_V13 = 77,660 UNW_AARCH64_V14 = 78,661 UNW_AARCH64_V15 = 79,662 UNW_AARCH64_V16 = 80,663 UNW_AARCH64_V17 = 81,664 UNW_AARCH64_V18 = 82,665 UNW_AARCH64_V19 = 83,666 UNW_AARCH64_V20 = 84,667 UNW_AARCH64_V21 = 85,668 UNW_AARCH64_V22 = 86,669 UNW_AARCH64_V23 = 87,670 UNW_AARCH64_V24 = 88,671 UNW_AARCH64_V25 = 89,672 UNW_AARCH64_V26 = 90,673 UNW_AARCH64_V27 = 91,674 UNW_AARCH64_V28 = 92,675 UNW_AARCH64_V29 = 93,676 UNW_AARCH64_V30 = 94,677 UNW_AARCH64_V31 = 95,678 679 // Compatibility aliases680 UNW_ARM64_X0 = UNW_AARCH64_X0,681 UNW_ARM64_X1 = UNW_AARCH64_X1,682 UNW_ARM64_X2 = UNW_AARCH64_X2,683 UNW_ARM64_X3 = UNW_AARCH64_X3,684 UNW_ARM64_X4 = UNW_AARCH64_X4,685 UNW_ARM64_X5 = UNW_AARCH64_X5,686 UNW_ARM64_X6 = UNW_AARCH64_X6,687 UNW_ARM64_X7 = UNW_AARCH64_X7,688 UNW_ARM64_X8 = UNW_AARCH64_X8,689 UNW_ARM64_X9 = UNW_AARCH64_X9,690 UNW_ARM64_X10 = UNW_AARCH64_X10,691 UNW_ARM64_X11 = UNW_AARCH64_X11,692 UNW_ARM64_X12 = UNW_AARCH64_X12,693 UNW_ARM64_X13 = UNW_AARCH64_X13,694 UNW_ARM64_X14 = UNW_AARCH64_X14,695 UNW_ARM64_X15 = UNW_AARCH64_X15,696 UNW_ARM64_X16 = UNW_AARCH64_X16,697 UNW_ARM64_X17 = UNW_AARCH64_X17,698 UNW_ARM64_X18 = UNW_AARCH64_X18,699 UNW_ARM64_X19 = UNW_AARCH64_X19,700 UNW_ARM64_X20 = UNW_AARCH64_X20,701 UNW_ARM64_X21 = UNW_AARCH64_X21,702 UNW_ARM64_X22 = UNW_AARCH64_X22,703 UNW_ARM64_X23 = UNW_AARCH64_X23,704 UNW_ARM64_X24 = UNW_AARCH64_X24,705 UNW_ARM64_X25 = UNW_AARCH64_X25,706 UNW_ARM64_X26 = UNW_AARCH64_X26,707 UNW_ARM64_X27 = UNW_AARCH64_X27,708 UNW_ARM64_X28 = UNW_AARCH64_X28,709 UNW_ARM64_X29 = UNW_AARCH64_X29,710 UNW_ARM64_FP = UNW_AARCH64_FP,711 UNW_ARM64_X30 = UNW_AARCH64_X30,712 UNW_ARM64_LR = UNW_AARCH64_LR,713 UNW_ARM64_X31 = UNW_AARCH64_X31,714 UNW_ARM64_SP = UNW_AARCH64_SP,715 UNW_ARM64_PC = UNW_AARCH64_PC,716 UNW_ARM64_RA_SIGN_STATE = UNW_AARCH64_RA_SIGN_STATE,717 UNW_ARM64_D0 = UNW_AARCH64_V0,718 UNW_ARM64_D1 = UNW_AARCH64_V1,719 UNW_ARM64_D2 = UNW_AARCH64_V2,720 UNW_ARM64_D3 = UNW_AARCH64_V3,721 UNW_ARM64_D4 = UNW_AARCH64_V4,722 UNW_ARM64_D5 = UNW_AARCH64_V5,723 UNW_ARM64_D6 = UNW_AARCH64_V6,724 UNW_ARM64_D7 = UNW_AARCH64_V7,725 UNW_ARM64_D8 = UNW_AARCH64_V8,726 UNW_ARM64_D9 = UNW_AARCH64_V9,727 UNW_ARM64_D10 = UNW_AARCH64_V10,728 UNW_ARM64_D11 = UNW_AARCH64_V11,729 UNW_ARM64_D12 = UNW_AARCH64_V12,730 UNW_ARM64_D13 = UNW_AARCH64_V13,731 UNW_ARM64_D14 = UNW_AARCH64_V14,732 UNW_ARM64_D15 = UNW_AARCH64_V15,733 UNW_ARM64_D16 = UNW_AARCH64_V16,734 UNW_ARM64_D17 = UNW_AARCH64_V17,735 UNW_ARM64_D18 = UNW_AARCH64_V18,736 UNW_ARM64_D19 = UNW_AARCH64_V19,737 UNW_ARM64_D20 = UNW_AARCH64_V20,738 UNW_ARM64_D21 = UNW_AARCH64_V21,739 UNW_ARM64_D22 = UNW_AARCH64_V22,740 UNW_ARM64_D23 = UNW_AARCH64_V23,741 UNW_ARM64_D24 = UNW_AARCH64_V24,742 UNW_ARM64_D25 = UNW_AARCH64_V25,743 UNW_ARM64_D26 = UNW_AARCH64_V26,744 UNW_ARM64_D27 = UNW_AARCH64_V27,745 UNW_ARM64_D28 = UNW_AARCH64_V28,746 UNW_ARM64_D29 = UNW_AARCH64_V29,747 UNW_ARM64_D30 = UNW_AARCH64_V30,748 UNW_ARM64_D31 = UNW_AARCH64_V31,749};750 751// 32-bit ARM registers. Numbers match DWARF for ARM spec #3.1 Table 1.752// Naming scheme uses recommendations given in Note 4 for VFP-v2 and VFP-v3.753// In this scheme, even though the 64-bit floating point registers D0-D31754// overlap physically with the 32-bit floating pointer registers S0-S31,755// they are given a non-overlapping range of register numbers.756//757// Commented out ranges are not preserved during unwinding.758enum {759 UNW_ARM_R0 = 0,760 UNW_ARM_R1 = 1,761 UNW_ARM_R2 = 2,762 UNW_ARM_R3 = 3,763 UNW_ARM_R4 = 4,764 UNW_ARM_R5 = 5,765 UNW_ARM_R6 = 6,766 UNW_ARM_R7 = 7,767 UNW_ARM_R8 = 8,768 UNW_ARM_R9 = 9,769 UNW_ARM_R10 = 10,770 UNW_ARM_R11 = 11,771 UNW_ARM_R12 = 12,772 UNW_ARM_SP = 13, // Logical alias for UNW_REG_SP773 UNW_ARM_R13 = 13,774 UNW_ARM_LR = 14,775 UNW_ARM_R14 = 14,776 UNW_ARM_IP = 15, // Logical alias for UNW_REG_IP777 UNW_ARM_R15 = 15,778 // 16-63 -- OBSOLETE. Used in VFP1 to represent both S0-S31 and D0-D31.779 UNW_ARM_S0 = 64,780 UNW_ARM_S1 = 65,781 UNW_ARM_S2 = 66,782 UNW_ARM_S3 = 67,783 UNW_ARM_S4 = 68,784 UNW_ARM_S5 = 69,785 UNW_ARM_S6 = 70,786 UNW_ARM_S7 = 71,787 UNW_ARM_S8 = 72,788 UNW_ARM_S9 = 73,789 UNW_ARM_S10 = 74,790 UNW_ARM_S11 = 75,791 UNW_ARM_S12 = 76,792 UNW_ARM_S13 = 77,793 UNW_ARM_S14 = 78,794 UNW_ARM_S15 = 79,795 UNW_ARM_S16 = 80,796 UNW_ARM_S17 = 81,797 UNW_ARM_S18 = 82,798 UNW_ARM_S19 = 83,799 UNW_ARM_S20 = 84,800 UNW_ARM_S21 = 85,801 UNW_ARM_S22 = 86,802 UNW_ARM_S23 = 87,803 UNW_ARM_S24 = 88,804 UNW_ARM_S25 = 89,805 UNW_ARM_S26 = 90,806 UNW_ARM_S27 = 91,807 UNW_ARM_S28 = 92,808 UNW_ARM_S29 = 93,809 UNW_ARM_S30 = 94,810 UNW_ARM_S31 = 95,811 // 96-103 -- OBSOLETE. F0-F7. Used by the FPA system. Superseded by VFP.812 // 104-111 -- wCGR0-wCGR7, ACC0-ACC7 (Intel wireless MMX)813 UNW_ARM_WR0 = 112,814 UNW_ARM_WR1 = 113,815 UNW_ARM_WR2 = 114,816 UNW_ARM_WR3 = 115,817 UNW_ARM_WR4 = 116,818 UNW_ARM_WR5 = 117,819 UNW_ARM_WR6 = 118,820 UNW_ARM_WR7 = 119,821 UNW_ARM_WR8 = 120,822 UNW_ARM_WR9 = 121,823 UNW_ARM_WR10 = 122,824 UNW_ARM_WR11 = 123,825 UNW_ARM_WR12 = 124,826 UNW_ARM_WR13 = 125,827 UNW_ARM_WR14 = 126,828 UNW_ARM_WR15 = 127,829 // 128-133 -- SPSR, SPSR_{FIQ|IRQ|ABT|UND|SVC}830 // 134-142 -- Reserved831 UNW_ARM_RA_AUTH_CODE = 143,832 // 144-150 -- R8_USR-R14_USR833 // 151-157 -- R8_FIQ-R14_FIQ834 // 158-159 -- R13_IRQ-R14_IRQ835 // 160-161 -- R13_ABT-R14_ABT836 // 162-163 -- R13_UND-R14_UND837 // 164-165 -- R13_SVC-R14_SVC838 // 166-191 -- Reserved839 UNW_ARM_WC0 = 192,840 UNW_ARM_WC1 = 193,841 UNW_ARM_WC2 = 194,842 UNW_ARM_WC3 = 195,843 // 196-199 -- wC4-wC7 (Intel wireless MMX control)844 // 200-255 -- Reserved845 UNW_ARM_D0 = 256,846 UNW_ARM_D1 = 257,847 UNW_ARM_D2 = 258,848 UNW_ARM_D3 = 259,849 UNW_ARM_D4 = 260,850 UNW_ARM_D5 = 261,851 UNW_ARM_D6 = 262,852 UNW_ARM_D7 = 263,853 UNW_ARM_D8 = 264,854 UNW_ARM_D9 = 265,855 UNW_ARM_D10 = 266,856 UNW_ARM_D11 = 267,857 UNW_ARM_D12 = 268,858 UNW_ARM_D13 = 269,859 UNW_ARM_D14 = 270,860 UNW_ARM_D15 = 271,861 UNW_ARM_D16 = 272,862 UNW_ARM_D17 = 273,863 UNW_ARM_D18 = 274,864 UNW_ARM_D19 = 275,865 UNW_ARM_D20 = 276,866 UNW_ARM_D21 = 277,867 UNW_ARM_D22 = 278,868 UNW_ARM_D23 = 279,869 UNW_ARM_D24 = 280,870 UNW_ARM_D25 = 281,871 UNW_ARM_D26 = 282,872 UNW_ARM_D27 = 283,873 UNW_ARM_D28 = 284,874 UNW_ARM_D29 = 285,875 UNW_ARM_D30 = 286,876 UNW_ARM_D31 = 287,877 // 288-319 -- Reserved for VFP/Neon878 // 320-8191 -- Reserved879 // 8192-16383 -- Unspecified vendor co-processor register.880};881 882// OpenRISC1000 register numbers883enum {884 UNW_OR1K_R0 = 0,885 UNW_OR1K_R1 = 1,886 UNW_OR1K_R2 = 2,887 UNW_OR1K_R3 = 3,888 UNW_OR1K_R4 = 4,889 UNW_OR1K_R5 = 5,890 UNW_OR1K_R6 = 6,891 UNW_OR1K_R7 = 7,892 UNW_OR1K_R8 = 8,893 UNW_OR1K_R9 = 9,894 UNW_OR1K_R10 = 10,895 UNW_OR1K_R11 = 11,896 UNW_OR1K_R12 = 12,897 UNW_OR1K_R13 = 13,898 UNW_OR1K_R14 = 14,899 UNW_OR1K_R15 = 15,900 UNW_OR1K_R16 = 16,901 UNW_OR1K_R17 = 17,902 UNW_OR1K_R18 = 18,903 UNW_OR1K_R19 = 19,904 UNW_OR1K_R20 = 20,905 UNW_OR1K_R21 = 21,906 UNW_OR1K_R22 = 22,907 UNW_OR1K_R23 = 23,908 UNW_OR1K_R24 = 24,909 UNW_OR1K_R25 = 25,910 UNW_OR1K_R26 = 26,911 UNW_OR1K_R27 = 27,912 UNW_OR1K_R28 = 28,913 UNW_OR1K_R29 = 29,914 UNW_OR1K_R30 = 30,915 UNW_OR1K_R31 = 31,916 UNW_OR1K_EPCR = 32,917};918 919// MIPS registers920enum {921 UNW_MIPS_R0 = 0,922 UNW_MIPS_R1 = 1,923 UNW_MIPS_R2 = 2,924 UNW_MIPS_R3 = 3,925 UNW_MIPS_R4 = 4,926 UNW_MIPS_R5 = 5,927 UNW_MIPS_R6 = 6,928 UNW_MIPS_R7 = 7,929 UNW_MIPS_R8 = 8,930 UNW_MIPS_R9 = 9,931 UNW_MIPS_R10 = 10,932 UNW_MIPS_R11 = 11,933 UNW_MIPS_R12 = 12,934 UNW_MIPS_R13 = 13,935 UNW_MIPS_R14 = 14,936 UNW_MIPS_R15 = 15,937 UNW_MIPS_R16 = 16,938 UNW_MIPS_R17 = 17,939 UNW_MIPS_R18 = 18,940 UNW_MIPS_R19 = 19,941 UNW_MIPS_R20 = 20,942 UNW_MIPS_R21 = 21,943 UNW_MIPS_R22 = 22,944 UNW_MIPS_R23 = 23,945 UNW_MIPS_R24 = 24,946 UNW_MIPS_R25 = 25,947 UNW_MIPS_R26 = 26,948 UNW_MIPS_R27 = 27,949 UNW_MIPS_R28 = 28,950 UNW_MIPS_R29 = 29,951 UNW_MIPS_R30 = 30,952 UNW_MIPS_R31 = 31,953 UNW_MIPS_F0 = 32,954 UNW_MIPS_F1 = 33,955 UNW_MIPS_F2 = 34,956 UNW_MIPS_F3 = 35,957 UNW_MIPS_F4 = 36,958 UNW_MIPS_F5 = 37,959 UNW_MIPS_F6 = 38,960 UNW_MIPS_F7 = 39,961 UNW_MIPS_F8 = 40,962 UNW_MIPS_F9 = 41,963 UNW_MIPS_F10 = 42,964 UNW_MIPS_F11 = 43,965 UNW_MIPS_F12 = 44,966 UNW_MIPS_F13 = 45,967 UNW_MIPS_F14 = 46,968 UNW_MIPS_F15 = 47,969 UNW_MIPS_F16 = 48,970 UNW_MIPS_F17 = 49,971 UNW_MIPS_F18 = 50,972 UNW_MIPS_F19 = 51,973 UNW_MIPS_F20 = 52,974 UNW_MIPS_F21 = 53,975 UNW_MIPS_F22 = 54,976 UNW_MIPS_F23 = 55,977 UNW_MIPS_F24 = 56,978 UNW_MIPS_F25 = 57,979 UNW_MIPS_F26 = 58,980 UNW_MIPS_F27 = 59,981 UNW_MIPS_F28 = 60,982 UNW_MIPS_F29 = 61,983 UNW_MIPS_F30 = 62,984 UNW_MIPS_F31 = 63,985 // HI,LO have been dropped since r6, we keep them here.986 // So, when we add DSP/MSA etc, we can use the same register indexes987 // for r6 and pre-r6.988 UNW_MIPS_HI = 64,989 UNW_MIPS_LO = 65,990};991 992// SPARC registers993enum {994 UNW_SPARC_G0 = 0,995 UNW_SPARC_G1 = 1,996 UNW_SPARC_G2 = 2,997 UNW_SPARC_G3 = 3,998 UNW_SPARC_G4 = 4,999 UNW_SPARC_G5 = 5,1000 UNW_SPARC_G6 = 6,1001 UNW_SPARC_G7 = 7,1002 UNW_SPARC_O0 = 8,1003 UNW_SPARC_O1 = 9,1004 UNW_SPARC_O2 = 10,1005 UNW_SPARC_O3 = 11,1006 UNW_SPARC_O4 = 12,1007 UNW_SPARC_O5 = 13,1008 UNW_SPARC_O6 = 14,1009 UNW_SPARC_O7 = 15,1010 UNW_SPARC_L0 = 16,1011 UNW_SPARC_L1 = 17,1012 UNW_SPARC_L2 = 18,1013 UNW_SPARC_L3 = 19,1014 UNW_SPARC_L4 = 20,1015 UNW_SPARC_L5 = 21,1016 UNW_SPARC_L6 = 22,1017 UNW_SPARC_L7 = 23,1018 UNW_SPARC_I0 = 24,1019 UNW_SPARC_I1 = 25,1020 UNW_SPARC_I2 = 26,1021 UNW_SPARC_I3 = 27,1022 UNW_SPARC_I4 = 28,1023 UNW_SPARC_I5 = 29,1024 UNW_SPARC_I6 = 30,1025 UNW_SPARC_I7 = 31,1026};1027 1028// Hexagon register numbers1029enum {1030 UNW_HEXAGON_R0,1031 UNW_HEXAGON_R1,1032 UNW_HEXAGON_R2,1033 UNW_HEXAGON_R3,1034 UNW_HEXAGON_R4,1035 UNW_HEXAGON_R5,1036 UNW_HEXAGON_R6,1037 UNW_HEXAGON_R7,1038 UNW_HEXAGON_R8,1039 UNW_HEXAGON_R9,1040 UNW_HEXAGON_R10,1041 UNW_HEXAGON_R11,1042 UNW_HEXAGON_R12,1043 UNW_HEXAGON_R13,1044 UNW_HEXAGON_R14,1045 UNW_HEXAGON_R15,1046 UNW_HEXAGON_R16,1047 UNW_HEXAGON_R17,1048 UNW_HEXAGON_R18,1049 UNW_HEXAGON_R19,1050 UNW_HEXAGON_R20,1051 UNW_HEXAGON_R21,1052 UNW_HEXAGON_R22,1053 UNW_HEXAGON_R23,1054 UNW_HEXAGON_R24,1055 UNW_HEXAGON_R25,1056 UNW_HEXAGON_R26,1057 UNW_HEXAGON_R27,1058 UNW_HEXAGON_R28,1059 UNW_HEXAGON_R29,1060 UNW_HEXAGON_R30,1061 UNW_HEXAGON_R31,1062 UNW_HEXAGON_P3_0,1063 UNW_HEXAGON_PC,1064};1065 1066// RISC-V registers. These match the DWARF register numbers defined by section1067// 4 of the RISC-V ELF psABI specification, which can be found at:1068//1069// https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md1070enum {1071 UNW_RISCV_X0 = 0,1072 UNW_RISCV_X1 = 1,1073 UNW_RISCV_X2 = 2,1074 UNW_RISCV_X3 = 3,1075 UNW_RISCV_X4 = 4,1076 UNW_RISCV_X5 = 5,1077 UNW_RISCV_X6 = 6,1078 UNW_RISCV_X7 = 7,1079 UNW_RISCV_X8 = 8,1080 UNW_RISCV_X9 = 9,1081 UNW_RISCV_X10 = 10,1082 UNW_RISCV_X11 = 11,1083 UNW_RISCV_X12 = 12,1084 UNW_RISCV_X13 = 13,1085 UNW_RISCV_X14 = 14,1086 UNW_RISCV_X15 = 15,1087 UNW_RISCV_X16 = 16,1088 UNW_RISCV_X17 = 17,1089 UNW_RISCV_X18 = 18,1090 UNW_RISCV_X19 = 19,1091 UNW_RISCV_X20 = 20,1092 UNW_RISCV_X21 = 21,1093 UNW_RISCV_X22 = 22,1094 UNW_RISCV_X23 = 23,1095 UNW_RISCV_X24 = 24,1096 UNW_RISCV_X25 = 25,1097 UNW_RISCV_X26 = 26,1098 UNW_RISCV_X27 = 27,1099 UNW_RISCV_X28 = 28,1100 UNW_RISCV_X29 = 29,1101 UNW_RISCV_X30 = 30,1102 UNW_RISCV_X31 = 31,1103 UNW_RISCV_F0 = 32,1104 UNW_RISCV_F1 = 33,1105 UNW_RISCV_F2 = 34,1106 UNW_RISCV_F3 = 35,1107 UNW_RISCV_F4 = 36,1108 UNW_RISCV_F5 = 37,1109 UNW_RISCV_F6 = 38,1110 UNW_RISCV_F7 = 39,1111 UNW_RISCV_F8 = 40,1112 UNW_RISCV_F9 = 41,1113 UNW_RISCV_F10 = 42,1114 UNW_RISCV_F11 = 43,1115 UNW_RISCV_F12 = 44,1116 UNW_RISCV_F13 = 45,1117 UNW_RISCV_F14 = 46,1118 UNW_RISCV_F15 = 47,1119 UNW_RISCV_F16 = 48,1120 UNW_RISCV_F17 = 49,1121 UNW_RISCV_F18 = 50,1122 UNW_RISCV_F19 = 51,1123 UNW_RISCV_F20 = 52,1124 UNW_RISCV_F21 = 53,1125 UNW_RISCV_F22 = 54,1126 UNW_RISCV_F23 = 55,1127 UNW_RISCV_F24 = 56,1128 UNW_RISCV_F25 = 57,1129 UNW_RISCV_F26 = 58,1130 UNW_RISCV_F27 = 59,1131 UNW_RISCV_F28 = 60,1132 UNW_RISCV_F29 = 61,1133 UNW_RISCV_F30 = 62,1134 UNW_RISCV_F31 = 63,1135 // 65-95 -- Reserved for future standard extensions1136 // 96-127 -- v0-v31 (Vector registers)1137 // 128-3071 -- Reserved for future standard extensions1138 // 3072-4095 -- Reserved for custom extensions1139 // 4096-8191 -- CSRs1140 //1141 // VLENB CSR number: 0xC22 -- defined by section 3 of v-spec:1142 // https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#3-vector-extension-programmers-model1143 // VLENB DWARF number: 0x1000 + 0xC221144 UNW_RISCV_VLENB = 0x1C22,1145};1146 1147// VE register numbers1148enum {1149 UNW_VE_S0 = 0,1150 UNW_VE_S1 = 1,1151 UNW_VE_S2 = 2,1152 UNW_VE_S3 = 3,1153 UNW_VE_S4 = 4,1154 UNW_VE_S5 = 5,1155 UNW_VE_S6 = 6,1156 UNW_VE_S7 = 7,1157 UNW_VE_S8 = 8,1158 UNW_VE_S9 = 9,1159 UNW_VE_S10 = 10,1160 UNW_VE_S11 = 11,1161 UNW_VE_S12 = 12,1162 UNW_VE_S13 = 13,1163 UNW_VE_S14 = 14,1164 UNW_VE_S15 = 15,1165 UNW_VE_S16 = 16,1166 UNW_VE_S17 = 17,1167 UNW_VE_S18 = 18,1168 UNW_VE_S19 = 19,1169 UNW_VE_S20 = 20,1170 UNW_VE_S21 = 21,1171 UNW_VE_S22 = 22,1172 UNW_VE_S23 = 23,1173 UNW_VE_S24 = 24,1174 UNW_VE_S25 = 25,1175 UNW_VE_S26 = 26,1176 UNW_VE_S27 = 27,1177 UNW_VE_S28 = 28,1178 UNW_VE_S29 = 29,1179 UNW_VE_S30 = 30,1180 UNW_VE_S31 = 31,1181 UNW_VE_S32 = 32,1182 UNW_VE_S33 = 33,1183 UNW_VE_S34 = 34,1184 UNW_VE_S35 = 35,1185 UNW_VE_S36 = 36,1186 UNW_VE_S37 = 37,1187 UNW_VE_S38 = 38,1188 UNW_VE_S39 = 39,1189 UNW_VE_S40 = 40,1190 UNW_VE_S41 = 41,1191 UNW_VE_S42 = 42,1192 UNW_VE_S43 = 43,1193 UNW_VE_S44 = 44,1194 UNW_VE_S45 = 45,1195 UNW_VE_S46 = 46,1196 UNW_VE_S47 = 47,1197 UNW_VE_S48 = 48,1198 UNW_VE_S49 = 49,1199 UNW_VE_S50 = 50,1200 UNW_VE_S51 = 51,1201 UNW_VE_S52 = 52,1202 UNW_VE_S53 = 53,1203 UNW_VE_S54 = 54,1204 UNW_VE_S55 = 55,1205 UNW_VE_S56 = 56,1206 UNW_VE_S57 = 57,1207 UNW_VE_S58 = 58,1208 UNW_VE_S59 = 59,1209 UNW_VE_S60 = 60,1210 UNW_VE_S61 = 61,1211 UNW_VE_S62 = 62,1212 UNW_VE_S63 = 63,1213 UNW_VE_V0 = 64 + 0,1214 UNW_VE_V1 = 64 + 1,1215 UNW_VE_V2 = 64 + 2,1216 UNW_VE_V3 = 64 + 3,1217 UNW_VE_V4 = 64 + 4,1218 UNW_VE_V5 = 64 + 5,1219 UNW_VE_V6 = 64 + 6,1220 UNW_VE_V7 = 64 + 7,1221 UNW_VE_V8 = 64 + 8,1222 UNW_VE_V9 = 64 + 9,1223 UNW_VE_V10 = 64 + 10,1224 UNW_VE_V11 = 64 + 11,1225 UNW_VE_V12 = 64 + 12,1226 UNW_VE_V13 = 64 + 13,1227 UNW_VE_V14 = 64 + 14,1228 UNW_VE_V15 = 64 + 15,1229 UNW_VE_V16 = 64 + 16,1230 UNW_VE_V17 = 64 + 17,1231 UNW_VE_V18 = 64 + 18,1232 UNW_VE_V19 = 64 + 19,1233 UNW_VE_V20 = 64 + 20,1234 UNW_VE_V21 = 64 + 21,1235 UNW_VE_V22 = 64 + 22,1236 UNW_VE_V23 = 64 + 23,1237 UNW_VE_V24 = 64 + 24,1238 UNW_VE_V25 = 64 + 25,1239 UNW_VE_V26 = 64 + 26,1240 UNW_VE_V27 = 64 + 27,1241 UNW_VE_V28 = 64 + 28,1242 UNW_VE_V29 = 64 + 29,1243 UNW_VE_V30 = 64 + 30,1244 UNW_VE_V31 = 64 + 31,1245 UNW_VE_V32 = 64 + 32,1246 UNW_VE_V33 = 64 + 33,1247 UNW_VE_V34 = 64 + 34,1248 UNW_VE_V35 = 64 + 35,1249 UNW_VE_V36 = 64 + 36,1250 UNW_VE_V37 = 64 + 37,1251 UNW_VE_V38 = 64 + 38,1252 UNW_VE_V39 = 64 + 39,1253 UNW_VE_V40 = 64 + 40,1254 UNW_VE_V41 = 64 + 41,1255 UNW_VE_V42 = 64 + 42,1256 UNW_VE_V43 = 64 + 43,1257 UNW_VE_V44 = 64 + 44,1258 UNW_VE_V45 = 64 + 45,1259 UNW_VE_V46 = 64 + 46,1260 UNW_VE_V47 = 64 + 47,1261 UNW_VE_V48 = 64 + 48,1262 UNW_VE_V49 = 64 + 49,1263 UNW_VE_V50 = 64 + 50,1264 UNW_VE_V51 = 64 + 51,1265 UNW_VE_V52 = 64 + 52,1266 UNW_VE_V53 = 64 + 53,1267 UNW_VE_V54 = 64 + 54,1268 UNW_VE_V55 = 64 + 55,1269 UNW_VE_V56 = 64 + 56,1270 UNW_VE_V57 = 64 + 57,1271 UNW_VE_V58 = 64 + 58,1272 UNW_VE_V59 = 64 + 59,1273 UNW_VE_V60 = 64 + 60,1274 UNW_VE_V61 = 64 + 61,1275 UNW_VE_V62 = 64 + 62,1276 UNW_VE_V63 = 64 + 63,1277 UNW_VE_VM0 = 128 + 0,1278 UNW_VE_VM1 = 128 + 1,1279 UNW_VE_VM2 = 128 + 2,1280 UNW_VE_VM3 = 128 + 3,1281 UNW_VE_VM4 = 128 + 4,1282 UNW_VE_VM5 = 128 + 5,1283 UNW_VE_VM6 = 128 + 6,1284 UNW_VE_VM7 = 128 + 7,1285 UNW_VE_VM8 = 128 + 8,1286 UNW_VE_VM9 = 128 + 9,1287 UNW_VE_VM10 = 128 + 10,1288 UNW_VE_VM11 = 128 + 11,1289 UNW_VE_VM12 = 128 + 12,1290 UNW_VE_VM13 = 128 + 13,1291 UNW_VE_VM14 = 128 + 14,1292 UNW_VE_VM15 = 128 + 15, // = 1431293 1294 // Following registers don't have DWARF register numbers.1295 UNW_VE_VIXR = 144,1296 UNW_VE_VL = 145,1297};1298 1299// s390x register numbers1300enum {1301 UNW_S390X_R0 = 0,1302 UNW_S390X_R1 = 1,1303 UNW_S390X_R2 = 2,1304 UNW_S390X_R3 = 3,1305 UNW_S390X_R4 = 4,1306 UNW_S390X_R5 = 5,1307 UNW_S390X_R6 = 6,1308 UNW_S390X_R7 = 7,1309 UNW_S390X_R8 = 8,1310 UNW_S390X_R9 = 9,1311 UNW_S390X_R10 = 10,1312 UNW_S390X_R11 = 11,1313 UNW_S390X_R12 = 12,1314 UNW_S390X_R13 = 13,1315 UNW_S390X_R14 = 14,1316 UNW_S390X_R15 = 15,1317 UNW_S390X_F0 = 16,1318 UNW_S390X_F2 = 17,1319 UNW_S390X_F4 = 18,1320 UNW_S390X_F6 = 19,1321 UNW_S390X_F1 = 20,1322 UNW_S390X_F3 = 21,1323 UNW_S390X_F5 = 22,1324 UNW_S390X_F7 = 23,1325 UNW_S390X_F8 = 24,1326 UNW_S390X_F10 = 25,1327 UNW_S390X_F12 = 26,1328 UNW_S390X_F14 = 27,1329 UNW_S390X_F9 = 28,1330 UNW_S390X_F11 = 29,1331 UNW_S390X_F13 = 30,1332 UNW_S390X_F15 = 31,1333 // 32-47 Control Registers1334 // 48-63 Access Registers1335 UNW_S390X_PSWM = 64,1336 UNW_S390X_PSWA = 65,1337 // 66-67 Reserved1338 // 68-83 Vector Registers %v16-%v311339};1340 1341// LoongArch registers.1342enum {1343 UNW_LOONGARCH_R0 = 0,1344 UNW_LOONGARCH_R1 = 1,1345 UNW_LOONGARCH_R2 = 2,1346 UNW_LOONGARCH_R3 = 3,1347 UNW_LOONGARCH_R4 = 4,1348 UNW_LOONGARCH_R5 = 5,1349 UNW_LOONGARCH_R6 = 6,1350 UNW_LOONGARCH_R7 = 7,1351 UNW_LOONGARCH_R8 = 8,1352 UNW_LOONGARCH_R9 = 9,1353 UNW_LOONGARCH_R10 = 10,1354 UNW_LOONGARCH_R11 = 11,1355 UNW_LOONGARCH_R12 = 12,1356 UNW_LOONGARCH_R13 = 13,1357 UNW_LOONGARCH_R14 = 14,1358 UNW_LOONGARCH_R15 = 15,1359 UNW_LOONGARCH_R16 = 16,1360 UNW_LOONGARCH_R17 = 17,1361 UNW_LOONGARCH_R18 = 18,1362 UNW_LOONGARCH_R19 = 19,1363 UNW_LOONGARCH_R20 = 20,1364 UNW_LOONGARCH_R21 = 21,1365 UNW_LOONGARCH_R22 = 22,1366 UNW_LOONGARCH_R23 = 23,1367 UNW_LOONGARCH_R24 = 24,1368 UNW_LOONGARCH_R25 = 25,1369 UNW_LOONGARCH_R26 = 26,1370 UNW_LOONGARCH_R27 = 27,1371 UNW_LOONGARCH_R28 = 28,1372 UNW_LOONGARCH_R29 = 29,1373 UNW_LOONGARCH_R30 = 30,1374 UNW_LOONGARCH_R31 = 31,1375 UNW_LOONGARCH_F0 = 32,1376 UNW_LOONGARCH_F1 = 33,1377 UNW_LOONGARCH_F2 = 34,1378 UNW_LOONGARCH_F3 = 35,1379 UNW_LOONGARCH_F4 = 36,1380 UNW_LOONGARCH_F5 = 37,1381 UNW_LOONGARCH_F6 = 38,1382 UNW_LOONGARCH_F7 = 39,1383 UNW_LOONGARCH_F8 = 40,1384 UNW_LOONGARCH_F9 = 41,1385 UNW_LOONGARCH_F10 = 42,1386 UNW_LOONGARCH_F11 = 43,1387 UNW_LOONGARCH_F12 = 44,1388 UNW_LOONGARCH_F13 = 45,1389 UNW_LOONGARCH_F14 = 46,1390 UNW_LOONGARCH_F15 = 47,1391 UNW_LOONGARCH_F16 = 48,1392 UNW_LOONGARCH_F17 = 49,1393 UNW_LOONGARCH_F18 = 50,1394 UNW_LOONGARCH_F19 = 51,1395 UNW_LOONGARCH_F20 = 52,1396 UNW_LOONGARCH_F21 = 53,1397 UNW_LOONGARCH_F22 = 54,1398 UNW_LOONGARCH_F23 = 55,1399 UNW_LOONGARCH_F24 = 56,1400 UNW_LOONGARCH_F25 = 57,1401 UNW_LOONGARCH_F26 = 58,1402 UNW_LOONGARCH_F27 = 59,1403 UNW_LOONGARCH_F28 = 60,1404 UNW_LOONGARCH_F29 = 61,1405 UNW_LOONGARCH_F30 = 62,1406 UNW_LOONGARCH_F31 = 63,1407};1408 1409#endif1410