1881 lines · cpp
1//===- PPC64.cpp ----------------------------------------------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#include "InputFiles.h"10#include "OutputSections.h"11#include "RelocScan.h"12#include "SymbolTable.h"13#include "Symbols.h"14#include "SyntheticSections.h"15#include "Target.h"16#include "Thunks.h"17 18using namespace llvm;19using namespace llvm::object;20using namespace llvm::support::endian;21using namespace llvm::ELF;22using namespace lld;23using namespace lld::elf;24 25constexpr uint64_t ppc64TocOffset = 0x8000;26constexpr uint64_t dynamicThreadPointerOffset = 0x8000;27 28namespace {29// The instruction encoding of bits 21-30 from the ISA for the Xform and Dform30// instructions that can be used as part of the initial exec TLS sequence.31enum XFormOpcd {32 LBZX = 87,33 LHZX = 279,34 LWZX = 23,35 LDX = 21,36 STBX = 215,37 STHX = 407,38 STWX = 151,39 STDX = 149,40 LHAX = 343,41 LWAX = 341,42 LFSX = 535,43 LFDX = 599,44 STFSX = 663,45 STFDX = 727,46 ADD = 266,47};48 49enum DFormOpcd {50 LBZ = 34,51 LBZU = 35,52 LHZ = 40,53 LHZU = 41,54 LHAU = 43,55 LWZ = 32,56 LWZU = 33,57 LFSU = 49,58 LFDU = 51,59 STB = 38,60 STBU = 39,61 STH = 44,62 STHU = 45,63 STW = 36,64 STWU = 37,65 STFSU = 53,66 STFDU = 55,67 LHA = 42,68 LFS = 48,69 LFD = 50,70 STFS = 52,71 STFD = 54,72 ADDI = 1473};74 75enum DSFormOpcd {76 LD = 58,77 LWA = 58,78 STD = 6279};80 81constexpr uint32_t NOP = 0x60000000;82 83enum class PPCLegacyInsn : uint32_t {84 NOINSN = 0,85 // Loads.86 LBZ = 0x88000000,87 LHZ = 0xa0000000,88 LWZ = 0x80000000,89 LHA = 0xa8000000,90 LWA = 0xe8000002,91 LD = 0xe8000000,92 LFS = 0xC0000000,93 LXSSP = 0xe4000003,94 LFD = 0xc8000000,95 LXSD = 0xe4000002,96 LXV = 0xf4000001,97 LXVP = 0x18000000,98 99 // Stores.100 STB = 0x98000000,101 STH = 0xb0000000,102 STW = 0x90000000,103 STD = 0xf8000000,104 STFS = 0xd0000000,105 STXSSP = 0xf4000003,106 STFD = 0xd8000000,107 STXSD = 0xf4000002,108 STXV = 0xf4000005,109 STXVP = 0x18000001110};111enum class PPCPrefixedInsn : uint64_t {112 NOINSN = 0,113 PREFIX_MLS = 0x0610000000000000,114 PREFIX_8LS = 0x0410000000000000,115 116 // Loads.117 PLBZ = PREFIX_MLS,118 PLHZ = PREFIX_MLS,119 PLWZ = PREFIX_MLS,120 PLHA = PREFIX_MLS,121 PLWA = PREFIX_8LS | 0xa4000000,122 PLD = PREFIX_8LS | 0xe4000000,123 PLFS = PREFIX_MLS,124 PLXSSP = PREFIX_8LS | 0xac000000,125 PLFD = PREFIX_MLS,126 PLXSD = PREFIX_8LS | 0xa8000000,127 PLXV = PREFIX_8LS | 0xc8000000,128 PLXVP = PREFIX_8LS | 0xe8000000,129 130 // Stores.131 PSTB = PREFIX_MLS,132 PSTH = PREFIX_MLS,133 PSTW = PREFIX_MLS,134 PSTD = PREFIX_8LS | 0xf4000000,135 PSTFS = PREFIX_MLS,136 PSTXSSP = PREFIX_8LS | 0xbc000000,137 PSTFD = PREFIX_MLS,138 PSTXSD = PREFIX_8LS | 0xb8000000,139 PSTXV = PREFIX_8LS | 0xd8000000,140 PSTXVP = PREFIX_8LS | 0xf8000000141};142 143static bool checkPPCLegacyInsn(uint32_t encoding) {144 PPCLegacyInsn insn = static_cast<PPCLegacyInsn>(encoding);145 if (insn == PPCLegacyInsn::NOINSN)146 return false;147#define PCREL_OPT(Legacy, PCRel, InsnMask) \148 if (insn == PPCLegacyInsn::Legacy) \149 return true;150#include "PPCInsns.def"151#undef PCREL_OPT152 return false;153}154 155// Masks to apply to legacy instructions when converting them to prefixed,156// pc-relative versions. For the most part, the primary opcode is shared157// between the legacy instruction and the suffix of its prefixed version.158// However, there are some instances where that isn't the case (DS-Form and159// DQ-form instructions).160enum class LegacyToPrefixMask : uint64_t {161 NOMASK = 0x0,162 OPC_AND_RST = 0xffe00000, // Primary opc (0-5) and R[ST] (6-10).163 ONLY_RST = 0x3e00000, // [RS]T (6-10).164 ST_STX28_TO5 =165 0x8000000003e00000, // S/T (6-10) - The [S/T]X bit moves from 28 to 5.166};167 168class PPC64 final : public TargetInfo {169public:170 PPC64(Ctx &);171 int getTlsGdRelaxSkip(RelType type) const override;172 uint32_t calcEFlags() const override;173 RelExpr getRelExpr(RelType type, const Symbol &s,174 const uint8_t *loc) const override;175 RelType getDynRel(RelType type) const override;176 int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;177 void writePltHeader(uint8_t *buf) const override;178 void writePlt(uint8_t *buf, const Symbol &sym,179 uint64_t pltEntryAddr) const override;180 void writeIplt(uint8_t *buf, const Symbol &sym,181 uint64_t pltEntryAddr) const override;182 template <class ELFT, class RelTy>183 void scanSectionImpl(InputSectionBase &, Relocs<RelTy>);184 template <class ELFT> void scanSection1(InputSectionBase &);185 void scanSection(InputSectionBase &) override;186 void relocate(uint8_t *loc, const Relocation &rel,187 uint64_t val) const override;188 void writeGotHeader(uint8_t *buf) const override;189 bool needsThunk(RelExpr expr, RelType type, const InputFile *file,190 uint64_t branchAddr, const Symbol &s,191 int64_t a) const override;192 uint32_t getThunkSectionSpacing() const override;193 bool inBranchRange(RelType type, uint64_t src, uint64_t dst) const override;194 RelExpr adjustTlsExpr(RelType type, RelExpr expr) const override;195 RelExpr adjustGotPcExpr(RelType type, int64_t addend,196 const uint8_t *loc) const override;197 void relaxGot(uint8_t *loc, const Relocation &rel, uint64_t val) const;198 void relocateAlloc(InputSection &sec, uint8_t *buf) const override;199 200 bool adjustPrologueForCrossSplitStack(uint8_t *loc, uint8_t *end,201 uint8_t stOther) const override;202 203private:204 void relaxTlsGdToIe(uint8_t *loc, const Relocation &rel, uint64_t val) const;205 void relaxTlsGdToLe(uint8_t *loc, const Relocation &rel, uint64_t val) const;206 void relaxTlsLdToLe(uint8_t *loc, const Relocation &rel, uint64_t val) const;207 void relaxTlsIeToLe(uint8_t *loc, const Relocation &rel, uint64_t val) const;208};209} // namespace210 211uint64_t elf::getPPC64TocBase(Ctx &ctx) {212 // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The213 // TOC starts where the first of these sections starts. We always create a214 // .got when we see a relocation that uses it, so for us the start is always215 // the .got.216 uint64_t tocVA = ctx.in.got->getVA();217 218 // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000219 // thus permitting a full 64 Kbytes segment. Note that the glibc startup220 // code (crt1.o) assumes that you can get from the TOC base to the221 // start of the .toc section with only a single (signed) 16-bit relocation.222 return tocVA + ppc64TocOffset;223}224 225unsigned elf::getPPC64GlobalEntryToLocalEntryOffset(Ctx &ctx, uint8_t stOther) {226 // The offset is encoded into the 3 most significant bits of the st_other227 // field, with some special values described in section 3.4.1 of the ABI:228 // 0 --> Zero offset between the GEP and LEP, and the function does NOT use229 // the TOC pointer (r2). r2 will hold the same value on returning from230 // the function as it did on entering the function.231 // 1 --> Zero offset between the GEP and LEP, and r2 should be treated as a232 // caller-saved register for all callers.233 // 2-6 --> The binary logarithm of the offset eg:234 // 2 --> 2^2 = 4 bytes --> 1 instruction.235 // 6 --> 2^6 = 64 bytes --> 16 instructions.236 // 7 --> Reserved.237 uint8_t gepToLep = (stOther >> 5) & 7;238 if (gepToLep < 2)239 return 0;240 241 // The value encoded in the st_other bits is the242 // log-base-2(offset).243 if (gepToLep < 7)244 return 1 << gepToLep;245 246 ErrAlways(ctx)247 << "reserved value of 7 in the 3 most-significant-bits of st_other";248 return 0;249}250 251void elf::writePrefixedInst(Ctx &ctx, uint8_t *loc, uint64_t insn) {252 insn = ctx.arg.isLE ? insn << 32 | insn >> 32 : insn;253 write64(ctx, loc, insn);254}255 256static bool addOptional(Ctx &ctx, StringRef name, uint64_t value,257 std::vector<Defined *> &defined) {258 Symbol *sym = ctx.symtab->find(name);259 if (!sym || sym->isDefined())260 return false;261 sym->resolve(ctx, Defined{ctx, ctx.internalFile, StringRef(), STB_GLOBAL,262 STV_HIDDEN, STT_FUNC, value,263 /*size=*/0, /*section=*/nullptr});264 defined.push_back(cast<Defined>(sym));265 return true;266}267 268// If from is 14, write ${prefix}14: firstInsn; ${prefix}15:269// firstInsn+0x200008; ...; ${prefix}31: firstInsn+(31-14)*0x200008; $tail270// The labels are defined only if they exist in the symbol table.271static void writeSequence(Ctx &ctx, const char *prefix, int from,272 uint32_t firstInsn, ArrayRef<uint32_t> tail) {273 std::vector<Defined *> defined;274 char name[16];275 int first;276 const size_t size = 32 - from + tail.size();277 MutableArrayRef<uint32_t> buf(ctx.bAlloc.Allocate<uint32_t>(size), size);278 uint32_t *ptr = buf.data();279 for (int r = from; r < 32; ++r) {280 format("%s%d", prefix, r).snprint(name, sizeof(name));281 if (addOptional(ctx, name, 4 * (r - from), defined) && defined.size() == 1)282 first = r - from;283 write32(ctx, ptr++, firstInsn + 0x200008 * (r - from));284 }285 for (uint32_t insn : tail)286 write32(ctx, ptr++, insn);287 assert(ptr == &*buf.end());288 289 if (defined.empty())290 return;291 // The full section content has the extent of [begin, end). We drop unused292 // instructions and write [first,end).293 auto *sec = make<InputSection>(294 ctx.internalFile, ".text", SHT_PROGBITS, SHF_ALLOC, /*addralign=*/4,295 /*entsize=*/0,296 ArrayRef(reinterpret_cast<uint8_t *>(buf.data() + first),297 4 * (buf.size() - first)));298 ctx.inputSections.push_back(sec);299 for (Defined *sym : defined) {300 sym->section = sec;301 sym->value -= 4 * first;302 }303}304 305// Implements some save and restore functions as described by ELF V2 ABI to be306// compatible with GCC. With GCC -Os, when the number of call-saved registers307// exceeds a certain threshold, GCC generates _savegpr0_* _restgpr0_* calls and308// expects the linker to define them. See309// https://sourceware.org/pipermail/binutils/2002-February/017444.html and310// https://sourceware.org/pipermail/binutils/2004-August/036765.html . This is311// weird because libgcc.a would be the natural place. The linker generation312// approach has the advantage that the linker can generate multiple copies to313// avoid long branch thunks. However, we don't consider the advantage314// significant enough to complicate our trunk implementation, so we take the315// simple approach and synthesize .text sections providing the implementation.316void elf::addPPC64SaveRestore(Ctx &ctx) {317 constexpr uint32_t blr = 0x4e800020, mtlr_0 = 0x7c0803a6;318 319 // _restgpr0_14: ld 14, -144(1); _restgpr0_15: ld 15, -136(1); ...320 // Tail: ld 0, 16(1); mtlr 0; blr321 writeSequence(ctx, "_restgpr0_", 14, 0xe9c1ff70, {0xe8010010, mtlr_0, blr});322 // _restgpr1_14: ld 14, -144(12); _restgpr1_15: ld 15, -136(12); ...323 // Tail: blr324 writeSequence(ctx, "_restgpr1_", 14, 0xe9ccff70, {blr});325 // _savegpr0_14: std 14, -144(1); _savegpr0_15: std 15, -136(1); ...326 // Tail: std 0, 16(1); blr327 writeSequence(ctx, "_savegpr0_", 14, 0xf9c1ff70, {0xf8010010, blr});328 // _savegpr1_14: std 14, -144(12); _savegpr1_15: std 15, -136(12); ...329 // Tail: blr330 writeSequence(ctx, "_savegpr1_", 14, 0xf9ccff70, {blr});331}332 333// Find the R_PPC64_ADDR64 in .rela.toc with matching offset.334template <typename ELFT>335static std::pair<Defined *, int64_t>336getRelaTocSymAndAddend(InputSectionBase *tocSec, uint64_t offset) {337 // .rela.toc contains exclusively R_PPC64_ADDR64 relocations sorted by338 // r_offset: 0, 8, 16, etc. For a given Offset, Offset / 8 gives us the339 // relocation index in most cases.340 //341 // In rare cases a TOC entry may store a constant that doesn't need an342 // R_PPC64_ADDR64, the corresponding r_offset is therefore missing. Offset / 8343 // points to a relocation with larger r_offset. Do a linear probe then.344 // Constants are extremely uncommon in .toc and the extra number of array345 // accesses can be seen as a small constant.346 ArrayRef<typename ELFT::Rela> relas =347 tocSec->template relsOrRelas<ELFT>().relas;348 if (relas.empty())349 return {};350 uint64_t index = std::min<uint64_t>(offset / 8, relas.size() - 1);351 for (;;) {352 if (relas[index].r_offset == offset) {353 Symbol &sym = tocSec->file->getRelocTargetSym(relas[index]);354 return {dyn_cast<Defined>(&sym), getAddend<ELFT>(relas[index])};355 }356 if (relas[index].r_offset < offset || index == 0)357 break;358 --index;359 }360 return {};361}362 363// When accessing a symbol defined in another translation unit, compilers364// reserve a .toc entry, allocate a local label and generate toc-indirect365// instructions:366//367// addis 3, 2, .LC0@toc@ha # R_PPC64_TOC16_HA368// ld 3, .LC0@toc@l(3) # R_PPC64_TOC16_LO_DS, load the address from a .toc entry369// ld/lwa 3, 0(3) # load the value from the address370//371// .section .toc,"aw",@progbits372// .LC0: .tc var[TC],var373//374// If var is defined, non-preemptable and addressable with a 32-bit signed375// offset from the toc base, the address of var can be computed by adding an376// offset to the toc base, saving a load.377//378// addis 3,2,var@toc@ha # this may be relaxed to a nop,379// addi 3,3,var@toc@l # then this becomes addi 3,2,var@toc380// ld/lwa 3, 0(3) # load the value from the address381//382// Returns true if the relaxation is performed.383static bool tryRelaxPPC64TocIndirection(Ctx &ctx, const Relocation &rel,384 uint8_t *bufLoc) {385 assert(ctx.arg.tocOptimize);386 if (rel.addend < 0)387 return false;388 389 // If the symbol is not the .toc section, this isn't a toc-indirection.390 Defined *defSym = dyn_cast<Defined>(rel.sym);391 if (!defSym || !defSym->isSection() || defSym->section->name != ".toc")392 return false;393 394 Defined *d;395 int64_t addend;396 auto *tocISB = cast<InputSectionBase>(defSym->section);397 std::tie(d, addend) =398 ctx.arg.isLE ? getRelaTocSymAndAddend<ELF64LE>(tocISB, rel.addend)399 : getRelaTocSymAndAddend<ELF64BE>(tocISB, rel.addend);400 401 // Only non-preemptable defined symbols can be relaxed.402 if (!d || d->isPreemptible)403 return false;404 405 // R_PPC64_ADDR64 should have created a canonical PLT for the non-preemptable406 // ifunc and changed its type to STT_FUNC.407 assert(!d->isGnuIFunc());408 409 // Two instructions can materialize a 32-bit signed offset from the toc base.410 uint64_t tocRelative = d->getVA(ctx, addend) - getPPC64TocBase(ctx);411 if (!isInt<32>(tocRelative))412 return false;413 414 // Add PPC64TocOffset that will be subtracted by PPC64::relocate().415 static_cast<const PPC64 &>(*ctx.target)416 .relaxGot(bufLoc, rel, tocRelative + ppc64TocOffset);417 return true;418}419 420// Relocation masks following the #lo(value), #hi(value), #ha(value),421// #higher(value), #highera(value), #highest(value), and #highesta(value)422// macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi423// document.424static uint16_t lo(uint64_t v) { return v; }425static uint16_t hi(uint64_t v) { return v >> 16; }426static uint64_t ha(uint64_t v) { return (v + 0x8000) >> 16; }427static uint16_t higher(uint64_t v) { return v >> 32; }428static uint16_t highera(uint64_t v) { return (v + 0x8000) >> 32; }429static uint16_t highest(uint64_t v) { return v >> 48; }430static uint16_t highesta(uint64_t v) { return (v + 0x8000) >> 48; }431 432// Extracts the 'PO' field of an instruction encoding.433static uint8_t getPrimaryOpCode(uint32_t encoding) { return (encoding >> 26); }434 435static bool isDQFormInstruction(uint32_t encoding) {436 switch (getPrimaryOpCode(encoding)) {437 default:438 return false;439 case 6: // Power10 paired loads/stores (lxvp, stxvp).440 case 56:441 // The only instruction with a primary opcode of 56 is `lq`.442 return true;443 case 61:444 // There are both DS and DQ instruction forms with this primary opcode.445 // Namely `lxv` and `stxv` are the DQ-forms that use it.446 // The DS 'XO' bits being set to 01 is restricted to DQ form.447 return (encoding & 3) == 0x1;448 }449}450 451static bool isDSFormInstruction(PPCLegacyInsn insn) {452 switch (insn) {453 default:454 return false;455 case PPCLegacyInsn::LWA:456 case PPCLegacyInsn::LD:457 case PPCLegacyInsn::LXSD:458 case PPCLegacyInsn::LXSSP:459 case PPCLegacyInsn::STD:460 case PPCLegacyInsn::STXSD:461 case PPCLegacyInsn::STXSSP:462 return true;463 }464}465 466static PPCLegacyInsn getPPCLegacyInsn(uint32_t encoding) {467 uint32_t opc = encoding & 0xfc000000;468 469 // If the primary opcode is shared between multiple instructions, we need to470 // fix it up to match the actual instruction we are after.471 if ((opc == 0xe4000000 || opc == 0xe8000000 || opc == 0xf4000000 ||472 opc == 0xf8000000) &&473 !isDQFormInstruction(encoding))474 opc = encoding & 0xfc000003;475 else if (opc == 0xf4000000)476 opc = encoding & 0xfc000007;477 else if (opc == 0x18000000)478 opc = encoding & 0xfc00000f;479 480 // If the value is not one of the enumerators in PPCLegacyInsn, we want to481 // return PPCLegacyInsn::NOINSN.482 if (!checkPPCLegacyInsn(opc))483 return PPCLegacyInsn::NOINSN;484 return static_cast<PPCLegacyInsn>(opc);485}486 487static PPCPrefixedInsn getPCRelativeForm(PPCLegacyInsn insn) {488 switch (insn) {489#define PCREL_OPT(Legacy, PCRel, InsnMask) \490 case PPCLegacyInsn::Legacy: \491 return PPCPrefixedInsn::PCRel492#include "PPCInsns.def"493#undef PCREL_OPT494 }495 return PPCPrefixedInsn::NOINSN;496}497 498static LegacyToPrefixMask getInsnMask(PPCLegacyInsn insn) {499 switch (insn) {500#define PCREL_OPT(Legacy, PCRel, InsnMask) \501 case PPCLegacyInsn::Legacy: \502 return LegacyToPrefixMask::InsnMask503#include "PPCInsns.def"504#undef PCREL_OPT505 }506 return LegacyToPrefixMask::NOMASK;507}508static uint64_t getPCRelativeForm(uint32_t encoding) {509 PPCLegacyInsn origInsn = getPPCLegacyInsn(encoding);510 PPCPrefixedInsn pcrelInsn = getPCRelativeForm(origInsn);511 if (pcrelInsn == PPCPrefixedInsn::NOINSN)512 return UINT64_C(-1);513 LegacyToPrefixMask origInsnMask = getInsnMask(origInsn);514 uint64_t pcrelEncoding =515 (uint64_t)pcrelInsn | (encoding & (uint64_t)origInsnMask);516 517 // If the mask requires moving bit 28 to bit 5, do that now.518 if (origInsnMask == LegacyToPrefixMask::ST_STX28_TO5)519 pcrelEncoding |= (encoding & 0x8) << 23;520 return pcrelEncoding;521}522 523static bool isInstructionUpdateForm(uint32_t encoding) {524 switch (getPrimaryOpCode(encoding)) {525 default:526 return false;527 case LBZU:528 case LHAU:529 case LHZU:530 case LWZU:531 case LFSU:532 case LFDU:533 case STBU:534 case STHU:535 case STWU:536 case STFSU:537 case STFDU:538 return true;539 // LWA has the same opcode as LD, and the DS bits is what differentiates540 // between LD/LDU/LWA541 case LD:542 case STD:543 return (encoding & 3) == 1;544 }545}546 547// Compute the total displacement between the prefixed instruction that gets548// to the start of the data and the load/store instruction that has the offset549// into the data structure.550// For example:551// paddi 3, 0, 1000, 1552// lwz 3, 20(3)553// Should add up to 1020 for total displacement.554static int64_t getTotalDisp(uint64_t prefixedInsn, uint32_t accessInsn) {555 int64_t disp34 = llvm::SignExtend64(556 ((prefixedInsn & 0x3ffff00000000) >> 16) | (prefixedInsn & 0xffff), 34);557 int32_t disp16 = llvm::SignExtend32(accessInsn & 0xffff, 16);558 // For DS and DQ form instructions, we need to mask out the XO bits.559 if (isDQFormInstruction(accessInsn))560 disp16 &= ~0xf;561 else if (isDSFormInstruction(getPPCLegacyInsn(accessInsn)))562 disp16 &= ~0x3;563 return disp34 + disp16;564}565 566// There are a number of places when we either want to read or write an567// instruction when handling a half16 relocation type. On big-endian the buffer568// pointer is pointing into the middle of the word we want to extract, and on569// little-endian it is pointing to the start of the word. These 2 helpers are to570// simplify reading and writing in that context.571static void writeFromHalf16(Ctx &ctx, uint8_t *loc, uint32_t insn) {572 write32(ctx, ctx.arg.isLE ? loc : loc - 2, insn);573}574 575static uint32_t readFromHalf16(Ctx &ctx, const uint8_t *loc) {576 return read32(ctx, ctx.arg.isLE ? loc : loc - 2);577}578 579static uint64_t readPrefixedInst(Ctx &ctx, const uint8_t *loc) {580 uint64_t fullInstr = read64(ctx, loc);581 return ctx.arg.isLE ? (fullInstr << 32 | fullInstr >> 32) : fullInstr;582}583 584PPC64::PPC64(Ctx &ctx) : TargetInfo(ctx) {585 copyRel = R_PPC64_COPY;586 gotRel = R_PPC64_GLOB_DAT;587 pltRel = R_PPC64_JMP_SLOT;588 relativeRel = R_PPC64_RELATIVE;589 iRelativeRel = R_PPC64_IRELATIVE;590 symbolicRel = R_PPC64_ADDR64;591 pltHeaderSize = 60;592 pltEntrySize = 4;593 ipltEntrySize = 16; // PPC64PltCallStub::size594 gotHeaderEntriesNum = 1;595 gotPltHeaderEntriesNum = 2;596 needsThunks = true;597 598 tlsModuleIndexRel = R_PPC64_DTPMOD64;599 tlsOffsetRel = R_PPC64_DTPREL64;600 601 tlsGotRel = R_PPC64_TPREL64;602 603 needsMoreStackNonSplit = false;604 605 // We need 64K pages (at least under glibc/Linux, the loader won't606 // set different permissions on a finer granularity than that).607 defaultMaxPageSize = 65536;608 609 // The PPC64 ELF ABI v1 spec, says:610 //611 // It is normally desirable to put segments with different characteristics612 // in separate 256 Mbyte portions of the address space, to give the613 // operating system full paging flexibility in the 64-bit address space.614 //615 // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers616 // use 0x10000000 as the starting address.617 defaultImageBase = 0x10000000;618 619 write32(ctx, trapInstr.data(), 0x7fe00008);620}621 622int PPC64::getTlsGdRelaxSkip(RelType type) const {623 // A __tls_get_addr call instruction is marked with 2 relocations:624 //625 // R_PPC64_TLSGD / R_PPC64_TLSLD: marker relocation626 // R_PPC64_REL24: __tls_get_addr627 //628 // After the relaxation we no longer call __tls_get_addr and should skip both629 // relocations to not create a false dependence on __tls_get_addr being630 // defined.631 if (type == R_PPC64_TLSGD || type == R_PPC64_TLSLD)632 return 2;633 return 1;634}635 636static uint32_t getEFlags(InputFile *file) {637 if (file->ekind == ELF64BEKind)638 return cast<ObjFile<ELF64BE>>(file)->getObj().getHeader().e_flags;639 return cast<ObjFile<ELF64LE>>(file)->getObj().getHeader().e_flags;640}641 642// This file implements v2 ABI. This function makes sure that all643// object files have v2 or an unspecified version as an ABI version.644uint32_t PPC64::calcEFlags() const {645 for (InputFile *f : ctx.objectFiles) {646 uint32_t flag = getEFlags(f);647 if (flag == 1)648 ErrAlways(ctx) << f << ": ABI version 1 is not supported";649 else if (flag > 2)650 ErrAlways(ctx) << f << ": unrecognized e_flags: " << flag;651 }652 return 2;653}654 655void PPC64::relaxGot(uint8_t *loc, const Relocation &rel, uint64_t val) const {656 switch (rel.type) {657 case R_PPC64_TOC16_HA:658 // Convert "addis reg, 2, .LC0@toc@h" to "addis reg, 2, var@toc@h" or "nop".659 relocate(loc, rel, val);660 break;661 case R_PPC64_TOC16_LO_DS: {662 // Convert "ld reg, .LC0@toc@l(reg)" to "addi reg, reg, var@toc@l" or663 // "addi reg, 2, var@toc".664 uint32_t insn = readFromHalf16(ctx, loc);665 if (getPrimaryOpCode(insn) != LD)666 ErrAlways(ctx)667 << "expected a 'ld' for got-indirect to toc-relative relaxing";668 writeFromHalf16(ctx, loc, (insn & 0x03ffffff) | 0x38000000);669 relocateNoSym(loc, R_PPC64_TOC16_LO, val);670 break;671 }672 case R_PPC64_GOT_PCREL34: {673 // Clear the first 8 bits of the prefix and the first 6 bits of the674 // instruction (the primary opcode).675 uint64_t insn = readPrefixedInst(ctx, loc);676 if ((insn & 0xfc000000) != 0xe4000000)677 ErrAlways(ctx)678 << "expected a 'pld' for got-indirect to pc-relative relaxing";679 insn &= ~0xff000000fc000000;680 681 // Replace the cleared bits with the values for PADDI (0x600000038000000);682 insn |= 0x600000038000000;683 writePrefixedInst(ctx, loc, insn);684 relocate(loc, rel, val);685 break;686 }687 case R_PPC64_PCREL_OPT: {688 // We can only relax this if the R_PPC64_GOT_PCREL34 at this offset can689 // be relaxed. The eligibility for the relaxation needs to be determined690 // on that relocation since this one does not relocate a symbol.691 uint64_t insn = readPrefixedInst(ctx, loc);692 uint32_t accessInsn = read32(ctx, loc + rel.addend);693 uint64_t pcRelInsn = getPCRelativeForm(accessInsn);694 695 // This error is not necessary for correctness but is emitted for now696 // to ensure we don't miss these opportunities in real code. It can be697 // removed at a later date.698 if (pcRelInsn == UINT64_C(-1)) {699 Err(ctx)700 << "unrecognized instruction for R_PPC64_PCREL_OPT relaxation: 0x"701 << utohexstr(accessInsn, true);702 break;703 }704 705 int64_t totalDisp = getTotalDisp(insn, accessInsn);706 if (!isInt<34>(totalDisp))707 break; // Displacement doesn't fit.708 // Convert the PADDI to the prefixed version of accessInsn and convert709 // accessInsn to a nop.710 writePrefixedInst(ctx, loc,711 pcRelInsn | ((totalDisp & 0x3ffff0000) << 16) |712 (totalDisp & 0xffff));713 write32(ctx, loc + rel.addend, NOP); // nop accessInsn.714 break;715 }716 default:717 llvm_unreachable("unexpected relocation type");718 }719}720 721void PPC64::relaxTlsGdToLe(uint8_t *loc, const Relocation &rel,722 uint64_t val) const {723 // Reference: 3.7.4.2 of the 64-bit ELF V2 abi supplement.724 // The general dynamic code sequence for a global `x` will look like:725 // Instruction Relocation Symbol726 // addis r3, r2, x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x727 // addi r3, r3, x@got@tlsgd@l R_PPC64_GOT_TLSGD16_LO x728 // bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x729 // R_PPC64_REL24 __tls_get_addr730 // nop None None731 732 // Relaxing to local exec entails converting:733 // addis r3, r2, x@got@tlsgd@ha into nop734 // addi r3, r3, x@got@tlsgd@l into addis r3, r13, x@tprel@ha735 // bl __tls_get_addr(x@tlsgd) into nop736 // nop into addi r3, r3, x@tprel@l737 738 switch (rel.type) {739 case R_PPC64_GOT_TLSGD16_HA:740 writeFromHalf16(ctx, loc, NOP);741 break;742 case R_PPC64_GOT_TLSGD16:743 case R_PPC64_GOT_TLSGD16_LO:744 writeFromHalf16(ctx, loc, 0x3c6d0000); // addis r3, r13745 relocateNoSym(loc, R_PPC64_TPREL16_HA, val);746 break;747 case R_PPC64_GOT_TLSGD_PCREL34:748 // Relax from paddi r3, 0, x@got@tlsgd@pcrel, 1 to749 // paddi r3, r13, x@tprel, 0750 writePrefixedInst(ctx, loc, 0x06000000386d0000);751 relocateNoSym(loc, R_PPC64_TPREL34, val);752 break;753 case R_PPC64_TLSGD: {754 // PC Relative Relaxation:755 // Relax from bl __tls_get_addr@notoc(x@tlsgd) to756 // nop757 // TOC Relaxation:758 // Relax from bl __tls_get_addr(x@tlsgd)759 // nop760 // to761 // nop762 // addi r3, r3, x@tprel@l763 const uintptr_t locAsInt = reinterpret_cast<uintptr_t>(loc);764 if (locAsInt % 4 == 0) {765 write32(ctx, loc, NOP); // nop766 write32(ctx, loc + 4, 0x38630000); // addi r3, r3767 // Since we are relocating a half16 type relocation and Loc + 4 points to768 // the start of an instruction we need to advance the buffer by an extra769 // 2 bytes on BE.770 relocateNoSym(loc + 4 + (ctx.arg.ekind == ELF64BEKind ? 2 : 0),771 R_PPC64_TPREL16_LO, val);772 } else if (locAsInt % 4 == 1) {773 write32(ctx, loc - 1, NOP);774 } else {775 Err(ctx) << "R_PPC64_TLSGD has unexpected byte alignment";776 }777 break;778 }779 default:780 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");781 }782}783 784void PPC64::relaxTlsLdToLe(uint8_t *loc, const Relocation &rel,785 uint64_t val) const {786 // Reference: 3.7.4.3 of the 64-bit ELF V2 abi supplement.787 // The local dynamic code sequence for a global `x` will look like:788 // Instruction Relocation Symbol789 // addis r3, r2, x@got@tlsld@ha R_PPC64_GOT_TLSLD16_HA x790 // addi r3, r3, x@got@tlsld@l R_PPC64_GOT_TLSLD16_LO x791 // bl __tls_get_addr(x@tlsgd) R_PPC64_TLSLD x792 // R_PPC64_REL24 __tls_get_addr793 // nop None None794 795 // Relaxing to local exec entails converting:796 // addis r3, r2, x@got@tlsld@ha into nop797 // addi r3, r3, x@got@tlsld@l into addis r3, r13, 0798 // bl __tls_get_addr(x@tlsgd) into nop799 // nop into addi r3, r3, 4096800 801 switch (rel.type) {802 case R_PPC64_GOT_TLSLD16_HA:803 writeFromHalf16(ctx, loc, NOP);804 break;805 case R_PPC64_GOT_TLSLD16_LO:806 writeFromHalf16(ctx, loc, 0x3c6d0000); // addis r3, r13, 0807 break;808 case R_PPC64_GOT_TLSLD_PCREL34:809 // Relax from paddi r3, 0, x1@got@tlsld@pcrel, 1 to810 // paddi r3, r13, 0x1000, 0811 writePrefixedInst(ctx, loc, 0x06000000386d1000);812 break;813 case R_PPC64_TLSLD: {814 // PC Relative Relaxation:815 // Relax from bl __tls_get_addr@notoc(x@tlsld)816 // to817 // nop818 // TOC Relaxation:819 // Relax from bl __tls_get_addr(x@tlsld)820 // nop821 // to822 // nop823 // addi r3, r3, 4096824 const uintptr_t locAsInt = reinterpret_cast<uintptr_t>(loc);825 if (locAsInt % 4 == 0) {826 write32(ctx, loc, NOP);827 write32(ctx, loc + 4, 0x38631000); // addi r3, r3, 4096828 } else if (locAsInt % 4 == 1) {829 write32(ctx, loc - 1, NOP);830 } else {831 Err(ctx) << "R_PPC64_TLSLD has unexpected byte alignment";832 }833 break;834 }835 case R_PPC64_DTPREL16:836 case R_PPC64_DTPREL16_HA:837 case R_PPC64_DTPREL16_HI:838 case R_PPC64_DTPREL16_DS:839 case R_PPC64_DTPREL16_LO:840 case R_PPC64_DTPREL16_LO_DS:841 case R_PPC64_DTPREL34:842 relocate(loc, rel, val);843 break;844 default:845 llvm_unreachable("unsupported relocation for TLS LD to LE relaxation");846 }847}848 849// Map X-Form instructions to their DS-Form counterparts, if applicable.850// The full encoding is returned here to distinguish between the different851// DS-Form instructions.852unsigned elf::getPPCDSFormOp(unsigned secondaryOp) {853 switch (secondaryOp) {854 case LWAX:855 return (LWA << 26) | 0x2;856 case LDX:857 return LD << 26;858 case STDX:859 return STD << 26;860 default:861 return 0;862 }863}864 865unsigned elf::getPPCDFormOp(unsigned secondaryOp) {866 switch (secondaryOp) {867 case LBZX:868 return LBZ << 26;869 case LHZX:870 return LHZ << 26;871 case LWZX:872 return LWZ << 26;873 case STBX:874 return STB << 26;875 case STHX:876 return STH << 26;877 case STWX:878 return STW << 26;879 case LHAX:880 return LHA << 26;881 case LFSX:882 return LFS << 26;883 case LFDX:884 return LFD << 26;885 case STFSX:886 return STFS << 26;887 case STFDX:888 return STFD << 26;889 case ADD:890 return ADDI << 26;891 default:892 return 0;893 }894}895 896void PPC64::relaxTlsIeToLe(uint8_t *loc, const Relocation &rel,897 uint64_t val) const {898 // The initial exec code sequence for a global `x` will look like:899 // Instruction Relocation Symbol900 // addis r9, r2, x@got@tprel@ha R_PPC64_GOT_TPREL16_HA x901 // ld r9, x@got@tprel@l(r9) R_PPC64_GOT_TPREL16_LO_DS x902 // add r9, r9, x@tls R_PPC64_TLS x903 904 // Relaxing to local exec entails converting:905 // addis r9, r2, x@got@tprel@ha into nop906 // ld r9, x@got@tprel@l(r9) into addis r9, r13, x@tprel@ha907 // add r9, r9, x@tls into addi r9, r9, x@tprel@l908 909 // x@tls R_PPC64_TLS is a relocation which does not compute anything,910 // it is replaced with r13 (thread pointer).911 912 // The add instruction in the initial exec sequence has multiple variations913 // that need to be handled. If we are building an address it will use an add914 // instruction, if we are accessing memory it will use any of the X-form915 // indexed load or store instructions.916 917 unsigned offset = (ctx.arg.ekind == ELF64BEKind) ? 2 : 0;918 switch (rel.type) {919 case R_PPC64_GOT_TPREL16_HA:920 write32(ctx, loc - offset, NOP);921 break;922 case R_PPC64_GOT_TPREL16_LO_DS:923 case R_PPC64_GOT_TPREL16_DS: {924 uint32_t regNo = read32(ctx, loc - offset) & 0x03e00000; // bits 6-10925 write32(ctx, loc - offset, 0x3c0d0000 | regNo); // addis RegNo, r13926 relocateNoSym(loc, R_PPC64_TPREL16_HA, val);927 break;928 }929 case R_PPC64_GOT_TPREL_PCREL34: {930 const uint64_t pldRT = readPrefixedInst(ctx, loc) & 0x0000000003e00000;931 // paddi RT(from pld), r13, symbol@tprel, 0932 writePrefixedInst(ctx, loc, 0x06000000380d0000 | pldRT);933 relocateNoSym(loc, R_PPC64_TPREL34, val);934 break;935 }936 case R_PPC64_TLS: {937 const uintptr_t locAsInt = reinterpret_cast<uintptr_t>(loc);938 if (locAsInt % 4 == 0) {939 uint32_t primaryOp = getPrimaryOpCode(read32(ctx, loc));940 if (primaryOp != 31)941 ErrAlways(ctx) << "unrecognized instruction for IE to LE R_PPC64_TLS";942 uint32_t secondaryOp = (read32(ctx, loc) & 0x000007fe) >> 1; // bits 21-30943 uint32_t dFormOp = getPPCDFormOp(secondaryOp);944 uint32_t finalReloc;945 if (dFormOp == 0) { // Expecting a DS-Form instruction.946 dFormOp = getPPCDSFormOp(secondaryOp);947 if (dFormOp == 0)948 ErrAlways(ctx) << "unrecognized instruction for IE to LE R_PPC64_TLS";949 finalReloc = R_PPC64_TPREL16_LO_DS;950 } else951 finalReloc = R_PPC64_TPREL16_LO;952 write32(ctx, loc, dFormOp | (read32(ctx, loc) & 0x03ff0000));953 relocateNoSym(loc + offset, finalReloc, val);954 } else if (locAsInt % 4 == 1) {955 // If the offset is not 4 byte aligned then we have a PCRel type reloc.956 // This version of the relocation is offset by one byte from the957 // instruction it references.958 uint32_t tlsInstr = read32(ctx, loc - 1);959 uint32_t primaryOp = getPrimaryOpCode(tlsInstr);960 if (primaryOp != 31)961 Err(ctx) << "unrecognized instruction for IE to LE R_PPC64_TLS";962 uint32_t secondaryOp = (tlsInstr & 0x000007FE) >> 1; // bits 21-30963 // The add is a special case and should be turned into a nop. The paddi964 // that comes before it will already have computed the address of the965 // symbol.966 if (secondaryOp == 266) {967 // Check if the add uses the same result register as the input register.968 uint32_t rt = (tlsInstr & 0x03E00000) >> 21; // bits 6-10969 uint32_t ra = (tlsInstr & 0x001F0000) >> 16; // bits 11-15970 if (ra == rt) {971 write32(ctx, loc - 1, NOP);972 } else {973 // mr rt, ra974 write32(ctx, loc - 1,975 0x7C000378 | (rt << 16) | (ra << 21) | (ra << 11));976 }977 } else {978 uint32_t dFormOp = getPPCDFormOp(secondaryOp);979 if (dFormOp == 0) { // Expecting a DS-Form instruction.980 dFormOp = getPPCDSFormOp(secondaryOp);981 if (dFormOp == 0)982 Err(ctx) << "unrecognized instruction for IE to LE R_PPC64_TLS";983 }984 write32(ctx, loc - 1, (dFormOp | (tlsInstr & 0x03ff0000)));985 }986 } else {987 Err(ctx) << "R_PPC64_TLS must be either 4 byte aligned or one byte "988 "offset from 4 byte aligned";989 }990 break;991 }992 default:993 llvm_unreachable("unknown relocation for IE to LE");994 break;995 }996}997 998RelExpr PPC64::getRelExpr(RelType type, const Symbol &s,999 const uint8_t *loc) const {1000 switch (type) {1001 case R_PPC64_NONE:1002 return R_NONE;1003 case R_PPC64_ADDR16:1004 case R_PPC64_ADDR16_DS:1005 case R_PPC64_ADDR16_HA:1006 case R_PPC64_ADDR16_HI:1007 case R_PPC64_ADDR16_HIGH:1008 case R_PPC64_ADDR16_HIGHER:1009 case R_PPC64_ADDR16_HIGHERA:1010 case R_PPC64_ADDR16_HIGHEST:1011 case R_PPC64_ADDR16_HIGHESTA:1012 case R_PPC64_ADDR16_LO:1013 case R_PPC64_ADDR16_LO_DS:1014 case R_PPC64_ADDR32:1015 case R_PPC64_ADDR64:1016 return R_ABS;1017 case R_PPC64_GOT16:1018 case R_PPC64_GOT16_DS:1019 case R_PPC64_GOT16_HA:1020 case R_PPC64_GOT16_HI:1021 case R_PPC64_GOT16_LO:1022 case R_PPC64_GOT16_LO_DS:1023 return R_GOT_OFF;1024 case R_PPC64_TOC16:1025 case R_PPC64_TOC16_DS:1026 case R_PPC64_TOC16_HI:1027 case R_PPC64_TOC16_LO:1028 return R_GOTREL;1029 case R_PPC64_GOT_PCREL34:1030 case R_PPC64_GOT_TPREL_PCREL34:1031 case R_PPC64_PCREL_OPT:1032 return R_GOT_PC;1033 case R_PPC64_TOC16_HA:1034 case R_PPC64_TOC16_LO_DS:1035 return ctx.arg.tocOptimize ? RE_PPC64_RELAX_TOC : R_GOTREL;1036 case R_PPC64_TOC:1037 return RE_PPC64_TOCBASE;1038 case R_PPC64_REL14:1039 case R_PPC64_REL24:1040 return RE_PPC64_CALL_PLT;1041 case R_PPC64_REL24_NOTOC:1042 return R_PLT_PC;1043 case R_PPC64_REL16_LO:1044 case R_PPC64_REL16_HA:1045 case R_PPC64_REL16_HI:1046 case R_PPC64_REL32:1047 case R_PPC64_REL64:1048 case R_PPC64_PCREL34:1049 return R_PC;1050 case R_PPC64_GOT_TLSGD16:1051 case R_PPC64_GOT_TLSGD16_HA:1052 case R_PPC64_GOT_TLSGD16_HI:1053 case R_PPC64_GOT_TLSGD16_LO:1054 return R_TLSGD_GOT;1055 case R_PPC64_GOT_TLSGD_PCREL34:1056 return R_TLSGD_PC;1057 case R_PPC64_GOT_TLSLD16:1058 case R_PPC64_GOT_TLSLD16_HA:1059 case R_PPC64_GOT_TLSLD16_HI:1060 case R_PPC64_GOT_TLSLD16_LO:1061 return R_TLSLD_GOT;1062 case R_PPC64_GOT_TLSLD_PCREL34:1063 return R_TLSLD_PC;1064 case R_PPC64_GOT_TPREL16_HA:1065 case R_PPC64_GOT_TPREL16_LO_DS:1066 case R_PPC64_GOT_TPREL16_DS:1067 case R_PPC64_GOT_TPREL16_HI:1068 return R_GOT_OFF;1069 case R_PPC64_GOT_DTPREL16_HA:1070 case R_PPC64_GOT_DTPREL16_LO_DS:1071 case R_PPC64_GOT_DTPREL16_DS:1072 case R_PPC64_GOT_DTPREL16_HI:1073 return R_TLSLD_GOT_OFF;1074 case R_PPC64_TPREL16:1075 case R_PPC64_TPREL16_HA:1076 case R_PPC64_TPREL16_LO:1077 case R_PPC64_TPREL16_HI:1078 case R_PPC64_TPREL16_DS:1079 case R_PPC64_TPREL16_LO_DS:1080 case R_PPC64_TPREL16_HIGHER:1081 case R_PPC64_TPREL16_HIGHERA:1082 case R_PPC64_TPREL16_HIGHEST:1083 case R_PPC64_TPREL16_HIGHESTA:1084 case R_PPC64_TPREL34:1085 return R_TPREL;1086 case R_PPC64_DTPREL16:1087 case R_PPC64_DTPREL16_DS:1088 case R_PPC64_DTPREL16_HA:1089 case R_PPC64_DTPREL16_HI:1090 case R_PPC64_DTPREL16_HIGHER:1091 case R_PPC64_DTPREL16_HIGHERA:1092 case R_PPC64_DTPREL16_HIGHEST:1093 case R_PPC64_DTPREL16_HIGHESTA:1094 case R_PPC64_DTPREL16_LO:1095 case R_PPC64_DTPREL16_LO_DS:1096 case R_PPC64_DTPREL64:1097 case R_PPC64_DTPREL34:1098 return R_DTPREL;1099 case R_PPC64_TLSGD:1100 return R_TLSDESC_CALL;1101 case R_PPC64_TLSLD:1102 return R_TLSLD_HINT;1103 case R_PPC64_TLS:1104 return R_TLSIE_HINT;1105 default:1106 Err(ctx) << getErrorLoc(ctx, loc) << "unknown relocation (" << type.v1107 << ") against symbol " << &s;1108 return R_NONE;1109 }1110}1111 1112RelType PPC64::getDynRel(RelType type) const {1113 if (type == R_PPC64_ADDR64 || type == R_PPC64_TOC)1114 return R_PPC64_ADDR64;1115 return R_PPC64_NONE;1116}1117 1118int64_t PPC64::getImplicitAddend(const uint8_t *buf, RelType type) const {1119 switch (type) {1120 case R_PPC64_NONE:1121 case R_PPC64_GLOB_DAT:1122 case R_PPC64_JMP_SLOT:1123 return 0;1124 case R_PPC64_REL32:1125 return SignExtend64<32>(read32(ctx, buf));1126 case R_PPC64_ADDR64:1127 case R_PPC64_REL64:1128 case R_PPC64_RELATIVE:1129 case R_PPC64_IRELATIVE:1130 case R_PPC64_DTPMOD64:1131 case R_PPC64_DTPREL64:1132 case R_PPC64_TPREL64:1133 return read64(ctx, buf);1134 default:1135 InternalErr(ctx, buf) << "cannot read addend for relocation " << type;1136 return 0;1137 }1138}1139 1140void PPC64::writeGotHeader(uint8_t *buf) const {1141 write64(ctx, buf, getPPC64TocBase(ctx));1142}1143 1144void PPC64::writePltHeader(uint8_t *buf) const {1145 // The generic resolver stub goes first.1146 write32(ctx, buf + 0, 0x7c0802a6); // mflr r01147 write32(ctx, buf + 4, 0x429f0005); // bcl 20,4*cr7+so,8 <_glink+0x8>1148 write32(ctx, buf + 8, 0x7d6802a6); // mflr r111149 write32(ctx, buf + 12, 0x7c0803a6); // mtlr r01150 write32(ctx, buf + 16, 0x7d8b6050); // subf r12, r11, r121151 write32(ctx, buf + 20, 0x380cffcc); // subi r0,r12,521152 write32(ctx, buf + 24, 0x7800f082); // srdi r0,r0,62,21153 write32(ctx, buf + 28, 0xe98b002c); // ld r12,44(r11)1154 write32(ctx, buf + 32, 0x7d6c5a14); // add r11,r12,r111155 write32(ctx, buf + 36, 0xe98b0000); // ld r12,0(r11)1156 write32(ctx, buf + 40, 0xe96b0008); // ld r11,8(r11)1157 write32(ctx, buf + 44, 0x7d8903a6); // mtctr r121158 write32(ctx, buf + 48, 0x4e800420); // bctr1159 1160 // The 'bcl' instruction will set the link register to the address of the1161 // following instruction ('mflr r11'). Here we store the offset from that1162 // instruction to the first entry in the GotPlt section.1163 int64_t gotPltOffset = ctx.in.gotPlt->getVA() - (ctx.in.plt->getVA() + 8);1164 write64(ctx, buf + 52, gotPltOffset);1165}1166 1167void PPC64::writePlt(uint8_t *buf, const Symbol &sym,1168 uint64_t /*pltEntryAddr*/) const {1169 int32_t offset = pltHeaderSize + sym.getPltIdx(ctx) * pltEntrySize;1170 // bl __glink_PLTresolve1171 write32(ctx, buf, 0x48000000 | ((-offset) & 0x03fffffc));1172}1173 1174void PPC64::writeIplt(uint8_t *buf, const Symbol &sym,1175 uint64_t /*pltEntryAddr*/) const {1176 writePPC64LoadAndBranch(ctx, buf,1177 sym.getGotPltVA(ctx) - getPPC64TocBase(ctx));1178}1179 1180static std::pair<RelType, uint64_t> toAddr16Rel(RelType type, uint64_t val) {1181 // Relocations relative to the toc-base need to be adjusted by the Toc offset.1182 uint64_t tocBiasedVal = val - ppc64TocOffset;1183 // Relocations relative to dtv[dtpmod] need to be adjusted by the DTP offset.1184 uint64_t dtpBiasedVal = val - dynamicThreadPointerOffset;1185 1186 switch (type) {1187 // TOC biased relocation.1188 case R_PPC64_GOT16:1189 case R_PPC64_GOT_TLSGD16:1190 case R_PPC64_GOT_TLSLD16:1191 case R_PPC64_TOC16:1192 return {R_PPC64_ADDR16, tocBiasedVal};1193 case R_PPC64_GOT16_DS:1194 case R_PPC64_TOC16_DS:1195 case R_PPC64_GOT_TPREL16_DS:1196 case R_PPC64_GOT_DTPREL16_DS:1197 return {R_PPC64_ADDR16_DS, tocBiasedVal};1198 case R_PPC64_GOT16_HA:1199 case R_PPC64_GOT_TLSGD16_HA:1200 case R_PPC64_GOT_TLSLD16_HA:1201 case R_PPC64_GOT_TPREL16_HA:1202 case R_PPC64_GOT_DTPREL16_HA:1203 case R_PPC64_TOC16_HA:1204 return {R_PPC64_ADDR16_HA, tocBiasedVal};1205 case R_PPC64_GOT16_HI:1206 case R_PPC64_GOT_TLSGD16_HI:1207 case R_PPC64_GOT_TLSLD16_HI:1208 case R_PPC64_GOT_TPREL16_HI:1209 case R_PPC64_GOT_DTPREL16_HI:1210 case R_PPC64_TOC16_HI:1211 return {R_PPC64_ADDR16_HI, tocBiasedVal};1212 case R_PPC64_GOT16_LO:1213 case R_PPC64_GOT_TLSGD16_LO:1214 case R_PPC64_GOT_TLSLD16_LO:1215 case R_PPC64_TOC16_LO:1216 return {R_PPC64_ADDR16_LO, tocBiasedVal};1217 case R_PPC64_GOT16_LO_DS:1218 case R_PPC64_TOC16_LO_DS:1219 case R_PPC64_GOT_TPREL16_LO_DS:1220 case R_PPC64_GOT_DTPREL16_LO_DS:1221 return {R_PPC64_ADDR16_LO_DS, tocBiasedVal};1222 1223 // Dynamic Thread pointer biased relocation types.1224 case R_PPC64_DTPREL16:1225 return {R_PPC64_ADDR16, dtpBiasedVal};1226 case R_PPC64_DTPREL16_DS:1227 return {R_PPC64_ADDR16_DS, dtpBiasedVal};1228 case R_PPC64_DTPREL16_HA:1229 return {R_PPC64_ADDR16_HA, dtpBiasedVal};1230 case R_PPC64_DTPREL16_HI:1231 return {R_PPC64_ADDR16_HI, dtpBiasedVal};1232 case R_PPC64_DTPREL16_HIGHER:1233 return {R_PPC64_ADDR16_HIGHER, dtpBiasedVal};1234 case R_PPC64_DTPREL16_HIGHERA:1235 return {R_PPC64_ADDR16_HIGHERA, dtpBiasedVal};1236 case R_PPC64_DTPREL16_HIGHEST:1237 return {R_PPC64_ADDR16_HIGHEST, dtpBiasedVal};1238 case R_PPC64_DTPREL16_HIGHESTA:1239 return {R_PPC64_ADDR16_HIGHESTA, dtpBiasedVal};1240 case R_PPC64_DTPREL16_LO:1241 return {R_PPC64_ADDR16_LO, dtpBiasedVal};1242 case R_PPC64_DTPREL16_LO_DS:1243 return {R_PPC64_ADDR16_LO_DS, dtpBiasedVal};1244 case R_PPC64_DTPREL64:1245 return {R_PPC64_ADDR64, dtpBiasedVal};1246 1247 default:1248 return {type, val};1249 }1250}1251 1252static bool isTocOptType(RelType type) {1253 switch (type) {1254 case R_PPC64_GOT16_HA:1255 case R_PPC64_GOT16_LO_DS:1256 case R_PPC64_TOC16_HA:1257 case R_PPC64_TOC16_LO_DS:1258 case R_PPC64_TOC16_LO:1259 return true;1260 default:1261 return false;1262 }1263}1264 1265// R_PPC64_TLSGD/R_PPC64_TLSLD is required to mark `bl __tls_get_addr` for1266// General Dynamic/Local Dynamic code sequences. If a GD/LD GOT relocation is1267// found but no R_PPC64_TLSGD/R_PPC64_TLSLD is seen, we assume that the1268// instructions are generated by very old IBM XL compilers. Work around the1269// issue by disabling GD/LD to IE/LE relaxation.1270template <class RelTy>1271static void checkPPC64TLSRelax(InputSectionBase &sec, Relocs<RelTy> rels) {1272 // Skip if sec is synthetic (sec.file is null) or if sec has been marked.1273 if (!sec.file || sec.file->ppc64DisableTLSRelax)1274 return;1275 bool hasGDLD = false;1276 for (const RelTy &rel : rels) {1277 RelType type = rel.getType(false);1278 switch (type) {1279 case R_PPC64_TLSGD:1280 case R_PPC64_TLSLD:1281 return; // Found a marker1282 case R_PPC64_GOT_TLSGD16:1283 case R_PPC64_GOT_TLSGD16_HA:1284 case R_PPC64_GOT_TLSGD16_HI:1285 case R_PPC64_GOT_TLSGD16_LO:1286 case R_PPC64_GOT_TLSLD16:1287 case R_PPC64_GOT_TLSLD16_HA:1288 case R_PPC64_GOT_TLSLD16_HI:1289 case R_PPC64_GOT_TLSLD16_LO:1290 hasGDLD = true;1291 break;1292 }1293 }1294 if (hasGDLD) {1295 sec.file->ppc64DisableTLSRelax = true;1296 Warn(sec.file->ctx)1297 << sec.file1298 << ": disable TLS relaxation due to R_PPC64_GOT_TLS* relocations "1299 "without "1300 "R_PPC64_TLSGD/R_PPC64_TLSLD relocations";1301 }1302}1303 1304template <class ELFT, class RelTy>1305void PPC64::scanSectionImpl(InputSectionBase &sec, Relocs<RelTy> rels) {1306 RelocScan rs(ctx, &sec);1307 sec.relocations.reserve(rels.size());1308 checkPPC64TLSRelax<RelTy>(sec, rels);1309 for (auto it = rels.begin(); it != rels.end(); ++it) {1310 const RelTy &rel = *it;1311 uint64_t offset = rel.r_offset;1312 uint32_t symIdx = rel.getSymbol(false);1313 Symbol &sym = sec.getFile<ELFT>()->getSymbol(symIdx);1314 RelType type = rel.getType(false);1315 RelExpr expr =1316 ctx.target->getRelExpr(type, sym, sec.content().data() + offset);1317 if (expr == R_NONE)1318 continue;1319 if (sym.isUndefined() && symIdx != 0 &&1320 rs.maybeReportUndefined(cast<Undefined>(sym), offset))1321 continue;1322 1323 auto addend = getAddend<ELFT>(rel);1324 if (ctx.arg.isPic && type == R_PPC64_TOC)1325 addend += getPPC64TocBase(ctx);1326 1327 // We can separate the small code model relocations into 2 categories:1328 // 1) Those that access the compiler generated .toc sections.1329 // 2) Those that access the linker allocated got entries.1330 // lld allocates got entries to symbols on demand. Since we don't try to1331 // sort the got entries in any way, we don't have to track which objects1332 // have got-based small code model relocs. The .toc sections get placed1333 // after the end of the linker allocated .got section and we do sort those1334 // so sections addressed with small code model relocations come first.1335 if (type == R_PPC64_TOC16 || type == R_PPC64_TOC16_DS)1336 sec.file->ppc64SmallCodeModelTocRelocs = true;1337 1338 // Record the TOC entry (.toc + addend) as not relaxable. See the comment in1339 // PPC64::relocateAlloc().1340 if (type == R_PPC64_TOC16_LO && sym.isSection() && isa<Defined>(sym) &&1341 cast<Defined>(sym).section->name == ".toc")1342 ctx.ppc64noTocRelax.insert({&sym, addend});1343 1344 if ((type == R_PPC64_TLSGD && expr == R_TLSDESC_CALL) ||1345 (type == R_PPC64_TLSLD && expr == R_TLSLD_HINT)) {1346 auto it1 = it;1347 ++it1;1348 if (it1 == rels.end()) {1349 auto diag = Err(ctx);1350 diag << "R_PPC64_TLSGD/R_PPC64_TLSLD may not be the last "1351 "relocation";1352 printLocation(diag, sec, sym, offset);1353 continue;1354 }1355 1356 // Offset the 4-byte aligned R_PPC64_TLSGD by one byte in the NOTOC1357 // case, so we can discern it later from the toc-case.1358 if (it1->getType(/*isMips64EL=*/false) == R_PPC64_REL24_NOTOC)1359 ++offset;1360 }1361 1362 if (oneof<R_GOTREL, RE_PPC64_TOCBASE, RE_PPC64_RELAX_TOC>(expr))1363 ctx.in.got->hasGotOffRel.store(true, std::memory_order_relaxed);1364 1365 if (sym.isTls()) {1366 if (unsigned processed =1367 rs.handleTlsRelocation(expr, type, offset, sym, addend)) {1368 it += processed - 1;1369 continue;1370 }1371 }1372 rs.process(expr, type, offset, sym, addend);1373 }1374}1375 1376template <class ELFT> void PPC64::scanSection1(InputSectionBase &sec) {1377 auto relocs = sec.template relsOrRelas<ELFT>();1378 if (relocs.areRelocsCrel())1379 scanSectionImpl<ELFT>(sec, relocs.crels);1380 else1381 scanSectionImpl<ELFT>(sec, relocs.relas);1382}1383 1384void PPC64::scanSection(InputSectionBase &sec) {1385 if (ctx.arg.isLE)1386 scanSection1<ELF64LE>(sec);1387 else1388 scanSection1<ELF64BE>(sec);1389}1390 1391void PPC64::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {1392 RelType type = rel.type;1393 bool shouldTocOptimize = isTocOptType(type);1394 // For dynamic thread pointer relative, toc-relative, and got-indirect1395 // relocations, proceed in terms of the corresponding ADDR16 relocation type.1396 std::tie(type, val) = toAddr16Rel(type, val);1397 1398 switch (type) {1399 case R_PPC64_ADDR14: {1400 checkAlignment(ctx, loc, val, 4, rel);1401 // Preserve the AA/LK bits in the branch instruction1402 uint8_t aalk = loc[3];1403 write16(ctx, loc + 2, (aalk & 3) | (val & 0xfffc));1404 break;1405 }1406 case R_PPC64_ADDR16:1407 checkIntUInt(ctx, loc, val, 16, rel);1408 write16(ctx, loc, val);1409 break;1410 case R_PPC64_ADDR32:1411 checkIntUInt(ctx, loc, val, 32, rel);1412 write32(ctx, loc, val);1413 break;1414 case R_PPC64_ADDR16_DS:1415 case R_PPC64_TPREL16_DS: {1416 checkInt(ctx, loc, val, 16, rel);1417 // DQ-form instructions use bits 28-31 as part of the instruction encoding1418 // DS-form instructions only use bits 30-31.1419 uint16_t mask = isDQFormInstruction(readFromHalf16(ctx, loc)) ? 0xf : 0x3;1420 checkAlignment(ctx, loc, lo(val), mask + 1, rel);1421 write16(ctx, loc, (read16(ctx, loc) & mask) | lo(val));1422 } break;1423 case R_PPC64_ADDR16_HA:1424 case R_PPC64_REL16_HA:1425 case R_PPC64_TPREL16_HA:1426 if (ctx.arg.tocOptimize && shouldTocOptimize && ha(val) == 0)1427 writeFromHalf16(ctx, loc, NOP);1428 else {1429 checkInt(ctx, loc, val + 0x8000, 32, rel);1430 write16(ctx, loc, ha(val));1431 }1432 break;1433 case R_PPC64_ADDR16_HI:1434 case R_PPC64_REL16_HI:1435 case R_PPC64_TPREL16_HI:1436 checkInt(ctx, loc, val, 32, rel);1437 write16(ctx, loc, hi(val));1438 break;1439 case R_PPC64_ADDR16_HIGH:1440 write16(ctx, loc, hi(val));1441 break;1442 case R_PPC64_ADDR16_HIGHER:1443 case R_PPC64_TPREL16_HIGHER:1444 write16(ctx, loc, higher(val));1445 break;1446 case R_PPC64_ADDR16_HIGHERA:1447 case R_PPC64_TPREL16_HIGHERA:1448 write16(ctx, loc, highera(val));1449 break;1450 case R_PPC64_ADDR16_HIGHEST:1451 case R_PPC64_TPREL16_HIGHEST:1452 write16(ctx, loc, highest(val));1453 break;1454 case R_PPC64_ADDR16_HIGHESTA:1455 case R_PPC64_TPREL16_HIGHESTA:1456 write16(ctx, loc, highesta(val));1457 break;1458 case R_PPC64_ADDR16_LO:1459 case R_PPC64_REL16_LO:1460 case R_PPC64_TPREL16_LO:1461 // When the high-adjusted part of a toc relocation evaluates to 0, it is1462 // changed into a nop. The lo part then needs to be updated to use the1463 // toc-pointer register r2, as the base register.1464 if (ctx.arg.tocOptimize && shouldTocOptimize && ha(val) == 0) {1465 uint32_t insn = readFromHalf16(ctx, loc);1466 if (isInstructionUpdateForm(insn))1467 Err(ctx) << getErrorLoc(ctx, loc)1468 << "can't toc-optimize an update instruction: 0x"1469 << utohexstr(insn, true);1470 writeFromHalf16(ctx, loc, (insn & 0xffe00000) | 0x00020000 | lo(val));1471 } else {1472 write16(ctx, loc, lo(val));1473 }1474 break;1475 case R_PPC64_ADDR16_LO_DS:1476 case R_PPC64_TPREL16_LO_DS: {1477 // DQ-form instructions use bits 28-31 as part of the instruction encoding1478 // DS-form instructions only use bits 30-31.1479 uint32_t insn = readFromHalf16(ctx, loc);1480 uint16_t mask = isDQFormInstruction(insn) ? 0xf : 0x3;1481 checkAlignment(ctx, loc, lo(val), mask + 1, rel);1482 if (ctx.arg.tocOptimize && shouldTocOptimize && ha(val) == 0) {1483 // When the high-adjusted part of a toc relocation evaluates to 0, it is1484 // changed into a nop. The lo part then needs to be updated to use the toc1485 // pointer register r2, as the base register.1486 if (isInstructionUpdateForm(insn))1487 Err(ctx) << getErrorLoc(ctx, loc)1488 << "can't toc-optimize an update instruction: 0x"1489 << utohexstr(insn, true);1490 insn &= 0xffe00000 | mask;1491 writeFromHalf16(ctx, loc, insn | 0x00020000 | lo(val));1492 } else {1493 write16(ctx, loc, (read16(ctx, loc) & mask) | lo(val));1494 }1495 } break;1496 case R_PPC64_TPREL16:1497 checkInt(ctx, loc, val, 16, rel);1498 write16(ctx, loc, val);1499 break;1500 case R_PPC64_REL32:1501 checkInt(ctx, loc, val, 32, rel);1502 write32(ctx, loc, val);1503 break;1504 case R_PPC64_ADDR64:1505 case R_PPC64_REL64:1506 case R_PPC64_TOC:1507 write64(ctx, loc, val);1508 break;1509 case R_PPC64_REL14: {1510 uint32_t mask = 0x0000FFFC;1511 checkInt(ctx, loc, val, 16, rel);1512 checkAlignment(ctx, loc, val, 4, rel);1513 write32(ctx, loc, (read32(ctx, loc) & ~mask) | (val & mask));1514 break;1515 }1516 case R_PPC64_REL24:1517 case R_PPC64_REL24_NOTOC: {1518 uint32_t mask = 0x03FFFFFC;1519 checkInt(ctx, loc, val, 26, rel);1520 checkAlignment(ctx, loc, val, 4, rel);1521 write32(ctx, loc, (read32(ctx, loc) & ~mask) | (val & mask));1522 break;1523 }1524 case R_PPC64_DTPREL64:1525 write64(ctx, loc, val - dynamicThreadPointerOffset);1526 break;1527 case R_PPC64_DTPREL34:1528 // The Dynamic Thread Vector actually points 0x8000 bytes past the start1529 // of the TLS block. Therefore, in the case of R_PPC64_DTPREL34 we first1530 // need to subtract that value then fallthrough to the general case.1531 val -= dynamicThreadPointerOffset;1532 [[fallthrough]];1533 case R_PPC64_PCREL34:1534 case R_PPC64_GOT_PCREL34:1535 case R_PPC64_GOT_TLSGD_PCREL34:1536 case R_PPC64_GOT_TLSLD_PCREL34:1537 case R_PPC64_GOT_TPREL_PCREL34:1538 case R_PPC64_TPREL34: {1539 const uint64_t si0Mask = 0x00000003ffff0000;1540 const uint64_t si1Mask = 0x000000000000ffff;1541 const uint64_t fullMask = 0x0003ffff0000ffff;1542 checkInt(ctx, loc, val, 34, rel);1543 1544 uint64_t instr = readPrefixedInst(ctx, loc) & ~fullMask;1545 writePrefixedInst(ctx, loc,1546 instr | ((val & si0Mask) << 16) | (val & si1Mask));1547 break;1548 }1549 // If we encounter a PCREL_OPT relocation that we won't optimize.1550 case R_PPC64_PCREL_OPT:1551 break;1552 default:1553 llvm_unreachable("unknown relocation");1554 }1555}1556 1557bool PPC64::needsThunk(RelExpr expr, RelType type, const InputFile *file,1558 uint64_t branchAddr, const Symbol &s, int64_t a) const {1559 if (type != R_PPC64_REL14 && type != R_PPC64_REL24 &&1560 type != R_PPC64_REL24_NOTOC)1561 return false;1562 1563 // If a function is in the Plt it needs to be called with a call-stub.1564 if (s.isInPlt(ctx))1565 return true;1566 1567 // This check looks at the st_other bits of the callee with relocation1568 // R_PPC64_REL14 or R_PPC64_REL24. If the value is 1, then the callee1569 // clobbers the TOC and we need an R2 save stub.1570 if (type != R_PPC64_REL24_NOTOC && (s.stOther >> 5) == 1)1571 return true;1572 1573 if (type == R_PPC64_REL24_NOTOC && (s.stOther >> 5) > 1)1574 return true;1575 1576 // An undefined weak symbol not in a PLT does not need a thunk. If it is1577 // hidden, its binding has been converted to local, so we just check1578 // isUndefined() here. A undefined non-weak symbol has been errored.1579 if (s.isUndefined())1580 return false;1581 1582 // If the offset exceeds the range of the branch type then it will need1583 // a range-extending thunk.1584 // See the comment in getRelocTargetVA() about RE_PPC64_CALL.1585 return !inBranchRange(1586 type, branchAddr,1587 s.getVA(ctx, a) + getPPC64GlobalEntryToLocalEntryOffset(ctx, s.stOther));1588}1589 1590uint32_t PPC64::getThunkSectionSpacing() const {1591 // See comment in Arch/ARM.cpp for a more detailed explanation of1592 // getThunkSectionSpacing(). For PPC64 we pick the constant here based on1593 // R_PPC64_REL24, which is used by unconditional branch instructions.1594 // 0x2000000 = (1 << 24-1) * 41595 return 0x2000000;1596}1597 1598bool PPC64::inBranchRange(RelType type, uint64_t src, uint64_t dst) const {1599 int64_t offset = dst - src;1600 if (type == R_PPC64_REL14)1601 return isInt<16>(offset);1602 if (type == R_PPC64_REL24 || type == R_PPC64_REL24_NOTOC)1603 return isInt<26>(offset);1604 llvm_unreachable("unsupported relocation type used in branch");1605}1606 1607RelExpr PPC64::adjustTlsExpr(RelType type, RelExpr expr) const {1608 if (type != R_PPC64_GOT_TLSGD_PCREL34 && expr == R_RELAX_TLS_GD_TO_IE)1609 return R_RELAX_TLS_GD_TO_IE_GOT_OFF;1610 if (expr == R_RELAX_TLS_LD_TO_LE)1611 return R_RELAX_TLS_LD_TO_LE_ABS;1612 return expr;1613}1614 1615RelExpr PPC64::adjustGotPcExpr(RelType type, int64_t addend,1616 const uint8_t *loc) const {1617 if ((type == R_PPC64_GOT_PCREL34 || type == R_PPC64_PCREL_OPT) &&1618 ctx.arg.pcRelOptimize) {1619 // It only makes sense to optimize pld since paddi means that the address1620 // of the object in the GOT is required rather than the object itself.1621 if ((readPrefixedInst(ctx, loc) & 0xfc000000) == 0xe4000000)1622 return RE_PPC64_RELAX_GOT_PC;1623 }1624 return R_GOT_PC;1625}1626 1627// Reference: 3.7.4.1 of the 64-bit ELF V2 abi supplement.1628// The general dynamic code sequence for a global `x` uses 4 instructions.1629// Instruction Relocation Symbol1630// addis r3, r2, x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x1631// addi r3, r3, x@got@tlsgd@l R_PPC64_GOT_TLSGD16_LO x1632// bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x1633// R_PPC64_REL24 __tls_get_addr1634// nop None None1635//1636// Relaxing to initial-exec entails:1637// 1) Convert the addis/addi pair that builds the address of the tls_index1638// struct for 'x' to an addis/ld pair that loads an offset from a got-entry.1639// 2) Convert the call to __tls_get_addr to a nop.1640// 3) Convert the nop following the call to an add of the loaded offset to the1641// thread pointer.1642// Since the nop must directly follow the call, the R_PPC64_TLSGD relocation is1643// used as the relaxation hint for both steps 2 and 3.1644void PPC64::relaxTlsGdToIe(uint8_t *loc, const Relocation &rel,1645 uint64_t val) const {1646 switch (rel.type) {1647 case R_PPC64_GOT_TLSGD16_HA:1648 // This is relaxed from addis rT, r2, sym@got@tlsgd@ha to1649 // addis rT, r2, sym@got@tprel@ha.1650 relocateNoSym(loc, R_PPC64_GOT_TPREL16_HA, val);1651 return;1652 case R_PPC64_GOT_TLSGD16:1653 case R_PPC64_GOT_TLSGD16_LO: {1654 // Relax from addi r3, rA, sym@got@tlsgd@l to1655 // ld r3, sym@got@tprel@l(rA)1656 uint32_t ra = (readFromHalf16(ctx, loc) & (0x1f << 16));1657 writeFromHalf16(ctx, loc, 0xe8600000 | ra);1658 relocateNoSym(loc, R_PPC64_GOT_TPREL16_LO_DS, val);1659 return;1660 }1661 case R_PPC64_GOT_TLSGD_PCREL34: {1662 // Relax from paddi r3, 0, sym@got@tlsgd@pcrel, 1 to1663 // pld r3, sym@got@tprel@pcrel1664 writePrefixedInst(ctx, loc, 0x04100000e4600000);1665 relocateNoSym(loc, R_PPC64_GOT_TPREL_PCREL34, val);1666 return;1667 }1668 case R_PPC64_TLSGD: {1669 // PC Relative Relaxation:1670 // Relax from bl __tls_get_addr@notoc(x@tlsgd) to1671 // nop1672 // TOC Relaxation:1673 // Relax from bl __tls_get_addr(x@tlsgd)1674 // nop1675 // to1676 // nop1677 // add r3, r3, r131678 const uintptr_t locAsInt = reinterpret_cast<uintptr_t>(loc);1679 if (locAsInt % 4 == 0) {1680 write32(ctx, loc, NOP); // bl __tls_get_addr(sym@tlsgd) --> nop1681 write32(ctx, loc + 4, 0x7c636a14); // nop --> add r3, r3, r131682 } else if (locAsInt % 4 == 1) {1683 // bl __tls_get_addr(sym@tlsgd) --> add r3, r3, r131684 write32(ctx, loc - 1, 0x7c636a14);1685 } else {1686 Err(ctx) << "R_PPC64_TLSGD has unexpected byte alignment";1687 }1688 return;1689 }1690 default:1691 llvm_unreachable("unsupported relocation for TLS GD to IE relaxation");1692 }1693}1694 1695void PPC64::relocateAlloc(InputSection &sec, uint8_t *buf) const {1696 uint64_t secAddr = sec.getOutputSection()->addr + sec.outSecOff;1697 uint64_t lastPPCRelaxedRelocOff = -1;1698 for (const Relocation &rel : sec.relocs()) {1699 uint8_t *loc = buf + rel.offset;1700 const uint64_t val = sec.getRelocTargetVA(ctx, rel, secAddr + rel.offset);1701 switch (rel.expr) {1702 case RE_PPC64_RELAX_GOT_PC: {1703 // The R_PPC64_PCREL_OPT relocation must appear immediately after1704 // R_PPC64_GOT_PCREL34 in the relocations table at the same offset.1705 // We can only relax R_PPC64_PCREL_OPT if we have also relaxed1706 // the associated R_PPC64_GOT_PCREL34 since only the latter has an1707 // associated symbol. So save the offset when relaxing R_PPC64_GOT_PCREL341708 // and only relax the other if the saved offset matches.1709 if (rel.type == R_PPC64_GOT_PCREL34)1710 lastPPCRelaxedRelocOff = rel.offset;1711 if (rel.type == R_PPC64_PCREL_OPT && rel.offset != lastPPCRelaxedRelocOff)1712 break;1713 relaxGot(loc, rel, val);1714 break;1715 }1716 case RE_PPC64_RELAX_TOC:1717 // rel.sym refers to the STT_SECTION symbol associated to the .toc input1718 // section. If an R_PPC64_TOC16_LO (.toc + addend) references the TOC1719 // entry, there may be R_PPC64_TOC16_HA not paired with1720 // R_PPC64_TOC16_LO_DS. Don't relax. This loses some relaxation1721 // opportunities but is safe.1722 if (ctx.ppc64noTocRelax.count({rel.sym, rel.addend}) ||1723 !tryRelaxPPC64TocIndirection(ctx, rel, loc))1724 relocate(loc, rel, val);1725 break;1726 case RE_PPC64_CALL:1727 // If this is a call to __tls_get_addr, it may be part of a TLS1728 // sequence that has been relaxed and turned into a nop. In this1729 // case, we don't want to handle it as a call.1730 if (read32(ctx, loc) == 0x60000000) // nop1731 break;1732 1733 // Patch a nop (0x60000000) to a ld.1734 if (rel.sym->needsTocRestore()) {1735 // gcc/gfortran 5.4, 6.3 and earlier versions do not add nop for1736 // recursive calls even if the function is preemptible. This is not1737 // wrong in the common case where the function is not preempted at1738 // runtime. Just ignore.1739 if ((rel.offset + 8 > sec.content().size() ||1740 read32(ctx, loc + 4) != 0x60000000) &&1741 rel.sym->file != sec.file) {1742 // Use substr(6) to remove the "__plt_" prefix.1743 Err(ctx) << getErrorLoc(ctx, loc) << "call to "1744 << toStr(ctx, *rel.sym).substr(6)1745 << " lacks nop, can't restore toc";1746 break;1747 }1748 write32(ctx, loc + 4, 0xe8410018); // ld %r2, 24(%r1)1749 }1750 relocate(loc, rel, val);1751 break;1752 case R_RELAX_TLS_GD_TO_IE:1753 case R_RELAX_TLS_GD_TO_IE_GOT_OFF:1754 relaxTlsGdToIe(loc, rel, val);1755 break;1756 case R_RELAX_TLS_GD_TO_LE:1757 relaxTlsGdToLe(loc, rel, val);1758 break;1759 case R_RELAX_TLS_LD_TO_LE_ABS:1760 relaxTlsLdToLe(loc, rel, val);1761 break;1762 case R_RELAX_TLS_IE_TO_LE:1763 relaxTlsIeToLe(loc, rel, val);1764 break;1765 default:1766 relocate(loc, rel, val);1767 break;1768 }1769 }1770}1771 1772// The prologue for a split-stack function is expected to look roughly1773// like this:1774// .Lglobal_entry_point:1775// # TOC pointer initialization.1776// ...1777// .Llocal_entry_point:1778// # load the __private_ss member of the threads tcbhead.1779// ld r0,-0x7000-64(r13)1780// # subtract the functions stack size from the stack pointer.1781// addis r12, r1, ha(-stack-frame size)1782// addi r12, r12, l(-stack-frame size)1783// # compare needed to actual and branch to allocate_more_stack if more1784// # space is needed, otherwise fallthrough to 'normal' function body.1785// cmpld cr7,r12,r01786// blt- cr7, .Lallocate_more_stack1787//1788// -) The allocate_more_stack block might be placed after the split-stack1789// prologue and the `blt-` replaced with a `bge+ .Lnormal_func_body`1790// instead.1791// -) If either the addis or addi is not needed due to the stack size being1792// smaller then 32K or a multiple of 64K they will be replaced with a nop,1793// but there will always be 2 instructions the linker can overwrite for the1794// adjusted stack size.1795//1796// The linkers job here is to increase the stack size used in the addis/addi1797// pair by split-stack-size-adjust.1798// addis r12, r1, ha(-stack-frame size - split-stack-adjust-size)1799// addi r12, r12, l(-stack-frame size - split-stack-adjust-size)1800bool PPC64::adjustPrologueForCrossSplitStack(uint8_t *loc, uint8_t *end,1801 uint8_t stOther) const {1802 // If the caller has a global entry point adjust the buffer past it. The start1803 // of the split-stack prologue will be at the local entry point.1804 loc += getPPC64GlobalEntryToLocalEntryOffset(ctx, stOther);1805 1806 // At the very least we expect to see a load of some split-stack data from the1807 // tcb, and 2 instructions that calculate the ending stack address this1808 // function will require. If there is not enough room for at least 31809 // instructions it can't be a split-stack prologue.1810 if (loc + 12 >= end)1811 return false;1812 1813 // First instruction must be `ld r0, -0x7000-64(r13)`1814 if (read32(ctx, loc) != 0xe80d8fc0)1815 return false;1816 1817 int16_t hiImm = 0;1818 int16_t loImm = 0;1819 // First instruction can be either an addis if the frame size is larger then1820 // 32K, or an addi if the size is less then 32K.1821 int32_t firstInstr = read32(ctx, loc + 4);1822 if (getPrimaryOpCode(firstInstr) == 15) {1823 hiImm = firstInstr & 0xFFFF;1824 } else if (getPrimaryOpCode(firstInstr) == 14) {1825 loImm = firstInstr & 0xFFFF;1826 } else {1827 return false;1828 }1829 1830 // Second instruction is either an addi or a nop. If the first instruction was1831 // an addi then LoImm is set and the second instruction must be a nop.1832 uint32_t secondInstr = read32(ctx, loc + 8);1833 if (!loImm && getPrimaryOpCode(secondInstr) == 14) {1834 loImm = secondInstr & 0xFFFF;1835 } else if (secondInstr != NOP) {1836 return false;1837 }1838 1839 // The register operands of the first instruction should be the stack-pointer1840 // (r1) as the input (RA) and r12 as the output (RT). If the second1841 // instruction is not a nop, then it should use r12 as both input and output.1842 auto checkRegOperands = [](uint32_t instr, uint8_t expectedRT,1843 uint8_t expectedRA) {1844 return ((instr & 0x3E00000) >> 21 == expectedRT) &&1845 ((instr & 0x1F0000) >> 16 == expectedRA);1846 };1847 if (!checkRegOperands(firstInstr, 12, 1))1848 return false;1849 if (secondInstr != NOP && !checkRegOperands(secondInstr, 12, 12))1850 return false;1851 1852 int32_t stackFrameSize = (hiImm * 65536) + loImm;1853 // Check that the adjusted size doesn't overflow what we can represent with 21854 // instructions.1855 if (stackFrameSize < ctx.arg.splitStackAdjustSize + INT32_MIN) {1856 Err(ctx) << getErrorLoc(ctx, loc)1857 << "split-stack prologue adjustment overflows";1858 return false;1859 }1860 1861 int32_t adjustedStackFrameSize =1862 stackFrameSize - ctx.arg.splitStackAdjustSize;1863 1864 loImm = adjustedStackFrameSize & 0xFFFF;1865 hiImm = (adjustedStackFrameSize + 0x8000) >> 16;1866 if (hiImm) {1867 write32(ctx, loc + 4, 0x3d810000 | (uint16_t)hiImm);1868 // If the low immediate is zero the second instruction will be a nop.1869 secondInstr = loImm ? 0x398C0000 | (uint16_t)loImm : NOP;1870 write32(ctx, loc + 8, secondInstr);1871 } else {1872 // addi r12, r1, imm1873 write32(ctx, loc + 4, (0x39810000) | (uint16_t)loImm);1874 write32(ctx, loc + 8, NOP);1875 }1876 1877 return true;1878}1879 1880void elf::setPPC64TargetInfo(Ctx &ctx) { ctx.target.reset(new PPC64(ctx)); }1881