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1// REQUIRES: aarch642// RUN: llvm-mc -filetype=obj -triple=aarch64 %s -o %t.o3// RUN: ld.lld --image-base=0x10000000 %t.o -o %t4// RUN: llvm-objdump -d -z --no-show-raw-insn %t | FileCheck %s5 6// Check that the ARM 64-bit ABI rules for undefined weak symbols are applied.7// Branch instructions are resolved to the next instruction. Undefined8// Symbols in relative are resolved to the place so S - P + A = A.9// We place the image-base at 0x10000000 to test that a range extensions thunk10// is not generated.11 .weak target12 13.weak undefweak214.hidden undefweak215 16 .text17 .global _start18_start:19// R_AARCH64_JUMP2620 b target21// R_AARCH64_CALL2622 bl target23// R_AARCH64_CONDBR1924 b.eq target25// R_AARCH64_TSTBR1426 cbz x1, target27// R_AARCH64_ADR_PREL_LO2128 adr x0, target29// R_AARCH64_ADR_PREL_PG_HI2130 adrp x0, target31// R_AARCH64_LD_PREL_LO1932 ldr x8, target33// R_AARCH64_PREL3234 .word target - .35// R_AARCH64_PREL6436 .xword target - .37// R_AARCH64_PREL1638 .hword target - .39// R_AARCH64_PLT3240 .word target@PLT - .41 42bl_undefweak2:43 bl undefweak244 45// CHECK: Disassembly of section .text:46// CHECK-EMPTY:47// CHECK-NEXT: 0000000010010120 <_start>:48// CHECK-NEXT: 10010120: b 0x1001012449// CHECK-NEXT: 10010124: bl 0x1001012850// CHECK-NEXT: 10010128: b.eq 0x1001012c51// CHECK-NEXT: 1001012c: cbz x1, 0x1001013052// CHECK-NEXT: 10010130: adr x0, 0x1001013053// CHECK-NEXT: 10010134: adrp x0, 0x1001000054// CHECK-NEXT: 10010138: ldr x8, 0x1001013855// CHECK: 1001013c: 00 00 00 00 .word 0x0000000056// CHECK-NEXT: 10010140: 00 00 00 00 .word 0x0000000057// CHECK-NEXT: 10010144: 00 00 00 00 .word 0x0000000058// CHECK-NEXT: 10010148: 00 00 00 00 .word 0x0000000059// CHECK-NEXT: 1001014c: 00 00 .short 0x000060// CHECK-LABEL: <bl_undefweak2>:61// CHECK-NEXT: bl {{.*}} <bl_undefweak2+0x4>62