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1# REQUIRES: loongarch2 3# RUN: llvm-mc --filetype=obj --triple=loongarch32 -mattr=+relax --defsym ELF32=1 %s -o %t.32.o4# RUN: llvm-mc --filetype=obj --triple=loongarch64 -mattr=+relax %s -o %t.64.o5 6# RUN: ld.lld %t.32.o -o %t.327# RUN: llvm-objdump -d --no-show-raw-insn %t.32 | FileCheck --check-prefixes=RELAX32 %s8 9# RUN: ld.lld %t.64.o -o %t.6410# RUN: llvm-objdump -d --no-show-raw-insn %t.64 | FileCheck --check-prefixes=RELAX64 %s11 12# RELAX32-LABEL: <_start>:13## .LANCHOR0@tprel = 814# RELAX32-NEXT: addi.w $a0, $tp, 8 15# RELAX32-NEXT: ld.w $a1, $a0, 016# RELAX32-NEXT: ld.w $a2, $tp, 817## .a@tprel - 4 = 0x7fc18# RELAX32-NEXT: addi.w $a1, $zero, 119# RELAX32-NEXT: addi.w $a1, $a1, 220# RELAX32-NEXT: st.w $a1, $tp, 204421## .a@tprel = 0x80022# RELAX32-NEXT: lu12i.w $a0, 123# RELAX32-NEXT: add.w $a0, $a0, $tp24# RELAX32-NEXT: addi.w $a0, $a0, -204825 26# RELAX64-LABEL: <_start>:27## .LANCHOR0@tprel = 828# RELAX64-NEXT: addi.d $a0, $tp, 8 29# RELAX64-NEXT: ld.d $a1, $a0, 030# RELAX64-NEXT: ld.d $a2, $tp, 831## .a@tprel - 4 = 0x7fc32# RELAX64-NEXT: addi.d $a1, $zero, 133# RELAX64-NEXT: addi.d $a1, $a1, 234# RELAX64-NEXT: st.d $a1, $tp, 204435## .a@tprel = 0x80036# RELAX64-NEXT: lu12i.w $a0, 137# RELAX64-NEXT: add.d $a0, $a0, $tp38# RELAX64-NEXT: addi.d $a0, $a0, -204839 40.macro add dst, src1, src2, src341.ifdef ELF3242 add.w \dst, \src1, \src2, \src343.else44 add.d \dst, \src1, \src2, \src345.endif46.endm47.macro inst op dst, src1, src248.ifdef ELF3249 .ifc \op, addi50 addi.w \dst, \src1, \src251 .else; .ifc \op, ld52 ld.w \dst, \src1, \src253 .else; .ifc \op, st54 st.w \dst, \src1, \src255 .else; .ifc \op, ldptr56 ldptr.w \dst, \src1, \src257 .else58 .error "Unknown op in ELF32 mode"59 .endif; .endif; .endif; .endif60.else61 .ifc \op, addi62 addi.d \dst, \src1, \src263 .else; .ifc \op, ld64 ld.d \dst, \src1, \src265 .else; .ifc \op, st66 st.d \dst, \src1, \src267 .else; .ifc \op, ldptr68 ldptr.d \dst, \src1, \src269 .else70 .error "Unknown op in ELF64 mode"71 .endif; .endif; .endif; .endif72.endif73.endm74 75.macro addi dst, src1, src276 inst addi \dst, \src1, \src277.endm78.macro ld dst, src1, src279 inst ld \dst, \src1, \src280.endm81.macro st dst, src1, src282 inst st \dst, \src1, \src283.endm84.macro ldptr dst, src1, src285 inst ldptr \dst, \src1, \src286.endm87 88_start:89 ## Test instructions not in pairs.90 lu12i.w $a0, %le_hi20_r(.LANCHOR0)91 add $a0, $a0, $tp, %le_add_r(.LANCHOR0)92 addi $a0, $a0, %le_lo12_r(.LANCHOR0)93 ld $a1, $a0, 094 ld $a2, $a0, %le_lo12_r(.LANCHOR0)95 96 ## hi20(a-4) = hi20(0x7fc) = 0. relaxable97 ## Test non-adjacent instructions.98 lu12i.w $a0, %le_hi20_r(a-4)99 addi $a1, $zero, 0x1100 add $a0, $a0, $tp, %le_add_r(a-4)101 addi $a1, $a1, 0x2102 st $a1, $a0, %le_lo12_r(a-4)103 104 ## hi20(a) = hi20(0x800) = 1. not relaxable105 lu12i.w $a0, %le_hi20_r(a)106 add $a0, $a0, $tp, %le_add_r(a)107 addi $a0, $a0, %le_lo12_r(a)108 109.section .tbss,"awT",@nobits110.space 8111.LANCHOR0:112.space 0x800-8113.globl a114a:115.zero 4116