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1//===-- NativeRegisterContextLinux_arm64.h ---------------------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#if defined(__arm64__) || defined(__aarch64__)10 11#ifndef lldb_NativeRegisterContextLinux_arm64_h12#define lldb_NativeRegisterContextLinux_arm64_h13 14#include "Plugins/Process/Linux/NativeRegisterContextLinux.h"15#include "Plugins/Process/Utility/LinuxPTraceDefines_arm64sve.h"16#include "Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.h"17#include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h"18 19#include <asm/ptrace.h>20 21namespace lldb_private {22namespace process_linux {23 24class NativeProcessLinux;25 26class NativeRegisterContextLinux_arm6427 : public NativeRegisterContextLinux,28 public NativeRegisterContextDBReg_arm64 {29public:30 NativeRegisterContextLinux_arm64(31 const ArchSpec &target_arch, NativeThreadProtocol &native_thread,32 std::unique_ptr<RegisterInfoPOSIX_arm64> register_info_up);33 34 uint32_t GetRegisterSetCount() const override;35 36 uint32_t GetUserRegisterCount() const override;37 38 const RegisterSet *GetRegisterSet(uint32_t set_index) const override;39 40 Status ReadRegister(const RegisterInfo *reg_info,41 RegisterValue ®_value) override;42 43 Status WriteRegister(const RegisterInfo *reg_info,44 const RegisterValue ®_value) override;45 46 Status ReadAllRegisterValues(lldb::WritableDataBufferSP &data_sp) override;47 48 Status WriteAllRegisterValues(const lldb::DataBufferSP &data_sp) override;49 50 void InvalidateAllRegisters() override;51 52 std::vector<uint32_t>53 GetExpeditedRegisters(ExpeditedRegs expType) const override;54 55 bool RegisterOffsetIsDynamic() const override { return true; }56 57 llvm::Expected<MemoryTaggingDetails>58 GetMemoryTaggingDetails(int32_t type) override;59 60protected:61 Status ReadGPR() override;62 63 Status WriteGPR() override;64 65 Status ReadFPR() override;66 67 Status WriteFPR() override;68 69 void *GetGPRBuffer() override { return &m_gpr_arm64; }70 71 // GetGPRBufferSize returns sizeof arm64 GPR ptrace buffer, it is different72 // from GetGPRSize which returns sizeof RegisterInfoPOSIX_arm64::GPR.73 size_t GetGPRBufferSize() { return sizeof(m_gpr_arm64); }74 75 void *GetFPRBuffer() override { return &m_fpr; }76 77 size_t GetFPRSize() override { return sizeof(m_fpr); }78 79 lldb::addr_t FixWatchpointHitAddress(lldb::addr_t hit_addr) override;80 81private:82 bool m_gpr_is_valid;83 bool m_fpu_is_valid;84 bool m_sve_buffer_is_valid;85 bool m_mte_ctrl_is_valid;86 bool m_zt_buffer_is_valid;87 bool m_fpmr_is_valid;88 89 bool m_sve_header_is_valid;90 bool m_za_buffer_is_valid;91 bool m_za_header_is_valid;92 bool m_pac_mask_is_valid;93 bool m_tls_is_valid;94 size_t m_tls_size;95 bool m_gcs_is_valid;96 97 struct user_pt_regs m_gpr_arm64; // 64-bit general purpose registers.98 99 RegisterInfoPOSIX_arm64::FPU100 m_fpr; // floating-point registers including extended register sets.101 102 SVEState m_sve_state = SVEState::Unknown;103 struct sve::user_sve_header m_sve_header;104 std::vector<uint8_t> m_sve_ptrace_payload;105 106 sve::user_za_header m_za_header;107 std::vector<uint8_t> m_za_ptrace_payload;108 109 bool m_refresh_hwdebug_info;110 111 struct user_pac_mask {112 uint64_t data_mask;113 uint64_t insn_mask;114 };115 116 struct user_pac_mask m_pac_mask;117 118 uint64_t m_mte_ctrl_reg;119 120 struct sme_pseudo_regs {121 uint64_t ctrl_reg;122 uint64_t svg_reg;123 };124 125 struct sme_pseudo_regs m_sme_pseudo_regs;126 127 struct tls_regs {128 uint64_t tpidr_reg;129 // Only valid when SME is present.130 uint64_t tpidr2_reg;131 };132 133 struct tls_regs m_tls_regs;134 135 // SME2's ZT is a 512 bit register.136 std::array<uint8_t, 64> m_zt_reg;137 138 uint64_t m_fpmr_reg;139 140 struct gcs_regs {141 uint64_t features_enabled;142 uint64_t features_locked;143 uint64_t gcspr_e0;144 } m_gcs_regs;145 146 bool IsGPR(unsigned reg) const;147 148 bool IsFPR(unsigned reg) const;149 150 Status ReadAllSVE();151 152 Status WriteAllSVE();153 154 Status ReadSVEHeader();155 156 Status WriteSVEHeader();157 158 Status ReadPAuthMask();159 160 Status ReadMTEControl();161 162 Status WriteMTEControl();163 164 Status ReadTLS();165 166 Status WriteTLS();167 168 Status ReadSMESVG();169 170 Status ReadZAHeader();171 172 Status ReadZA();173 174 Status WriteZA();175 176 Status ReadGCS();177 178 Status WriteGCS();179 180 // No WriteZAHeader because writing only the header will disable ZA.181 // Instead use WriteZA and ensure you have the correct ZA buffer size set182 // beforehand if you wish to disable it.183 184 Status ReadZT();185 186 Status WriteZT();187 188 // SVCR is a pseudo register and we do not allow writes to it.189 Status ReadSMEControl();190 191 Status ReadFPMR();192 193 Status WriteFPMR();194 195 bool IsSVE(unsigned reg) const;196 bool IsSME(unsigned reg) const;197 bool IsPAuth(unsigned reg) const;198 bool IsMTE(unsigned reg) const;199 bool IsTLS(unsigned reg) const;200 bool IsFPMR(unsigned reg) const;201 bool IsGCS(unsigned reg) const;202 203 uint64_t GetSVERegVG() { return m_sve_header.vl / 8; }204 205 void SetSVERegVG(uint64_t vg) { m_sve_header.vl = vg * 8; }206 207 void *GetSVEHeader() { return &m_sve_header; }208 209 void *GetZAHeader() { return &m_za_header; }210 211 size_t GetZAHeaderSize() { return sizeof(m_za_header); }212 213 void *GetPACMask() { return &m_pac_mask; }214 215 void *GetMTEControl() { return &m_mte_ctrl_reg; }216 217 void *GetTLSBuffer() { return &m_tls_regs; }218 219 void *GetSMEPseudoBuffer() { return &m_sme_pseudo_regs; }220 221 void *GetZTBuffer() { return m_zt_reg.data(); }222 223 void *GetSVEBuffer() { return m_sve_ptrace_payload.data(); }224 225 void *GetFPMRBuffer() { return &m_fpmr_reg; }226 227 void *GetGCSBuffer() { return &m_gcs_regs; }228 229 size_t GetSVEHeaderSize() { return sizeof(m_sve_header); }230 231 size_t GetPACMaskSize() { return sizeof(m_pac_mask); }232 233 size_t GetSVEBufferSize() { return m_sve_ptrace_payload.size(); }234 235 unsigned GetSVERegSet();236 237 void *GetZABuffer() { return m_za_ptrace_payload.data(); };238 239 size_t GetZABufferSize() { return m_za_ptrace_payload.size(); }240 241 size_t GetMTEControlSize() { return sizeof(m_mte_ctrl_reg); }242 243 size_t GetTLSBufferSize() { return m_tls_size; }244 245 size_t GetSMEPseudoBufferSize() { return sizeof(m_sme_pseudo_regs); }246 247 size_t GetZTBufferSize() { return m_zt_reg.size(); }248 249 size_t GetFPMRBufferSize() { return sizeof(m_fpmr_reg); }250 251 size_t GetGCSBufferSize() { return sizeof(m_gcs_regs); }252 253 llvm::Error ReadHardwareDebugInfo() override;254 255 llvm::Error WriteHardwareDebugRegs(DREGType hwbType) override;256 257 uint32_t CalculateFprOffset(const RegisterInfo *reg_info) const;258 259 RegisterInfoPOSIX_arm64 &GetRegisterInfo() const;260 261 void ConfigureRegisterContext();262 263 uint32_t CalculateSVEOffset(const RegisterInfo *reg_info) const;264 265 Status CacheAllRegisters(uint32_t &cached_size);266};267 268} // namespace process_linux269} // namespace lldb_private270 271#endif // #ifndef lldb_NativeRegisterContextLinux_arm64_h272 273#endif // defined (__arm64__) || defined (__aarch64__)274