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1//===-- RegisterInfoPOSIX_arm64.h -------------------------------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_ARM64_H10#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_ARM64_H11 12#include "RegisterInfoAndSetInterface.h"13#include "lldb/Target/RegisterContext.h"14#include "lldb/Utility/Flags.h"15#include "lldb/lldb-private.h"16#include <map>17 18enum class SVEState : uint8_t { Unknown, Disabled, FPSIMD, Full, Streaming };19 20class RegisterInfoPOSIX_arm6421 : public lldb_private::RegisterInfoAndSetInterface {22public:23 enum { GPRegSet = 0, FPRegSet };24 25 // AArch64 register set mask value26 enum {27 eRegsetMaskDefault = 0,28 eRegsetMaskSVE = 1,29 eRegsetMaskSSVE = 2,30 eRegsetMaskPAuth = 4,31 eRegsetMaskMTE = 8,32 eRegsetMaskTLS = 16,33 eRegsetMaskZA = 32,34 eRegsetMaskZT = 64,35 eRegsetMaskFPMR = 128,36 eRegsetMaskGCS = 256,37 eRegsetMaskDynamic = ~1,38 };39 40 // AArch64 Register set FP/SIMD feature configuration41 enum {42 eVectorQuadwordAArch64,43 eVectorQuadwordAArch64SVE,44 eVectorQuadwordAArch64SVEMax = 25645 };46 47 // based on RegisterContextDarwin_arm64.h48 // Pack this so there are no extra bytes, but align its start address to at49 // least 8 bytes to prevent alignment errors.50 LLVM_PACKED_START51 struct alignas(8) GPR {52 uint64_t x[29]; // x0-x2853 uint64_t fp; // x2954 uint64_t lr; // x3055 uint64_t sp; // x3156 uint64_t pc; // pc57 uint32_t cpsr; // cpsr58 uint32_t pad;59 };60 LLVM_PACKED_END61 62 // based on RegisterContextDarwin_arm64.h63 struct VReg {64 uint8_t bytes[16];65 };66 67 // based on RegisterContextDarwin_arm64.h68 struct FPU {69 VReg v[32];70 uint32_t fpsr;71 uint32_t fpcr;72 };73 74 // based on RegisterContextDarwin_arm64.h75 struct EXC {76 uint64_t far; // Virtual Fault Address77 uint32_t esr; // Exception syndrome78 uint32_t exception; // number of arm exception token79 };80 81 // based on RegisterContextDarwin_arm64.h82 struct DBG {83 uint64_t bvr[16];84 uint64_t bcr[16];85 uint64_t wvr[16];86 uint64_t wcr[16];87 uint64_t mdscr_el1;88 };89 90 RegisterInfoPOSIX_arm64(const lldb_private::ArchSpec &target_arch,91 lldb_private::Flags opt_regsets);92 93 static size_t GetGPRSizeStatic();94 size_t GetGPRSize() const override { return GetGPRSizeStatic(); }95 96 size_t GetFPRSize() const override;97 98 const lldb_private::RegisterInfo *GetRegisterInfo() const override;99 100 uint32_t GetRegisterCount() const override;101 102 const lldb_private::RegisterSet *103 GetRegisterSet(size_t reg_set) const override;104 105 size_t GetRegisterSetCount() const override;106 107 size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override;108 109 void AddRegSetPAuth();110 111 void AddRegSetMTE();112 113 void AddRegSetTLS(bool has_tpidr2);114 115 void AddRegSetSME(bool has_zt);116 117 void AddRegSetFPMR();118 119 void AddRegSetGCS();120 121 uint32_t ConfigureVectorLengthSVE(uint32_t sve_vq);122 123 void ConfigureVectorLengthZA(uint32_t za_vq);124 125 bool VectorSizeIsValid(uint32_t vq) {126 // coverity[unsigned_compare]127 if (vq >= eVectorQuadwordAArch64 && vq <= eVectorQuadwordAArch64SVEMax)128 return true;129 return false;130 }131 132 bool IsSVEPresent() const { return m_opt_regsets.AnySet(eRegsetMaskSVE); }133 bool IsSSVEPresent() const { return m_opt_regsets.AnySet(eRegsetMaskSSVE); }134 bool IsZAPresent() const { return m_opt_regsets.AnySet(eRegsetMaskZA); }135 bool IsZTPresent() const { return m_opt_regsets.AnySet(eRegsetMaskZT); }136 bool IsPAuthPresent() const { return m_opt_regsets.AnySet(eRegsetMaskPAuth); }137 bool IsMTEPresent() const { return m_opt_regsets.AnySet(eRegsetMaskMTE); }138 bool IsTLSPresent() const { return m_opt_regsets.AnySet(eRegsetMaskTLS); }139 bool IsFPMRPresent() const { return m_opt_regsets.AnySet(eRegsetMaskFPMR); }140 bool IsGCSPresent() const { return m_opt_regsets.AnySet(eRegsetMaskGCS); }141 142 bool IsSVEReg(unsigned reg) const;143 bool IsSVEZReg(unsigned reg) const;144 bool IsSVEPReg(unsigned reg) const;145 bool IsSVERegVG(unsigned reg) const;146 bool IsPAuthReg(unsigned reg) const;147 bool IsMTEReg(unsigned reg) const;148 bool IsTLSReg(unsigned reg) const;149 bool IsSMEReg(unsigned reg) const;150 bool IsSMERegZA(unsigned reg) const;151 bool IsSMERegZT(unsigned reg) const;152 bool IsFPMRReg(unsigned reg) const;153 bool IsGCSReg(unsigned reg) const;154 155 uint32_t GetRegNumSVEZ0() const;156 uint32_t GetRegNumSVEFFR() const;157 uint32_t GetRegNumFPCR() const;158 uint32_t GetRegNumFPSR() const;159 uint32_t GetRegNumSVEVG() const;160 uint32_t GetRegNumSMESVG() const;161 uint32_t GetPAuthOffset() const;162 uint32_t GetMTEOffset() const;163 uint32_t GetTLSOffset() const;164 uint32_t GetSMEOffset() const;165 uint32_t GetFPMROffset() const;166 uint32_t GetGCSOffset() const;167 168private:169 typedef std::map<uint32_t, std::vector<lldb_private::RegisterInfo>>170 per_vq_register_infos;171 172 per_vq_register_infos m_per_vq_reg_infos;173 174 uint32_t m_vector_reg_vq = eVectorQuadwordAArch64;175 uint32_t m_za_reg_vq = eVectorQuadwordAArch64;176 177 // In normal operation this is const. Only when SVE or SME registers change178 // size is it either replaced or the content modified.179 const lldb_private::RegisterInfo *m_register_info_p;180 uint32_t m_register_info_count;181 182 const lldb_private::RegisterSet *m_register_set_p;183 uint32_t m_register_set_count;184 185 // Contains pair of [start, end] register numbers of a register set with start186 // and end included.187 std::map<uint32_t, std::pair<uint32_t, uint32_t>> m_per_regset_regnum_range;188 189 lldb_private::Flags m_opt_regsets;190 191 std::vector<lldb_private::RegisterInfo> m_dynamic_reg_infos;192 std::vector<lldb_private::RegisterSet> m_dynamic_reg_sets;193 194 std::vector<uint32_t> pauth_regnum_collection;195 std::vector<uint32_t> m_mte_regnum_collection;196 std::vector<uint32_t> m_tls_regnum_collection;197 std::vector<uint32_t> m_sme_regnum_collection;198 std::vector<uint32_t> m_fpmr_regnum_collection;199 std::vector<uint32_t> m_gcs_regnum_collection;200};201 202#endif203