143 lines · cpp
1//===-- RegisterInfoPOSIX_riscv32.cpp -------------------------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===---------------------------------------------------------------------===//8 9#include "RegisterInfoPOSIX_riscv32.h"10#include "lldb/Utility/Flags.h"11#include "lldb/lldb-defines.h"12#include "llvm/Support/Compiler.h"13 14#include <cassert>15#include <stddef.h>16 17#define GPR_OFFSET(idx) ((idx) * 4 + 0)18#define FPR_OFFSET(idx) ((idx) * 4 + sizeof(RegisterInfoPOSIX_riscv32::GPR))19 20#define REG_CONTEXT_SIZE \21 (sizeof(RegisterInfoPOSIX_riscv32::GPR) + \22 sizeof(RegisterInfoPOSIX_riscv32::FPR))23 24#define DECLARE_REGISTER_INFOS_RISCV32_STRUCT25#include "RegisterInfos_riscv32.h"26#undef DECLARE_REGISTER_INFOS_RISCV32_STRUCT27 28const lldb_private::RegisterInfo *RegisterInfoPOSIX_riscv32::GetRegisterInfoPtr(29 const lldb_private::ArchSpec &target_arch) {30 switch (target_arch.GetMachine()) {31 case llvm::Triple::riscv32:32 return g_register_infos_riscv32_le;33 default:34 assert(false && "Unhandled target architecture.");35 return nullptr;36 }37}38 39uint32_t RegisterInfoPOSIX_riscv32::GetRegisterInfoCount(40 const lldb_private::ArchSpec &target_arch) {41 switch (target_arch.GetMachine()) {42 case llvm::Triple::riscv32:43 return static_cast<uint32_t>(sizeof(g_register_infos_riscv32_le) /44 sizeof(g_register_infos_riscv32_le[0]));45 default:46 assert(false && "Unhandled target architecture.");47 return 0;48 }49}50 51// Number of register sets provided by this context.52enum {53 k_num_gpr_registers = gpr_last_riscv - gpr_first_riscv + 1,54 k_num_fpr_registers = fpr_last_riscv - fpr_first_riscv + 1,55 k_num_register_sets = 256};57 58// RISC-V32 general purpose registers.59static const uint32_t g_gpr_regnums_riscv32[] = {60 gpr_pc_riscv, gpr_ra_riscv, gpr_sp_riscv, gpr_x3_riscv,61 gpr_x4_riscv, gpr_x5_riscv, gpr_x6_riscv, gpr_x7_riscv,62 gpr_fp_riscv, gpr_x9_riscv, gpr_x10_riscv, gpr_x11_riscv,63 gpr_x12_riscv, gpr_x13_riscv, gpr_x14_riscv, gpr_x15_riscv,64 gpr_x16_riscv, gpr_x17_riscv, gpr_x18_riscv, gpr_x19_riscv,65 gpr_x20_riscv, gpr_x21_riscv, gpr_x22_riscv, gpr_x23_riscv,66 gpr_x24_riscv, gpr_x25_riscv, gpr_x26_riscv, gpr_x27_riscv,67 gpr_x28_riscv, gpr_x29_riscv, gpr_x30_riscv, gpr_x31_riscv,68 gpr_x0_riscv, LLDB_INVALID_REGNUM};69 70static_assert(((sizeof g_gpr_regnums_riscv32 /71 sizeof g_gpr_regnums_riscv32[0]) -72 1) == k_num_gpr_registers,73 "g_gpr_regnums_riscv32 has wrong number of register infos");74 75// RISC-V32 floating point registers.76static const uint32_t g_fpr_regnums_riscv32[] = {77 fpr_f0_riscv, fpr_f1_riscv, fpr_f2_riscv, fpr_f3_riscv,78 fpr_f4_riscv, fpr_f5_riscv, fpr_f6_riscv, fpr_f7_riscv,79 fpr_f8_riscv, fpr_f9_riscv, fpr_f10_riscv, fpr_f11_riscv,80 fpr_f12_riscv, fpr_f13_riscv, fpr_f14_riscv, fpr_f15_riscv,81 fpr_f16_riscv, fpr_f17_riscv, fpr_f18_riscv, fpr_f19_riscv,82 fpr_f20_riscv, fpr_f21_riscv, fpr_f22_riscv, fpr_f23_riscv,83 fpr_f24_riscv, fpr_f25_riscv, fpr_f26_riscv, fpr_f27_riscv,84 fpr_f28_riscv, fpr_f29_riscv, fpr_f30_riscv, fpr_f31_riscv,85 fpr_fcsr_riscv, LLDB_INVALID_REGNUM};86 87static_assert(((sizeof g_fpr_regnums_riscv32 /88 sizeof g_fpr_regnums_riscv32[0]) -89 1) == k_num_fpr_registers,90 "g_fpr_regnums_riscv32 has wrong number of register infos");91 92// Register sets for RISC-V32.93static const lldb_private::RegisterSet g_reg_sets_riscv32[k_num_register_sets] =94 {{"General Purpose Registers", "gpr", k_num_gpr_registers,95 g_gpr_regnums_riscv32},96 {"Floating Point Registers", "fpr", k_num_fpr_registers,97 g_fpr_regnums_riscv32}};98 99RegisterInfoPOSIX_riscv32::RegisterInfoPOSIX_riscv32(100 const lldb_private::ArchSpec &target_arch, lldb_private::Flags opt_regsets)101 : lldb_private::RegisterInfoAndSetInterface(target_arch),102 m_register_info_p(GetRegisterInfoPtr(target_arch)),103 m_register_info_count(GetRegisterInfoCount(target_arch)),104 m_opt_regsets(opt_regsets) {}105 106uint32_t RegisterInfoPOSIX_riscv32::GetRegisterCount() const {107 return m_register_info_count;108}109 110size_t RegisterInfoPOSIX_riscv32::GetGPRSize() const {111 return sizeof(struct RegisterInfoPOSIX_riscv32::GPR);112}113 114size_t RegisterInfoPOSIX_riscv32::GetFPRSize() const {115 return sizeof(struct RegisterInfoPOSIX_riscv32::FPR);116}117 118const lldb_private::RegisterInfo *119RegisterInfoPOSIX_riscv32::GetRegisterInfo() const {120 return m_register_info_p;121}122 123size_t RegisterInfoPOSIX_riscv32::GetRegisterSetCount() const {124 return k_num_register_sets;125}126 127size_t RegisterInfoPOSIX_riscv32::GetRegisterSetFromRegisterIndex(128 uint32_t reg_index) const {129 // coverity[unsigned_compare]130 if (reg_index >= gpr_first_riscv && reg_index <= gpr_last_riscv)131 return eRegsetMaskDefault;132 if (reg_index >= fpr_first_riscv && reg_index <= fpr_last_riscv)133 return eRegsetMaskFP;134 return LLDB_INVALID_REGNUM;135}136 137const lldb_private::RegisterSet *138RegisterInfoPOSIX_riscv32::GetRegisterSet(size_t set_index) const {139 if (set_index < GetRegisterSetCount())140 return &g_reg_sets_riscv32[set_index];141 return nullptr;142}143