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1//===-- lldb-arm-register-enums.h -----------------------------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_ARM_REGISTER_ENUMS_H10#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_ARM_REGISTER_ENUMS_H11 12namespace lldb_private {13// LLDB register codes (e.g. RegisterKind == eRegisterKindLLDB)14 15// Internal codes for all ARM registers.16enum {17 k_first_gpr_arm = 0,18 gpr_r0_arm = k_first_gpr_arm,19 gpr_r1_arm,20 gpr_r2_arm,21 gpr_r3_arm,22 gpr_r4_arm,23 gpr_r5_arm,24 gpr_r6_arm,25 gpr_r7_arm,26 gpr_r8_arm,27 gpr_r9_arm,28 gpr_r10_arm,29 gpr_r11_arm,30 gpr_r12_arm,31 gpr_r13_arm,32 gpr_sp_arm = gpr_r13_arm,33 gpr_r14_arm,34 gpr_lr_arm = gpr_r14_arm,35 gpr_r15_arm,36 gpr_pc_arm = gpr_r15_arm,37 gpr_cpsr_arm,38 39 k_last_gpr_arm = gpr_cpsr_arm,40 41 k_first_fpr_arm,42 fpu_s0_arm = k_first_fpr_arm,43 fpu_s1_arm,44 fpu_s2_arm,45 fpu_s3_arm,46 fpu_s4_arm,47 fpu_s5_arm,48 fpu_s6_arm,49 fpu_s7_arm,50 fpu_s8_arm,51 fpu_s9_arm,52 fpu_s10_arm,53 fpu_s11_arm,54 fpu_s12_arm,55 fpu_s13_arm,56 fpu_s14_arm,57 fpu_s15_arm,58 fpu_s16_arm,59 fpu_s17_arm,60 fpu_s18_arm,61 fpu_s19_arm,62 fpu_s20_arm,63 fpu_s21_arm,64 fpu_s22_arm,65 fpu_s23_arm,66 fpu_s24_arm,67 fpu_s25_arm,68 fpu_s26_arm,69 fpu_s27_arm,70 fpu_s28_arm,71 fpu_s29_arm,72 fpu_s30_arm,73 fpu_s31_arm,74 fpu_fpscr_arm,75 fpu_d0_arm,76 fpu_d1_arm,77 fpu_d2_arm,78 fpu_d3_arm,79 fpu_d4_arm,80 fpu_d5_arm,81 fpu_d6_arm,82 fpu_d7_arm,83 fpu_d8_arm,84 fpu_d9_arm,85 fpu_d10_arm,86 fpu_d11_arm,87 fpu_d12_arm,88 fpu_d13_arm,89 fpu_d14_arm,90 fpu_d15_arm,91 fpu_d16_arm,92 fpu_d17_arm,93 fpu_d18_arm,94 fpu_d19_arm,95 fpu_d20_arm,96 fpu_d21_arm,97 fpu_d22_arm,98 fpu_d23_arm,99 fpu_d24_arm,100 fpu_d25_arm,101 fpu_d26_arm,102 fpu_d27_arm,103 fpu_d28_arm,104 fpu_d29_arm,105 fpu_d30_arm,106 fpu_d31_arm,107 fpu_q0_arm,108 fpu_q1_arm,109 fpu_q2_arm,110 fpu_q3_arm,111 fpu_q4_arm,112 fpu_q5_arm,113 fpu_q6_arm,114 fpu_q7_arm,115 fpu_q8_arm,116 fpu_q9_arm,117 fpu_q10_arm,118 fpu_q11_arm,119 fpu_q12_arm,120 fpu_q13_arm,121 fpu_q14_arm,122 fpu_q15_arm,123 k_last_fpr_arm = fpu_q15_arm,124 exc_exception_arm,125 exc_fsr_arm,126 exc_far_arm,127 128 dbg_bvr0_arm,129 dbg_bvr1_arm,130 dbg_bvr2_arm,131 dbg_bvr3_arm,132 dbg_bvr4_arm,133 dbg_bvr5_arm,134 dbg_bvr6_arm,135 dbg_bvr7_arm,136 dbg_bvr8_arm,137 dbg_bvr9_arm,138 dbg_bvr10_arm,139 dbg_bvr11_arm,140 dbg_bvr12_arm,141 dbg_bvr13_arm,142 dbg_bvr14_arm,143 dbg_bvr15_arm,144 dbg_bcr0_arm,145 dbg_bcr1_arm,146 dbg_bcr2_arm,147 dbg_bcr3_arm,148 dbg_bcr4_arm,149 dbg_bcr5_arm,150 dbg_bcr6_arm,151 dbg_bcr7_arm,152 dbg_bcr8_arm,153 dbg_bcr9_arm,154 dbg_bcr10_arm,155 dbg_bcr11_arm,156 dbg_bcr12_arm,157 dbg_bcr13_arm,158 dbg_bcr14_arm,159 dbg_bcr15_arm,160 dbg_wvr0_arm,161 dbg_wvr1_arm,162 dbg_wvr2_arm,163 dbg_wvr3_arm,164 dbg_wvr4_arm,165 dbg_wvr5_arm,166 dbg_wvr6_arm,167 dbg_wvr7_arm,168 dbg_wvr8_arm,169 dbg_wvr9_arm,170 dbg_wvr10_arm,171 dbg_wvr11_arm,172 dbg_wvr12_arm,173 dbg_wvr13_arm,174 dbg_wvr14_arm,175 dbg_wvr15_arm,176 dbg_wcr0_arm,177 dbg_wcr1_arm,178 dbg_wcr2_arm,179 dbg_wcr3_arm,180 dbg_wcr4_arm,181 dbg_wcr5_arm,182 dbg_wcr6_arm,183 dbg_wcr7_arm,184 dbg_wcr8_arm,185 dbg_wcr9_arm,186 dbg_wcr10_arm,187 dbg_wcr11_arm,188 dbg_wcr12_arm,189 dbg_wcr13_arm,190 dbg_wcr14_arm,191 dbg_wcr15_arm,192 193 k_num_registers_arm,194 k_num_gpr_registers_arm = k_last_gpr_arm - k_first_gpr_arm + 1,195 k_num_fpr_registers_arm = k_last_fpr_arm - k_first_fpr_arm + 1196};197}198 199#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_ARM_REGISTER_ENUMS_H200