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1//===-- lldb-arm64-register-enums.h -----------------------------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_ARM64_REGISTER_ENUMS_H10#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_ARM64_REGISTER_ENUMS_H11 12namespace lldb_private {13// LLDB register codes (e.g. RegisterKind == eRegisterKindLLDB)14 15// Internal codes for all ARM64 registers.16enum {17 k_first_gpr_arm64,18 gpr_x0_arm64 = k_first_gpr_arm64,19 gpr_x1_arm64,20 gpr_x2_arm64,21 gpr_x3_arm64,22 gpr_x4_arm64,23 gpr_x5_arm64,24 gpr_x6_arm64,25 gpr_x7_arm64,26 gpr_x8_arm64,27 gpr_x9_arm64,28 gpr_x10_arm64,29 gpr_x11_arm64,30 gpr_x12_arm64,31 gpr_x13_arm64,32 gpr_x14_arm64,33 gpr_x15_arm64,34 gpr_x16_arm64,35 gpr_x17_arm64,36 gpr_x18_arm64,37 gpr_x19_arm64,38 gpr_x20_arm64,39 gpr_x21_arm64,40 gpr_x22_arm64,41 gpr_x23_arm64,42 gpr_x24_arm64,43 gpr_x25_arm64,44 gpr_x26_arm64,45 gpr_x27_arm64,46 gpr_x28_arm64,47 gpr_fp_arm64,48 gpr_lr_arm64,49 gpr_sp_arm64,50 gpr_pc_arm64,51 gpr_cpsr_arm64,52 53 gpr_w0_arm64,54 gpr_w1_arm64,55 gpr_w2_arm64,56 gpr_w3_arm64,57 gpr_w4_arm64,58 gpr_w5_arm64,59 gpr_w6_arm64,60 gpr_w7_arm64,61 gpr_w8_arm64,62 gpr_w9_arm64,63 gpr_w10_arm64,64 gpr_w11_arm64,65 gpr_w12_arm64,66 gpr_w13_arm64,67 gpr_w14_arm64,68 gpr_w15_arm64,69 gpr_w16_arm64,70 gpr_w17_arm64,71 gpr_w18_arm64,72 gpr_w19_arm64,73 gpr_w20_arm64,74 gpr_w21_arm64,75 gpr_w22_arm64,76 gpr_w23_arm64,77 gpr_w24_arm64,78 gpr_w25_arm64,79 gpr_w26_arm64,80 gpr_w27_arm64,81 gpr_w28_arm64,82 83 k_last_gpr_arm64 = gpr_w28_arm64,84 85 k_first_fpr_arm64,86 fpu_v0_arm64 = k_first_fpr_arm64,87 fpu_v1_arm64,88 fpu_v2_arm64,89 fpu_v3_arm64,90 fpu_v4_arm64,91 fpu_v5_arm64,92 fpu_v6_arm64,93 fpu_v7_arm64,94 fpu_v8_arm64,95 fpu_v9_arm64,96 fpu_v10_arm64,97 fpu_v11_arm64,98 fpu_v12_arm64,99 fpu_v13_arm64,100 fpu_v14_arm64,101 fpu_v15_arm64,102 fpu_v16_arm64,103 fpu_v17_arm64,104 fpu_v18_arm64,105 fpu_v19_arm64,106 fpu_v20_arm64,107 fpu_v21_arm64,108 fpu_v22_arm64,109 fpu_v23_arm64,110 fpu_v24_arm64,111 fpu_v25_arm64,112 fpu_v26_arm64,113 fpu_v27_arm64,114 fpu_v28_arm64,115 fpu_v29_arm64,116 fpu_v30_arm64,117 fpu_v31_arm64,118 119 fpu_s0_arm64,120 fpu_s1_arm64,121 fpu_s2_arm64,122 fpu_s3_arm64,123 fpu_s4_arm64,124 fpu_s5_arm64,125 fpu_s6_arm64,126 fpu_s7_arm64,127 fpu_s8_arm64,128 fpu_s9_arm64,129 fpu_s10_arm64,130 fpu_s11_arm64,131 fpu_s12_arm64,132 fpu_s13_arm64,133 fpu_s14_arm64,134 fpu_s15_arm64,135 fpu_s16_arm64,136 fpu_s17_arm64,137 fpu_s18_arm64,138 fpu_s19_arm64,139 fpu_s20_arm64,140 fpu_s21_arm64,141 fpu_s22_arm64,142 fpu_s23_arm64,143 fpu_s24_arm64,144 fpu_s25_arm64,145 fpu_s26_arm64,146 fpu_s27_arm64,147 fpu_s28_arm64,148 fpu_s29_arm64,149 fpu_s30_arm64,150 fpu_s31_arm64,151 152 fpu_d0_arm64,153 fpu_d1_arm64,154 fpu_d2_arm64,155 fpu_d3_arm64,156 fpu_d4_arm64,157 fpu_d5_arm64,158 fpu_d6_arm64,159 fpu_d7_arm64,160 fpu_d8_arm64,161 fpu_d9_arm64,162 fpu_d10_arm64,163 fpu_d11_arm64,164 fpu_d12_arm64,165 fpu_d13_arm64,166 fpu_d14_arm64,167 fpu_d15_arm64,168 fpu_d16_arm64,169 fpu_d17_arm64,170 fpu_d18_arm64,171 fpu_d19_arm64,172 fpu_d20_arm64,173 fpu_d21_arm64,174 fpu_d22_arm64,175 fpu_d23_arm64,176 fpu_d24_arm64,177 fpu_d25_arm64,178 fpu_d26_arm64,179 fpu_d27_arm64,180 fpu_d28_arm64,181 fpu_d29_arm64,182 fpu_d30_arm64,183 fpu_d31_arm64,184 185 fpu_fpsr_arm64,186 fpu_fpcr_arm64,187 k_last_fpr_arm64 = fpu_fpcr_arm64,188 189 exc_far_arm64,190 exc_esr_arm64,191 exc_exception_arm64,192 193 dbg_bvr0_arm64,194 dbg_bvr1_arm64,195 dbg_bvr2_arm64,196 dbg_bvr3_arm64,197 dbg_bvr4_arm64,198 dbg_bvr5_arm64,199 dbg_bvr6_arm64,200 dbg_bvr7_arm64,201 dbg_bvr8_arm64,202 dbg_bvr9_arm64,203 dbg_bvr10_arm64,204 dbg_bvr11_arm64,205 dbg_bvr12_arm64,206 dbg_bvr13_arm64,207 dbg_bvr14_arm64,208 dbg_bvr15_arm64,209 dbg_bcr0_arm64,210 dbg_bcr1_arm64,211 dbg_bcr2_arm64,212 dbg_bcr3_arm64,213 dbg_bcr4_arm64,214 dbg_bcr5_arm64,215 dbg_bcr6_arm64,216 dbg_bcr7_arm64,217 dbg_bcr8_arm64,218 dbg_bcr9_arm64,219 dbg_bcr10_arm64,220 dbg_bcr11_arm64,221 dbg_bcr12_arm64,222 dbg_bcr13_arm64,223 dbg_bcr14_arm64,224 dbg_bcr15_arm64,225 dbg_wvr0_arm64,226 dbg_wvr1_arm64,227 dbg_wvr2_arm64,228 dbg_wvr3_arm64,229 dbg_wvr4_arm64,230 dbg_wvr5_arm64,231 dbg_wvr6_arm64,232 dbg_wvr7_arm64,233 dbg_wvr8_arm64,234 dbg_wvr9_arm64,235 dbg_wvr10_arm64,236 dbg_wvr11_arm64,237 dbg_wvr12_arm64,238 dbg_wvr13_arm64,239 dbg_wvr14_arm64,240 dbg_wvr15_arm64,241 dbg_wcr0_arm64,242 dbg_wcr1_arm64,243 dbg_wcr2_arm64,244 dbg_wcr3_arm64,245 dbg_wcr4_arm64,246 dbg_wcr5_arm64,247 dbg_wcr6_arm64,248 dbg_wcr7_arm64,249 dbg_wcr8_arm64,250 dbg_wcr9_arm64,251 dbg_wcr10_arm64,252 dbg_wcr11_arm64,253 dbg_wcr12_arm64,254 dbg_wcr13_arm64,255 dbg_wcr14_arm64,256 dbg_wcr15_arm64,257 258 k_num_registers_arm64,259 k_num_gpr_registers_arm64 = k_last_gpr_arm64 - k_first_gpr_arm64 + 1,260 k_num_fpr_registers_arm64 = k_last_fpr_arm64 - k_first_fpr_arm64 + 1261};262}263 264#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_ARM64_REGISTER_ENUMS_H265