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1//===-- ARM_DWARF_Registers.h -----------------------------------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#ifndef LLDB_SOURCE_UTILITY_ARM_DWARF_REGISTERS_H10#define LLDB_SOURCE_UTILITY_ARM_DWARF_REGISTERS_H11 12#include "lldb/lldb-private.h"13 14enum {15 dwarf_r0 = 0,16 dwarf_r1,17 dwarf_r2,18 dwarf_r3,19 dwarf_r4,20 dwarf_r5,21 dwarf_r6,22 dwarf_r7,23 dwarf_r8,24 dwarf_r9,25 dwarf_r10,26 dwarf_r11,27 dwarf_r12,28 dwarf_sp,29 dwarf_lr,30 dwarf_pc,31 dwarf_cpsr,32 33 dwarf_s0 = 64,34 dwarf_s1,35 dwarf_s2,36 dwarf_s3,37 dwarf_s4,38 dwarf_s5,39 dwarf_s6,40 dwarf_s7,41 dwarf_s8,42 dwarf_s9,43 dwarf_s10,44 dwarf_s11,45 dwarf_s12,46 dwarf_s13,47 dwarf_s14,48 dwarf_s15,49 dwarf_s16,50 dwarf_s17,51 dwarf_s18,52 dwarf_s19,53 dwarf_s20,54 dwarf_s21,55 dwarf_s22,56 dwarf_s23,57 dwarf_s24,58 dwarf_s25,59 dwarf_s26,60 dwarf_s27,61 dwarf_s28,62 dwarf_s29,63 dwarf_s30,64 dwarf_s31,65 66 // FPA Registers 0-767 dwarf_f0 = 96,68 dwarf_f1,69 dwarf_f2,70 dwarf_f3,71 dwarf_f4,72 dwarf_f5,73 dwarf_f6,74 dwarf_f7,75 76 // Intel wireless MMX general purpose registers 0 - 777 dwarf_wCGR0 = 104,78 dwarf_wCGR1,79 dwarf_wCGR2,80 dwarf_wCGR3,81 dwarf_wCGR4,82 dwarf_wCGR5,83 dwarf_wCGR6,84 dwarf_wCGR7,85 86 // XScale accumulator register 0 - 7 (they do overlap with wCGR0 - wCGR7)87 dwarf_ACC0 = 104,88 dwarf_ACC1,89 dwarf_ACC2,90 dwarf_ACC3,91 dwarf_ACC4,92 dwarf_ACC5,93 dwarf_ACC6,94 dwarf_ACC7,95 96 // Intel wireless MMX data registers 0 - 1597 dwarf_wR0 = 112,98 dwarf_wR1,99 dwarf_wR2,100 dwarf_wR3,101 dwarf_wR4,102 dwarf_wR5,103 dwarf_wR6,104 dwarf_wR7,105 dwarf_wR8,106 dwarf_wR9,107 dwarf_wR10,108 dwarf_wR11,109 dwarf_wR12,110 dwarf_wR13,111 dwarf_wR14,112 dwarf_wR15,113 114 dwarf_spsr = 128,115 dwarf_spsr_fiq,116 dwarf_spsr_irq,117 dwarf_spsr_abt,118 dwarf_spsr_und,119 dwarf_spsr_svc,120 121 dwarf_r8_usr = 144,122 dwarf_r9_usr,123 dwarf_r10_usr,124 dwarf_r11_usr,125 dwarf_r12_usr,126 dwarf_r13_usr,127 dwarf_r14_usr,128 dwarf_r8_fiq,129 dwarf_r9_fiq,130 dwarf_r10_fiq,131 dwarf_r11_fiq,132 dwarf_r12_fiq,133 dwarf_r13_fiq,134 dwarf_r14_fiq,135 dwarf_r13_irq,136 dwarf_r14_irq,137 dwarf_r13_abt,138 dwarf_r14_abt,139 dwarf_r13_und,140 dwarf_r14_und,141 dwarf_r13_svc,142 dwarf_r14_svc,143 144 // Intel wireless MMX control register in co-processor 0 - 7145 dwarf_wC0 = 192,146 dwarf_wC1,147 dwarf_wC2,148 dwarf_wC3,149 dwarf_wC4,150 dwarf_wC5,151 dwarf_wC6,152 dwarf_wC7,153 154 // VFP-v3/Neon155 dwarf_d0 = 256,156 dwarf_d1,157 dwarf_d2,158 dwarf_d3,159 dwarf_d4,160 dwarf_d5,161 dwarf_d6,162 dwarf_d7,163 dwarf_d8,164 dwarf_d9,165 dwarf_d10,166 dwarf_d11,167 dwarf_d12,168 dwarf_d13,169 dwarf_d14,170 dwarf_d15,171 dwarf_d16,172 dwarf_d17,173 dwarf_d18,174 dwarf_d19,175 dwarf_d20,176 dwarf_d21,177 dwarf_d22,178 dwarf_d23,179 dwarf_d24,180 dwarf_d25,181 dwarf_d26,182 dwarf_d27,183 dwarf_d28,184 dwarf_d29,185 dwarf_d30,186 dwarf_d31,187 188 // Neon quadword registers189 dwarf_q0 = 288,190 dwarf_q1,191 dwarf_q2,192 dwarf_q3,193 dwarf_q4,194 dwarf_q5,195 dwarf_q6,196 dwarf_q7,197 dwarf_q8,198 dwarf_q9,199 dwarf_q10,200 dwarf_q11,201 dwarf_q12,202 dwarf_q13,203 dwarf_q14,204 dwarf_q15205};206 207#endif // LLDB_SOURCE_UTILITY_ARM_DWARF_REGISTERS_H208