1054 lines · python
1import lldb2from lldbsuite.test.lldbtest import *3from lldbsuite.test.decorators import *4from lldbsuite.test.gdbclientutils import *5from lldbsuite.test.lldbgdbclient import GDBRemoteTestBase6 7 8class TestGDBServerTargetXML(GDBRemoteTestBase):9 @skipIfXmlSupportMissing10 @skipIfRemote11 @skipIfLLVMTargetMissing("X86")12 def test_x86_64_regs(self):13 """Test grabbing various x86_64 registers from gdbserver."""14 15 class MyResponder(MockGDBServerResponder):16 reg_data = (17 (18 "0102030405060708" # rcx19 "1112131415161718" # rdx20 "2122232425262728" # rsi21 "3132333435363738" # rdi22 "4142434445464748" # rbp23 "5152535455565758" # rsp24 "6162636465666768" # r825 "7172737475767778" # r926 "8182838485868788" # rip27 "91929394" # eflags28 "0102030405060708090a" # st029 "1112131415161718191a" # st130 )31 + 6 * ("2122232425262728292a") # st2..st732 + (33 "8182838485868788898a8b8c8d8e8f90" # xmm034 "9192939495969798999a9b9c9d9e9fa0" # xmm135 )36 + 14 * ("a1a2a3a4a5a6a7a8a9aaabacadaeafb0") # xmm2..xmm1537 + ("00000000") # mxcsr38 + (39 "b1b2b3b4b5b6b7b8b9babbbcbdbebfc0" # ymm0h40 "c1c2c3c4c5c6c7c8c9cacbcccdcecfd0" # ymm1h41 )42 + 14 * ("d1d2d3d4d5d6d7d8d9dadbdcdddedfe0") # ymm2h..ymm15h43 )44 45 def qXferRead(self, obj, annex, offset, length):46 if annex == "target.xml":47 return (48 """<?xml version="1.0"?>49 <!DOCTYPE feature SYSTEM "gdb-target.dtd">50 <target>51 <architecture>i386:x86-64</architecture>52 <osabi>GNU/Linux</osabi>53 <feature name="org.gnu.gdb.i386.core">54 <reg name="rcx" bitsize="64" type="int64" regnum="2"/>55 <reg name="rdx" bitsize="64" type="int64" regnum="3"/>56 <reg name="rsi" bitsize="64" type="int64" regnum="4"/>57 <reg name="rdi" bitsize="64" type="int64" regnum="5"/>58 <reg name="rbp" bitsize="64" type="data_ptr" regnum="6"/>59 <reg name="rsp" bitsize="64" type="data_ptr" regnum="7"/>60 <reg name="r8" bitsize="64" type="int64" regnum="8"/>61 <reg name="r9" bitsize="64" type="int64" regnum="9"/>62 <reg name="rip" bitsize="64" type="code_ptr" regnum="16"/>63 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="17"/>64 <reg name="st0" bitsize="80" type="i387_ext" regnum="24"/>65 <reg name="st1" bitsize="80" type="i387_ext" regnum="25"/>66 <reg name="st2" bitsize="80" type="i387_ext" regnum="26"/>67 <reg name="st3" bitsize="80" type="i387_ext" regnum="27"/>68 <reg name="st4" bitsize="80" type="i387_ext" regnum="28"/>69 <reg name="st5" bitsize="80" type="i387_ext" regnum="29"/>70 <reg name="st6" bitsize="80" type="i387_ext" regnum="30"/>71 <reg name="st7" bitsize="80" type="i387_ext" regnum="31"/>72 </feature>73 <feature name="org.gnu.gdb.i386.sse">74 <reg name="xmm0" bitsize="128" type="vec128" regnum="40"/>75 <reg name="xmm1" bitsize="128" type="vec128" regnum="41"/>76 <reg name="xmm2" bitsize="128" type="vec128" regnum="42"/>77 <reg name="xmm3" bitsize="128" type="vec128" regnum="43"/>78 <reg name="xmm4" bitsize="128" type="vec128" regnum="44"/>79 <reg name="xmm5" bitsize="128" type="vec128" regnum="45"/>80 <reg name="xmm6" bitsize="128" type="vec128" regnum="46"/>81 <reg name="xmm7" bitsize="128" type="vec128" regnum="47"/>82 <reg name="xmm8" bitsize="128" type="vec128" regnum="48"/>83 <reg name="xmm9" bitsize="128" type="vec128" regnum="49"/>84 <reg name="xmm10" bitsize="128" type="vec128" regnum="50"/>85 <reg name="xmm11" bitsize="128" type="vec128" regnum="51"/>86 <reg name="xmm12" bitsize="128" type="vec128" regnum="52"/>87 <reg name="xmm13" bitsize="128" type="vec128" regnum="53"/>88 <reg name="xmm14" bitsize="128" type="vec128" regnum="54"/>89 <reg name="xmm15" bitsize="128" type="vec128" regnum="55"/>90 <reg name="mxcsr" bitsize="32" type="i386_mxcsr" regnum="56" group="vector"/>91 </feature>92 <feature name="org.gnu.gdb.i386.avx">93 <reg name="ymm0h" bitsize="128" type="uint128" regnum="60"/>94 <reg name="ymm1h" bitsize="128" type="uint128" regnum="61"/>95 <reg name="ymm2h" bitsize="128" type="uint128" regnum="62"/>96 <reg name="ymm3h" bitsize="128" type="uint128" regnum="63"/>97 <reg name="ymm4h" bitsize="128" type="uint128" regnum="64"/>98 <reg name="ymm5h" bitsize="128" type="uint128" regnum="65"/>99 <reg name="ymm6h" bitsize="128" type="uint128" regnum="66"/>100 <reg name="ymm7h" bitsize="128" type="uint128" regnum="67"/>101 <reg name="ymm8h" bitsize="128" type="uint128" regnum="68"/>102 <reg name="ymm9h" bitsize="128" type="uint128" regnum="69"/>103 <reg name="ymm10h" bitsize="128" type="uint128" regnum="70"/>104 <reg name="ymm11h" bitsize="128" type="uint128" regnum="71"/>105 <reg name="ymm12h" bitsize="128" type="uint128" regnum="72"/>106 <reg name="ymm13h" bitsize="128" type="uint128" regnum="73"/>107 <reg name="ymm14h" bitsize="128" type="uint128" regnum="74"/>108 <reg name="ymm15h" bitsize="128" type="uint128" regnum="75"/>109 </feature>110 </target>""",111 False,112 )113 else:114 return None, False115 116 def readRegister(self, regnum):117 return ""118 119 def readRegisters(self):120 return self.reg_data121 122 def writeRegisters(self, reg_hex):123 self.reg_data = reg_hex124 return "OK"125 126 def haltReason(self):127 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;"128 129 self.server.responder = MyResponder()130 131 target = self.createTarget("basic_eh_frame.yaml")132 process = self.connect(target)133 lldbutil.expect_state_changes(134 self, self.dbg.GetListener(), process, [lldb.eStateStopped]135 )136 137 # test generic aliases138 self.match("register read arg4", ["rcx = 0x0807060504030201"])139 self.match("register read arg3", ["rdx = 0x1817161514131211"])140 self.match("register read arg2", ["rsi = 0x2827262524232221"])141 self.match("register read arg1", ["rdi = 0x3837363534333231"])142 self.match("register read fp", ["rbp = 0x4847464544434241"])143 self.match("register read sp", ["rsp = 0x5857565554535251"])144 self.match("register read arg5", ["r8 = 0x6867666564636261"])145 self.match("register read arg6", ["r9 = 0x7877767574737271"])146 self.match("register read pc", ["rip = 0x8887868584838281"])147 self.match("register read flags", ["eflags = 0x94939291"])148 149 # both stX and xmmX should be displayed as vectors150 self.match(151 "register read st0",152 ["st0 = {0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a}"],153 )154 self.match(155 "register read st1",156 ["st1 = {0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a}"],157 )158 self.match(159 "register read xmm0",160 [161 "xmm0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 "162 "0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"163 ],164 )165 self.match(166 "register read xmm1",167 [168 "xmm1 = {0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 "169 "0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0}"170 ],171 )172 173 # test pseudo-registers174 self.filecheck(175 "register read --all",176 os.path.join(os.path.dirname(__file__), "amd64-partial-regs.FileCheck"),177 )178 179 # test writing into pseudo-registers180 self.runCmd("register write ecx 0xfffefdfc")181 self.match("register read rcx", ["rcx = 0x08070605fffefdfc"])182 183 self.runCmd("register write cx 0xfbfa")184 self.match("register read ecx", ["ecx = 0xfffefbfa"])185 self.match("register read rcx", ["rcx = 0x08070605fffefbfa"])186 187 self.runCmd("register write ch 0xf9")188 self.match("register read cx", ["cx = 0xf9fa"])189 self.match("register read ecx", ["ecx = 0xfffef9fa"])190 self.match("register read rcx", ["rcx = 0x08070605fffef9fa"])191 192 self.runCmd("register write cl 0xf8")193 self.match("register read cx", ["cx = 0xf9f8"])194 self.match("register read ecx", ["ecx = 0xfffef9f8"])195 self.match("register read rcx", ["rcx = 0x08070605fffef9f8"])196 197 self.runCmd("register write mm0 0xfffefdfcfbfaf9f8")198 self.match(199 "register read st0",200 ["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"],201 )202 203 self.runCmd(204 'register write xmm0 "{0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 '205 '0xf8 0xf7 0xf6 0xf5 0xf4 0xf3 0xf2 0xf1 0xf0}"'206 )207 self.match(208 "register read ymm0",209 [210 "ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 "211 "0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xb1 0xb2 0xb3 0xb4 0xb5 "212 "0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0}"213 ],214 )215 216 self.runCmd(217 'register write ymm0h "{0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 '218 '0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}"'219 )220 self.match(221 "register read ymm0",222 [223 "ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 "224 "0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xef 0xee 0xed 0xec 0xeb "225 "0xea 0xe9 0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}"226 ],227 )228 229 self.runCmd(230 'register write ymm0 "{0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 '231 "0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 "232 "0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec "233 '0xed 0xee 0xef}"'234 )235 self.match(236 "register read ymm0",237 [238 "ymm0 = {0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 "239 "0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 "240 "0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef}"241 ],242 )243 244 @skipIfXmlSupportMissing245 @skipIfRemote246 @skipIfLLVMTargetMissing("X86")247 def test_i386_regs(self):248 """Test grabbing various i386 registers from gdbserver."""249 250 class MyResponder(MockGDBServerResponder):251 reg_data = (252 (253 "01020304" # eax254 "11121314" # ecx255 "21222324" # edx256 "31323334" # ebx257 "41424344" # esp258 "51525354" # ebp259 "61626364" # esi260 "71727374" # edi261 "81828384" # eip262 "91929394" # eflags263 "0102030405060708090a" # st0264 "1112131415161718191a" # st1265 )266 + 6 * ("2122232425262728292a") # st2..st7267 + (268 "8182838485868788898a8b8c8d8e8f90" # xmm0269 "9192939495969798999a9b9c9d9e9fa0" # xmm1270 )271 + 6 * ("a1a2a3a4a5a6a7a8a9aaabacadaeafb0") # xmm2..xmm7272 + ("00000000") # mxcsr273 + (274 "b1b2b3b4b5b6b7b8b9babbbcbdbebfc0" # ymm0h275 "c1c2c3c4c5c6c7c8c9cacbcccdcecfd0" # ymm1h276 )277 + 6 * ("d1d2d3d4d5d6d7d8d9dadbdcdddedfe0") # ymm2h..ymm7h278 )279 280 def qXferRead(self, obj, annex, offset, length):281 if annex == "target.xml":282 return (283 """<?xml version="1.0"?>284 <!DOCTYPE feature SYSTEM "gdb-target.dtd">285 <target>286 <architecture>i386</architecture>287 <osabi>GNU/Linux</osabi>288 <feature name="org.gnu.gdb.i386.core">289 <reg name="eax" bitsize="32" type="int32" regnum="0"/>290 <reg name="ecx" bitsize="32" type="int32" regnum="1"/>291 <reg name="edx" bitsize="32" type="int32" regnum="2"/>292 <reg name="ebx" bitsize="32" type="int32" regnum="3"/>293 <reg name="esp" bitsize="32" type="data_ptr" regnum="4"/>294 <reg name="ebp" bitsize="32" type="data_ptr" regnum="5"/>295 <reg name="esi" bitsize="32" type="int32" regnum="6"/>296 <reg name="edi" bitsize="32" type="int32" regnum="7"/>297 <reg name="eip" bitsize="32" type="code_ptr" regnum="8"/>298 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="9"/>299 <reg name="st0" bitsize="80" type="i387_ext" regnum="16"/>300 <reg name="st1" bitsize="80" type="i387_ext" regnum="17"/>301 <reg name="st2" bitsize="80" type="i387_ext" regnum="18"/>302 <reg name="st3" bitsize="80" type="i387_ext" regnum="19"/>303 <reg name="st4" bitsize="80" type="i387_ext" regnum="20"/>304 <reg name="st5" bitsize="80" type="i387_ext" regnum="21"/>305 <reg name="st6" bitsize="80" type="i387_ext" regnum="22"/>306 <reg name="st7" bitsize="80" type="i387_ext" regnum="23"/>307 </feature>308 <feature name="org.gnu.gdb.i386.sse">309 <reg name="xmm0" bitsize="128" type="vec128" regnum="32"/>310 <reg name="xmm1" bitsize="128" type="vec128" regnum="33"/>311 <reg name="xmm2" bitsize="128" type="vec128" regnum="34"/>312 <reg name="xmm3" bitsize="128" type="vec128" regnum="35"/>313 <reg name="xmm4" bitsize="128" type="vec128" regnum="36"/>314 <reg name="xmm5" bitsize="128" type="vec128" regnum="37"/>315 <reg name="xmm6" bitsize="128" type="vec128" regnum="38"/>316 <reg name="xmm7" bitsize="128" type="vec128" regnum="39"/>317 <reg name="mxcsr" bitsize="32" type="i386_mxcsr" regnum="40" group="vector"/>318 </feature>319 <feature name="org.gnu.gdb.i386.avx">320 <reg name="ymm0h" bitsize="128" type="uint128" regnum="42"/>321 <reg name="ymm1h" bitsize="128" type="uint128" regnum="43"/>322 <reg name="ymm2h" bitsize="128" type="uint128" regnum="44"/>323 <reg name="ymm3h" bitsize="128" type="uint128" regnum="45"/>324 <reg name="ymm4h" bitsize="128" type="uint128" regnum="46"/>325 <reg name="ymm5h" bitsize="128" type="uint128" regnum="47"/>326 <reg name="ymm6h" bitsize="128" type="uint128" regnum="48"/>327 <reg name="ymm7h" bitsize="128" type="uint128" regnum="49"/>328 </feature>329 </target>""",330 False,331 )332 else:333 return None, False334 335 def readRegister(self, regnum):336 return ""337 338 def readRegisters(self):339 return self.reg_data340 341 def writeRegisters(self, reg_hex):342 self.reg_data = reg_hex343 return "OK"344 345 def haltReason(self):346 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;"347 348 self.server.responder = MyResponder()349 350 target = self.createTarget("basic_eh_frame-i386.yaml")351 process = self.connect(target)352 lldbutil.expect_state_changes(353 self, self.dbg.GetListener(), process, [lldb.eStateStopped]354 )355 356 # test generic aliases357 self.match("register read fp", ["ebp = 0x54535251"])358 self.match("register read sp", ["esp = 0x44434241"])359 self.match("register read pc", ["eip = 0x84838281"])360 self.match("register read flags", ["eflags = 0x94939291"])361 362 # test pseudo-registers363 self.match("register read cx", ["cx = 0x1211"])364 self.match("register read ch", ["ch = 0x12"])365 self.match("register read cl", ["cl = 0x11"])366 self.match("register read mm0", ["mm0 = 0x0807060504030201"])367 self.match("register read mm1", ["mm1 = 0x1817161514131211"])368 369 # both stX and xmmX should be displayed as vectors370 self.match(371 "register read st0",372 ["st0 = {0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a}"],373 )374 self.match(375 "register read st1",376 ["st1 = {0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a}"],377 )378 self.match(379 "register read xmm0",380 [381 "xmm0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 "382 "0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"383 ],384 )385 self.match(386 "register read xmm1",387 [388 "xmm1 = {0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 "389 "0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0}"390 ],391 )392 393 # test writing into pseudo-registers394 self.runCmd("register write cx 0xfbfa")395 self.match("register read ecx", ["ecx = 0x1413fbfa"])396 397 self.runCmd("register write ch 0xf9")398 self.match("register read cx", ["cx = 0xf9fa"])399 self.match("register read ecx", ["ecx = 0x1413f9fa"])400 401 self.runCmd("register write cl 0xf8")402 self.match("register read cx", ["cx = 0xf9f8"])403 self.match("register read ecx", ["ecx = 0x1413f9f8"])404 405 self.runCmd("register write mm0 0xfffefdfcfbfaf9f8")406 self.match(407 "register read st0",408 ["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"],409 )410 411 self.runCmd(412 'register write xmm0 "{0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 '413 '0xf8 0xf7 0xf6 0xf5 0xf4 0xf3 0xf2 0xf1 0xf0}"'414 )415 self.match(416 "register read ymm0",417 [418 "ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 "419 "0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xb1 0xb2 0xb3 0xb4 0xb5 "420 "0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0}"421 ],422 )423 424 self.runCmd(425 'register write ymm0h "{0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 '426 '0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}"'427 )428 self.match(429 "register read ymm0",430 [431 "ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 "432 "0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xef 0xee 0xed 0xec 0xeb "433 "0xea 0xe9 0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}"434 ],435 )436 437 self.runCmd(438 'register write ymm0 "{0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 '439 "0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 "440 "0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec "441 '0xed 0xee 0xef}"'442 )443 self.match(444 "register read ymm0",445 [446 "ymm0 = {0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 "447 "0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 "448 "0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef}"449 ],450 )451 452 @skipIfXmlSupportMissing453 @skipIfRemote454 @skipIfLLVMTargetMissing("AArch64")455 def test_aarch64_regs(self):456 """Test grabbing various aarch64 registers from gdbserver."""457 458 class MyResponder(MockGDBServerResponder):459 reg_data = (460 ("0102030405060708" "1112131415161718") # x0 # x1461 + 27 * ("2122232425262728") # x2..x28462 + (463 "3132333435363738" # x29 (fp)464 "4142434445464748" # x30 (lr)465 "5152535455565758" # x31 (sp)466 "6162636465666768" # pc467 "71727374" # cpsr468 "8182838485868788898a8b8c8d8e8f90" # v0469 "9192939495969798999a9b9c9d9e9fa0" # v1470 )471 + 30 * ("a1a2a3a4a5a6a7a8a9aaabacadaeafb0") # v2..v31472 + ("00000000" "00000000") # fpsr # fpcr473 )474 475 def qXferRead(self, obj, annex, offset, length):476 if annex == "target.xml":477 return (478 """<?xml version="1.0"?>479 <!DOCTYPE feature SYSTEM "gdb-target.dtd">480 <target>481 <architecture>aarch64</architecture>482 <feature name="org.gnu.gdb.aarch64.core">483 <reg name="x0" bitsize="64" type="int" regnum="0"/>484 <reg name="x1" bitsize="64" type="int" regnum="1"/>485 <reg name="x2" bitsize="64" type="int" regnum="2"/>486 <reg name="x3" bitsize="64" type="int" regnum="3"/>487 <reg name="x4" bitsize="64" type="int" regnum="4"/>488 <reg name="x5" bitsize="64" type="int" regnum="5"/>489 <reg name="x6" bitsize="64" type="int" regnum="6"/>490 <reg name="x7" bitsize="64" type="int" regnum="7"/>491 <reg name="x8" bitsize="64" type="int" regnum="8"/>492 <reg name="x9" bitsize="64" type="int" regnum="9"/>493 <reg name="x10" bitsize="64" type="int" regnum="10"/>494 <reg name="x11" bitsize="64" type="int" regnum="11"/>495 <reg name="x12" bitsize="64" type="int" regnum="12"/>496 <reg name="x13" bitsize="64" type="int" regnum="13"/>497 <reg name="x14" bitsize="64" type="int" regnum="14"/>498 <reg name="x15" bitsize="64" type="int" regnum="15"/>499 <reg name="x16" bitsize="64" type="int" regnum="16"/>500 <reg name="x17" bitsize="64" type="int" regnum="17"/>501 <reg name="x18" bitsize="64" type="int" regnum="18"/>502 <reg name="x19" bitsize="64" type="int" regnum="19"/>503 <reg name="x20" bitsize="64" type="int" regnum="20"/>504 <reg name="x21" bitsize="64" type="int" regnum="21"/>505 <reg name="x22" bitsize="64" type="int" regnum="22"/>506 <reg name="x23" bitsize="64" type="int" regnum="23"/>507 <reg name="x24" bitsize="64" type="int" regnum="24"/>508 <reg name="x25" bitsize="64" type="int" regnum="25"/>509 <reg name="x26" bitsize="64" type="int" regnum="26"/>510 <reg name="x27" bitsize="64" type="int" regnum="27"/>511 <reg name="x28" bitsize="64" type="int" regnum="28"/>512 <reg name="x29" bitsize="64" type="int" regnum="29"/>513 <reg name="x30" bitsize="64" type="int" regnum="30"/>514 <reg name="sp" bitsize="64" type="data_ptr" regnum="31"/>515 <reg name="pc" bitsize="64" type="code_ptr" regnum="32"/>516 <reg name="cpsr" bitsize="32" type="cpsr_flags" regnum="33"/>517 </feature>518 <feature name="org.gnu.gdb.aarch64.fpu">519 <reg name="v0" bitsize="128" type="aarch64v" regnum="34"/>520 <reg name="v1" bitsize="128" type="aarch64v" regnum="35"/>521 <reg name="v2" bitsize="128" type="aarch64v" regnum="36"/>522 <reg name="v3" bitsize="128" type="aarch64v" regnum="37"/>523 <reg name="v4" bitsize="128" type="aarch64v" regnum="38"/>524 <reg name="v5" bitsize="128" type="aarch64v" regnum="39"/>525 <reg name="v6" bitsize="128" type="aarch64v" regnum="40"/>526 <reg name="v7" bitsize="128" type="aarch64v" regnum="41"/>527 <reg name="v8" bitsize="128" type="aarch64v" regnum="42"/>528 <reg name="v9" bitsize="128" type="aarch64v" regnum="43"/>529 <reg name="v10" bitsize="128" type="aarch64v" regnum="44"/>530 <reg name="v11" bitsize="128" type="aarch64v" regnum="45"/>531 <reg name="v12" bitsize="128" type="aarch64v" regnum="46"/>532 <reg name="v13" bitsize="128" type="aarch64v" regnum="47"/>533 <reg name="v14" bitsize="128" type="aarch64v" regnum="48"/>534 <reg name="v15" bitsize="128" type="aarch64v" regnum="49"/>535 <reg name="v16" bitsize="128" type="aarch64v" regnum="50"/>536 <reg name="v17" bitsize="128" type="aarch64v" regnum="51"/>537 <reg name="v18" bitsize="128" type="aarch64v" regnum="52"/>538 <reg name="v19" bitsize="128" type="aarch64v" regnum="53"/>539 <reg name="v20" bitsize="128" type="aarch64v" regnum="54"/>540 <reg name="v21" bitsize="128" type="aarch64v" regnum="55"/>541 <reg name="v22" bitsize="128" type="aarch64v" regnum="56"/>542 <reg name="v23" bitsize="128" type="aarch64v" regnum="57"/>543 <reg name="v24" bitsize="128" type="aarch64v" regnum="58"/>544 <reg name="v25" bitsize="128" type="aarch64v" regnum="59"/>545 <reg name="v26" bitsize="128" type="aarch64v" regnum="60"/>546 <reg name="v27" bitsize="128" type="aarch64v" regnum="61"/>547 <reg name="v28" bitsize="128" type="aarch64v" regnum="62"/>548 <reg name="v29" bitsize="128" type="aarch64v" regnum="63"/>549 <reg name="v30" bitsize="128" type="aarch64v" regnum="64"/>550 <reg name="v31" bitsize="128" type="aarch64v" regnum="65"/>551 <reg name="fpsr" bitsize="32" type="int" regnum="66"/>552 <reg name="fpcr" bitsize="32" type="int" regnum="67"/>553 </feature>554 </target>""",555 False,556 )557 else:558 return None, False559 560 def readRegister(self, regnum):561 return ""562 563 def readRegisters(self):564 return self.reg_data565 566 def writeRegisters(self, reg_hex):567 self.reg_data = reg_hex568 return "OK"569 570 def haltReason(self):571 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;"572 573 self.server.responder = MyResponder()574 575 target = self.createTarget("basic_eh_frame-aarch64.yaml")576 process = self.connect(target)577 lldbutil.expect_state_changes(578 self, self.dbg.GetListener(), process, [lldb.eStateStopped]579 )580 581 # test GPRs582 self.match("register read x0", ["x0 = 0x0807060504030201"])583 self.match("register read x1", ["x1 = 0x1817161514131211"])584 self.match("register read x29", ["x29 = 0x3837363534333231"])585 self.match("register read x30", ["x30 = 0x4847464544434241"])586 self.match("register read x31", ["sp = 0x5857565554535251"])587 self.match("register read sp", ["sp = 0x5857565554535251"])588 self.match("register read pc", ["pc = 0x6867666564636261"])589 self.match("register read cpsr", ["cpsr = 0x74737271"])590 591 # test generic aliases592 self.match("register read arg1", ["x0 = 0x0807060504030201"])593 self.match("register read arg2", ["x1 = 0x1817161514131211"])594 self.match("register read fp", ["x29 = 0x3837363534333231"])595 self.match("register read lr", ["x30 = 0x4847464544434241"])596 self.match("register read ra", ["x30 = 0x4847464544434241"])597 self.match("register read flags", ["cpsr = 0x74737271"])598 599 # test vector registers600 self.match(601 "register read v0",602 [603 "v0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"604 ],605 )606 self.match(607 "register read v31",608 [609 "v31 = {0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0}"610 ],611 )612 613 # test partial registers614 self.match("register read w0", ["w0 = 0x04030201"])615 self.runCmd("register write w0 0xfffefdfc")616 self.match("register read x0", ["x0 = 0x08070605fffefdfc"])617 618 self.match("register read w1", ["w1 = 0x14131211"])619 self.runCmd("register write w1 0xefeeedec")620 self.match("register read x1", ["x1 = 0x18171615efeeedec"])621 622 self.match("register read w30", ["w30 = 0x44434241"])623 self.runCmd("register write w30 0xdfdedddc")624 self.match("register read x30", ["x30 = 0x48474645dfdedddc"])625 626 self.match("register read w31", ["w31 = 0x54535251"])627 self.runCmd("register write w31 0xcfcecdcc")628 self.match("register read x31", ["sp = 0x58575655cfcecdcc"])629 630 # test FPU registers (overlapping with vector registers)631 self.runCmd("register write d0 16")632 self.match(633 "register read v0",634 [635 "v0 = {0x00 0x00 0x00 0x00 0x00 0x00 0x30 0x40 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"636 ],637 )638 self.runCmd(639 "register write v31 '{0x00 0x00 0x00 0x00 0x00 0x00 0x50 0x40 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff}'"640 )641 self.match("register read d31", ["d31 = 64"])642 643 self.runCmd("register write s0 32")644 self.match(645 "register read v0",646 [647 "v0 = {0x00 0x00 0x00 0x42 0x00 0x00 0x30 0x40 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"648 ],649 )650 self.runCmd(651 "register write v31 '{0x00 0x00 0x00 0x43 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff}'"652 )653 self.match("register read s31", ["s31 = 128"])654 655 @skipIfXmlSupportMissing656 @skipIfRemote657 @skipIfLLVMTargetMissing("RISCV")658 def test_riscv64_regs(self):659 """Test grabbing various riscv64 registers from gdbserver."""660 661 class MyResponder(MockGDBServerResponder):662 reg_data = (663 "0102030405060708" # zero664 "0102030405060708" # ra665 "0102030405060708" # sp666 "0102030405060708" # gp667 "0102030405060708" # tp668 "0102030405060708" # t0669 "0102030405060708" # t1670 "0102030405060708" # t2671 "0102030405060708" # fp672 "0102030405060708" # s1673 "0102030405060708" # a0674 "0102030405060708" # a1675 "0102030405060708" # a2676 "0102030405060708" # a3677 "0102030405060708" # a4678 "0102030405060708" # a5679 "0102030405060708" # a6680 "0102030405060708" # a7681 "0102030405060708" # s2682 "0102030405060708" # s3683 "0102030405060708" # s4684 "0102030405060708" # s5685 "0102030405060708" # s6686 "0102030405060708" # s7687 "0102030405060708" # s8688 "0102030405060708" # s9689 "0102030405060708" # s10690 "0102030405060708" # s11691 "0102030405060708" # t3692 "0102030405060708" # t4693 "0102030405060708" # t5694 "0102030405060708" # t6695 "6162636465666768" # pc696 "0000C03F" # ft0697 "e07a6147a8a40940" # ft1698 )699 700 def qXferRead(self, obj, annex, offset, length):701 if annex == "target.xml":702 # Note that this XML does not include any aliases, LLDB must generate them itself.703 return (704 """<?xml version="1.0"?>705 <!DOCTYPE feature SYSTEM "gdb-target.dtd">706 <target>707 <architecture>riscv</architecture>708 <feature name="org.gnu.gdb.riscv.cpu">709 <reg name="zero" bitsize="64" type="int"/>710 <reg name="ra" bitsize="64" type="code_ptr"/>711 <reg name="sp" bitsize="64" type="data_ptr"/>712 <reg name="gp" bitsize="64" type="data_ptr"/>713 <reg name="tp" bitsize="64" type="data_ptr"/>714 <reg name="t0" bitsize="64" type="int"/>715 <reg name="t1" bitsize="64" type="int"/>716 <reg name="t2" bitsize="64" type="int"/>717 <reg name="fp" bitsize="64" type="data_ptr"/>718 <reg name="s1" bitsize="64" type="int"/>719 <reg name="a0" bitsize="64" type="int"/>720 <reg name="a1" bitsize="64" type="int"/>721 <reg name="a2" bitsize="64" type="int"/>722 <reg name="a3" bitsize="64" type="int"/>723 <reg name="a4" bitsize="64" type="int"/>724 <reg name="a5" bitsize="64" type="int"/>725 <reg name="a6" bitsize="64" type="int"/>726 <reg name="a7" bitsize="64" type="int"/>727 <reg name="s2" bitsize="64" type="int"/>728 <reg name="s3" bitsize="64" type="int"/>729 <reg name="s4" bitsize="64" type="int"/>730 <reg name="s5" bitsize="64" type="int"/>731 <reg name="s6" bitsize="64" type="int"/>732 <reg name="s7" bitsize="64" type="int"/>733 <reg name="s8" bitsize="64" type="int"/>734 <reg name="s9" bitsize="64" type="int"/>735 <reg name="s10" bitsize="64" type="int"/>736 <reg name="s11" bitsize="64" type="int"/>737 <reg name="t3" bitsize="64" type="int"/>738 <reg name="t4" bitsize="64" type="int"/>739 <reg name="t5" bitsize="64" type="int"/>740 <reg name="t6" bitsize="64" type="int"/>741 <reg name="pc" bitsize="64" type="code_ptr"/>742 </feature>743 <feature name='org.gnu.gdb.riscv.fpu'>744 <reg name='ft0' bitsize='32' type='ieee_single'/>745 <reg name='ft1' bitsize='64' type='ieee_double'/>746 </feature>747 </target>""",748 False,749 )750 else:751 return None, False752 753 def readRegister(self, regnum):754 return ""755 756 def readRegisters(self):757 return self.reg_data758 759 def writeRegisters(self, reg_hex):760 self.reg_data = reg_hex761 return "OK"762 763 def haltReason(self):764 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;"765 766 self.server.responder = MyResponder()767 768 target = self.createTarget("basic_eh_frame-riscv64.yaml")769 process = self.connect(target)770 lldbutil.expect_state_changes(771 self, self.dbg.GetListener(), process, [lldb.eStateStopped]772 )773 774 # test generic aliases775 self.match("register read x0", ["zero = 0x0807060504030201"])776 self.match("register read x1", ["ra = 0x0807060504030201"])777 self.match("register read x2", ["sp = 0x0807060504030201"])778 self.match("register read x3", ["gp = 0x0807060504030201"])779 self.match("register read x4", ["tp = 0x0807060504030201"])780 self.match("register read x5", ["t0 = 0x0807060504030201"])781 self.match("register read x6", ["t1 = 0x0807060504030201"])782 self.match("register read x7", ["t2 = 0x0807060504030201"])783 # Register x8 is probably not working because it has two aliases fp, s0784 # See issue #127900785 # self.match("register read x8", ["fp = 0x0807060504030201"])786 self.match("register read x9", ["s1 = 0x0807060504030201"])787 self.match("register read x10", ["a0 = 0x0807060504030201"])788 self.match("register read x11", ["a1 = 0x0807060504030201"])789 self.match("register read x12", ["a2 = 0x0807060504030201"])790 self.match("register read x13", ["a3 = 0x0807060504030201"])791 self.match("register read x14", ["a4 = 0x0807060504030201"])792 self.match("register read x15", ["a5 = 0x0807060504030201"])793 self.match("register read x16", ["a6 = 0x0807060504030201"])794 self.match("register read x17", ["a7 = 0x0807060504030201"])795 self.match("register read x18", ["s2 = 0x0807060504030201"])796 self.match("register read x19", ["s3 = 0x0807060504030201"])797 self.match("register read x20", ["s4 = 0x0807060504030201"])798 self.match("register read x21", ["s5 = 0x0807060504030201"])799 self.match("register read x22", ["s6 = 0x0807060504030201"])800 self.match("register read x23", ["s7 = 0x0807060504030201"])801 self.match("register read x24", ["s8 = 0x0807060504030201"])802 self.match("register read x25", ["s9 = 0x0807060504030201"])803 self.match("register read x26", ["s10 = 0x0807060504030201"])804 self.match("register read x27", ["s11 = 0x0807060504030201"])805 self.match("register read x28", ["t3 = 0x0807060504030201"])806 self.match("register read x29", ["t4 = 0x0807060504030201"])807 self.match("register read x30", ["t5 = 0x0807060504030201"])808 self.match("register read x31", ["t6 = 0x0807060504030201"])809 self.match("register read pc", ["pc = 0x6867666564636261"])810 # test FPU registers811 self.match("register read ft0", ["ft0 = 1.5"])812 self.match("register read ft1", ["ft1 = 3.2053990913985757"])813 814 @skipIfXmlSupportMissing815 @skipIfRemote816 @skipIfLLVMTargetMissing("X86")817 def test_x86_64_no_duplicate_subregs(self):818 """Test that duplicate subregisters are not added (on x86_64)."""819 820 class MyResponder(MockGDBServerResponder):821 reg_data = (822 "0102030405060708" # rcx823 "1112131415161718" # rdx824 "2122232425262728" # rsi825 "3132333435363738" # rdi826 "4142434445464748" # rbp827 "5152535455565758" # rsp828 "6162636465666768" # r8829 "7172737475767778" # r9830 "8182838485868788" # rip831 "91929394" # eflags832 )833 834 def qXferRead(self, obj, annex, offset, length):835 if annex == "target.xml":836 return (837 """<?xml version="1.0"?>838 <!DOCTYPE feature SYSTEM "gdb-target.dtd">839 <target>840 <architecture>i386:x86-64</architecture>841 <osabi>GNU/Linux</osabi>842 <feature name="org.gnu.gdb.i386.core">843 <reg name="rcx" bitsize="64" type="int64" regnum="2"/>844 <reg name="rdx" bitsize="64" type="int64" regnum="3"/>845 <reg name="rsi" bitsize="64" type="int64" regnum="4"/>846 <reg name="rdi" bitsize="64" type="int64" regnum="5"/>847 <reg name="rbp" bitsize="64" type="data_ptr" regnum="6"/>848 <reg name="rsp" bitsize="64" type="data_ptr" regnum="7"/>849 <reg name="r8" bitsize="64" type="int64" regnum="8"/>850 <reg name="r9" bitsize="64" type="int64" regnum="9"/>851 <reg name="rip" bitsize="64" type="code_ptr" regnum="16"/>852 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="17"/>853 <reg name="ecx" bitsize="32" type="int" regnum="18" value_regnums="2"/>854 </feature>855 </target>""",856 False,857 )858 else:859 return None, False860 861 def readRegister(self, regnum):862 return ""863 864 def readRegisters(self):865 return self.reg_data866 867 def haltReason(self):868 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;"869 870 self.server.responder = MyResponder()871 872 target = self.createTarget("basic_eh_frame.yaml")873 process = self.connect(target)874 lldbutil.expect_state_changes(875 self, self.dbg.GetListener(), process, [lldb.eStateStopped]876 )877 878 self.match("register read rcx", ["rcx = 0x0807060504030201"])879 # ecx is supplied via target.xml880 self.match("register read ecx", ["ecx = 0x04030201"])881 self.match("register read rdx", ["rdx = 0x1817161514131211"])882 # edx should not be added883 self.match(884 "register read edx", ["error: Invalid register name 'edx'."], error=True885 )886 887 @skipIfXmlSupportMissing888 @skipIfRemote889 @skipIfLLVMTargetMissing("X86")890 def test_i386_no_duplicate_subregs(self):891 """Test that duplicate subregisters are not added (on i386)."""892 893 class MyResponder(MockGDBServerResponder):894 reg_data = (895 "01020304" # eax896 "11121314" # ecx897 "21222324" # edx898 "31323334" # ebx899 "41424344" # esp900 "51525354" # ebp901 "61626364" # esi902 "71727374" # edi903 "81828384" # eip904 "91929394" # eflags905 )906 907 def qXferRead(self, obj, annex, offset, length):908 if annex == "target.xml":909 return (910 """<?xml version="1.0"?>911 <!DOCTYPE feature SYSTEM "gdb-target.dtd">912 <target>913 <architecture>i386</architecture>914 <osabi>GNU/Linux</osabi>915 <feature name="org.gnu.gdb.i386.core">916 <reg name="eax" bitsize="32" type="int32" regnum="0"/>917 <reg name="ecx" bitsize="32" type="int32" regnum="1"/>918 <reg name="edx" bitsize="32" type="int32" regnum="2"/>919 <reg name="ebx" bitsize="32" type="int32" regnum="3"/>920 <reg name="esp" bitsize="32" type="data_ptr" regnum="4"/>921 <reg name="ebp" bitsize="32" type="data_ptr" regnum="5"/>922 <reg name="esi" bitsize="32" type="int32" regnum="6"/>923 <reg name="edi" bitsize="32" type="int32" regnum="7"/>924 <reg name="eip" bitsize="32" type="code_ptr" regnum="8"/>925 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="9"/>926 <reg name="ax" bitsize="16" type="int" regnum="10" value_regnums="0"/>927 </feature>928 </target>""",929 False,930 )931 else:932 return None, False933 934 def readRegister(self, regnum):935 return ""936 937 def readRegisters(self):938 return self.reg_data939 940 def haltReason(self):941 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;"942 943 self.server.responder = MyResponder()944 945 target = self.createTarget("basic_eh_frame-i386.yaml")946 process = self.connect(target)947 lldbutil.expect_state_changes(948 self, self.dbg.GetListener(), process, [lldb.eStateStopped]949 )950 951 self.match("register read eax", ["eax = 0x04030201"])952 # cx is supplied via target.xml953 self.match("register read ax", ["ax = 0x0201"])954 self.match("register read ecx", ["ecx = 0x14131211"])955 # dx should not be added956 self.match(957 "register read cx", ["error: Invalid register name 'cx'."], error=True958 )959 960 @skipIfXmlSupportMissing961 @skipIfRemote962 @skipIfLLVMTargetMissing("AArch64")963 def test_aarch64_no_duplicate_subregs(self):964 """Test that duplicate subregisters are not added."""965 966 class MyResponder(MockGDBServerResponder):967 reg_data = (968 ("0102030405060708" "1112131415161718") # x0 # x1969 + 27 * ("2122232425262728") # x2..x28970 + (971 "3132333435363738" # x29 (fp)972 "4142434445464748" # x30 (lr)973 "5152535455565758" # x31 (sp)974 "6162636465666768" # pc975 "71727374" # cpsr976 )977 )978 979 def qXferRead(self, obj, annex, offset, length):980 if annex == "target.xml":981 return (982 """<?xml version="1.0"?>983 <!DOCTYPE feature SYSTEM "gdb-target.dtd">984 <target>985 <architecture>aarch64</architecture>986 <feature name="org.gnu.gdb.aarch64.core">987 <reg name="x0" bitsize="64" type="int" regnum="0"/>988 <reg name="x1" bitsize="64" type="int" regnum="1"/>989 <reg name="x2" bitsize="64" type="int" regnum="2"/>990 <reg name="x3" bitsize="64" type="int" regnum="3"/>991 <reg name="x4" bitsize="64" type="int" regnum="4"/>992 <reg name="x5" bitsize="64" type="int" regnum="5"/>993 <reg name="x6" bitsize="64" type="int" regnum="6"/>994 <reg name="x7" bitsize="64" type="int" regnum="7"/>995 <reg name="x8" bitsize="64" type="int" regnum="8"/>996 <reg name="x9" bitsize="64" type="int" regnum="9"/>997 <reg name="x10" bitsize="64" type="int" regnum="10"/>998 <reg name="x11" bitsize="64" type="int" regnum="11"/>999 <reg name="x12" bitsize="64" type="int" regnum="12"/>1000 <reg name="x13" bitsize="64" type="int" regnum="13"/>1001 <reg name="x14" bitsize="64" type="int" regnum="14"/>1002 <reg name="x15" bitsize="64" type="int" regnum="15"/>1003 <reg name="x16" bitsize="64" type="int" regnum="16"/>1004 <reg name="x17" bitsize="64" type="int" regnum="17"/>1005 <reg name="x18" bitsize="64" type="int" regnum="18"/>1006 <reg name="x19" bitsize="64" type="int" regnum="19"/>1007 <reg name="x20" bitsize="64" type="int" regnum="20"/>1008 <reg name="x21" bitsize="64" type="int" regnum="21"/>1009 <reg name="x22" bitsize="64" type="int" regnum="22"/>1010 <reg name="x23" bitsize="64" type="int" regnum="23"/>1011 <reg name="x24" bitsize="64" type="int" regnum="24"/>1012 <reg name="x25" bitsize="64" type="int" regnum="25"/>1013 <reg name="x26" bitsize="64" type="int" regnum="26"/>1014 <reg name="x27" bitsize="64" type="int" regnum="27"/>1015 <reg name="x28" bitsize="64" type="int" regnum="28"/>1016 <reg name="x29" bitsize="64" type="int" regnum="29"/>1017 <reg name="x30" bitsize="64" type="int" regnum="30"/>1018 <reg name="sp" bitsize="64" type="data_ptr" regnum="31"/>1019 <reg name="pc" bitsize="64" type="code_ptr" regnum="32"/>1020 <reg name="cpsr" bitsize="32" type="cpsr_flags" regnum="33"/>1021 <reg name="w0" bitsize="32" type="int" regnum="34" value_regnums="0"/>1022 </feature>1023 </target>""",1024 False,1025 )1026 else:1027 return None, False1028 1029 def readRegister(self, regnum):1030 return ""1031 1032 def readRegisters(self):1033 return self.reg_data1034 1035 def haltReason(self):1036 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;"1037 1038 self.server.responder = MyResponder()1039 1040 target = self.createTarget("basic_eh_frame-aarch64.yaml")1041 process = self.connect(target)1042 lldbutil.expect_state_changes(1043 self, self.dbg.GetListener(), process, [lldb.eStateStopped]1044 )1045 1046 self.match("register read x0", ["x0 = 0x0807060504030201"])1047 # w0 comes from target.xml1048 self.match("register read w0", ["w0 = 0x04030201"])1049 self.match("register read x1", ["x1 = 0x1817161514131211"])1050 # w1 should not be added1051 self.match(1052 "register read w1", ["error: Invalid register name 'w1'."], error=True1053 )1054