90 lines · python
1"""Test that all of the GPR registers are read correctly from a riscv32 corefile."""2 3import os4import re5import subprocess6 7import lldb8from lldbsuite.test.decorators import *9from lldbsuite.test.lldbtest import *10from lldbsuite.test import lldbutil11 12 13class TestRV32MachOCorefile(TestBase):14 NO_DEBUG_INFO_TESTCASE = True15 16 @no_debug_info_test17 def test_riscv32_gpr_corefile_registers(self):18 corefile = self.getBuildArtifact("core")19 self.yaml2macho_core("riscv32-registers.yaml", corefile)20 21 target = self.dbg.CreateTarget("")22 process = target.LoadCore(corefile)23 24 process = target.GetProcess()25 self.assertEqual(process.GetNumThreads(), 2)26 27 thread = process.GetThreadAtIndex(0)28 self.assertEqual(thread.GetNumFrames(), 1)29 30 frame = thread.GetFrameAtIndex(0)31 gpr_regs = frame.registers.GetValueAtIndex(0)32 33 self.assertEqual(gpr_regs.GetName(), "General Purpose Registers")34 self.assertEqual(gpr_regs.GetNumChildren(), 33)35 regnames = [36 "zero",37 "ra",38 "sp",39 "gp",40 "tp",41 "t0",42 "t1",43 "t2",44 "fp",45 "s1",46 "a0",47 "a1",48 "a2",49 "a3",50 "a4",51 "a5",52 "a6",53 "a7",54 "s2",55 "s3",56 "s4",57 "s5",58 "s6",59 "s7",60 "s8",61 "s9",62 "s10",63 "s11",64 "t3",65 "t4",66 "t5",67 "t6",68 "pc",69 ]70 71 idx = 072 while idx < len(regnames):73 self.assertEqual(gpr_regs.GetChildAtIndex(idx).GetName(), regnames[idx])74 idx = idx + 175 76 idx = 077 while idx < len(regnames):78 val = idx | (idx << 8) | (idx << 16) | (idx << 24)79 self.assertEqual(gpr_regs.GetChildAtIndex(idx).GetValueAsUnsigned(), val)80 idx = idx + 181 82 thread = process.GetThreadAtIndex(1)83 self.assertEqual(thread.GetNumFrames(), 1)84 85 frame = thread.GetFrameAtIndex(0)86 gpr_regs = frame.registers.GetValueAtIndex(0)87 88 self.assertEqual(gpr_regs.GetChildAtIndex(0).GetValueAsUnsigned(), 0x90000000)89 self.assertEqual(gpr_regs.GetChildAtIndex(32).GetValueAsUnsigned(), 0x90202020)90