87 lines · python
1"""2Test software step-inst, also known as instruction level single step, in risc-v atomic sequence.3For more information about atomic sequences, see the RISC-V Unprivileged ISA specification.4"""5 6import lldb7from lldbsuite.test.decorators import *8from lldbsuite.test.lldbtest import *9from lldbsuite.test import lldbutil10 11 12class TestSoftwareStep(TestBase):13 def do_sequence_test(self, filename, bkpt_name):14 source_file = filename + ".c"15 exe_file = filename + ".x"16 17 self.build(dictionary={"C_SOURCES": source_file, "EXE": exe_file})18 (target, process, cur_thread, bkpt) = lldbutil.run_to_name_breakpoint(19 self, bkpt_name, exe_name=exe_file20 )21 entry_pc = cur_thread.GetFrameAtIndex(0).GetPC()22 23 self.runCmd("thread step-inst")24 self.expect(25 "thread list",26 substrs=["stopped", "stop reason = instruction step into"],27 )28 29 # Get the instruction we stopped at30 pc = cur_thread.GetFrameAtIndex(0).GetPCAddress()31 inst = target.ReadInstructions(pc, 1).GetInstructionAtIndex(0)32 33 inst_mnemonic = inst.GetMnemonic(target)34 inst_operands = inst.GetOperands(target)35 if not inst_operands:36 return inst_mnemonic37 38 return f"{inst_mnemonic} {inst_operands}"39 40 @skipIf(archs=no_match("^riscv.*"))41 def test_cas(self):42 """43 This test verifies LLDB instruction step handling of a proper lr/sc pair.44 """45 instruction = self.do_sequence_test("main", "cas")46 self.assertEqual(instruction, "nop")47 48 @skipIf(archs=no_match("^riscv.*"))49 def test_branch_cas(self):50 """51 LLDB cannot predict the actual state of registers within a critical section (i.e., inside an atomic52 sequence). Therefore, it should identify all forward branches inside the atomic sequence and set53 breakpoints at every jump address that lies beyond the end of the sequence (after the sc instruction).54 This ensures that if any such branch is taken, execution will pause at its target address.55 56 This test includes an lr/sc sequence containing an active forward branch with a jump address located57 after the end of the atomic section. LLDB should correctly stop at this branch's target address. The58 test is nearly identical to the previous one, except for the branch condition, which is inverted and59 will result in a taken jump.60 """61 instruction = self.do_sequence_test("branch", "branch_cas")62 self.assertEqual(instruction, "ret")63 64 @skipIf(archs=no_match("^riscv.*"))65 def test_incomplete_sequence_without_lr(self):66 """67 This test verifies the behavior of a standalone sc instruction without a preceding lr. Since the sc68 lacks the required lr pairing, LLDB should treat it as a non-atomic store rather than part of an69 atomic sequence.70 """71 instruction = self.do_sequence_test(72 "incomplete_sequence_without_lr", "incomplete_cas"73 )74 self.assertEqual(instruction, "and a5, a2, a4")75 76 @skipIf(archs=no_match("^riscv.*"))77 def test_incomplete_sequence_without_sc(self):78 """79 This test checks the behavior of a standalone lr instruction without a subsequent sc. Since the lr80 lacks its required sc counterpart, LLDB should treat it as a non-atomic load rather than part of an81 atomic sequence.82 """83 instruction = self.do_sequence_test(84 "incomplete_sequence_without_sc", "incomplete_cas"85 )86 self.assertEqual(instruction, "and a5, a2, a4")87