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1This file is a partial list of people who have contributed to the LLVM2project. If you have contributed a patch or made some other contribution to3LLVM, please submit a patch to this file to add yourself, and it will be4done!5 6The list is sorted by surname and formatted to allow easy grepping and7beautification by scripts. The fields are: name (N), email (E), web-address8(W), PGP key ID and fingerprint (P), and description (D).9 10N: Vikram Adve11E: vadve@cs.uiuc.edu12W: http://www.cs.uiuc.edu/~vadve/13D: The Sparc64 backend, provider of much wisdom, and motivator for LLVM14 15N: Owen Anderson16E: resistor@mac.com17D: LCSSA pass and related LoopUnswitch work18D: GVNPRE pass, DataLayout refactoring, random improvements19 20N: Henrik Bach21D: MingW Win32 API portability layer22 23N: Aaron Ballman24E: aaron@aaronballman.com25D: Clang frontend, frontend attributes, Windows support, general bug fixing26 27N: Alexey Bataev28E: a.bataev@outlook.com29D: Clang frontend, OpenMP in clang, SLP vectorizer, Loop vectorizer, InstCombine30 31N: Nate Begeman32E: natebegeman@mac.com33D: PowerPC backend developer34D: Target-independent code generator and analysis improvements35 36N: Daniel Berlin37E: dberlin@dberlin.org38D: ET-Forest implementation.39D: Sparse bitmap40 41N: Geoff Berry42E: gberry@codeaurora.org43E: gcb@acm.org44D: AArch64 backend improvements45D: Added EarlyCSE MemorySSA support46D: CodeGen improvements47 48N: David Blaikie49E: dblaikie@gmail.com50D: General bug fixing/fit & finish, mostly in Clang51 52N: Neil Booth53E: neil@daikokuya.co.uk54D: APFloat implementation.55 56N: Alex Bradbury57E: asb@igalia.com58D: RISC-V backend59 60N: Misha Brukman61E: brukman+llvm@uiuc.edu62W: http://misha.brukman.net63D: Portions of X86 and Sparc JIT compilers, PowerPC backend64D: Incremental bitcode loader65 66N: Cameron Buschardt67E: buschard@uiuc.edu68D: The `mem2reg' pass - promotes values stored in memory to registers69 70N: Brendon Cahoon71E: bcahoon@codeaurora.org72D: Loop unrolling with run-time trip counts.73 74N: Chandler Carruth75E: chandlerc@gmail.com76E: chandlerc@google.com77D: Hashing algorithms and interfaces78D: Inline cost analysis79D: Machine block placement pass80D: SROA81 82N: Casey Carter83E: ccarter@uiuc.edu84D: Fixes to the Reassociation pass, various improvement patches85 86N: Evan Cheng87E: evan.cheng@apple.com88D: ARM and X86 backends89D: Instruction scheduler improvements90D: Register allocator improvements91D: Loop optimizer improvements92D: Target-independent code generator improvements93 94N: Dan Villiom Podlaski Christiansen95E: danchr@gmail.com96E: danchr@cs.au.dk97W: http://villiom.dk98D: LLVM Makefile improvements99D: Clang diagnostic & driver tweaks100S: Aarhus, Denmark101 102N: Jeff Cohen103E: jeffc@jolt-lang.org104W: http://jolt-lang.org105D: Native Win32 API portability layer106 107N: John T. Criswell108E: criswell@uiuc.edu109D: Original Autoconf support, documentation improvements, bug fixes110 111N: Anshuman Dasgupta112E: adasgupt@codeaurora.org113D: Deterministic finite automaton based infrastructure for VLIW packetization114 115N: Stefanus Du Toit116E: stefanus.du.toit@intel.com117D: Bug fixes and minor improvements118 119N: Rafael Avila de Espindola120E: rafael@espindo.la121D: MC and LLD work122 123N: Dave Estes124E: cestes@codeaurora.org125D: AArch64 machine description for Cortex-A53126 127N: Alkis Evlogimenos128E: alkis@evlogimenos.com129D: Linear scan register allocator, many codegen improvements, Java frontend130 131N: Hal Finkel132E: hfinkel@anl.gov133D: Basic-block autovectorization, PowerPC backend improvements134 135N: Eric Fiselier136E: eric@efcs.ca137D: LIT patches and documentation138 139N: Ryan Flynn140E: pizza@parseerror.com141D: Miscellaneous bug fixes142 143N: Brian Gaeke144E: gaeke@uiuc.edu145W: http://www.students.uiuc.edu/~gaeke/146D: Portions of X86 static and JIT compilers; initial SparcV8 backend147D: Dynamic trace optimizer148D: FreeBSD/X86 compatibility fixes, the llvm-nm tool149 150N: Nicolas Geoffray151E: nicolas.geoffray@lip6.fr152W: http://www-src.lip6.fr/homepages/Nicolas.Geoffray/153D: PPC backend fixes for Linux154 155N: Louis Gerbarg156E: lgg@apple.com157D: Portions of the PowerPC backend158 159N: Saem Ghani160E: saemghani@gmail.com161D: Callgraph class cleanups162 163N: Mikhail Glushenkov164E: foldr@codedgers.com165D: Author of llvmc2166 167N: Dan Gohman168E: llvm@sunfishcode.online169D: Miscellaneous bug fixes170D: WebAssembly Backend171 172N: Renato Golin173E: rengolin@systemcall.eu174E: rengolin@gmail.com175D: ARM/AArch64 back-end improvements176D: Loop Vectorizer improvements177D: Regression and Test Suite improvements178D: Linux compatibility (GNU, musl, etc)179D: Initial Linux kernel / Android support effort180 181N: David Goodwin182E: david@goodwinz.net183D: Thumb-2 code generator184 185N: David Greene186E: greened@obbligato.org187D: Miscellaneous bug fixes188D: Register allocation refactoring189 190N: Gabor Greif191E: ggreif@gmail.com192D: Improvements for space efficiency193 194N: James Grosbach195E: grosbach@apple.com196D: SjLj exception handling support197D: General fixes and improvements for the ARM back-end198D: MCJIT199D: ARM integrated assembler and assembly parser200D: Led effort for the backend formerly known as ARM64201 202N: Lang Hames203E: lhames@gmail.com204D: PBQP-based register allocator205 206N: Gordon Henriksen207E: gordonhenriksen@mac.com208D: Pluggable GC support209D: C interface210D: Ocaml bindings211 212N: Raul Fernandes Herbster213E: raul@dsc.ufcg.edu.br214D: JIT support for ARM215 216N: Paolo Invernizzi217E: arathorn@fastwebnet.it218D: Visual C++ compatibility fixes219 220N: Patrick Jenkins221E: patjenk@wam.umd.edu222D: Nightly Tester223 224N: Tony(Yanjun) Jiang225E: jtony@ca.ibm.com226D: PowerPC Backend Developer227D: Improvements to the PPC backend and miscellaneous bug fixes228 229N: Dale Johannesen230E: dalej@apple.com231D: ARM constant islands improvements232D: Tail merging improvements233D: Rewrite X87 back end234D: Use APFloat for floating point constants widely throughout compiler235D: Implement X87 long double236 237N: Brad Jones238E: kungfoomaster@nondot.org239D: Support for packed types240 241N: Rod Kay242E: rkay@auroraux.org243D: Author of LLVM Ada bindings244 245N: Erich Keane246E: erich.keane@intel.com247D: A variety of Clang contributions including function multiversioning, regcall/vectorcall.248 249N: Eric Kidd250W: http://randomhacks.net/251D: llvm-config script252 253N: Anton Korobeynikov254E: anton at korobeynikov dot info255D: Mingw32 fixes, cross-compiling support, stdcall/fastcall calling conv.256D: x86/linux PIC codegen, aliases, regparm/visibility attributes257D: Switch lowering refactoring258 259N: Sumant Kowshik260E: kowshik@uiuc.edu261D: Author of the original C backend262 263N: Benjamin Kramer264E: benny.kra@gmail.com265D: Miscellaneous bug fixes266 267N: Michael Kuperstein268E: mkuper@google.com269D: Loop Vectorizer270 271N: Sundeep Kushwaha272E: sundeepk@codeaurora.org273D: Implemented DFA-based target independent VLIW packetizer274 275N: Christopher Lamb276E: christopher.lamb@gmail.com277D: aligned load/store support, parts of noalias and restrict support278D: vreg subreg infrastructure, X86 codegen improvements based on subregs279D: address spaces280 281N: Jim Laskey282E: jlaskey@apple.com283D: Improvements to the PPC backend, instruction scheduling284D: Debug and Dwarf implementation285D: Auto upgrade mangler286D: llvm-gcc4 svn wrangler287 288N: Chris Lattner289E: sabre@nondot.org290W: http://nondot.org/~sabre/291D: Primary architect of LLVM292 293N: Tanya Lattner (Tanya Brethour)294E: tonic@nondot.org295W: http://nondot.org/~tonic/296D: The initial llvm-ar tool, converted regression testsuite to dejagnu297D: Modulo scheduling in the SparcV9 backend298D: Release manager (1.7+)299 300N: Sylvestre Ledru301E: sylvestre@debian.org302W: http://sylvestre.ledru.info/303W: https://apt.llvm.org/304D: Debian and Ubuntu packaging305D: Continuous integration with jenkins306 307N: Andrew Lenharth308E: alenhar2@cs.uiuc.edu309W: http://www.lenharth.org/~andrewl/310D: Alpha backend311D: Sampling based profiling312 313N: Nick Lewycky314E: nicholas@mxc.ca315D: PredicateSimplifier pass316 317N: Tony Linthicum, et. al.318E: tlinth@codeaurora.org319D: Backend for Qualcomm's Hexagon VLIW processor.320 321N: Bruno Cardoso Lopes322E: bruno.cardoso@gmail.com323W: http://brunocardoso.cc324D: Mips backend325D: Random ARM integrated assembler and assembly parser improvements326D: General X86 AVX1 support327 328N: Weining Lu329E: luweining@loongson.cn330D: LoongArch backend331 332N: Duraid Madina333E: duraid@octopus.com.au334W: http://kinoko.c.u-tokyo.ac.jp/~duraid/335D: IA64 backend, BigBlock register allocator336 337N: John McCall338E: rjmccall@apple.com339D: Clang semantic analysis and IR generation340 341N: Michael McCracken342E: michael.mccracken@gmail.com343D: Line number support for llvmgcc344 345N: Fanbo Meng346E: fanbo.meng@ibm.com347D: z/OS support348 349N: Vladimir Merzliakov350E: wanderer@rsu.ru351D: Test suite fixes for FreeBSD352 353N: Scott Michel354E: scottm@aero.org355D: Added STI Cell SPU backend.356 357N: Kai Nacke358E: kai@redstar.de359D: Support for implicit TLS model used with MS VC runtime360D: Dumping of Win64 EH structures361 362N: Takumi Nakamura363E: geek4civic@gmail.com364E: chapuni@hf.rim.or.jp365D: Maintaining the Git monorepo366W: https://github.com/llvm-project/367S: Ebina, Japan368 369N: Edward O'Callaghan370E: eocallaghan@auroraux.org371W: http://www.auroraux.org372D: Add Clang support with various other improvements to utils/NewNightlyTest.pl373D: Fix and maintain Solaris & AuroraUX support for llvm, various build warnings374D: and error clean ups.375 376N: Morten Ofstad377E: morten@hue.no378D: Visual C++ compatibility fixes379 380N: Jakob Stoklund Olesen381E: stoklund@2pi.dk382D: Machine code verifier383D: Blackfin backend384D: Fast register allocator385D: Greedy register allocator386 387N: Richard Osborne388E: richard@xmos.com389D: XCore backend390 391N: Piotr Padlewski392E: piotr.padlewski@gmail.com393D: !invariant.group metadata and other intrinsics for devirtualization in clang394 395N: Devang Patel396E: dpatel@apple.com397D: LTO tool, PassManager rewrite, Loop Pass Manager, Loop Rotate398D: GCC PCH Integration (llvm-gcc), llvm-gcc improvements399D: Optimizer improvements, Loop Index Split400 401N: Ana Pazos402E: apazos@codeaurora.org403D: Fixes and improvements to the AArch64 backend404 405N: Wesley Peck406E: peckw@wesleypeck.com407W: http://wesleypeck.com/408D: MicroBlaze backend409 410N: Francois Pichet411E: pichet2000@gmail.com412D: MSVC support413 414N: Simon Pilgrim415E: llvm-dev@redking.me.uk416D: X86 backend, Selection DAG, Scheduler Models and Cost Tables.417 418N: Adrian Prantl419E: aprantl@apple.com420D: Debug Information421 422N: Vladimir Prus423W: http://vladimir_prus.blogspot.com424E: ghost@cs.msu.su425D: Made inst_iterator behave like a proper iterator, LowerConstantExprs pass426 427N: Kalle Raiskila428E: kalle.rasikila@nokia.com429D: Some bugfixes to CellSPU430 431N: Xerxes Ranby432E: xerxes@zafena.se433D: Cmake dependency chain and various bug fixes434 435N: Alex Rosenberg436E: alexr@leftfield.org437D: ARM calling conventions rewrite, hard float support438 439N: Chad Rosier440E: mcrosier@codeaurora.org441D: AArch64 fast instruction selection pass442D: Fixes and improvements to the ARM fast-isel pass443D: Fixes and improvements to the AArch64 backend444 445N: Nadav Rotem446E: nadav.rotem@me.com447D: X86 code generation improvements, Loop Vectorizer, SLP Vectorizer448 449N: Roman Samoilov450E: roman@codedgers.com451D: MSIL backend452 453N: Duncan Sands454E: baldrick@free.fr455D: Ada support in llvm-gcc456D: Dragonegg plugin457D: Exception handling improvements458D: Type legalizer rewrite459 460N: Ruchira Sasanka461E: sasanka@uiuc.edu462D: Graph coloring register allocator for the Sparc64 backend463 464N: Alina Sbirlea465E: alina.sbirlea@gmail.com466D: MemorySSA, BatchAA, misc loop and new pass manager work.467 468N: Arnold Schwaighofer469E: arnold.schwaighofer@gmail.com470D: Tail call optimization for the x86 backend471 472N: Shantonu Sen473E: ssen@apple.com474D: Miscellaneous bug fixes475 476N: Anand Shukla477E: ashukla@cs.uiuc.edu478D: The `paths' pass479 480N: Michael J. Spencer481E: bigcheesegs@gmail.com482D: Shepherding Windows COFF support into MC.483D: Lots of Windows stuff.484 485N: Reid Spencer486E: rspencer@reidspencer.com487W: http://reidspencer.com/488D: Lots of stuff, see: http://wiki.llvm.org/index.php/User:Reid489 490N: Abhina Sreeskantharajan491E: Abhina.Sreeskantharajan@ibm.com492D: z/OS support493 494N: Alp Toker495E: alp@nuanti.com496W: http://atoker.com/497D: C++ frontend next generation standards implementation498 499N: Craig Topper500E: craig.topper@gmail.com501D: X86 codegen and disassembler improvements. AVX2 support.502 503N: Edwin Torok504E: edwintorok@gmail.com505D: Miscellaneous bug fixes506 507N: Adam Treat508E: manyoso@yahoo.com509D: C++ bugs filed, and C++ front-end bug fixes.510 511N: Andrew Trick512E: atrick@apple.com513D: Instruction Scheduling, ...514 515N: Lauro Ramos Venancio516E: lauro.venancio@indt.org.br517D: ARM backend improvements518D: Thread Local Storage implementation519 520N: Phoebe Wang521E: phoebe.wang@intel.com522D: X86 bug fixes and new instruction support.523 524N: Bill Wendling525E: isanbard@gmail.com526D: Release manager, IR Linker, LTO.527D: Bunches of stuff.528 529N: Bob Wilson530E: bob.wilson@acm.org531D: Advanced SIMD (NEON) support in the ARM backend.532 533N: QingShan Zhang534N: steven.zhang535E: zhangqingshan.zll@bytedance.com536 537N: Li Jia He538E: hljhehlj@cn.ibm.com539D: PowerPC Backend Developer540 541N: Zi Xuan Wu542N: Zeson543E: zixuan.wu@linux.alibaba.com544 545N: Kang Zhang546E: shkzhang@cn.ibm.com547D: PowerPC Backend Developer548 549N: Zheng Chen550E: czhengsz@cn.ibm.com551D: PowerPC Backend Developer552 553N: Djordje Todorovic554E: djordje.todorovic@rt-rk.com555D: Debug Information556 557N: Biplob Mishra558E: biplmish@in.ibm.com559D: PowerPC Analysis560