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1..2 **************************************************3 * *4 * Automatically generated file, do not edit! *5 * *6 **************************************************7 8.. _amdgpu_synid_gfx10_hwreg:9 10hwreg11=====12 13Bits of a hardware register being accessed.14 15The bits of this operand have the following meaning:16 17 ======= ===================== ============18 Bits Description Value Range19 ======= ===================== ============20 5:0 Register *id*. 0..6321 10:6 First bit *offset*. 0..3122 15:11 *Size* in bits. 1..3223 ======= ===================== ============24 25This operand may be specified as one of the following:26 27* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from 0 to 0xFFFF.28* An *hwreg* value which is described below.29 30 ==================================== ===============================================================================31 Hwreg Value Syntax Description32 ==================================== ===============================================================================33 hwreg({0..63}) All bits of a register indicated by the register *id*.34 hwreg(<*name*>) All bits of a register indicated by the register *name*.35 hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by the register *id*, first bit *offset* and *size*.36 hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by the register *name*, first bit *offset* and *size*.37 ==================================== ===============================================================================38 39Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`40or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.41 42Predefined register *names* include:43 44 ============================== ==========================================45 Name Description46 ============================== ==========================================47 HW_REG_MODE Shader writable mode bits.48 HW_REG_STATUS Shader read-only status.49 HW_REG_TRAPSTS Trap status.50 HW_REG_HW_ID1 Id of wave, simd, compute unit, etc.51 HW_REG_HW_ID2 Id of queue, pipeline, etc.52 HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.53 HW_REG_LDS_ALLOC Per-wave LDS allocation.54 HW_REG_IB_STS Counters of outstanding instructions.55 HW_REG_SH_MEM_BASES Memory aperture.56 HW_REG_TBA_LO tba_lo register.57 HW_REG_TBA_HI tba_hi register.58 HW_REG_TMA_LO tma_lo register.59 HW_REG_TMA_HI tma_hi register.60 HW_REG_FLAT_SCR_LO flat_scratch_lo register.61 HW_REG_FLAT_SCR_HI flat_scratch_hi register.62 HW_REG_XNACK_MASK xnack_mask register.63 HW_REG_POPS_PACKER pops_packer register.64 ============================== ==========================================65 66Examples:67 68.. parsed-literal::69 70 reg = 171 offset = 272 size = 473 hwreg_enc = reg | (offset << 6) | ((size - 1) << 11)74 75 s_getreg_b32 s2, 0x188176 s_getreg_b32 s2, hwreg_enc // the same as above77 s_getreg_b32 s2, hwreg(1, 2, 4) // the same as above78 s_getreg_b32 s2, hwreg(reg, offset, size) // the same as above79 80 s_getreg_b32 s2, hwreg(15)81 s_getreg_b32 s2, hwreg(51, 1, 31)82 s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)83