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1..2 **************************************************3 * *4 * Automatically generated file, do not edit! *5 * *6 **************************************************7 8.. _amdgpu_synid_gfx11_delay:9 10delay11=====12 13A delay between dependent SALU/VALU instructions.14This operand may specify a delay for 2 instructions:15the one after the current *s_delay_alu* instruction16and for the second instruction indicated by *SKIP*.17 18The bits of this operand have the following meaning:19 20 ===== ========================================================== ============21 Bits Description Value Range22 ===== ========================================================== ============23 3:0 ID0: indicates a delay for the first instruction. 0..1124 6:4 SKIP: indicates the position of the second instruction. 0..525 10:7 ID1: indicates a delay for the second instruction. 0..1126 ===== ========================================================== ============27 28This operand may be specified as one of the following:29 30* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from 0 to 0xFFFF.31* A combination of *instid0*, *instskip*, *instid1* values which are described below.32 33 ======================== =========================== ===============34 Syntax Description Default Value35 ======================== =========================== ===============36 instid0(<*ID name*>) A symbolic *ID0* value. instid0(NO_DEP)37 instskip(<*SKIP name*>) A symbolic *SKIP* value. instskip(SAME)38 instid1(<*ID name*>) A symbolic *ID1* value. instid1(NO_DEP)39 ======================== =========================== ===============40 41These values may be specified in any order.42When more than one value is specified, the values must be separated from each other by a '|'.43 44Valid *ID names* are defined below.45 46 =================== ===================================================================47 Name Description48 =================== ===================================================================49 NO_DEP No dependency on any prior instruction. This is the default value.50 VALU_DEP_1 Dependency on a previous VALU instruction, 1 opcode back.51 VALU_DEP_2 Dependency on a previous VALU instruction, 2 opcodes back.52 VALU_DEP_3 Dependency on a previous VALU instruction, 3 opcodes back.53 VALU_DEP_4 Dependency on a previous VALU instruction, 4 opcodes back.54 TRANS32_DEP_1 Dependency on a previous TRANS32 instruction, 1 opcode back.55 TRANS32_DEP_2 Dependency on a previous TRANS32 instruction, 2 opcodes back.56 TRANS32_DEP_3 Dependency on a previous TRANS32 instruction, 3 opcodes back.57 FMA_ACCUM_CYCLE_1 Single cycle penalty for FMA accumulation.58 SALU_CYCLE_1 1 cycle penalty for a prior SALU instruction.59 SALU_CYCLE_2 2 cycle penalty for a prior SALU instruction.60 SALU_CYCLE_3 3 cycle penalty for a prior SALU instruction.61 =================== ===================================================================62 63Legal *SKIP names* are described in the following table.64 65 ======== ============================================================================66 Name Description67 ======== ============================================================================68 SAME Apply second dependency to the same instruction. This is the default value.69 NEXT Apply second dependency to the next instruction.70 SKIP_1 Skip 1 instruction then apply dependency.71 SKIP_2 Skip 2 instructions then apply dependency.72 SKIP_3 Skip 3 instructions then apply dependency.73 SKIP_4 Skip 4 instructions then apply dependency.74 ======== ============================================================================75 76Examples:77 78.. parsed-literal::79 80 s_delay_alu instid0(VALU_DEP_1)81 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)82