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1.. _amdgpu_synid_delay:2 3delay4=====5 6A delay between dependent SALU/VALU instructions.7This operand may specify a delay for 2 instructions:8the one after the current *s_delay_alu* instruction9and for the second instruction indicated by *SKIP*.10 11The bits of this operand have the following meaning:12 13 ===== ========================================================== ============14 Bits Description Value Range15 ===== ========================================================== ============16 3:0 ID0: indicates a delay for the first instruction. 0..1117 6:4 SKIP: indicates the position of the second instruction. 0..518 10:7 ID1: indicates a delay for the second instruction. 0..1119 ===== ========================================================== ============20 21This operand may be specified as one of the following:22 23* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.24* A combination of *instid0*, *instskip*, *instid1* values described below.25 26 ======================== =========================== ===============27 Syntax Description Default Value28 ======================== =========================== ===============29 instid0(<*ID name*>) A symbolic *ID0* value. instid0(NO_DEP)30 instskip(<*SKIP name*>) A symbolic *SKIP* value. instskip(SAME)31 instid1(<*ID name*>) A symbolic *ID1* value. instid1(NO_DEP)32 ======================== =========================== ===============33 34These values may be specified in any order.35When more than one value is specified, the values must be separated from each other by a '|'.36 37Valid *ID names* are defined below.38 39 =================== ===================================================================40 Name Description41 =================== ===================================================================42 NO_DEP No dependency on any prior instruction. This is the default value.43 VALU_DEP_1 Dependency on a previous VALU instruction, 1 opcode back.44 VALU_DEP_2 Dependency on a previous VALU instruction, 2 opcodes back.45 VALU_DEP_3 Dependency on a previous VALU instruction, 3 opcodes back.46 VALU_DEP_4 Dependency on a previous VALU instruction, 4 opcodes back.47 TRANS32_DEP_1 Dependency on a previous TRANS32 instruction, 1 opcode back.48 TRANS32_DEP_2 Dependency on a previous TRANS32 instruction, 2 opcodes back.49 TRANS32_DEP_3 Dependency on a previous TRANS32 instruction, 3 opcodes back.50 FMA_ACCUM_CYCLE_1 Single cycle penalty for FMA accumulation.51 SALU_CYCLE_1 1 cycle penalty for a prior SALU instruction.52 SALU_CYCLE_2 2 cycle penalty for a prior SALU instruction.53 SALU_CYCLE_3 3 cycle penalty for a prior SALU instruction.54 =================== ===================================================================55 56Legal *SKIP names* are described in the following table.57 58 ======== ============================================================================59 Name Description60 ======== ============================================================================61 SAME Apply second dependency to the same instruction. This is the default value.62 NEXT Apply second dependency to the next instruction.63 SKIP_1 Skip 1 instruction then apply dependency.64 SKIP_2 Skip 2 instructions then apply dependency.65 SKIP_3 Skip 3 instructions then apply dependency.66 SKIP_4 Skip 4 instructions then apply dependency.67 ======== ============================================================================68 69Examples:70 71.. parsed-literal::72 73 s_delay_alu instid0(VALU_DEP_1)74 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)75