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1======================================2Syntax of AMDGPU Instruction Modifiers3======================================4 5.. contents::6 :local:7 8Conventions9===========10 11The following notation is used throughout this document:12 13 =================== =============================================================14 Notation Description15 =================== =============================================================16 {0..N} Any integer value in the range from 0 to N (inclusive).17 <x> Syntax and meaning of *x* are explained elsewhere.18 =================== =============================================================19 20.. _amdgpu_syn_modifiers:21 22Modifiers23=========24 25DS Modifiers26------------27 28.. _amdgpu_synid_ds_offset80:29 30offset031~~~~~~~32 33Specifies the first 8-bit offset, in bytes. The default value is 0.34 35Used with DS instructions that expect two addresses.36 37 =================== ====================================================================38 Syntax Description39 =================== ====================================================================40 offset0:{0..0xFF} Specifies an unsigned 8-bit offset as a positive41 :ref:`integer number <amdgpu_synid_integer_number>`42 or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.43 =================== ====================================================================44 45Examples:46 47.. parsed-literal::48 49 offset0:0xff50 offset0:2-x51 offset0:-x-y52 53.. _amdgpu_synid_ds_offset81:54 55offset156~~~~~~~57 58Specifies the second 8-bit offset, in bytes. The default value is 0.59 60Used with DS instructions that expect two addresses.61 62 =================== ====================================================================63 Syntax Description64 =================== ====================================================================65 offset1:{0..0xFF} Specifies an unsigned 8-bit offset as a positive66 :ref:`integer number <amdgpu_synid_integer_number>`67 or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.68 =================== ====================================================================69 70Examples:71 72.. parsed-literal::73 74 offset1:0xff75 offset1:2-x76 offset1:-x-y77 78.. _amdgpu_synid_ds_offset16:79 80offset81~~~~~~82 83Specifies a 16-bit offset, in bytes. The default value is 0.84 85Used with DS instructions that expect a single address.86 87 ==================== ====================================================================88 Syntax Description89 ==================== ====================================================================90 offset:{0..0xFFFF} Specifies an unsigned 16-bit offset as a positive91 :ref:`integer number <amdgpu_synid_integer_number>`92 or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.93 ==================== ====================================================================94 95Examples:96 97.. parsed-literal::98 99 offset:65535100 offset:0xffff101 offset:-x-y102 103.. _amdgpu_synid_sw_offset16:104 105swizzle pattern106~~~~~~~~~~~~~~~107 108This is a special modifier that may be used with *ds_swizzle_b32* instruction only.109It specifies a swizzle pattern in numeric or symbolic form. The default value is 0.110 111 ======================================================= ===========================================================112 Syntax Description113 ======================================================= ===========================================================114 offset:{0..0xFFFF} Specifies a 16-bit swizzle pattern.115 offset:swizzle(QUAD_PERM,{0..3},{0..3},{0..3},{0..3}) Specifies a quad permute mode pattern116 117 Each number is a lane *id*.118 offset:swizzle(BITMASK_PERM, "<mask>") Specifies a bitmask permute mode pattern.119 120 The pattern converts a 5-bit lane *id* to another121 lane *id* with which the lane interacts.122 123 The *mask* is a 5-character sequence which124 specifies how to transform the bits of the125 lane *id*.126 127 The following characters are allowed:128 129 * "0" - set bit to 0.130 131 * "1" - set bit to 1.132 133 * "p" - preserve bit.134 135 * "i" - inverse bit.136 137 offset:swizzle(BROADCAST,{2..32},{0..N}) Specifies a broadcast mode.138 139 Broadcasts the value of any particular lane to140 all lanes in its group.141 142 The first numeric parameter is a group143 size and must be equal to 2, 4, 8, 16 or 32.144 145 The second numeric parameter is an index of the146 lane being broadcast.147 148 The index must not exceed group size.149 offset:swizzle(SWAP,{1..16}) Specifies a swap mode.150 151 Swaps the neighboring groups of152 1, 2, 4, 8 or 16 lanes.153 offset:swizzle(REVERSE,{2..32}) Specifies a reverse mode.154 155 Reverses the lanes for groups of 2, 4, 8, 16 or 32 lanes.156 ======================================================= ===========================================================157 158Note: numeric values may be specified as either159:ref:`integer numbers<amdgpu_synid_integer_number>` or160:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.161 162Examples:163 164.. parsed-literal::165 166 offset:255167 offset:0xffff168 offset:swizzle(QUAD_PERM, 0, 1, 2, 3)169 offset:swizzle(BITMASK_PERM, "01pi0")170 offset:swizzle(BROADCAST, 2, 0)171 offset:swizzle(SWAP, 8)172 offset:swizzle(REVERSE, 30 + 2)173 174.. _amdgpu_synid_gds:175 176gds177~~~178 179Specifies whether to use GDS or LDS memory (LDS is the default).180 181 ======================================== ================================================182 Syntax Description183 ======================================== ================================================184 gds Use GDS memory.185 ======================================== ================================================186 187 188EXP Modifiers189-------------190 191.. _amdgpu_synid_done:192 193done194~~~~195 196Specifies if this is the last export from the shader to the target. By default,197an *export* instruction does not finish an export sequence.198 199 ======================================== ================================================200 Syntax Description201 ======================================== ================================================202 done Indicates the last export operation.203 ======================================== ================================================204 205.. _amdgpu_synid_compr:206 207compr208~~~~~209 210Indicates if the data is compressed (data is not compressed by default).211 212 ======================================== ================================================213 Syntax Description214 ======================================== ================================================215 compr Data is compressed.216 ======================================== ================================================217 218.. _amdgpu_synid_vm:219 220vm221~~222 223Specifies if the :ref:`exec<amdgpu_synid_exec>` mask is valid for this *export* instruction224(the mask is not valid by default).225 226 ======================================== ================================================227 Syntax Description228 ======================================== ================================================229 vm Set the flag indicating a valid230 :ref:`exec<amdgpu_synid_exec>` mask.231 ======================================== ================================================232 233.. _amdgpu_synid_row_en:234 235row_en236~~~~~~237 238Specifies whether to export one row or multiple rows of data.239 240 ======================================== ================================================241 Syntax Description242 ======================================== ================================================243 row_en Export multiple rows using row index from M0.244 ======================================== ================================================245 246FLAT Modifiers247--------------248 249.. _amdgpu_synid_flat_offset12:250 251offset12252~~~~~~~~253 254Specifies an immediate unsigned 12-bit offset, in bytes. The default value is 0.255 256 ================= ====================================================================257 Syntax Description258 ================= ====================================================================259 offset:{0..4095} Specifies a 12-bit unsigned offset as a positive260 :ref:`integer number <amdgpu_synid_integer_number>`261 or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.262 ================= ====================================================================263 264Examples:265 266.. parsed-literal::267 268 offset:4095269 offset:x-0xff270 271.. _amdgpu_synid_flat_offset13s:272 273offset13s274~~~~~~~~~275 276Specifies an immediate signed 13-bit offset, in bytes. The default value is 0.277 278 ===================== ====================================================================279 Syntax Description280 ===================== ====================================================================281 offset:{-4096..4095} Specifies a 13-bit signed offset as an282 :ref:`integer number <amdgpu_synid_integer_number>`283 or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.284 ===================== ====================================================================285 286Examples:287 288.. parsed-literal::289 290 offset:-4000291 offset:0x10292 offset:-x293 294.. _amdgpu_synid_flat_offset12s:295 296offset12s297~~~~~~~~~298 299Specifies an immediate signed 12-bit offset, in bytes. The default value is 0.300 301 ===================== ====================================================================302 Syntax Description303 ===================== ====================================================================304 offset:{-2048..2047} Specifies a 12-bit signed offset as an305 :ref:`integer number <amdgpu_synid_integer_number>`306 or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.307 ===================== ====================================================================308 309Examples:310 311.. parsed-literal::312 313 offset:-2000314 offset:0x10315 offset:-x+y316 317.. _amdgpu_synid_flat_offset11:318 319offset11320~~~~~~~~321 322Specifies an immediate unsigned 11-bit offset, in bytes. The default value is 0.323 324 ================= ====================================================================325 Syntax Description326 ================= ====================================================================327 offset:{0..2047} Specifies an 11-bit unsigned offset as a positive328 :ref:`integer number <amdgpu_synid_integer_number>`329 or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.330 ================= ====================================================================331 332Examples:333 334.. parsed-literal::335 336 offset:2047337 offset:x+0xff338 339dlc340~~~341 342See a description :ref:`here<amdgpu_synid_dlc>`.343 344glc345~~~346 347See a description :ref:`here<amdgpu_synid_glc>`.348 349lds350~~~351 352See a description :ref:`here<amdgpu_synid_lds>`.353 354slc355~~~356 357See a description :ref:`here<amdgpu_synid_slc>`.358 359tfe360~~~361 362See a description :ref:`here<amdgpu_synid_tfe>`.363 364nv365~~366 367See a description :ref:`here<amdgpu_synid_nv>`.368 369sc0370~~~371 372See a description :ref:`here<amdgpu_synid_sc0>`.373 374sc1375~~~376 377See a description :ref:`here<amdgpu_synid_sc1>`.378 379nt380~~381 382See a description :ref:`here<amdgpu_synid_nt>`.383 384MIMG Modifiers385--------------386 387.. _amdgpu_synid_dmask:388 389dmask390~~~~~391 392Specifies which channels (image components) are used by the operation.393By default, no channels are used.394 395 =============== ====================================================================396 Syntax Description397 =============== ====================================================================398 dmask:{0..15} Specifies image channels as a positive399 :ref:`integer number <amdgpu_synid_integer_number>`400 or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.401 402 Each bit corresponds to one of 4 image components (RGBA).403 404 If the specified bit value is 0, the image component is not used,405 while value 1 means that the component is used.406 =============== ====================================================================407 408This modifier has some limitations depending on the instruction kind:409 410 =================================================== ========================411 Instruction Kind Valid dmask Values412 =================================================== ========================413 32-bit atomic *cmpswap* 0x3414 32-bit atomic instructions except for *cmpswap* 0x1415 64-bit atomic *cmpswap* 0xF416 64-bit atomic instructions except for *cmpswap* 0x3417 *gather4* 0x1, 0x2, 0x4, 0x8418 GFX11+ *msaa_load* 0x1, 0x2, 0x4, 0x8419 Other instructions any value420 =================================================== ========================421 422Examples:423 424.. parsed-literal::425 426 dmask:0xf427 dmask:0b1111428 dmask:x|y|z429 430.. _amdgpu_synid_unorm:431 432unorm433~~~~~434 435Specifies whether the address is normalized or not (the address is normalized by default).436 437 ======================== ========================================438 Syntax Description439 ======================== ========================================440 unorm Force the address to be not normalized.441 ======================== ========================================442 443glc444~~~445 446See a description :ref:`here<amdgpu_synid_glc>`.447 448slc449~~~450 451See a description :ref:`here<amdgpu_synid_slc>`.452 453.. _amdgpu_synid_r128:454 455r128456~~~~457 458Specifies texture resource size. The default size is 256 bits.459 460 =================== ================================================461 Syntax Description462 =================== ================================================463 r128 Specifies 128 bits texture resource size.464 =================== ================================================465 466.. WARNING:: Using this modifier shall decrease *rsrc* operand size from 8 to 4 dwords, \467 but assembler does not currently support this feature.468 469tfe470~~~471 472See a description :ref:`here<amdgpu_synid_tfe>`.473 474.. _amdgpu_synid_lwe:475 476lwe477~~~478 479Specifies LOD warning status (LOD warning is disabled by default).480 481 ======================================== ================================================482 Syntax Description483 ======================================== ================================================484 lwe Enables LOD warning.485 ======================================== ================================================486 487.. _amdgpu_synid_da:488 489da490~~491 492Specifies if an array index must be sent to TA. By default, the array index is not sent.493 494 ======================================== ================================================495 Syntax Description496 ======================================== ================================================497 da Send an array index to TA.498 ======================================== ================================================499 500.. _amdgpu_synid_d16:501 502d16503~~~504 505Specifies data size: 16 or 32 bits (32 bits by default).506 507 ======================================== ================================================508 Syntax Description509 ======================================== ================================================510 d16 Enables 16-bits data mode.511 512 On loads, convert data in memory to 16-bit513 format before storing it in VGPRs.514 515 For stores, convert 16-bit data in VGPRs to516 32 bits before writing the values to memory.517 518 Note that GFX8.0 does not support data packing.519 Each 16-bit data element occupies 1 VGPR.520 521 GFX8.1 and GFX9+ support data packing.522 Each pair of 16-bit data elements523 occupies 1 VGPR.524 ======================================== ================================================525 526.. _amdgpu_synid_a16:527 528a16529~~~530 531Specifies the size of image address components: 16 or 32 bits (32 bits by default).532 533 ======================================== ================================================534 Syntax Description535 ======================================== ================================================536 a16 Enables 16-bits image address components.537 ======================================== ================================================538 539.. _amdgpu_synid_dim:540 541dim542~~~543 544Specifies surface dimension. This is a mandatory modifier. There is no default value.545 546 =============================== =========================================================547 Syntax Description548 =============================== =========================================================549 dim:1D One-dimensional image.550 dim:2D Two-dimensional image.551 dim:3D Three-dimensional image.552 dim:CUBE Cubemap array.553 dim:1D_ARRAY One-dimensional image array.554 dim:2D_ARRAY Two-dimensional image array.555 dim:2D_MSAA Two-dimensional multi-sample auto-aliasing image.556 dim:2D_MSAA_ARRAY Two-dimensional multi-sample auto-aliasing image array.557 =============================== =========================================================558 559The following table defines an alternative syntax which is supported560for compatibility with SP3 assembler:561 562 =============================== =========================================================563 Syntax Description564 =============================== =========================================================565 dim:SQ_RSRC_IMG_1D One-dimensional image.566 dim:SQ_RSRC_IMG_2D Two-dimensional image.567 dim:SQ_RSRC_IMG_3D Three-dimensional image.568 dim:SQ_RSRC_IMG_CUBE Cubemap array.569 dim:SQ_RSRC_IMG_1D_ARRAY One-dimensional image array.570 dim:SQ_RSRC_IMG_2D_ARRAY Two-dimensional image array.571 dim:SQ_RSRC_IMG_2D_MSAA Two-dimensional multi-sample auto-aliasing image.572 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY Two-dimensional multi-sample auto-aliasing image array.573 =============================== =========================================================574 575dlc576~~~577 578See a description :ref:`here<amdgpu_synid_dlc>`.579 580Miscellaneous Modifiers581-----------------------582 583.. _amdgpu_synid_dlc:584 585dlc586~~~587 588Controls device level cache policy for memory operations. Used for synchronization.589When specified, forces operation to bypass device level cache, making the operation device590level coherent. By default, instructions use device level cache.591 592 ======================================== ================================================593 Syntax Description594 ======================================== ================================================595 dlc Bypass device level cache.596 ======================================== ================================================597 598.. _amdgpu_synid_glc:599 600glc601~~~602 603For atomic opcodes, this modifier indicates that the instruction returns the value from memory604before the operation. For other opcodes, it is used together with :ref:`slc<amdgpu_synid_slc>`605to specify cache policy.606 607The default value is off (0).608 609 ======================================== ================================================610 Syntax Description611 ======================================== ================================================612 glc Set glc bit to 1.613 ======================================== ================================================614 615.. _amdgpu_synid_lds:616 617lds618~~~619 620Specifies where to store the result: VGPRs or LDS (VGPRs by default).621 622 ======================================== ===========================623 Syntax Description624 ======================================== ===========================625 lds Store the result in LDS.626 ======================================== ===========================627 628.. _amdgpu_synid_nv:629 630nv631~~632 633Specifies if the instruction is operating on non-volatile memory.634By default, memory is volatile.635 636 ======================================== ================================================637 Syntax Description638 ======================================== ================================================639 nv Indicates that the instruction operates on640 non-volatile memory.641 ======================================== ================================================642 643.. _amdgpu_synid_slc:644 645slc646~~~647 648Controls behavior of L2 cache. The default value is off (0).649 650 ======================================== ================================================651 Syntax Description652 ======================================== ================================================653 slc Set slc bit to 1.654 ======================================== ================================================655 656.. _amdgpu_synid_tfe:657 658tfe659~~~660 661Controls access to partially resident textures. The default value is off (0).662 663 ======================================== ================================================664 Syntax Description665 ======================================== ================================================666 tfe Set tfe bit to 1.667 ======================================== ================================================668 669.. _amdgpu_synid_sc0:670 671sc0672~~~673 674For atomic opcodes, this modifier indicates that the instruction returns the value from memory675before the operation. For other opcodes, it is used together with :ref:`sc1<amdgpu_synid_sc1>`676to specify cache policy.677 678 ======================================== ================================================679 Syntax Description680 ======================================== ================================================681 sc0 Set sc0 bit to 1.682 ======================================== ================================================683 684.. _amdgpu_synid_sc1:685 686sc1687~~~688 689This modifier is used together with :ref:`sc0<amdgpu_synid_sc0>` to specify cache690policy.691 692 ======================================== ================================================693 Syntax Description694 ======================================== ================================================695 sc1 Set sc1 bit to 1.696 ======================================== ================================================697 698.. _amdgpu_synid_nt:699 700nt701~~702 703Indicates an operation with non-temporal data.704 705 ======================================== ================================================706 Syntax Description707 ======================================== ================================================708 nt Set nt bit to 1.709 ======================================== ================================================710 711MUBUF/MTBUF Modifiers712---------------------713 714.. _amdgpu_synid_idxen:715 716idxen717~~~~~718 719Specifies whether address components include an index. By default, the index is not used.720 721May be used together with :ref:`offen<amdgpu_synid_offen>`.722 723Cannot be used with :ref:`addr64<amdgpu_synid_addr64>`.724 725 ======================================== ================================================726 Syntax Description727 ======================================== ================================================728 idxen Address components include an index.729 ======================================== ================================================730 731.. _amdgpu_synid_offen:732 733offen734~~~~~735 736Specifies whether address components include an offset. By default, the offset is not used.737 738May be used together with :ref:`idxen<amdgpu_synid_idxen>`.739 740Cannot be used with :ref:`addr64<amdgpu_synid_addr64>`.741 742 ======================================== ================================================743 Syntax Description744 ======================================== ================================================745 offen Address components include an offset.746 ======================================== ================================================747 748.. _amdgpu_synid_addr64:749 750addr64751~~~~~~752 753Specifies whether a 64-bit address is used. By default, no address is used.754 755Cannot be used with :ref:`offen<amdgpu_synid_offen>` and756:ref:`idxen<amdgpu_synid_idxen>` modifiers.757 758 ======================================== ================================================759 Syntax Description760 ======================================== ================================================761 addr64 A 64-bit address is used.762 ======================================== ================================================763 764.. _amdgpu_synid_buf_offset12:765 766offset12767~~~~~~~~768 769Specifies an immediate unsigned 12-bit offset, in bytes. The default value is 0.770 771 ================== ====================================================================772 Syntax Description773 ================== ====================================================================774 offset:{0..0xFFF} Specifies a 12-bit unsigned offset as a positive775 :ref:`integer number <amdgpu_synid_integer_number>`776 or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.777 ================== ====================================================================778 779Examples:780 781.. parsed-literal::782 783 offset:x+y784 offset:0x10785 786glc787~~~788 789See a description :ref:`here<amdgpu_synid_glc>`.790 791slc792~~~793 794See a description :ref:`here<amdgpu_synid_slc>`.795 796lds797~~~798 799See a description :ref:`here<amdgpu_synid_lds>`.800 801dlc802~~~803 804See a description :ref:`here<amdgpu_synid_dlc>`.805 806tfe807~~~808 809See a description :ref:`here<amdgpu_synid_tfe>`.810 811.. _amdgpu_synid_fmt:812 813fmt814~~~815 816Specifies data and numeric formats used by the operation.817The default numeric format is BUF_NUM_FORMAT_UNORM.818The default data format is BUF_DATA_FORMAT_8.819 820 ========================================= ===============================================================821 Syntax Description822 ========================================= ===============================================================823 format:{0..127} Use a format specified as either an824 :ref:`integer number<amdgpu_synid_integer_number>` or an825 :ref:`absolute expression<amdgpu_synid_absolute_expression>`.826 format:[<data format>] Use the specified data format and827 default numeric format.828 format:[<numeric format>] Use the specified numeric format and829 default data format.830 format:[<data format>,<numeric format>] Use the specified data and numeric formats.831 format:[<numeric format>,<data format>] Use the specified data and numeric formats.832 ========================================= ===============================================================833 834.. _amdgpu_synid_format_data:835 836Supported data formats are defined in the following table:837 838 ========================================= ===============================839 Syntax Note840 ========================================= ===============================841 BUF_DATA_FORMAT_INVALID842 BUF_DATA_FORMAT_8 The default value.843 BUF_DATA_FORMAT_16844 BUF_DATA_FORMAT_8_8845 BUF_DATA_FORMAT_32846 BUF_DATA_FORMAT_16_16847 BUF_DATA_FORMAT_10_11_11848 BUF_DATA_FORMAT_11_11_10849 BUF_DATA_FORMAT_10_10_10_2850 BUF_DATA_FORMAT_2_10_10_10851 BUF_DATA_FORMAT_8_8_8_8852 BUF_DATA_FORMAT_32_32853 BUF_DATA_FORMAT_16_16_16_16854 BUF_DATA_FORMAT_32_32_32855 BUF_DATA_FORMAT_32_32_32_32856 BUF_DATA_FORMAT_RESERVED_15857 ========================================= ===============================858 859.. _amdgpu_synid_format_num:860 861Supported numeric formats are defined below:862 863 ========================================= ===============================864 Syntax Note865 ========================================= ===============================866 BUF_NUM_FORMAT_UNORM The default value.867 BUF_NUM_FORMAT_SNORM868 BUF_NUM_FORMAT_USCALED869 BUF_NUM_FORMAT_SSCALED870 BUF_NUM_FORMAT_UINT871 BUF_NUM_FORMAT_SINT872 BUF_NUM_FORMAT_SNORM_OGL GFX7 only.873 BUF_NUM_FORMAT_RESERVED_6 GFX8 and GFX9 only.874 BUF_NUM_FORMAT_FLOAT875 ========================================= ===============================876 877Examples:878 879.. parsed-literal::880 881 format:0882 format:127883 format:[BUF_DATA_FORMAT_16]884 format:[BUF_DATA_FORMAT_16,BUF_NUM_FORMAT_SSCALED]885 format:[BUF_NUM_FORMAT_FLOAT]886 887.. _amdgpu_synid_ufmt:888 889ufmt890~~~~891 892Specifies a unified format used by the operation.893The default format is BUF_FMT_8_UNORM.894 895 ========================================= ===============================================================896 Syntax Description897 ========================================= ===============================================================898 format:{0..127} Use a unified format specified as either an899 :ref:`integer number<amdgpu_synid_integer_number>` or an900 :ref:`absolute expression<amdgpu_synid_absolute_expression>`.901 Note that unified format numbers are incompatible with902 format numbers used for pre-GFX10 ISA.903 format:[<unified format>] Use the specified unified format.904 ========================================= ===============================================================905 906Unified format is a replacement for :ref:`data<amdgpu_synid_format_data>`907and :ref:`numeric<amdgpu_synid_format_num>` formats. For compatibility with older ISA,908:ref:`the syntax with data and numeric formats<amdgpu_synid_fmt>` is still accepted909provided that the combination of formats can be mapped to a unified format.910 911Supported unified formats and equivalent combinations of data and numeric formats912are defined below:913 914 ============================== ============================== ============================= ============915 Unified Format Syntax Equivalent Data Format Equivalent Numeric Format Note916 ============================== ============================== ============================= ============917 BUF_FMT_INVALID BUF_DATA_FORMAT_INVALID BUF_NUM_FORMAT_UNORM918 919 BUF_FMT_8_UNORM BUF_DATA_FORMAT_8 BUF_NUM_FORMAT_UNORM920 BUF_FMT_8_SNORM BUF_DATA_FORMAT_8 BUF_NUM_FORMAT_SNORM921 BUF_FMT_8_USCALED BUF_DATA_FORMAT_8 BUF_NUM_FORMAT_USCALED922 BUF_FMT_8_SSCALED BUF_DATA_FORMAT_8 BUF_NUM_FORMAT_SSCALED923 BUF_FMT_8_UINT BUF_DATA_FORMAT_8 BUF_NUM_FORMAT_UINT924 BUF_FMT_8_SINT BUF_DATA_FORMAT_8 BUF_NUM_FORMAT_SINT925 926 BUF_FMT_16_UNORM BUF_DATA_FORMAT_16 BUF_NUM_FORMAT_UNORM927 BUF_FMT_16_SNORM BUF_DATA_FORMAT_16 BUF_NUM_FORMAT_SNORM928 BUF_FMT_16_USCALED BUF_DATA_FORMAT_16 BUF_NUM_FORMAT_USCALED929 BUF_FMT_16_SSCALED BUF_DATA_FORMAT_16 BUF_NUM_FORMAT_SSCALED930 BUF_FMT_16_UINT BUF_DATA_FORMAT_16 BUF_NUM_FORMAT_UINT931 BUF_FMT_16_SINT BUF_DATA_FORMAT_16 BUF_NUM_FORMAT_SINT932 BUF_FMT_16_FLOAT BUF_DATA_FORMAT_16 BUF_NUM_FORMAT_FLOAT933 934 BUF_FMT_8_8_UNORM BUF_DATA_FORMAT_8_8 BUF_NUM_FORMAT_UNORM935 BUF_FMT_8_8_SNORM BUF_DATA_FORMAT_8_8 BUF_NUM_FORMAT_SNORM936 BUF_FMT_8_8_USCALED BUF_DATA_FORMAT_8_8 BUF_NUM_FORMAT_USCALED937 BUF_FMT_8_8_SSCALED BUF_DATA_FORMAT_8_8 BUF_NUM_FORMAT_SSCALED938 BUF_FMT_8_8_UINT BUF_DATA_FORMAT_8_8 BUF_NUM_FORMAT_UINT939 BUF_FMT_8_8_SINT BUF_DATA_FORMAT_8_8 BUF_NUM_FORMAT_SINT940 941 BUF_FMT_32_UINT BUF_DATA_FORMAT_32 BUF_NUM_FORMAT_UINT942 BUF_FMT_32_SINT BUF_DATA_FORMAT_32 BUF_NUM_FORMAT_SINT943 BUF_FMT_32_FLOAT BUF_DATA_FORMAT_32 BUF_NUM_FORMAT_FLOAT944 945 BUF_FMT_16_16_UNORM BUF_DATA_FORMAT_16_16 BUF_NUM_FORMAT_UNORM946 BUF_FMT_16_16_SNORM BUF_DATA_FORMAT_16_16 BUF_NUM_FORMAT_SNORM947 BUF_FMT_16_16_USCALED BUF_DATA_FORMAT_16_16 BUF_NUM_FORMAT_USCALED948 BUF_FMT_16_16_SSCALED BUF_DATA_FORMAT_16_16 BUF_NUM_FORMAT_SSCALED949 BUF_FMT_16_16_UINT BUF_DATA_FORMAT_16_16 BUF_NUM_FORMAT_UINT950 BUF_FMT_16_16_SINT BUF_DATA_FORMAT_16_16 BUF_NUM_FORMAT_SINT951 BUF_FMT_16_16_FLOAT BUF_DATA_FORMAT_16_16 BUF_NUM_FORMAT_FLOAT952 953 BUF_FMT_10_11_11_UNORM BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_UNORM GFX10 only954 BUF_FMT_10_11_11_SNORM BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_SNORM GFX10 only955 BUF_FMT_10_11_11_USCALED BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_USCALED GFX10 only956 BUF_FMT_10_11_11_SSCALED BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_SSCALED GFX10 only957 BUF_FMT_10_11_11_UINT BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_UINT GFX10 only958 BUF_FMT_10_11_11_SINT BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_SINT GFX10 only959 BUF_FMT_10_11_11_FLOAT BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_FLOAT960 961 BUF_FMT_11_11_10_UNORM BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_UNORM GFX10 only962 BUF_FMT_11_11_10_SNORM BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_SNORM GFX10 only963 BUF_FMT_11_11_10_USCALED BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_USCALED GFX10 only964 BUF_FMT_11_11_10_SSCALED BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_SSCALED GFX10 only965 BUF_FMT_11_11_10_UINT BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_UINT GFX10 only966 BUF_FMT_11_11_10_SINT BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_SINT GFX10 only967 BUF_FMT_11_11_10_FLOAT BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_FLOAT968 969 BUF_FMT_10_10_10_2_UNORM BUF_DATA_FORMAT_10_10_10_2 BUF_NUM_FORMAT_UNORM970 BUF_FMT_10_10_10_2_SNORM BUF_DATA_FORMAT_10_10_10_2 BUF_NUM_FORMAT_SNORM971 BUF_FMT_10_10_10_2_USCALED BUF_DATA_FORMAT_10_10_10_2 BUF_NUM_FORMAT_USCALED GFX10 only972 BUF_FMT_10_10_10_2_SSCALED BUF_DATA_FORMAT_10_10_10_2 BUF_NUM_FORMAT_SSCALED GFX10 only973 BUF_FMT_10_10_10_2_UINT BUF_DATA_FORMAT_10_10_10_2 BUF_NUM_FORMAT_UINT974 BUF_FMT_10_10_10_2_SINT BUF_DATA_FORMAT_10_10_10_2 BUF_NUM_FORMAT_SINT975 976 BUF_FMT_2_10_10_10_UNORM BUF_DATA_FORMAT_2_10_10_10 BUF_NUM_FORMAT_UNORM977 BUF_FMT_2_10_10_10_SNORM BUF_DATA_FORMAT_2_10_10_10 BUF_NUM_FORMAT_SNORM978 BUF_FMT_2_10_10_10_USCALED BUF_DATA_FORMAT_2_10_10_10 BUF_NUM_FORMAT_USCALED979 BUF_FMT_2_10_10_10_SSCALED BUF_DATA_FORMAT_2_10_10_10 BUF_NUM_FORMAT_SSCALED980 BUF_FMT_2_10_10_10_UINT BUF_DATA_FORMAT_2_10_10_10 BUF_NUM_FORMAT_UINT981 BUF_FMT_2_10_10_10_SINT BUF_DATA_FORMAT_2_10_10_10 BUF_NUM_FORMAT_SINT982 983 BUF_FMT_8_8_8_8_UNORM BUF_DATA_FORMAT_8_8_8_8 BUF_NUM_FORMAT_UNORM984 BUF_FMT_8_8_8_8_SNORM BUF_DATA_FORMAT_8_8_8_8 BUF_NUM_FORMAT_SNORM985 BUF_FMT_8_8_8_8_USCALED BUF_DATA_FORMAT_8_8_8_8 BUF_NUM_FORMAT_USCALED986 BUF_FMT_8_8_8_8_SSCALED BUF_DATA_FORMAT_8_8_8_8 BUF_NUM_FORMAT_SSCALED987 BUF_FMT_8_8_8_8_UINT BUF_DATA_FORMAT_8_8_8_8 BUF_NUM_FORMAT_UINT988 BUF_FMT_8_8_8_8_SINT BUF_DATA_FORMAT_8_8_8_8 BUF_NUM_FORMAT_SINT989 990 BUF_FMT_32_32_UINT BUF_DATA_FORMAT_32_32 BUF_NUM_FORMAT_UINT991 BUF_FMT_32_32_SINT BUF_DATA_FORMAT_32_32 BUF_NUM_FORMAT_SINT992 BUF_FMT_32_32_FLOAT BUF_DATA_FORMAT_32_32 BUF_NUM_FORMAT_FLOAT993 994 BUF_FMT_16_16_16_16_UNORM BUF_DATA_FORMAT_16_16_16_16 BUF_NUM_FORMAT_UNORM995 BUF_FMT_16_16_16_16_SNORM BUF_DATA_FORMAT_16_16_16_16 BUF_NUM_FORMAT_SNORM996 BUF_FMT_16_16_16_16_USCALED BUF_DATA_FORMAT_16_16_16_16 BUF_NUM_FORMAT_USCALED997 BUF_FMT_16_16_16_16_SSCALED BUF_DATA_FORMAT_16_16_16_16 BUF_NUM_FORMAT_SSCALED998 BUF_FMT_16_16_16_16_UINT BUF_DATA_FORMAT_16_16_16_16 BUF_NUM_FORMAT_UINT999 BUF_FMT_16_16_16_16_SINT BUF_DATA_FORMAT_16_16_16_16 BUF_NUM_FORMAT_SINT1000 BUF_FMT_16_16_16_16_FLOAT BUF_DATA_FORMAT_16_16_16_16 BUF_NUM_FORMAT_FLOAT1001 1002 BUF_FMT_32_32_32_UINT BUF_DATA_FORMAT_32_32_32 BUF_NUM_FORMAT_UINT1003 BUF_FMT_32_32_32_SINT BUF_DATA_FORMAT_32_32_32 BUF_NUM_FORMAT_SINT1004 BUF_FMT_32_32_32_FLOAT BUF_DATA_FORMAT_32_32_32 BUF_NUM_FORMAT_FLOAT1005 BUF_FMT_32_32_32_32_UINT BUF_DATA_FORMAT_32_32_32_32 BUF_NUM_FORMAT_UINT1006 BUF_FMT_32_32_32_32_SINT BUF_DATA_FORMAT_32_32_32_32 BUF_NUM_FORMAT_SINT1007 BUF_FMT_32_32_32_32_FLOAT BUF_DATA_FORMAT_32_32_32_32 BUF_NUM_FORMAT_FLOAT1008 ============================== ============================== ============================= ============1009 1010Examples:1011 1012.. parsed-literal::1013 1014 format:01015 format:[BUF_FMT_32_UINT]1016 1017SMRD/SMEM Modifiers1018-------------------1019 1020glc1021~~~1022 1023See a description :ref:`here<amdgpu_synid_glc>`.1024 1025nv1026~~1027 1028See a description :ref:`here<amdgpu_synid_nv>`.1029 1030dlc1031~~~1032 1033See a description :ref:`here<amdgpu_synid_dlc>`.1034 1035.. _amdgpu_synid_smem_offset20u:1036 1037offset20u1038~~~~~~~~~1039 1040Specifies an unsigned 20-bit offset, in bytes. The default value is 0.1041 1042 ==================== ====================================================================1043 Syntax Description1044 ==================== ====================================================================1045 offset:{0..0xFFFFF} Specifies an offset as a positive1046 :ref:`integer number <amdgpu_synid_integer_number>`1047 or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.1048 ==================== ====================================================================1049 1050Examples:1051 1052.. parsed-literal::1053 1054 offset:11055 offset:0xfffff1056 offset:x-y1057 1058.. _amdgpu_synid_smem_offset21s:1059 1060offset21s1061~~~~~~~~~1062 1063Specifies a signed 21-bit offset, in bytes. The default value is 0.1064 1065 ============================= ====================================================================1066 Syntax Description1067 ============================= ====================================================================1068 offset:{-0x100000..0xFFFFF} Specifies an offset as an1069 :ref:`integer number <amdgpu_synid_integer_number>`1070 or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.1071 ============================= ====================================================================1072 1073Examples:1074 1075.. parsed-literal::1076 1077 offset:-11078 offset:0xfffff1079 offset:-x1080 1081.. _amdgpu_synid_smem_offset24s:1082 1083offset24s1084~~~~~~~~~1085 1086Specifies a signed 24-bit offset, in bytes. The default value is 0.1087 1088 ============================= ====================================================================1089 Syntax Description1090 ============================= ====================================================================1091 offset:{-0x1000000..0xFFFFFF} Specifies an offset as an1092 :ref:`integer number <amdgpu_synid_integer_number>`1093 or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.1094 ============================= ====================================================================1095 1096Examples:1097 1098.. parsed-literal::1099 1100 offset:-11101 offset:0xfffff1102 offset:-x1103 1104.. _amdgpu_synid_th:1105 1106th1107~~1108 1109Specifies temporal hint of memory operation.1110 1111 =============================== =========================================================1112 Syntax Description1113 =============================== =========================================================1114 TH_{LOAD|STORE}_RT Regular1115 TH_{LOAD|STORE}_NT Non-temporal1116 TH_{LOAD|STORE}_HT High-temporal1117 TH_{LOAD|STORE}_LU Last use. Not available in SYS scope.1118 TH_{LOAD|STORE}_WB Regular (CU, SE); High-temporal with write-back (MALL)1119 TH_{LOAD|STORE}_NT_RT Non-temporal (CU, SE); Regular (MALL)1120 TH_{LOAD|STORE}_RT_NT Regular (CU, SE); Non-temporal (MALL)1121 TH_{LOAD|STORE}_NT_HT Non-temporal (CU, SE); High-temporal (MALL)1122 TH_{LOAD|STORE}_NT_WB Non-temporal (CU, SE); High-temporal with write-back (MALL)1123 TH_{LOAD|STORE}_BYPASS Available for SYS scope only.1124 TH_ATOMIC_RT Regular1125 TH_ATOMIC_RT_RETURN Regular. For atomic instructions that return values.1126 TH_ATOMIC_NT Non-temporal1127 TH_ATOMIC_NT_RETURN Non-temporal. For atomic instructions that return values.1128 TH_ATOMIC_CASCADE_RT Cascading atomic; Regular.1129 TH_ATOMIC_CASCADE_NT Cascading atomic; Non-temporal.1130 =============================== =========================================================1131 1132.. _amdgpu_synid_scope:1133 1134scope1135~~~~~1136 1137Specifies scope of memory operation.1138 1139 =============================== =========================================================1140 Syntax Description1141 =============================== =========================================================1142 SCOPE_CU Coherency within a Compute Unit.1143 SCOPE_SE Coherency within a Shader Engine.1144 SCOPE_DEV Coherency within a single device.1145 SCOPE_SYS Coherency across the full system.1146 =============================== =========================================================1147 1148VINTRP/VINTERP/LDSDIR Modifiers1149-------------------------------1150 1151.. _amdgpu_synid_high:1152 1153high1154~~~~1155 1156Specifies which half of the LDS word to use. Low half of LDS word is used by default.1157 1158 ======================================== ================================1159 Syntax Description1160 ======================================== ================================1161 high Use the high half of LDS word.1162 ======================================== ================================1163 1164neg1165~~~1166 1167See a description :ref:`here<amdgpu_synid_neg>`.1168 1169.. _amdgpu_synid_wait_exp:1170 1171wait_exp1172~~~~~~~~1173 1174Specifies a wait on the EXP counter before issuing the current instruction.1175The counter must be less than or equal to this value before the instruction is issued.1176If set to 7, no wait is performed.1177 1178The default value is zero. This is a safe value, but it may be suboptimal.1179 1180 ================ ======================================================1181 Syntax Description1182 ================ ======================================================1183 wait_exp:{0..7} An additional wait on the EXP counter before1184 issuing this instruction.1185 ================ ======================================================1186 1187.. _amdgpu_synid_wait_va_vdst:1188 1189wait_va_vdst1190~~~~~~~~~~~~1191 1192Manually specify a wait on the VA_VDST counter before issuing this instruction. VA_VDST must be less1193than or equal to this value before the instruction is issued. If set to 15, no wait is performed.1194 1195If unspecified the current default is zero. This is a safe value but may have poor performance characteristics.1196 1197This modifier is a shorthand for the WAR hazard where VALU reads a VGPR that is written by a parameter1198load. Since there is no VA_VSRC counter we must use VA_VDST as a proxy to detect when the1199VALU instruction has completed:1200 1201Examples:1202 1203.. parsed-literal::1204 1205 v_mov_b32 v1, v01206 ds_param_load v0, . . . wait_va_vdst:01207 1208.. _amdgpu_synid_wait_vdst:1209 1210wait_vdst1211~~~~~~~~~1212 1213Specifies a wait on the VA_VDST counter before issuing the current instruction.1214The counter must be less than or equal to this value before the instruction is issued.1215If set to 15, no wait is performed.1216 1217The default value is zero. This is a safe value, but it may be suboptimal.1218 1219 ================== ======================================================1220 Syntax Description1221 ================== ======================================================1222 wait_vdst:{0..15} An additional wait on the VA_VDST counter before1223 issuing this instruction.1224 ================== ======================================================1225 1226.. _amdgpu_synid_wait_vm_vsrc:1227 1228wait_vm_vsrc1229~~~~~~~~~~~~1230 1231Manually specify a wait on the VM_VSRC counter before issuing this instruction. VM_VSRC must be less1232than or equal to this value before the instruction is issued. If set to 1, no wait is performed.1233 1234If unspecified the current default is zero. This is a safe value but may have poor performance characteristics.1235 1236This modifier is a shorthand for the WAR hazard where VMEM reads a VGPR that is written by a parameter1237load.1238 1239Examples:1240 1241.. parsed-literal::1242 1243 buffer_load_b32 v1, v0, s0, 01244 ds_param_load v0, . . . wait_vm_vsrc:01245 1246 1247DPP8 Modifiers1248--------------1249 1250.. _amdgpu_synid_dpp8_sel:1251 1252dpp8_sel1253~~~~~~~~1254 1255Selects which lanes to pull data from, within a group of 8 lanes. This is a mandatory modifier.1256There is no default value.1257 1258The *dpp8_sel* modifier must specify exactly 8 values.1259The first value selects which lane to read from to supply data into lane 0.1260The second value controls lane 1 and so on.1261 1262Each value may be specified as either1263an :ref:`integer number<amdgpu_synid_integer_number>` or1264an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.1265 1266 =============================================================== ===========================1267 Syntax Description1268 =============================================================== ===========================1269 dpp8:[{0..7},{0..7},{0..7},{0..7},{0..7},{0..7},{0..7},{0..7}] Select lanes to read from.1270 =============================================================== ===========================1271 1272Examples:1273 1274.. parsed-literal::1275 1276 dpp8:[7,6,5,4,3,2,1,0]1277 dpp8:[0,1,0,1,0,1,0,1]1278 1279.. _amdgpu_synid_fi8:1280 1281fi1282~~1283 1284Controls interaction with inactive lanes for *dpp8* instructions. The default value is zero.1285 1286Note: *inactive* lanes are those whose :ref:`exec<amdgpu_synid_exec>` mask bit is zero.1287 1288 ==================================== =====================================================1289 Syntax Description1290 ==================================== =====================================================1291 fi:0 Fetch zero when accessing data from inactive lanes.1292 fi:1 Fetch pre-existing values from inactive lanes.1293 ==================================== =====================================================1294 1295Note: numeric values may be specified as either1296:ref:`integer numbers<amdgpu_synid_integer_number>` or1297:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.1298 1299DPP Modifiers1300-------------1301 1302.. _amdgpu_synid_dpp_ctrl:1303 1304dpp_ctrl1305~~~~~~~~1306 1307Specifies how data is shared between threads. This is a mandatory modifier.1308There is no default value.1309 1310Note: the lanes of a wavefront are organized in four *rows* and four *banks*.1311 1312 ======================================== ========================================================1313 Syntax Description1314 ======================================== ========================================================1315 quad_perm:[{0..3},{0..3},{0..3},{0..3}] Full permute of 4 threads.1316 row_mirror Mirror threads within row.1317 row_half_mirror Mirror threads within 1/2 row (8 threads).1318 row_bcast:15 Broadcast the 15th thread of each row to the next row.1319 row_bcast:31 Broadcast thread 31 to rows 2 and 3.1320 wave_shl:1 Wavefront left shift by 1 thread.1321 wave_rol:1 Wavefront left rotate by 1 thread.1322 wave_shr:1 Wavefront right shift by 1 thread.1323 wave_ror:1 Wavefront right rotate by 1 thread.1324 row_shl:{1..15} Row shift left by 1-15 threads.1325 row_shr:{1..15} Row shift right by 1-15 threads.1326 row_ror:{1..15} Row rotate right by 1-15 threads.1327 ======================================== ========================================================1328 1329Note: numeric values may be specified as either1330:ref:`integer numbers<amdgpu_synid_integer_number>` or1331:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.1332 1333Examples:1334 1335.. parsed-literal::1336 1337 quad_perm:[0, 1, 2, 3]1338 row_shl:31339 1340.. _amdgpu_synid_dpp16_ctrl:1341 1342dpp16_ctrl1343~~~~~~~~~~1344 1345Specifies how data is shared between threads. This is a mandatory modifier.1346There is no default value.1347 1348Note: the lanes of a wavefront are organized in four *rows* and four *banks*.1349(There are only two rows in *wave32* mode.)1350 1351 ======================================== =======================================================1352 Syntax Description1353 ======================================== =======================================================1354 quad_perm:[{0..3},{0..3},{0..3},{0..3}] Full permute of 4 threads.1355 row_mirror Mirror threads within row.1356 row_half_mirror Mirror threads within 1/2 row (8 threads).1357 row_share:{0..15} Share the value from the specified lane with other1358 lanes in the row.1359 row_xmask:{0..15} Fetch from XOR(<current lane id>,<specified lane id>).1360 row_shl:{1..15} Row shift left by 1-15 threads.1361 row_shr:{1..15} Row shift right by 1-15 threads.1362 row_ror:{1..15} Row rotate right by 1-15 threads.1363 ======================================== =======================================================1364 1365Note: numeric values may be specified as either1366:ref:`integer numbers<amdgpu_synid_integer_number>` or1367:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.1368 1369Examples:1370 1371.. parsed-literal::1372 1373 quad_perm:[0, 1, 2, 3]1374 row_shl:31375 1376.. _amdgpu_synid_dpp32_ctrl:1377 1378dpp32_ctrl1379~~~~~~~~~~1380 1381Specifies how data is shared between threads. This is a mandatory modifier.1382There is no default value.1383 1384Note: the lanes of a wavefront are organized in four *rows* and four *banks*.1385 1386 ======================================== =========================================================1387 Syntax Description1388 ======================================== =========================================================1389 quad_perm:[{0..3},{0..3},{0..3},{0..3}] Full permute of 4 threads.1390 row_mirror Mirror threads within row.1391 row_half_mirror Mirror threads within 1/2 row (8 threads).1392 row_bcast:15 Broadcast the 15th thread of each row to the next row.1393 row_bcast:31 Broadcast thread 31 to rows 2 and 3.1394 wave_shl:1 Wavefront left shift by 1 thread.1395 wave_rol:1 Wavefront left rotate by 1 thread.1396 wave_shr:1 Wavefront right shift by 1 thread.1397 wave_ror:1 Wavefront right rotate by 1 thread.1398 row_shl:{1..15} Row shift left by 1-15 threads.1399 row_shr:{1..15} Row shift right by 1-15 threads.1400 row_ror:{1..15} Row rotate right by 1-15 threads.1401 row_newbcast:{1..15} Broadcast a thread within a row to the whole row.1402 ======================================== =========================================================1403 1404Note: numeric values may be specified as either1405:ref:`integer numbers<amdgpu_synid_integer_number>` or1406:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.1407 1408Examples:1409 1410.. parsed-literal::1411 1412 quad_perm:[0, 1, 2, 3]1413 row_shl:31414 1415 1416.. _amdgpu_synid_dpp64_ctrl:1417 1418dpp64_ctrl1419~~~~~~~~~~1420 1421Specifies how data is shared between threads. This is a mandatory modifier.1422There is no default value.1423 1424Note: the lanes of a wavefront are organized in four *rows* and four *banks*.1425 1426 ======================================== ==================================================1427 Syntax Description1428 ======================================== ==================================================1429 row_newbcast:{1..15} Broadcast a thread within a row to the whole row.1430 ======================================== ==================================================1431 1432Note: numeric values may be specified as either1433:ref:`integer numbers<amdgpu_synid_integer_number>` or1434:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.1435 1436Examples:1437 1438.. parsed-literal::1439 1440 row_newbcast:31441 1442 1443.. _amdgpu_synid_row_mask:1444 1445row_mask1446~~~~~~~~1447 1448Controls which rows are enabled for data sharing. By default, all rows are enabled.1449 1450Note: the lanes of a wavefront are organized in four *rows* and four *banks*.1451(There are only two rows in *wave32* mode.)1452 1453 ================= ====================================================================1454 Syntax Description1455 ================= ====================================================================1456 row_mask:{0..15} Specifies a *row mask* as a positive1457 :ref:`integer number <amdgpu_synid_integer_number>`1458 or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.1459 1460 Each of the 4 bits in the mask controls one row1461 (0 - disabled, 1 - enabled).1462 1463 In *wave32* mode, the values shall be limited to {0..7}.1464 ================= ====================================================================1465 1466Examples:1467 1468.. parsed-literal::1469 1470 row_mask:0xf1471 row_mask:0b10101472 row_mask:x|y1473 1474.. _amdgpu_synid_bank_mask:1475 1476bank_mask1477~~~~~~~~~1478 1479Controls which banks are enabled for data sharing. By default, all banks are enabled.1480 1481Note: the lanes of a wavefront are organized in four *rows* and four *banks*.1482(There are only two rows in *wave32* mode.)1483 1484 ================== ====================================================================1485 Syntax Description1486 ================== ====================================================================1487 bank_mask:{0..15} Specifies a *bank mask* as a positive1488 :ref:`integer number <amdgpu_synid_integer_number>`1489 or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.1490 1491 Each of the 4 bits in the mask controls one bank1492 (0 - disabled, 1 - enabled).1493 ================== ====================================================================1494 1495Examples:1496 1497.. parsed-literal::1498 1499 bank_mask:0x31500 bank_mask:0b00111501 bank_mask:x&y1502 1503.. _amdgpu_synid_bound_ctrl:1504 1505bound_ctrl1506~~~~~~~~~~1507 1508Controls data sharing when accessing an invalid lane. By default, data sharing with1509invalid lanes is disabled.1510 1511 ======================================== ================================================1512 Syntax Description1513 ======================================== ================================================1514 bound_ctrl:1 Enables data sharing with invalid lanes.1515 1516 Accessing data from an invalid lane will1517 return zero.1518 1519 bound_ctrl:0 (GFX11+) Disables data sharing with invalid lanes.1520 ======================================== ================================================1521 1522.. WARNING:: For historical reasons, *bound_ctrl:0* has the same meaning as *bound_ctrl:1* for older architectures.1523 1524.. _amdgpu_synid_fi16:1525 1526fi1527~~1528 1529Controls interaction with *inactive* lanes for *dpp16* instructions. The default value is zero.1530 1531Note: *inactive* lanes are those whose :ref:`exec<amdgpu_synid_exec>` mask bit is zero.1532 1533 ======================================== ==================================================1534 Syntax Description1535 ======================================== ==================================================1536 fi:0 Interaction with inactive lanes is controlled by1537 :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`.1538 1539 fi:1 Fetch pre-existing values from inactive lanes.1540 ======================================== ==================================================1541 1542Note: numeric values may be specified as either1543:ref:`integer numbers<amdgpu_synid_integer_number>` or1544:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.1545 1546SDWA Modifiers1547--------------1548 1549clamp1550~~~~~1551 1552See a description :ref:`here<amdgpu_synid_clamp>`.1553 1554omod1555~~~~1556 1557See a description :ref:`here<amdgpu_synid_omod>`.1558 1559.. _amdgpu_synid_dst_sel:1560 1561dst_sel1562~~~~~~~1563 1564Selects which bits in the destination are affected. By default, all bits are affected.1565 1566 ======================================== ================================================1567 Syntax Description1568 ======================================== ================================================1569 dst_sel:DWORD Use bits 31:0.1570 dst_sel:BYTE_0 Use bits 7:0.1571 dst_sel:BYTE_1 Use bits 15:8.1572 dst_sel:BYTE_2 Use bits 23:16.1573 dst_sel:BYTE_3 Use bits 31:24.1574 dst_sel:WORD_0 Use bits 15:0.1575 dst_sel:WORD_1 Use bits 31:16.1576 ======================================== ================================================1577 1578.. _amdgpu_synid_dst_unused:1579 1580dst_unused1581~~~~~~~~~~1582 1583Controls what to do with the bits in the destination which are not selected1584by :ref:`dst_sel<amdgpu_synid_dst_sel>`.1585By default, unused bits are preserved.1586 1587 ======================================== ================================================1588 Syntax Description1589 ======================================== ================================================1590 dst_unused:UNUSED_PAD Pad with zeros.1591 dst_unused:UNUSED_SEXT Sign-extend upper bits, zero lower bits.1592 dst_unused:UNUSED_PRESERVE Preserve bits.1593 ======================================== ================================================1594 1595.. _amdgpu_synid_src0_sel:1596 1597src0_sel1598~~~~~~~~1599 1600Controls which bits in the src0 are used. By default, all bits are used.1601 1602 ======================================== ================================================1603 Syntax Description1604 ======================================== ================================================1605 src0_sel:DWORD Use bits 31:0.1606 src0_sel:BYTE_0 Use bits 7:0.1607 src0_sel:BYTE_1 Use bits 15:8.1608 src0_sel:BYTE_2 Use bits 23:16.1609 src0_sel:BYTE_3 Use bits 31:24.1610 src0_sel:WORD_0 Use bits 15:0.1611 src0_sel:WORD_1 Use bits 31:16.1612 ======================================== ================================================1613 1614.. _amdgpu_synid_src1_sel:1615 1616src1_sel1617~~~~~~~~1618 1619Controls which bits in the src1 are used. By default, all bits are used.1620 1621 ======================================== ================================================1622 Syntax Description1623 ======================================== ================================================1624 src1_sel:DWORD Use bits 31:0.1625 src1_sel:BYTE_0 Use bits 7:0.1626 src1_sel:BYTE_1 Use bits 15:8.1627 src1_sel:BYTE_2 Use bits 23:16.1628 src1_sel:BYTE_3 Use bits 31:24.1629 src1_sel:WORD_0 Use bits 15:0.1630 src1_sel:WORD_1 Use bits 31:16.1631 ======================================== ================================================1632 1633.. _amdgpu_synid_sdwa_operand_modifiers:1634 1635SDWA Operand Modifiers1636----------------------1637 1638Operand modifiers are not used separately. They are applied to source operands.1639 1640abs1641~~~1642 1643See a description :ref:`here<amdgpu_synid_abs>`.1644 1645neg1646~~~1647 1648See a description :ref:`here<amdgpu_synid_neg>`.1649 1650.. _amdgpu_synid_sext:1651 1652sext1653~~~~1654 1655Sign-extends the value of a (sub-dword) integer operand to fill all 32 bits.1656 1657Valid for integer operands only.1658 1659 ======================================== ================================================1660 Syntax Description1661 ======================================== ================================================1662 sext(<operand>) Sign-extend operand value.1663 ======================================== ================================================1664 1665Examples:1666 1667.. parsed-literal::1668 1669 sext(v4)1670 sext(v255)1671 1672VOP3 Modifiers1673--------------1674 1675.. _amdgpu_synid_vop3_op_sel:1676 1677op_sel1678~~~~~~1679 1680Selects the low [15:0] or high [31:16] operand bits for source and destination operands.1681By default, low bits are used for all operands.1682 1683The number of values specified with the op_sel modifier must match the number of instruction1684operands (both source and destination). The first value controls src0, the second value controls src11685and so on, except that the last value controls destination.1686The value 0 selects the low bits, while 1 selects the high bits.1687 1688Note: op_sel modifier affects 16-bit operands only. For 32-bit operands, the value specified1689by op_sel must be 0.1690 1691 ======================================== ============================================================1692 Syntax Description1693 ======================================== ============================================================1694 op_sel:[{0..1},{0..1}] Select operand bits for instructions with 1 source operand.1695 op_sel:[{0..1},{0..1},{0..1}] Select operand bits for instructions with 2 source operands.1696 op_sel:[{0..1},{0..1},{0..1},{0..1}] Select operand bits for instructions with 3 source operands.1697 ======================================== ============================================================1698 1699Note: numeric values may be specified as either1700:ref:`integer numbers<amdgpu_synid_integer_number>` or1701:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.1702 1703Examples:1704 1705.. parsed-literal::1706 1707 op_sel:[0,0]1708 op_sel:[0,1]1709 1710.. _amdgpu_synid_dpp_op_sel:1711 1712dpp_op_sel1713~~~~~~~~~~1714 1715This is a special version of *op_sel* used for *permlane* opcodes to specify1716dpp-like mode bits - :ref:`fi<amdgpu_synid_fi16>` and1717:ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`.1718 1719 ======================================== =================================================================1720 Syntax Description1721 ======================================== =================================================================1722 op_sel:[{0..1},{0..1}] The first bit specifies :ref:`fi<amdgpu_synid_fi16>`, the second1723 bit specifies :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`.1724 ======================================== =================================================================1725 1726Note: numeric values may be specified as either1727:ref:`integer numbers<amdgpu_synid_integer_number>` or1728:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.1729 1730Examples:1731 1732.. parsed-literal::1733 1734 op_sel:[0,0]1735 1736.. _amdgpu_synid_clamp:1737 1738clamp1739~~~~~1740 1741Clamp meaning depends on instruction.1742 1743For *v_cmp* instructions, clamp modifier indicates that the compare signals1744if a floating-point exception occurs. By default, signaling is disabled.1745 1746For integer operations, clamp modifier indicates that the result must be clamped1747to the largest and smallest representable value. By default, there is no clamping.1748 1749For floating-point operations, clamp modifier indicates that the result must be clamped1750to the range [0.0, 1.0]. By default, there is no clamping.1751 1752Note: clamp modifier is applied after :ref:`output modifiers<amdgpu_synid_omod>` (if any).1753 1754 ======================================== ================================================1755 Syntax Description1756 ======================================== ================================================1757 clamp Enables clamping (or signaling).1758 ======================================== ================================================1759 1760.. _amdgpu_synid_omod:1761 1762omod1763~~~~1764 1765Specifies if an output modifier must be applied to the result.1766It is assumed that the result is a floating-point number.1767 1768By default, no output modifiers are applied.1769 1770Note: output modifiers are applied before :ref:`clamping<amdgpu_synid_clamp>` (if any).1771 1772 ======================================== ================================================1773 Syntax Description1774 ======================================== ================================================1775 mul:2 Multiply the result by 2.1776 mul:4 Multiply the result by 4.1777 div:2 Multiply the result by 0.5.1778 ======================================== ================================================1779 1780Note: numeric values may be specified as either1781:ref:`integer numbers<amdgpu_synid_integer_number>` or1782:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.1783 1784Examples:1785 1786.. parsed-literal::1787 1788 mul:21789 mul:x // x must be equal to 2 or 41790 1791.. _amdgpu_synid_vop3_operand_modifiers:1792 1793VOP3 Operand Modifiers1794----------------------1795 1796Operand modifiers are not used separately. They are applied to source operands.1797 1798.. _amdgpu_synid_abs:1799 1800abs1801~~~1802 1803Computes the absolute value of its operand. Must be applied before :ref:`neg<amdgpu_synid_neg>`1804(if any). Valid for floating-point operands only.1805 1806 ======================================== ====================================================1807 Syntax Description1808 ======================================== ====================================================1809 abs(<operand>) Get the absolute value of a floating-point operand.1810 \|<operand>| The same as above (an SP3 syntax).1811 ======================================== ====================================================1812 1813Note: avoid using SP3 syntax with operands specified as expressions because the trailing '|'1814may be misinterpreted. Such operands should be enclosed into additional parentheses, as shown1815in examples below.1816 1817Examples:1818 1819.. parsed-literal::1820 1821 abs(v36)1822 \|v36|1823 abs(x|y) // ok1824 \|(x|y)| // additional parentheses are required1825 1826.. _amdgpu_synid_neg:1827 1828neg1829~~~1830 1831Computes the negative value of its operand. Must be applied after :ref:`abs<amdgpu_synid_abs>`1832(if any). Valid for floating-point operands only.1833 1834 ================== ====================================================1835 Syntax Description1836 ================== ====================================================1837 neg(<operand>) Get the negative value of a floating-point operand.1838 An optional :ref:`abs<amdgpu_synid_abs>` modifier1839 may be applied to the operand before negation.1840 -<operand> The same as above (an SP3 syntax).1841 ================== ====================================================1842 1843Note: SP3 syntax is supported with limitations because of a potential ambiguity.1844Currently, it is allowed in the following cases:1845 1846* Before a register.1847* Before an :ref:`abs<amdgpu_synid_abs>` modifier.1848* Before an SP3 :ref:`abs<amdgpu_synid_abs>` modifier.1849 1850In all other cases, "-" is handled as a part of an expression that follows the sign.1851 1852Examples:1853 1854.. parsed-literal::1855 1856 // Operands with negate modifiers1857 neg(v[0])1858 neg(1.0)1859 neg(abs(v0))1860 -v51861 -abs(v5)1862 -\|v5|1863 1864 // Expressions where "-" has a different meaning1865 -11866 -x+y1867 1868VOP3P Modifiers1869---------------1870 1871This section describes modifiers of *regular* VOP3P instructions.1872 1873*v_mad_mix\** and *v_fma_mix\**1874instructions use these modifiers :ref:`in a special manner<amdgpu_synid_mad_mix>`.1875 1876.. _amdgpu_synid_op_sel:1877 1878op_sel1879~~~~~~1880 1881Selects the low [15:0] or high [31:16] operand bits as input to the operation,1882which results in the lower-half of the destination.1883By default, low 16 bits are used for all operands.1884 1885The number of values specified by the *op_sel* modifier must match the number of source1886operands. The first value controls src0, the second value controls src1 and so on.1887 1888The value 0 selects the low bits, while 1 selects the high bits.1889 1890 ================================= =============================================================1891 Syntax Description1892 ================================= =============================================================1893 op_sel:[{0..1}] Select operand bits for instructions with 1 source operand.1894 op_sel:[{0..1},{0..1}] Select operand bits for instructions with 2 source operands.1895 op_sel:[{0..1},{0..1},{0..1}] Select operand bits for instructions with 3 source operands.1896 ================================= =============================================================1897 1898Note: numeric values may be specified as either1899:ref:`integer numbers<amdgpu_synid_integer_number>` or1900:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.1901 1902Examples:1903 1904.. parsed-literal::1905 1906 op_sel:[0,0]1907 op_sel:[0,1,0]1908 1909.. _amdgpu_synid_op_sel_hi:1910 1911op_sel_hi1912~~~~~~~~~1913 1914Selects the low [15:0] or high [31:16] operand bits as input to the operation,1915which results in the upper-half of the destination.1916By default, high 16 bits are used for all operands.1917 1918The number of values specified by the *op_sel_hi* modifier must match the number of source1919operands. The first value controls src0, the second value controls src1 and so on.1920 1921The value 0 selects the low bits, while 1 selects the high bits.1922 1923 =================================== =============================================================1924 Syntax Description1925 =================================== =============================================================1926 op_sel_hi:[{0..1}] Select operand bits for instructions with 1 source operand.1927 op_sel_hi:[{0..1},{0..1}] Select operand bits for instructions with 2 source operands.1928 op_sel_hi:[{0..1},{0..1},{0..1}] Select operand bits for instructions with 3 source operands.1929 =================================== =============================================================1930 1931Note: numeric values may be specified as either1932:ref:`integer numbers<amdgpu_synid_integer_number>` or1933:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.1934 1935Examples:1936 1937.. parsed-literal::1938 1939 op_sel_hi:[0,0]1940 op_sel_hi:[0,0,1]1941 1942.. _amdgpu_synid_neg_lo:1943 1944neg_lo1945~~~~~~1946 1947Specifies whether to change the sign of operand values selected by1948:ref:`op_sel<amdgpu_synid_op_sel>`. These values are then used1949as input to the operation, which results in the upper-half of the destination.1950 1951The number of values specified by this modifier must match the number of source1952operands. The first value controls src0, the second value controls src1 and so on.1953 1954The value 0 indicates that the corresponding operand value is used unmodified,1955the value 1 indicates that the negative value of the operand must be used.1956 1957By default, operand values are used unmodified.1958 1959This modifier is valid for floating-point operands only.1960 1961 ================================ ==================================================================1962 Syntax Description1963 ================================ ==================================================================1964 neg_lo:[{0..1}] Select affected operands for instructions with 1 source operand.1965 neg_lo:[{0..1},{0..1}] Select affected operands for instructions with 2 source operands.1966 neg_lo:[{0..1},{0..1},{0..1}] Select affected operands for instructions with 3 source operands.1967 ================================ ==================================================================1968 1969Note: numeric values may be specified as either1970:ref:`integer numbers<amdgpu_synid_integer_number>` or1971:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.1972 1973Examples:1974 1975.. parsed-literal::1976 1977 neg_lo:[0]1978 neg_lo:[0,1]1979 1980.. _amdgpu_synid_neg_hi:1981 1982neg_hi1983~~~~~~1984 1985Specifies whether to change sign of operand values selected by1986:ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`. These values are then used1987as input to the operation, which results in the upper-half of the destination.1988 1989The number of values specified by this modifier must match the number of source1990operands. The first value controls src0, the second value controls src1 and so on.1991 1992The value 0 indicates that the corresponding operand value is used unmodified,1993the value 1 indicates that the negative value of the operand must be used.1994 1995By default, operand values are used unmodified.1996 1997This modifier is valid for floating-point operands only.1998 1999 =============================== ==================================================================2000 Syntax Description2001 =============================== ==================================================================2002 neg_hi:[{0..1}] Select affected operands for instructions with 1 source operand.2003 neg_hi:[{0..1},{0..1}] Select affected operands for instructions with 2 source operands.2004 neg_hi:[{0..1},{0..1},{0..1}] Select affected operands for instructions with 3 source operands.2005 =============================== ==================================================================2006 2007Note: numeric values may be specified as either2008:ref:`integer numbers<amdgpu_synid_integer_number>` or2009:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.2010 2011Examples:2012 2013.. parsed-literal::2014 2015 neg_hi:[1,0]2016 neg_hi:[0,1,1]2017 2018clamp2019~~~~~2020 2021See a description :ref:`here<amdgpu_synid_clamp>`.2022 2023.. _amdgpu_synid_mad_mix:2024 2025VOP3P MAD_MIX/FMA_MIX Modifiers2026-------------------------------2027 2028*v_mad_mix\** and *v_fma_mix\**2029instructions use *op_sel* and *op_sel_hi* modifiers2030in a manner different from *regular* VOP3P instructions.2031 2032See a description below.2033 2034.. _amdgpu_synid_mad_mix_op_sel:2035 2036m_op_sel2037~~~~~~~~2038 2039This operand has meaning only for 16-bit source operands, as indicated by2040:ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.2041It specifies to select either the low [15:0] or high [31:16] operand bits2042as input to the operation.2043 2044The number of values specified by the *op_sel* modifier must match the number of source2045operands. The first value controls src0, the second value controls src1 and so on.2046 2047The value 0 indicates the low bits, the value 1 indicates the high 16 bits.2048 2049By default, low bits are used for all operands.2050 2051 =============================== ===================================================2052 Syntax Description2053 =============================== ===================================================2054 op_sel:[{0..1},{0..1},{0..1}] Select the location of each 16-bit source operand.2055 =============================== ===================================================2056 2057Note: numeric values may be specified as either2058:ref:`integer numbers<amdgpu_synid_integer_number>` or2059:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.2060 2061Examples:2062 2063.. parsed-literal::2064 2065 op_sel:[0,1]2066 2067.. _amdgpu_synid_mad_mix_op_sel_hi:2068 2069m_op_sel_hi2070~~~~~~~~~~~2071 2072Selects the size of source operands: either 32 bits or 16 bits.2073By default, 32 bits are used for all source operands.2074 2075The number of values specified by the *op_sel_hi* modifier must match the number of source2076operands. The first value controls src0, the second value controls src1 and so on.2077 2078The value 0 indicates 32 bits, the value 1 indicates 16 bits.2079 2080The location of 16 bits in the operand may be specified by2081:ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.2082 2083 ======================================== ========================================2084 Syntax Description2085 ======================================== ========================================2086 op_sel_hi:[{0..1},{0..1},{0..1}] Select the size of each source operand.2087 ======================================== ========================================2088 2089Note: numeric values may be specified as either2090:ref:`integer numbers<amdgpu_synid_integer_number>` or2091:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.2092 2093Examples:2094 2095.. parsed-literal::2096 2097 op_sel_hi:[1,1,1]2098 2099abs2100~~~2101 2102See a description :ref:`here<amdgpu_synid_abs>`.2103 2104neg2105~~~2106 2107See a description :ref:`here<amdgpu_synid_neg>`.2108 2109clamp2110~~~~~2111 2112See a description :ref:`here<amdgpu_synid_clamp>`.2113 2114VOP3P MFMA Modifiers2115--------------------2116 2117.. _amdgpu_synid_cbsz:2118 2119cbsz2120~~~~2121 2122Specifies a broadcast mode.2123 2124 =============================== ==================================================================2125 Syntax Description2126 =============================== ==================================================================2127 cbsz:[{0..7}] A broadcast mode.2128 =============================== ==================================================================2129 2130Note: numeric value may be specified as either2131an :ref:`integer number<amdgpu_synid_integer_number>` or2132an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.2133 2134.. _amdgpu_synid_abid:2135 2136abid2137~~~~2138 2139Specifies matrix A group select.2140 2141 =============================== ==================================================================2142 Syntax Description2143 =============================== ==================================================================2144 abid:[{0..15}] Matrix A group select id.2145 =============================== ==================================================================2146 2147Note: numeric value may be specified as either2148an :ref:`integer number<amdgpu_synid_integer_number>` or2149an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.2150 2151.. _amdgpu_synid_blgp:2152 2153blgp2154~~~~2155 2156Specifies matrix B lane group pattern.2157 2158 =============================== ==================================================================2159 Syntax Description2160 =============================== ==================================================================2161 blgp:[{0..7}] Matrix B lane group pattern.2162 =============================== ==================================================================2163 2164Note: numeric value may be specified as either2165an :ref:`integer number<amdgpu_synid_integer_number>` or2166an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.2167 2168.. _amdgpu_synid_mfma_neg:2169 2170neg2171~~~2172 2173Indicates operands that must be negated before the operation.2174The number of values specified by this modifier must match the number of source2175operands. The first value controls src0, the second value controls src1 and so on.2176 2177The value 0 indicates that the corresponding operand value is used unmodified,2178the value 1 indicates that the operand value must be negated before the operation.2179 2180By default, operand values are used unmodified.2181 2182 =============================== ==================================================================2183 Syntax Description2184 =============================== ==================================================================2185 neg:[{0..1},{0..1},{0..1}] Select operands which must be negated before the operation.2186 =============================== ==================================================================2187 2188Note: numeric values may be specified as either2189:ref:`integer numbers<amdgpu_synid_integer_number>` or2190:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.2191 2192Examples:2193 2194.. parsed-literal::2195 2196 neg:[0,1,1]2197