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1.. _irtranslator:2 3IRTranslator4============5 6.. contents::7 :local:8 9This pass translates the input LLVM-IR ``Function`` to a :doc:`GMIR`10``MachineFunction``. This is typically a direct translation but does11occasionally get a bit more involved. For example:12 13.. code-block:: llvm14 15 %2 = add i32 %0, %116 17becomes:18 19.. code-block:: none20 21 %2:_(s32) = G_ADD %0:_(s32), %1:_(s32)22 23whereas24 25.. code-block:: llvm26 27 call i32 @puts(i8* %cast210)28 29is translated according to the ABI rules of the target.30 31.. note::32 33 The currently implemented portion of the :doc:`../LangRef` is sufficient for34 many compilations but it is not 100% complete. Users seeking to compile35 LLVM-IR containing some of the rarer features may need to implement the36 translation.37 38Target Intrinsics39-----------------40 41There has been some (off-list) debate about whether to add target hooks for42translating target intrinsics. Among those who discussed it, it was generally43agreed that the IRTranslator should be able to lower target intrinsics in a44customizable way but no work has happened to implement this at the time of45writing.46 47.. _translator-call-lower:48 49Translating Function Calls50--------------------------51 52The ``IRTranslator`` also implements the ABI's calling convention by lowering53calls, returns, and arguments to the appropriate physical register usage and54instruction sequences. This is achieved using the ``CallLowering`` interface,55which provides several hooks that targets should implement:56``lowerFormalArguments``, ``lowerReturn``, ``lowerCall`` etc.57 58In essence, all of these hooks need to find a way to move the argument/return59values between the virtual registers used in the rest of the function and either60physical registers or the stack, as dictated by the ABI. This may involve61splitting large types into smaller ones, introducing sign/zero extensions etc.62In order to share as much of this code as possible between the different63backends, ``CallLowering`` makes available a few helpers and interfaces:64 65* ``ArgInfo`` - used for formal arguments, but also return values, actual66 arguments and call results; contains info such as the IR type, the virtual67 registers etc; large values will likely have to be split into several68 ``ArgInfo`` objects (``CallLowering::splitToValueTypes`` can help with that);69 70* ``ValueAssigner`` - uses a ``CCAssignFn``, usually generated by TableGen (see71 :ref:`backend-calling-convs`), to decide where to put each72 ``ArgInfo`` (physical register or stack); backends can use the provided73 ``IncomingValueAssigner`` (for formal arguments and call results) and74 ``OutgoingValueAssigner`` (for actual arguments and function returns), but75 it's also possible to subclass them;76 77* ``ValueHandler`` - inserts the necessary instructions for putting each value78 where it belongs; it has pure virtual methods for assigning values to79 registers or to addresses, and a host of other helpers;80 81* ``determineAndHandleAssignments`` (or for more fine grained control,82 ``determineAssignments`` and ``handleAssignments``) - contains some boilerplate83 for invoking a given ``ValueAssigner`` and ``ValueHandler`` on a series of84 ``ArgInfo`` objects.85 86.. _irtranslator-aggregates:87 88Aggregates89^^^^^^^^^^90 91.. caution::92 93 This has changed since it was written and is no longer accurate. It has not94 been refreshed in this pass of improving the documentation as I haven't95 worked much in this part of the codebase and it should have attention from96 someone more knowledgeable about it.97 98Aggregates are lowered into multiple virtual registers, similar to99SelectionDAG's multiple vregs via ``GetValueVTs``.100 101``TODO``:102As some of the bits are undef (padding), we should consider augmenting the103representation with additional metadata (in effect, caching computeKnownBits104information on vregs).105See `PR26161 <https://llvm.org/PR26161>`_: [GlobalISel] Value to vreg during106IR to MachineInstr translation for aggregate type107 108.. _irtranslator-constants:109 110Translation of Constants111------------------------112 113Constant operands are translated as a use of a virtual register that is defined114by a ``G_CONSTANT`` or ``G_FCONSTANT`` instruction. These instructions are115placed in the entry block to allow them to be subject to the continuous CSE116implementation (``CSEMIRBuilder``). Their debug location information is removed117to prevent this from confusing debuggers.118 119This is beneficial as it allows us to fold constants into immediate operands120during :ref:`instructionselect`, while still avoiding redundant materializations121for expensive non-foldable constants. However, this can lead to unnecessary122spills and reloads in an -O0 pipeline, as these virtual registers can have long123live ranges. This can be mitigated by running a `localizer <https://github.com/llvm/llvm-project/blob/main/llvm/lib/CodeGen/GlobalISel/Localizer.cpp>`_124after the translator.125