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1=============================2User Guide for RISC-V Target3=============================4 5.. contents::6 :local:7 8Introduction9============10 11The RISC-V target provides code generation for processors implementing12supported variations of the RISC-V specification. It lives in the13``llvm/lib/Target/RISCV`` directory.14 15Specification Documents16=======================17 18There have been a number of revisions to the RISC-V specifications. LLVM aims19to implement the most recent ratified version of the standard RISC-V base ISAs20and ISA extensions with pragmatic variances. The most recent specification can21be found at: https://github.com/riscv/riscv-isa-manual/releases/.22 23`The official RISC-V International specification page24<https://riscv.org/technical/specifications/>`__. is also worth checking, but25tends to significantly lag the specifications linked above. Make sure to check26the `wiki for not yet integrated extensions27<https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions>`__ and note28that in addition, we sometimes carry support for extensions that have not yet29been ratified (these will be marked as experimental - see below) and support30various vendor-specific extensions (see below).31 32The current known variances from the specification are:33 34* Unconditionally allowing instructions from zifencei, zicsr, zicntr, and35 zihpm without gating them on the extensions being enabled. Previous36 revisions of the specification included these instructions in the base37 ISA, and we preserve this behavior to avoid breaking existing code. If38 a future revision of the specification reuses these opcodes for other39 extensions, we may need to reevaluate this choice, and thus recommend40 users migrate build systems so as not to rely on this.41* Allowing CSRs to be named without gating on specific extensions. This42 applies to all CSR names, not just those in zicsr, zicntr, and zihpm.43* The ordering of ``z*``, ``s*``, and ``x*`` prefixed extension names is not44 enforced in user-specified ISA naming strings (e.g. ``-march``).45 46We are actively deciding not to support multiple specification revisions47at this time. We acknowledge a likely future need, but actively defer the48decisions making around handling this until we have a concrete example of49real hardware having shipped and an incompatible change to the50specification made afterwards.51 52Base ISAs53=========54 55The specification defines five base instruction sets: RV32I, RV32E, RV64I,56RV64E, and RV128I. Currently, LLVM fully supports RV32I, and RV64I. RV32E and57RV64E are supported by the assembly-based tools only. RV128I is not supported.58 59To specify the target triple:60 61 .. table:: RISC-V Architectures62 63 ============ ==============================================================64 Architecture Description65 ============ ==============================================================66 ``riscv32`` RISC-V with XLEN=32 (i.e. RV32I or RV32E)67 ``riscv64`` RISC-V with XLEN=64 (i.e. RV64I or RV64E)68 ============ ==============================================================69 70To select an E variant ISA (e.g. RV32E instead of RV32I), use the base71architecture string (e.g. ``riscv32``) with the extension ``e``.72 73Profiles74========75 76Supported profile names can be passed using ``-march`` instead of a standard77ISA naming string. Currently supported profiles:78 79* ``rvi20u32``80* ``rvi20u64``81* ``rva20u64``82* ``rva20s64``83* ``rva22u64``84* ``rva22s64``85* ``rva23u64``86* ``rva23s64``87* ``rvb23u64``88* ``rvb23s64``89 90Note that you can also append additional extension names to be enabled, e.g.91``rva20u64_zicond`` will enable the ``zicond`` extension in addition to those92in the ``rva20u64`` profile.93 94Profiles that are not yet ratified cannot be used unless95``-menable-experimental-extensions`` (or equivalent for other tools) is96specified. This applies to the following profiles:97 98* ``rvm23u32``99 100.. _riscv-extensions:101 102Extensions103==========104 105The following table provides a status summary for extensions which have been106ratified and thus have finalized specifications. When relevant, detailed notes107on support follow.108 109 .. table:: Ratified Extensions by Status110 111 ================ =================================================================112 Extension Status113 ================ =================================================================114 ``A`` Supported115 ``B`` Supported116 ``C`` Supported117 ``D`` Supported118 ``F`` Supported119 ``E`` Supported (`See note <#riscv-rve-note>`__)120 ``H`` Assembly Support121 ``M`` Supported122 ``Q`` Assembly Support123 ``Sdext`` Assembly Support (`See note <#riscv-debug-specification-note>`__)124 ``Sdtrig`` Assembly Support (`See note <#riscv-debug-specification-note>`__)125 ``Sha`` Supported126 ``Shcounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)127 ``Shgatpa`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)128 ``Shlcofideleg`` Supported129 ``Shtvala`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)130 ``Shvsatpa`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)131 ``Shvstvala`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)132 ``Shvstvecd`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)133 ``Smaia`` Supported134 ``Smcdeleg`` Supported135 ``Smcntrpmf`` Supported136 ``Smcsrind`` Supported137 ``Smctr`` Assembly Support138 ``Smdbltrp`` Supported139 ``Smepmp`` Supported140 ``Smmpm`` Supported141 ``Smnpm`` Supported142 ``Smrnmi`` Supported143 ``Smstateen`` Assembly Support144 ``Ssaia`` Supported145 ``Ssccfg`` Supported146 ``Ssccptr`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)147 ``Sscofpmf`` Assembly Support148 ``Sscounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)149 ``Sscsrind`` Supported150 ``Ssctr`` Assembly Support151 ``Ssdbltrp`` Supported152 ``Ssnpm`` Supported153 ``Sspm`` Supported154 ``Ssqosid`` Assembly Support155 ``Ssstateen`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)156 ``Ssstrict`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)157 ``Sstc`` Assembly Support158 ``Sstvala`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)159 ``Sstvecd`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)160 ``Ssu64xl`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)161 ``Supm`` Supported162 ``Svade`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)163 ``Svadu`` Assembly Support164 ``Svbare`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)165 ``Svinval`` Assembly Support166 ``Svnapot`` Assembly Support167 ``Svpbmt`` Supported168 ``Svvptc`` Supported169 ``V`` Supported170 ``Za128rs`` Supported (`See note <#riscv-profiles-extensions-note>`__)171 ``Za64rs`` Supported (`See note <#riscv-profiles-extensions-note>`__)172 ``Zaamo`` Assembly Support173 ``Zabha`` Supported174 ``Zacas`` Supported (`See note <#riscv-zacas-note>`__)175 ``Zalrsc`` Assembly Support176 ``Zama16b`` Supported (`See note <#riscv-profiles-extensions-note>`__)177 ``Zawrs`` Assembly Support178 ``Zba`` Supported179 ``Zbb`` Supported180 ``Zbc`` Supported181 ``Zbkb`` Supported (`See note <#riscv-scalar-crypto-note1>`__)182 ``Zbkc`` Supported183 ``Zbkx`` Supported (`See note <#riscv-scalar-crypto-note1>`__)184 ``Zbs`` Supported185 ``Zca`` Supported186 ``Zcb`` Supported187 ``Zcd`` Supported188 ``Zcf`` Supported189 ``Zclsd`` Assembly Support190 ``Zcmop`` Supported191 ``Zcmp`` Supported192 ``Zcmt`` Assembly Support193 ``Zdinx`` Supported194 ``Zfa`` Supported195 ``Zfbfmin`` Supported196 ``Zfh`` Supported197 ``Zfhmin`` Supported198 ``Zfinx`` Supported199 ``Zhinx`` Supported200 ``Zhinxmin`` Supported201 ``Zic64b`` Supported (`See note <#riscv-profiles-extensions-note>`__)202 ``Zicbom`` Assembly Support203 ``Zicbop`` Supported204 ``Zicboz`` Assembly Support205 ``Ziccamoa`` Supported (`See note <#riscv-profiles-extensions-note>`__)206 ``Ziccamoc`` Supported (`See note <#riscv-profiles-extensions-note>`__)207 ``Ziccif`` Supported (`See note <#riscv-profiles-extensions-note>`__)208 ``Zicclsm`` Supported (`See note <#riscv-profiles-extensions-note>`__)209 ``Ziccrse`` Supported (`See note <#riscv-profiles-extensions-note>`__)210 ``Zicntr`` (`See Note <#riscv-i2p1-note>`__)211 ``Zicond`` Supported212 ``Zicsr`` (`See Note <#riscv-i2p1-note>`__)213 ``Zifencei`` (`See Note <#riscv-i2p1-note>`__)214 ``Zihintntl`` Supported215 ``Zihintpause`` Assembly Support216 ``Zihpm`` (`See Note <#riscv-i2p1-note>`__)217 ``Zilsd`` Supported218 ``Zimop`` Supported219 ``Zkn`` Supported220 ``Zknd`` Supported (`See note <#riscv-scalar-crypto-note2>`__)221 ``Zkne`` Supported (`See note <#riscv-scalar-crypto-note2>`__)222 ``Zknh`` Supported (`See note <#riscv-scalar-crypto-note2>`__)223 ``Zksed`` Supported (`See note <#riscv-scalar-crypto-note2>`__)224 ``Zksh`` Supported (`See note <#riscv-scalar-crypto-note2>`__)225 ``Zk`` Supported226 ``Zkr`` Supported227 ``Zks`` Supported228 ``Zkt`` Supported229 ``Zmmul`` Supported230 ``Ztso`` Supported231 ``Zvbb`` Supported232 ``Zvbc`` Supported (`See note <#riscv-vector-crypto-note>`__)233 ``Zve32x`` (`Partially <#riscv-vlen-32-note>`__) Supported234 ``Zve32f`` (`Partially <#riscv-vlen-32-note>`__) Supported235 ``Zve64x`` Supported236 ``Zve64f`` Supported237 ``Zve64d`` Supported238 ``Zvfbfa`` Assembly Support239 ``Zvfbfmin`` Supported240 ``Zvfbfwma`` Supported241 ``Zvfh`` Supported242 ``Zvfhmin`` Supported243 ``Zvfofp8min`` Assembly Support244 ``Zvkb`` Supported245 ``Zvkg`` Supported (`See note <#riscv-vector-crypto-note>`__)246 ``Zvkn`` Supported (`See note <#riscv-vector-crypto-note>`__)247 ``Zvknc`` Supported (`See note <#riscv-vector-crypto-note>`__)248 ``Zvkned`` Supported (`See note <#riscv-vector-crypto-note>`__)249 ``Zvkng`` Supported (`See note <#riscv-vector-crypto-note>`__)250 ``Zvknha`` Supported (`See note <#riscv-vector-crypto-note>`__)251 ``Zvknhb`` Supported (`See note <#riscv-vector-crypto-note>`__)252 ``Zvks`` Supported (`See note <#riscv-vector-crypto-note>`__)253 ``Zvksc`` Supported (`See note <#riscv-vector-crypto-note>`__)254 ``Zvksed`` Supported (`See note <#riscv-vector-crypto-note>`__)255 ``Zvksg`` Supported (`See note <#riscv-vector-crypto-note>`__)256 ``Zvksh`` Supported (`See note <#riscv-vector-crypto-note>`__)257 ``Zvkt`` Supported258 ``Zvl32b`` (`Partially <#riscv-vlen-32-note>`__) Supported259 ``Zvl64b`` Supported260 ``Zvl128b`` Supported261 ``Zvl256b`` Supported262 ``Zvl512b`` Supported263 ``Zvl1024b`` Supported264 ``Zvl2048b`` Supported265 ``Zvl4096b`` Supported266 ``Zvl8192b`` Supported267 ``Zvl16384b`` Supported268 ``Zvl32768b`` Supported269 ``Zvl65536b`` Supported270 ================ =================================================================271 272Assembly Support273 LLVM supports the associated instructions in assembly. All assembly related tools (e.g. assembler, disassembler, llvm-objdump, etc..) are supported. Compiler and linker will accept extension names, and linked binaries will contain appropriate ELF flags and attributes to reflect use of named extension.274 275Supported276 Fully supported by the compiler. This includes everything in Assembly Support, along with - if relevant - C language intrinsics for the instructions and pattern matching by the compiler to recognize idiomatic patterns which can be lowered to the associated instructions.277 278.. _riscv-rve-note:279 280``E``281 Support of RV32E/RV64E and ilp32e/lp64e ABIs are experimental. To be compatible with the implementation of ilp32e in GCC, we don't use aligned registers to pass variadic arguments. Furthermore, we set the stack alignment to 4 bytes for types with length of 2*XLEN.282 283.. _riscv-scalar-crypto-note1:284 285``Zbkb``, ``Zbkx``286 Pattern matching support for these instructions is incomplete.287 288.. _riscv-scalar-crypto-note2:289 290``Zknd``, ``Zkne``, ``Zknh``, ``Zksed``, ``Zksh``291 No pattern matching exists. As a result, these instructions can only be used from assembler or via intrinsic calls.292 293.. _riscv-vector-crypto-note:294 295``Zvbc``, ``Zvkg``, ``Zvkn``, ``Zvknc``, ``Zvkned``, ``Zvkng``, ``Zvknha``, ``Zvknhb``, ``Zvks``, ``Zvks``, ``Zvks``, ``Zvksc``, ``Zvksed``, ``Zvksg``, ``Zvksh``.296 No pattern matching exists. As a result, these instructions can only be used from assembler or via intrinsic calls.297 298.. _riscv-vlen-32-note:299 300``Zve32x``, ``Zve32f``, ``Zvl32b``301 LLVM currently assumes a minimum VLEN (vector register width) of 64 bits during compilation, and as a result ``Zve32x`` and ``Zve32f`` are supported only for VLEN>=64. Assembly support doesn't have this restriction.302 303.. _riscv-i2p1-note:304 305``Zicntr``, ``Zicsr``, ``Zifencei``, ``Zihpm``306 Between versions 2.0 and 2.1 of the base I specification, a backwards incompatible change was made to remove selected instructions and CSRs from the base ISA. These instructions were grouped into a set of new extensions, but were no longer required by the base ISA. This change is partially described in "Preface to Document Version 20190608-Base-Ratified" from the specification document (the ``zicntr`` and ``zihpm`` bits are not mentioned). LLVM currently implements version 2.1 of the base specification. To maintain compatibility, instructions from these extensions are accepted without being in the ``-march`` string. LLVM also allows the explicit specification of the extensions in an ``-march`` string.307 308.. _riscv-profiles-extensions-note:309 310``Za128rs``, ``Za64rs``, ``Zama16b``, ``Zic64b``, ``Ziccamoa``, ``Ziccamoc``, ``Ziccif``, ``Zicclsm``, ``Ziccrse``, ``Shcounterenvw``, ``Shgatpa``, ``Shtvala``, ``Shvsatpa``, ``Shvstvala``, ``Shvstvecd``, ``Ssccptr``, ``Sscounterenw``, ``Ssstateen``, ``Ssstrict``, ``Sstvala``, ``Sstvecd``, ``Ssu64xl``, ``Svade``, ``Svbare``311 These extensions are defined as part of the `RISC-V Profiles specification <https://github.com/riscv/riscv-profiles/releases/tag/v1.0>`__. They do not introduce any new features themselves, but instead describe existing hardware features.312 313.. _riscv-debug-specification-note:314 315``Sdext``, ``Sdtrig`` `The RISC-V Debug Specification <https://github.com/riscv/riscv-debug-spec/releases/download/1.0/riscv-debug-specification.pdf>`__.316 317.. _riscv-zacas-note:318 319``Zacas``320 The compiler will not generate amocas.d on RV32 or amocas.q on RV64 due to ABI compatibility. These can only be used in the assembler.321 322Atomics ABIs323============324 325At the time of writing there are three atomics mappings (ABIs) `defined for RISC-V <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#tag_riscv_atomic_abi-14-uleb128version>`__. As of LLVM 19, LLVM defaults to "A6S", which is compatible with both the original "A6" and the future "A7" ABI. See `the psABI atomics document <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-atomic.adoc>`__ for more information on these mappings.326 327Note that although the "A6S" mapping is used, the ELF attribute recording the mapping isn't currently emitted by default due to a bug causing a crash in older versions of binutils when processing files containing this attribute.328 329Experimental Extensions330=======================331 332LLVM supports (to various degrees) a number of experimental extensions. All experimental extensions have ``experimental-`` as a prefix. There is explicitly no compatibility promised between versions of the toolchain, and regular users are strongly advised *not* to make use of experimental extensions before they reach ratification.333 334The primary goal of experimental support is to assist in the process of ratification by providing an existence proof of an implementation, and simplifying efforts to validate the value of a proposed extension against large code bases. Experimental extensions are expected to either transition to ratified status, or be eventually removed. The decision on whether to accept an experimental extension is currently done on an entirely case by case basis; if you want to propose one, attending the bi-weekly RISC-V sync-up call is strongly advised.335 336``experimental-zalasr``337 LLVM implements the `0.9 draft specification <https://github.com/riscv/riscv-zalasr/releases/tag/v0.9>`__.338 339``experimental-zibi``340 LLVM implements the `0.1 release specification <https://github.com/riscv/zibi/releases/tag/v0.1.0>`__.341 342``experimental-zicfilp``, ``experimental-zicfiss``343 LLVM implements the `1.0 release specification <https://github.com/riscv/riscv-cfi/releases/tag/v1.0>`__.344 345``experimental-zvbc32e``, ``experimental-zvkgs``346 LLVM implements the `0.7 release specification <https://github.com/user-attachments/files/16450464/riscv-crypto-spec-vector-extra_v0.0.7.pdf>`__.347 348``experimental-svukte``349 LLVM implements the `0.3 draft specification <https://github.com/riscv/riscv-isa-manual/pull/1564>`__.350 351``experimental-zvqdotq``352 LLVM implements the `0.0.1 draft specification <https://github.com/riscv/riscv-dot-product/releases/tag/v0.0.1>`__.353 354``experimental-smpmpmt``355 LLVM implements the `0.6 draft specification <https://github.com/riscv/riscv-isa-manual/blob/smpmpmt/src/smpmpmt.adoc>`__.356 357To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`.358 359Vendor Extensions360=================361 362Vendor extensions are extensions which are not standardized by RISC-V International, and are instead defined by a hardware vendor. The term vendor extension roughly parallels the definition of a `non-standard` extension from Section 1.3 of the Volume I: RISC-V Unprivileged ISA specification. In particular, we expect to eventually accept both `custom` extensions and `non-conforming` extensions.363 364Inclusion of a vendor extension will be considered on a case by case basis. All proposals should be brought to the bi-weekly RISC-V sync calls for discussion. For a general idea of the factors likely to be considered, please see the `Clang documentation <https://clang.llvm.org/get_involved.html>`__.365 366It is our intention to follow the naming conventions described in `riscv-non-isa/riscv-toolchain-conventions <https://github.com/riscv-non-isa/riscv-toolchain-conventions#conventions-for-vendor-extensions>`__. Exceptions to this naming will need to be strongly motivated.367 368The current vendor extensions supported are:369 370``XTHeadBa``371 LLVM implements `the THeadBa (address-generation) vendor-defined instructions specified in <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf>`__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification.372 373``XTHeadBb``374 LLVM implements `the THeadBb (basic bit-manipulation) vendor-defined instructions specified in <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf>`__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification.375 376``XTHeadBs``377 LLVM implements `the THeadBs (single-bit operations) vendor-defined instructions specified in <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf>`__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification.378 379``XTHeadCondMov``380 LLVM implements `the THeadCondMov (conditional move) vendor-defined instructions specified in <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf>`__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification.381 382``XTHeadCmo``383 LLVM implements `the THeadCmo (cache management operations) vendor-defined instructions specified in <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf>`__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification.384 385``XTHeadFMemIdx``386 LLVM implements `the THeadFMemIdx (indexed memory operations for floating point) vendor-defined instructions specified in <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf>`__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification.387 388``XTheadMac``389 LLVM implements `the XTheadMac (multiply-accumulate instructions) vendor-defined instructions specified in <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf>`__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification.390 391``XTHeadMemIdx``392 LLVM implements `the THeadMemIdx (indexed memory operations) vendor-defined instructions specified in <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf>`__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification.393 394``XTHeadMemPair``395 LLVM implements `the THeadMemPair (two-GPR memory operations) vendor-defined instructions specified in <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf>`__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification.396 397``XTHeadSync``398 LLVM implements `the THeadSync (multi-core synchronization instructions) vendor-defined instructions specified in <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf>`__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification.399 400``XTHeadVdot``401 LLVM implements `version 1.0.0 of the THeadV-family custom instructions specification <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.0/xthead-2022-12-04-2.2.0.pdf>`__ by T-HEAD of Alibaba. All instructions are prefixed with `th.` as described in the specification, and the riscv-toolchain-convention document linked above.402 403``XVentanaCondOps``404 LLVM implements `version 1.0.0 of the VTx-family custom instructions specification <https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf>`__ by Ventana Micro Systems. All instructions are prefixed with `vt.` as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for riscv64 at this time.405 406``Xsfmm*``407 LLVM implements `version 0.6 of the Xsfmm Family of Attached Matrix Extensions Specification <https://www.sifive.com/document-file/xsfmm-matrix-extensions-specification>`__ by SiFive. All instructions are prefixed with `sf.` as described in the specification.408 409``XSfvcp``410 LLVM implements `version 1.1.0 of the SiFive Vector Coprocessor Interface (VCIX) Software Specification <https://sifive.cdn.prismic.io/sifive/Zn3m1R5LeNNTwnLS_vcix-spec-software-v1p1.pdf>`__ by SiFive. All instructions are prefixed with `sf.vc.` as described in the specification, and the riscv-toolchain-convention document linked above.411 412``Xsfvfexp16e``, ``Xsfvfbfexp16e``, and ``Xsfvfexp32e``413 LLVM implements `version 0.5 of the Vector Exponential Extension Specification <https://www.sifive.com/document-file/exponential-function-instruction-xsfvfexp32e-xsfvf>`__ by SiFive. All instructions are prefixed with `sf.` as described in the specification linked above.414 415``Xsfvfexpa`` and ``Xsfvfexpa64e``416 LLVM implements `version 0.2 of the Vector Exponential Approximation Extension Specification <https://www.sifive.com/document-file/exponential-approximation-instruction-xsfvfexpa-ex>`__ by SiFive. All instructions are prefixed with `sf.` as described in the specification linked above.417 418``XSfvqmaccdod``, ``XSfvqmaccqoq``419 LLVM implements `version 1.1.0 of the SiFive Int8 Matrix Multiplication Extensions Specification <https://sifive.cdn.prismic.io/sifive/1a2ad85b-d818-49f7-ba83-f51f1731edbe_int8-matmul-spec.pdf>`__ by SiFive. All instructions are prefixed with `sf.` as described in the specification linked above.420 421``Xsfvfnrclipxfqf``422 LLVM implements `version 1.0.0 of the FP32-to-int8 Ranged Clip Instructions Extension Specification <https://sifive.cdn.prismic.io/sifive/0aacff47-f530-43dc-8446-5caa2260ece0_xsfvfnrclipxfqf-spec.pdf>`__ by SiFive. All instructions are prefixed with `sf.` as described in the specification linked above.423 424``Xsfvfwmaccqqq``425 LLVM implements `version 1.0.0 of the Matrix Multiply Accumulate Instruction Extension Specification <https://sifive.cdn.prismic.io/sifive/c391d53e-ffcf-4091-82f6-c37bf3e883ed_xsfvfwmaccqqq-spec.pdf>`__ by SiFive. All instructions are prefixed with `sf.` as described in the specification linked above.426 427``XCVbitmanip``428 LLVM implements `version 1.0.0 of the CORE-V Bit Manipulation custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst>`__ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification.429 430``XCVelw``431 LLVM implements `version 1.0.0 of the CORE-V Event load custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst>`__ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.432 433``XCVmac``434 LLVM implements `version 1.0.0 of the CORE-V Multiply-Accumulate (MAC) custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/4f024fe4b15a68b76615b0630c07a6745c620da7/docs/source/instruction_set_extensions.rst>`__ by OpenHW Group. All instructions are prefixed with `cv.mac` as described in the specification. These instructions are only available for riscv32 at this time.435 436``XCVmem``437 LLVM implements `version 1.0.0 of the CORE-V Post-Increment load and stores custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst>`__ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.438 439``XCValu``440 LLVM implements `version 1.0.0 of the Core-V ALU custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/4f024fe4b15a68b76615b0630c07a6745c620da7/docs/source/instruction_set_extensions.rst>`__ by Core-V. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.441 442``XCVsimd``443 LLVM implements `version 1.0.0 of the CORE-V SIMD custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/cv32e40p_v1.3.2/docs/source/instruction_set_extensions.rst>`__ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification.444 445``XCVbi``446 LLVM implements `version 1.0.0 of the CORE-V immediate branching custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/cv32e40p_v1.3.2/docs/source/instruction_set_extensions.rst>`__ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.447 448``XSiFivecdiscarddlone``449 LLVM implements `the SiFive sf.cdiscard.d.l1 instruction specified in <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.450 451``XSiFivecflushdlone``452 LLVM implements `the SiFive sf.cflush.d.l1 instruction specified in <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.453 454``XSfcease``455 LLVM implements `the SiFive sf.cease instruction specified in <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.456 457``Xwchc``458 LLVM implements `the custom compressed opcodes present in some QingKe cores` by WCH / Nanjing Qinheng Microelectronics. The vendor refers to these opcodes by the name "XW".459 460``experimental-Xqccmp``461 LLVM implements `version 0.3 of the 16-bit Push/Pop instructions and double-moves extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqccmp_extension-0.3.0>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification.462 463``experimental-Xqcia``464 LLVM implements `version 0.7 of the Qualcomm uC Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.465 466``experimental-Xqciac``467 LLVM implements `version 0.3 of the Qualcomm uC Load-Store Address Calculation extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.468 469``experimental-Xqcibi``470 LLVM implements `version 0.2 of the Qualcomm uC Branch Immediate extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.471 472``experimental-Xqcibm``473 LLVM implements `version 0.8 of the Qualcomm uC Bit Manipulation extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.474 475``experimental-Xqcicli``476 LLVM implements `version 0.3 of the Qualcomm uC Conditional Load Immediate extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.477 478``experimental-Xqcicm``479 LLVM implements `version 0.2 of the Qualcomm uC Conditional Move extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.480 481``experimental-Xqcics``482 LLVM implements `version 0.2 of the Qualcomm uC Conditional Select extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.483 484``experimental-Xqcicsr``485 LLVM implements `version 0.4 of the Qualcomm uC CSR extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.486 487``experimental-Xqciint``488 LLVM implements `version 0.10 of the Qualcomm uC Interrupts extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.489 490``experimental-Xqciio``491 LLVM implements `version 0.1 of the Qualcomm uC External Input Output extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.492 493``experimental-Xqcilb``494 LLVM implements `version 0.2 of the Qualcomm uC Long Branch extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.495 496``experimental-Xqcili``497 LLVM implements `version 0.2 of the Qualcomm uC Load Large Immediate extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.498 499``experimental-Xqcilia``500 LLVM implements `version 0.2 of the Qualcomm uC Large Immediate Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.501 502``experimental-Xqcilo``503 LLVM implements `version 0.3 of the Qualcomm uC Large Offset Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.504 505``experimental-Xqcilsm``506 LLVM implements `version 0.6 of the Qualcomm uC Load Store Multiple extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.507 508``experimental-Xqcisim``509 LLVM implements `version 0.2 of the Qualcomm uC Simulation Hint extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.510 511``experimental-Xqcisls``512 LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.513 514``experimental-Xqcisync``515 LLVM implements `version 0.3 of the Qualcomm uC Sync Delay extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.516 517``Xmipscbop``518 LLVM implements MIPS prefetch extension `p8700 processor <https://mips.com/products/hardware/p8700/>`__ by MIPS.519 520``Xmipscmov``521 LLVM implements conditional move for the `p8700 processor <https://mips.com/products/hardware/p8700/>`__ by MIPS.522 523``Xmipslsp``524 LLVM implements load/store pair instructions for the `p8700 processor <https://mips.com/products/hardware/p8700/>`__ by MIPS.525 526``experimental-XRivosVisni``527 LLVM implements `version 0.1 of the Rivos Vector Integer Small New Instructions extension specification <https://github.com/rivosinc/rivos-custom-extensions>`__.528 529``experimental-XRivosVizip``530 LLVM implements `version 0.1 of the Rivos Vector Register Zips extension specification <https://github.com/rivosinc/rivos-custom-extensions>`__.531 532``XAndesPerf``533 LLVM implements `version 5.0.0 of the Andes Performance Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.534 535``XAndesBFHCvt``536 LLVM implements `version 5.0.0 of the Andes Scalar BFLOAT16 Conversion Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.537 538``XAndesVBFHCvt``539 LLVM implements `version 5.0.0 of the Andes Vector BFLOAT16 Conversion Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.540 541``XAndesVSINTH``542 LLVM implements `version 5.0.0 of the Andes Vector Small Int Handling Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.543 544``XAndesVSINTLoad``545 LLVM implements `version 5.0.0 of the Andes Vector INT4 Load Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.546 547``XAndesVPackFPH``548 LLVM implements `version 5.0.0 of the Andes Vector Packed FP16 Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.549 550``XAndesVDot``551 LLVM implements `version 5.0.0 of the Andes Vector Dot Product Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.552 553``XSMTVDot``554 SpacemiT defines `Intrinsic Matrix Extension (IME) specification <https://github.com/space-mit/riscv-ime-extension-spec/releases/tag/v0429>`__.555 LLVM implement the hardware-adapted subset for SpacemiT X60, defined in the `feature document <https://developer.spacemit.com/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb#2.1>`__ by SpacemiT. All instructions are prefixed with `smt.` as described in the implementation guide. Note that this implemented subset is `version 1.0.0 of the SpacemiT Vector Dot Product Extension specification`, which is strictly a subset of the full IME specification to reflect the capabilities of SpacemiT X60 hardware correctly.556 557Experimental C Intrinsics558=========================559 560In some cases an extension is non-experimental but the C intrinsics for that561extension are still experimental. To use C intrinsics for such an extension562from `clang`, you must add `-menable-experimental-extensions` to the command563line. This currently applies to the following extensions:564 565No extensions have experimental intrinsics.566 567Long (>32-bit) Instruction Support568==================================569 570RISC-V is a variable-length ISA, but the standard currently only defines 16- and 32-bit instructions. The specification describes longer instruction encodings, but these are not ratified.571 572The LLVM disassembler, `llvm-objdump`, does use the longer instruction encodings described in the specification to guess the instruction length (up to 176 bits) and will group the disassembly view of encoding bytes correspondingly.573 574The LLVM integrated assembler for RISC-V supports two different kinds of ``.insn`` directive, for assembling instructions that LLVM does not yet support:575 576* ``.insn type, args*`` which takes a known instruction type, and a list of fields. You are strongly recommended to use this variant of the directive if your instruction fits an existing instruction type.577* ``.insn [ length , ] encoding`` which takes an (optional) explicit length (in bytes) and a raw encoding for the instruction. When given an explicit length, this variant can encode instructions up to 64 bits long. The encoding part of the directive must be given all bits for the instruction, none are filled in for the user. When used without the optional length, this variant of the directive will use the LSBs of the raw encoding to work out if an instruction is 16 or 32 bits long. LLVM does not infer that an instruction might be longer than 32 bits - in this case, the user must give the length explicitly.578 579It is strongly recommended to use the ``.insn`` directive for assembling unsupported instructions instead of ``.word`` or ``.hword``, because it will produce the correct mapping symbols to mark the word as an instruction, not data.580 581Global Pointer (GP) Relaxation and the Small Data Limit582=======================================================583 584Some of the RISC-V psABI variants reserve ``gp`` (``x3``) for use as a "Global Pointer", to make generating data addresses more efficient.585 586To use this functionality, you need to be doing all of the following:587 588* Use the ``medlow`` (aka ``small``) code model;589* Not use the ``gp`` register for any other uses (some platforms use it for the shadow stack and others as a temporary -- as denoted by the ``Tag_RISCV_x3_reg_usage`` build attribute);590* Compile your objects with Clang's ``-mrelax`` option, to enable relaxation annotations on relocatable objects (this is the default, but ``-mno-relax`` disables these relaxation annotations);591* Compile for a position-dependent static executable (not a shared library, and ``-fno-PIC`` / ``-fno-pic`` / ``-fno-pie``); and592* Use LLD's ``--relax-gp`` option.593 594LLD will relax (rewrite) any code sequences that materialize an address within 2048 bytes of ``__global_pointer$`` (which will be defined if it is used and does not already exist) to instead generate the address using ``gp`` and the correct (signed) 12-bit immediate. This usually saves at least one instruction compared to materialising a full 32-bit address value.595 596There can only be one ``gp`` value in a process (as ``gp`` is not changed when calling into a function in a shared library), so the symbol is is only defined and this relaxation is only done for executables, and not for shared libraries. The linker expects executable startup code to put the value of ``__global_pointer$`` (from the executable) into ``gp`` before any user code is run.597 598Arguably, the most efficient use for this addressing mode is for smaller global variables, as larger global variables likely need many more loads or stores when they are being accessed anyway, so the cost of materializing the upper bits can be shared.599 600Therefore the compiler can place smaller global variables into sections with names starting with ``.sdata`` or ``.sbss`` (matching sections with names starting with ``.data`` and ``.bss`` respectively). LLD knows to define the ``global_pointer$`` symbol close to these sections, and to lay these sections out adjacent to the ``.data`` section.601 602Clang's ``-msmall-data-limit=`` option controls what the threshold size is (in bytes) for a global variable to be considered small. ``-msmall-data-limit=0`` disables the use of sections starting ``.sdata`` and ``.sbss``. The ``-msmall-data-limit=`` option will not move global variables that have an explicit data section, and will keep globals in separate sections if you are using ``-fdata-sections``.603 604The small data limit threshold is also used to separate small constants into sections with names starting with ``.srodata``. LLD does not place these with the ``.sdata`` and ``.sbss`` sections as ``.srodata`` sections are read only and the other two are writable. Instead the ``.srodata`` sections are placed adjacent to ``.rodata``.605 606Data suggests that these options can produce significant improvements across a range of benchmarks.607