2329 lines · cpp
1//===- lib/CodeGen/GlobalISel/GISelValueTracking.cpp --------------*- C++2//*-===//3//4// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.5// See https://llvm.org/LICENSE.txt for license information.6// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception7//8//===----------------------------------------------------------------------===//9//10/// Provides analysis for querying information about KnownBits during GISel11/// passes.12//13//===----------------------------------------------------------------------===//14#include "llvm/CodeGen/GlobalISel/GISelValueTracking.h"15#include "llvm/ADT/APFloat.h"16#include "llvm/ADT/FloatingPointMode.h"17#include "llvm/ADT/ScopeExit.h"18#include "llvm/ADT/StringExtras.h"19#include "llvm/Analysis/ValueTracking.h"20#include "llvm/Analysis/VectorUtils.h"21#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"22#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"23#include "llvm/CodeGen/GlobalISel/MachineFloatingPointPredicateUtils.h"24#include "llvm/CodeGen/GlobalISel/Utils.h"25#include "llvm/CodeGen/LowLevelTypeUtils.h"26#include "llvm/CodeGen/MachineFrameInfo.h"27#include "llvm/CodeGen/MachineInstr.h"28#include "llvm/CodeGen/MachineOperand.h"29#include "llvm/CodeGen/MachineRegisterInfo.h"30#include "llvm/CodeGen/Register.h"31#include "llvm/CodeGen/TargetLowering.h"32#include "llvm/CodeGen/TargetOpcodes.h"33#include "llvm/IR/ConstantRange.h"34#include "llvm/IR/DerivedTypes.h"35#include "llvm/IR/FMF.h"36#include "llvm/MC/TargetRegistry.h"37#include "llvm/Support/KnownBits.h"38#include "llvm/Support/KnownFPClass.h"39#include "llvm/Target/TargetMachine.h"40 41#define DEBUG_TYPE "gisel-known-bits"42 43using namespace llvm;44using namespace MIPatternMatch;45 46char llvm::GISelValueTrackingAnalysisLegacy::ID = 0;47 48INITIALIZE_PASS(GISelValueTrackingAnalysisLegacy, DEBUG_TYPE,49 "Analysis for ComputingKnownBits", false, true)50 51GISelValueTracking::GISelValueTracking(MachineFunction &MF, unsigned MaxDepth)52 : MF(MF), MRI(MF.getRegInfo()), TL(*MF.getSubtarget().getTargetLowering()),53 DL(MF.getFunction().getDataLayout()), MaxDepth(MaxDepth) {}54 55Align GISelValueTracking::computeKnownAlignment(Register R, unsigned Depth) {56 const MachineInstr *MI = MRI.getVRegDef(R);57 switch (MI->getOpcode()) {58 case TargetOpcode::COPY:59 return computeKnownAlignment(MI->getOperand(1).getReg(), Depth);60 case TargetOpcode::G_ASSERT_ALIGN: {61 // TODO: Min with source62 return Align(MI->getOperand(2).getImm());63 }64 case TargetOpcode::G_FRAME_INDEX: {65 int FrameIdx = MI->getOperand(1).getIndex();66 return MF.getFrameInfo().getObjectAlign(FrameIdx);67 }68 case TargetOpcode::G_INTRINSIC:69 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:70 case TargetOpcode::G_INTRINSIC_CONVERGENT:71 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:72 default:73 return TL.computeKnownAlignForTargetInstr(*this, R, MRI, Depth + 1);74 }75}76 77KnownBits GISelValueTracking::getKnownBits(MachineInstr &MI) {78 assert(MI.getNumExplicitDefs() == 1 &&79 "expected single return generic instruction");80 return getKnownBits(MI.getOperand(0).getReg());81}82 83KnownBits GISelValueTracking::getKnownBits(Register R) {84 const LLT Ty = MRI.getType(R);85 // Since the number of lanes in a scalable vector is unknown at compile time,86 // we track one bit which is implicitly broadcast to all lanes. This means87 // that all lanes in a scalable vector are considered demanded.88 APInt DemandedElts =89 Ty.isFixedVector() ? APInt::getAllOnes(Ty.getNumElements()) : APInt(1, 1);90 return getKnownBits(R, DemandedElts);91}92 93KnownBits GISelValueTracking::getKnownBits(Register R,94 const APInt &DemandedElts,95 unsigned Depth) {96 KnownBits Known;97 computeKnownBitsImpl(R, Known, DemandedElts, Depth);98 return Known;99}100 101bool GISelValueTracking::signBitIsZero(Register R) {102 LLT Ty = MRI.getType(R);103 unsigned BitWidth = Ty.getScalarSizeInBits();104 return maskedValueIsZero(R, APInt::getSignMask(BitWidth));105}106 107APInt GISelValueTracking::getKnownZeroes(Register R) {108 return getKnownBits(R).Zero;109}110 111APInt GISelValueTracking::getKnownOnes(Register R) {112 return getKnownBits(R).One;113}114 115[[maybe_unused]] static void116dumpResult(const MachineInstr &MI, const KnownBits &Known, unsigned Depth) {117 dbgs() << "[" << Depth << "] Compute known bits: " << MI << "[" << Depth118 << "] Computed for: " << MI << "[" << Depth << "] Known: 0x"119 << toString(Known.Zero | Known.One, 16, false) << "\n"120 << "[" << Depth << "] Zero: 0x" << toString(Known.Zero, 16, false)121 << "\n"122 << "[" << Depth << "] One: 0x" << toString(Known.One, 16, false)123 << "\n";124}125 126/// Compute known bits for the intersection of \p Src0 and \p Src1127void GISelValueTracking::computeKnownBitsMin(Register Src0, Register Src1,128 KnownBits &Known,129 const APInt &DemandedElts,130 unsigned Depth) {131 // Test src1 first, since we canonicalize simpler expressions to the RHS.132 computeKnownBitsImpl(Src1, Known, DemandedElts, Depth);133 134 // If we don't know any bits, early out.135 if (Known.isUnknown())136 return;137 138 KnownBits Known2;139 computeKnownBitsImpl(Src0, Known2, DemandedElts, Depth);140 141 // Only known if known in both the LHS and RHS.142 Known = Known.intersectWith(Known2);143}144 145// Bitfield extract is computed as (Src >> Offset) & Mask, where Mask is146// created using Width. Use this function when the inputs are KnownBits147// objects. TODO: Move this KnownBits.h if this is usable in more cases.148static KnownBits extractBits(unsigned BitWidth, const KnownBits &SrcOpKnown,149 const KnownBits &OffsetKnown,150 const KnownBits &WidthKnown) {151 KnownBits Mask(BitWidth);152 Mask.Zero = APInt::getBitsSetFrom(153 BitWidth, WidthKnown.getMaxValue().getLimitedValue(BitWidth));154 Mask.One = APInt::getLowBitsSet(155 BitWidth, WidthKnown.getMinValue().getLimitedValue(BitWidth));156 return KnownBits::lshr(SrcOpKnown, OffsetKnown) & Mask;157}158 159void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,160 const APInt &DemandedElts,161 unsigned Depth) {162 MachineInstr &MI = *MRI.getVRegDef(R);163 unsigned Opcode = MI.getOpcode();164 LLT DstTy = MRI.getType(R);165 166 // Handle the case where this is called on a register that does not have a167 // type constraint. For example, it may be post-ISel or this target might not168 // preserve the type when early-selecting instructions.169 if (!DstTy.isValid()) {170 Known = KnownBits();171 return;172 }173 174#ifndef NDEBUG175 if (DstTy.isFixedVector()) {176 assert(177 DstTy.getNumElements() == DemandedElts.getBitWidth() &&178 "DemandedElt width should equal the fixed vector number of elements");179 } else {180 assert(DemandedElts.getBitWidth() == 1 && DemandedElts == APInt(1, 1) &&181 "DemandedElt width should be 1 for scalars or scalable vectors");182 }183#endif184 185 unsigned BitWidth = DstTy.getScalarSizeInBits();186 Known = KnownBits(BitWidth); // Don't know anything187 188 // Depth may get bigger than max depth if it gets passed to a different189 // GISelValueTracking object.190 // This may happen when say a generic part uses a GISelValueTracking object191 // with some max depth, but then we hit TL.computeKnownBitsForTargetInstr192 // which creates a new GISelValueTracking object with a different and smaller193 // depth. If we just check for equality, we would never exit if the depth194 // that is passed down to the target specific GISelValueTracking object is195 // already bigger than its max depth.196 if (Depth >= getMaxDepth())197 return;198 199 if (!DemandedElts)200 return; // No demanded elts, better to assume we don't know anything.201 202 KnownBits Known2;203 204 switch (Opcode) {205 default:206 TL.computeKnownBitsForTargetInstr(*this, R, Known, DemandedElts, MRI,207 Depth);208 break;209 case TargetOpcode::G_BUILD_VECTOR: {210 // Collect the known bits that are shared by every demanded vector element.211 Known.Zero.setAllBits();212 Known.One.setAllBits();213 for (const auto &[I, MO] : enumerate(drop_begin(MI.operands()))) {214 if (!DemandedElts[I])215 continue;216 217 computeKnownBitsImpl(MO.getReg(), Known2, APInt(1, 1), Depth + 1);218 219 // Known bits are the values that are shared by every demanded element.220 Known = Known.intersectWith(Known2);221 222 // If we don't know any bits, early out.223 if (Known.isUnknown())224 break;225 }226 break;227 }228 case TargetOpcode::G_SPLAT_VECTOR: {229 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, APInt(1, 1),230 Depth + 1);231 // Implicitly truncate the bits to match the official semantics of232 // G_SPLAT_VECTOR.233 Known = Known.trunc(BitWidth);234 break;235 }236 case TargetOpcode::COPY:237 case TargetOpcode::G_PHI:238 case TargetOpcode::PHI: {239 Known.One = APInt::getAllOnes(BitWidth);240 Known.Zero = APInt::getAllOnes(BitWidth);241 // Destination registers should not have subregisters at this242 // point of the pipeline, otherwise the main live-range will be243 // defined more than once, which is against SSA.244 assert(MI.getOperand(0).getSubReg() == 0 && "Is this code in SSA?");245 // PHI's operand are a mix of registers and basic blocks interleaved.246 // We only care about the register ones.247 for (unsigned Idx = 1; Idx < MI.getNumOperands(); Idx += 2) {248 const MachineOperand &Src = MI.getOperand(Idx);249 Register SrcReg = Src.getReg();250 LLT SrcTy = MRI.getType(SrcReg);251 // Look through trivial copies and phis but don't look through trivial252 // copies or phis of the form `%1:(s32) = OP %0:gpr32`, known-bits253 // analysis is currently unable to determine the bit width of a254 // register class.255 //256 // We can't use NoSubRegister by name as it's defined by each target but257 // it's always defined to be 0 by tablegen.258 if (SrcReg.isVirtual() && Src.getSubReg() == 0 /*NoSubRegister*/ &&259 SrcTy.isValid()) {260 // In case we're forwarding from a vector register to a non-vector261 // register we need to update the demanded elements to reflect this262 // before recursing.263 APInt NowDemandedElts = SrcTy.isFixedVector() && !DstTy.isFixedVector()264 ? APInt::getAllOnes(SrcTy.getNumElements())265 : DemandedElts; // Known to be APInt(1, 1)266 // For COPYs we don't do anything, don't increase the depth.267 computeKnownBitsImpl(SrcReg, Known2, NowDemandedElts,268 Depth + (Opcode != TargetOpcode::COPY));269 Known2 = Known2.anyextOrTrunc(BitWidth);270 Known = Known.intersectWith(Known2);271 // If we reach a point where we don't know anything272 // just stop looking through the operands.273 if (Known.isUnknown())274 break;275 } else {276 // We know nothing.277 Known = KnownBits(BitWidth);278 break;279 }280 }281 break;282 }283 case TargetOpcode::G_CONSTANT: {284 Known = KnownBits::makeConstant(MI.getOperand(1).getCImm()->getValue());285 break;286 }287 case TargetOpcode::G_FRAME_INDEX: {288 int FrameIdx = MI.getOperand(1).getIndex();289 TL.computeKnownBitsForFrameIndex(FrameIdx, Known, MF);290 break;291 }292 case TargetOpcode::G_SUB: {293 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,294 Depth + 1);295 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts,296 Depth + 1);297 Known = KnownBits::sub(Known, Known2);298 break;299 }300 case TargetOpcode::G_XOR: {301 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,302 Depth + 1);303 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,304 Depth + 1);305 306 Known ^= Known2;307 break;308 }309 case TargetOpcode::G_PTR_ADD: {310 if (DstTy.isVector())311 break;312 // G_PTR_ADD is like G_ADD. FIXME: Is this true for all targets?313 LLT Ty = MRI.getType(MI.getOperand(1).getReg());314 if (DL.isNonIntegralAddressSpace(Ty.getAddressSpace()))315 break;316 [[fallthrough]];317 }318 case TargetOpcode::G_ADD: {319 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,320 Depth + 1);321 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts,322 Depth + 1);323 Known = KnownBits::add(Known, Known2);324 break;325 }326 case TargetOpcode::G_AND: {327 // If either the LHS or the RHS are Zero, the result is zero.328 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,329 Depth + 1);330 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,331 Depth + 1);332 333 Known &= Known2;334 break;335 }336 case TargetOpcode::G_OR: {337 // If either the LHS or the RHS are Zero, the result is zero.338 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,339 Depth + 1);340 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,341 Depth + 1);342 343 Known |= Known2;344 break;345 }346 case TargetOpcode::G_MUL: {347 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,348 Depth + 1);349 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,350 Depth + 1);351 Known = KnownBits::mul(Known, Known2);352 break;353 }354 case TargetOpcode::G_UMULH: {355 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,356 Depth + 1);357 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,358 Depth + 1);359 Known = KnownBits::mulhu(Known, Known2);360 break;361 }362 case TargetOpcode::G_SMULH: {363 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,364 Depth + 1);365 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,366 Depth + 1);367 Known = KnownBits::mulhs(Known, Known2);368 break;369 }370 case TargetOpcode::G_SELECT: {371 computeKnownBitsMin(MI.getOperand(2).getReg(), MI.getOperand(3).getReg(),372 Known, DemandedElts, Depth + 1);373 break;374 }375 case TargetOpcode::G_SMIN: {376 // TODO: Handle clamp pattern with number of sign bits377 KnownBits KnownRHS;378 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,379 Depth + 1);380 computeKnownBitsImpl(MI.getOperand(2).getReg(), KnownRHS, DemandedElts,381 Depth + 1);382 Known = KnownBits::smin(Known, KnownRHS);383 break;384 }385 case TargetOpcode::G_SMAX: {386 // TODO: Handle clamp pattern with number of sign bits387 KnownBits KnownRHS;388 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,389 Depth + 1);390 computeKnownBitsImpl(MI.getOperand(2).getReg(), KnownRHS, DemandedElts,391 Depth + 1);392 Known = KnownBits::smax(Known, KnownRHS);393 break;394 }395 case TargetOpcode::G_UMIN: {396 KnownBits KnownRHS;397 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,398 Depth + 1);399 computeKnownBitsImpl(MI.getOperand(2).getReg(), KnownRHS, DemandedElts,400 Depth + 1);401 Known = KnownBits::umin(Known, KnownRHS);402 break;403 }404 case TargetOpcode::G_UMAX: {405 KnownBits KnownRHS;406 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,407 Depth + 1);408 computeKnownBitsImpl(MI.getOperand(2).getReg(), KnownRHS, DemandedElts,409 Depth + 1);410 Known = KnownBits::umax(Known, KnownRHS);411 break;412 }413 case TargetOpcode::G_FCMP:414 case TargetOpcode::G_ICMP: {415 if (DstTy.isVector())416 break;417 if (TL.getBooleanContents(DstTy.isVector(),418 Opcode == TargetOpcode::G_FCMP) ==419 TargetLowering::ZeroOrOneBooleanContent &&420 BitWidth > 1)421 Known.Zero.setBitsFrom(1);422 break;423 }424 case TargetOpcode::G_SEXT: {425 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,426 Depth + 1);427 // If the sign bit is known to be zero or one, then sext will extend428 // it to the top bits, else it will just zext.429 Known = Known.sext(BitWidth);430 break;431 }432 case TargetOpcode::G_ASSERT_SEXT:433 case TargetOpcode::G_SEXT_INREG: {434 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,435 Depth + 1);436 Known = Known.sextInReg(MI.getOperand(2).getImm());437 break;438 }439 case TargetOpcode::G_ANYEXT: {440 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,441 Depth + 1);442 Known = Known.anyext(BitWidth);443 break;444 }445 case TargetOpcode::G_LOAD: {446 const MachineMemOperand *MMO = *MI.memoperands_begin();447 KnownBits KnownRange(MMO->getMemoryType().getScalarSizeInBits());448 if (const MDNode *Ranges = MMO->getRanges())449 computeKnownBitsFromRangeMetadata(*Ranges, KnownRange);450 Known = KnownRange.anyext(Known.getBitWidth());451 break;452 }453 case TargetOpcode::G_SEXTLOAD:454 case TargetOpcode::G_ZEXTLOAD: {455 if (DstTy.isVector())456 break;457 const MachineMemOperand *MMO = *MI.memoperands_begin();458 KnownBits KnownRange(MMO->getMemoryType().getScalarSizeInBits());459 if (const MDNode *Ranges = MMO->getRanges())460 computeKnownBitsFromRangeMetadata(*Ranges, KnownRange);461 Known = Opcode == TargetOpcode::G_SEXTLOAD462 ? KnownRange.sext(Known.getBitWidth())463 : KnownRange.zext(Known.getBitWidth());464 break;465 }466 case TargetOpcode::G_ASHR: {467 KnownBits LHSKnown, RHSKnown;468 computeKnownBitsImpl(MI.getOperand(1).getReg(), LHSKnown, DemandedElts,469 Depth + 1);470 computeKnownBitsImpl(MI.getOperand(2).getReg(), RHSKnown, DemandedElts,471 Depth + 1);472 Known = KnownBits::ashr(LHSKnown, RHSKnown);473 break;474 }475 case TargetOpcode::G_LSHR: {476 KnownBits LHSKnown, RHSKnown;477 computeKnownBitsImpl(MI.getOperand(1).getReg(), LHSKnown, DemandedElts,478 Depth + 1);479 computeKnownBitsImpl(MI.getOperand(2).getReg(), RHSKnown, DemandedElts,480 Depth + 1);481 Known = KnownBits::lshr(LHSKnown, RHSKnown);482 break;483 }484 case TargetOpcode::G_SHL: {485 KnownBits LHSKnown, RHSKnown;486 computeKnownBitsImpl(MI.getOperand(1).getReg(), LHSKnown, DemandedElts,487 Depth + 1);488 computeKnownBitsImpl(MI.getOperand(2).getReg(), RHSKnown, DemandedElts,489 Depth + 1);490 Known = KnownBits::shl(LHSKnown, RHSKnown);491 break;492 }493 case TargetOpcode::G_INTTOPTR:494 case TargetOpcode::G_PTRTOINT:495 if (DstTy.isVector())496 break;497 // Fall through and handle them the same as zext/trunc.498 [[fallthrough]];499 case TargetOpcode::G_ZEXT:500 case TargetOpcode::G_TRUNC: {501 Register SrcReg = MI.getOperand(1).getReg();502 computeKnownBitsImpl(SrcReg, Known, DemandedElts, Depth + 1);503 Known = Known.zextOrTrunc(BitWidth);504 break;505 }506 case TargetOpcode::G_ASSERT_ZEXT: {507 Register SrcReg = MI.getOperand(1).getReg();508 computeKnownBitsImpl(SrcReg, Known, DemandedElts, Depth + 1);509 510 unsigned SrcBitWidth = MI.getOperand(2).getImm();511 assert(SrcBitWidth && "SrcBitWidth can't be zero");512 APInt InMask = APInt::getLowBitsSet(BitWidth, SrcBitWidth);513 Known.Zero |= (~InMask);514 Known.One &= (~Known.Zero);515 break;516 }517 case TargetOpcode::G_ASSERT_ALIGN: {518 int64_t LogOfAlign = Log2_64(MI.getOperand(2).getImm());519 520 // TODO: Should use maximum with source521 // If a node is guaranteed to be aligned, set low zero bits accordingly as522 // well as clearing one bits.523 Known.Zero.setLowBits(LogOfAlign);524 Known.One.clearLowBits(LogOfAlign);525 break;526 }527 case TargetOpcode::G_MERGE_VALUES: {528 unsigned NumOps = MI.getNumOperands();529 unsigned OpSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();530 531 for (unsigned I = 0; I != NumOps - 1; ++I) {532 KnownBits SrcOpKnown;533 computeKnownBitsImpl(MI.getOperand(I + 1).getReg(), SrcOpKnown,534 DemandedElts, Depth + 1);535 Known.insertBits(SrcOpKnown, I * OpSize);536 }537 break;538 }539 case TargetOpcode::G_UNMERGE_VALUES: {540 unsigned NumOps = MI.getNumOperands();541 Register SrcReg = MI.getOperand(NumOps - 1).getReg();542 LLT SrcTy = MRI.getType(SrcReg);543 544 if (SrcTy.isVector() && SrcTy.getScalarType() != DstTy.getScalarType())545 return; // TODO: Handle vector->subelement unmerges546 547 // Figure out the result operand index548 unsigned DstIdx = 0;549 for (; DstIdx != NumOps - 1 && MI.getOperand(DstIdx).getReg() != R;550 ++DstIdx)551 ;552 553 APInt SubDemandedElts = DemandedElts;554 if (SrcTy.isVector()) {555 unsigned DstLanes = DstTy.isVector() ? DstTy.getNumElements() : 1;556 SubDemandedElts =557 DemandedElts.zext(SrcTy.getNumElements()).shl(DstIdx * DstLanes);558 }559 560 KnownBits SrcOpKnown;561 computeKnownBitsImpl(SrcReg, SrcOpKnown, SubDemandedElts, Depth + 1);562 563 if (SrcTy.isVector())564 Known = std::move(SrcOpKnown);565 else566 Known = SrcOpKnown.extractBits(BitWidth, BitWidth * DstIdx);567 break;568 }569 case TargetOpcode::G_BSWAP: {570 Register SrcReg = MI.getOperand(1).getReg();571 computeKnownBitsImpl(SrcReg, Known, DemandedElts, Depth + 1);572 Known = Known.byteSwap();573 break;574 }575 case TargetOpcode::G_BITREVERSE: {576 Register SrcReg = MI.getOperand(1).getReg();577 computeKnownBitsImpl(SrcReg, Known, DemandedElts, Depth + 1);578 Known = Known.reverseBits();579 break;580 }581 case TargetOpcode::G_CTPOP: {582 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,583 Depth + 1);584 // We can bound the space the count needs. Also, bits known to be zero585 // can't contribute to the population.586 unsigned BitsPossiblySet = Known2.countMaxPopulation();587 unsigned LowBits = llvm::bit_width(BitsPossiblySet);588 Known.Zero.setBitsFrom(LowBits);589 // TODO: we could bound Known.One using the lower bound on the number of590 // bits which might be set provided by popcnt KnownOne2.591 break;592 }593 case TargetOpcode::G_UBFX: {594 KnownBits SrcOpKnown, OffsetKnown, WidthKnown;595 computeKnownBitsImpl(MI.getOperand(1).getReg(), SrcOpKnown, DemandedElts,596 Depth + 1);597 computeKnownBitsImpl(MI.getOperand(2).getReg(), OffsetKnown, DemandedElts,598 Depth + 1);599 computeKnownBitsImpl(MI.getOperand(3).getReg(), WidthKnown, DemandedElts,600 Depth + 1);601 Known = extractBits(BitWidth, SrcOpKnown, OffsetKnown, WidthKnown);602 break;603 }604 case TargetOpcode::G_SBFX: {605 KnownBits SrcOpKnown, OffsetKnown, WidthKnown;606 computeKnownBitsImpl(MI.getOperand(1).getReg(), SrcOpKnown, DemandedElts,607 Depth + 1);608 computeKnownBitsImpl(MI.getOperand(2).getReg(), OffsetKnown, DemandedElts,609 Depth + 1);610 computeKnownBitsImpl(MI.getOperand(3).getReg(), WidthKnown, DemandedElts,611 Depth + 1);612 OffsetKnown = OffsetKnown.sext(BitWidth);613 WidthKnown = WidthKnown.sext(BitWidth);614 Known = extractBits(BitWidth, SrcOpKnown, OffsetKnown, WidthKnown);615 // Sign extend the extracted value using shift left and arithmetic shift616 // right.617 KnownBits ExtKnown = KnownBits::makeConstant(APInt(BitWidth, BitWidth));618 KnownBits ShiftKnown = KnownBits::sub(ExtKnown, WidthKnown);619 Known = KnownBits::ashr(KnownBits::shl(Known, ShiftKnown), ShiftKnown);620 break;621 }622 case TargetOpcode::G_UADDO:623 case TargetOpcode::G_UADDE:624 case TargetOpcode::G_SADDO:625 case TargetOpcode::G_SADDE:626 case TargetOpcode::G_USUBO:627 case TargetOpcode::G_USUBE:628 case TargetOpcode::G_SSUBO:629 case TargetOpcode::G_SSUBE:630 case TargetOpcode::G_UMULO:631 case TargetOpcode::G_SMULO: {632 if (MI.getOperand(1).getReg() == R) {633 // If we know the result of a compare has the top bits zero, use this634 // info.635 if (TL.getBooleanContents(DstTy.isVector(), false) ==636 TargetLowering::ZeroOrOneBooleanContent &&637 BitWidth > 1)638 Known.Zero.setBitsFrom(1);639 }640 break;641 }642 case TargetOpcode::G_CTLZ:643 case TargetOpcode::G_CTLZ_ZERO_UNDEF: {644 KnownBits SrcOpKnown;645 computeKnownBitsImpl(MI.getOperand(1).getReg(), SrcOpKnown, DemandedElts,646 Depth + 1);647 // If we have a known 1, its position is our upper bound.648 unsigned PossibleLZ = SrcOpKnown.countMaxLeadingZeros();649 unsigned LowBits = llvm::bit_width(PossibleLZ);650 Known.Zero.setBitsFrom(LowBits);651 break;652 }653 case TargetOpcode::G_EXTRACT_VECTOR_ELT: {654 GExtractVectorElement &Extract = cast<GExtractVectorElement>(MI);655 Register InVec = Extract.getVectorReg();656 Register EltNo = Extract.getIndexReg();657 658 auto ConstEltNo = getIConstantVRegVal(EltNo, MRI);659 660 LLT VecVT = MRI.getType(InVec);661 // computeKnownBits not yet implemented for scalable vectors.662 if (VecVT.isScalableVector())663 break;664 665 const unsigned EltBitWidth = VecVT.getScalarSizeInBits();666 const unsigned NumSrcElts = VecVT.getNumElements();667 // A return type different from the vector's element type may lead to668 // issues with pattern selection. Bail out to avoid that.669 if (BitWidth > EltBitWidth)670 break;671 672 Known.Zero.setAllBits();673 Known.One.setAllBits();674 675 // If we know the element index, just demand that vector element, else for676 // an unknown element index, ignore DemandedElts and demand them all.677 APInt DemandedSrcElts = APInt::getAllOnes(NumSrcElts);678 if (ConstEltNo && ConstEltNo->ult(NumSrcElts))679 DemandedSrcElts =680 APInt::getOneBitSet(NumSrcElts, ConstEltNo->getZExtValue());681 682 computeKnownBitsImpl(InVec, Known, DemandedSrcElts, Depth + 1);683 break;684 }685 case TargetOpcode::G_SHUFFLE_VECTOR: {686 APInt DemandedLHS, DemandedRHS;687 // Collect the known bits that are shared by every vector element referenced688 // by the shuffle.689 unsigned NumElts = MRI.getType(MI.getOperand(1).getReg()).getNumElements();690 if (!getShuffleDemandedElts(NumElts, MI.getOperand(3).getShuffleMask(),691 DemandedElts, DemandedLHS, DemandedRHS))692 break;693 694 // Known bits are the values that are shared by every demanded element.695 Known.Zero.setAllBits();696 Known.One.setAllBits();697 if (!!DemandedLHS) {698 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedLHS,699 Depth + 1);700 Known = Known.intersectWith(Known2);701 }702 // If we don't know any bits, early out.703 if (Known.isUnknown())704 break;705 if (!!DemandedRHS) {706 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedRHS,707 Depth + 1);708 Known = Known.intersectWith(Known2);709 }710 break;711 }712 case TargetOpcode::G_CONCAT_VECTORS: {713 if (MRI.getType(MI.getOperand(0).getReg()).isScalableVector())714 break;715 // Split DemandedElts and test each of the demanded subvectors.716 Known.Zero.setAllBits();717 Known.One.setAllBits();718 unsigned NumSubVectorElts =719 MRI.getType(MI.getOperand(1).getReg()).getNumElements();720 721 for (const auto &[I, MO] : enumerate(drop_begin(MI.operands()))) {722 APInt DemandedSub =723 DemandedElts.extractBits(NumSubVectorElts, I * NumSubVectorElts);724 if (!!DemandedSub) {725 computeKnownBitsImpl(MO.getReg(), Known2, DemandedSub, Depth + 1);726 727 Known = Known.intersectWith(Known2);728 }729 // If we don't know any bits, early out.730 if (Known.isUnknown())731 break;732 }733 break;734 }735 case TargetOpcode::G_ABS: {736 Register SrcReg = MI.getOperand(1).getReg();737 computeKnownBitsImpl(SrcReg, Known, DemandedElts, Depth + 1);738 Known = Known.abs();739 Known.Zero.setHighBits(computeNumSignBits(SrcReg, DemandedElts, Depth + 1) -740 1);741 break;742 }743 }744 745 LLVM_DEBUG(dumpResult(MI, Known, Depth));746}747 748static bool outputDenormalIsIEEEOrPosZero(const MachineFunction &MF, LLT Ty) {749 Ty = Ty.getScalarType();750 DenormalMode Mode = MF.getDenormalMode(getFltSemanticForLLT(Ty));751 return Mode.Output == DenormalMode::IEEE ||752 Mode.Output == DenormalMode::PositiveZero;753}754 755void GISelValueTracking::computeKnownFPClass(Register R, KnownFPClass &Known,756 FPClassTest InterestedClasses,757 unsigned Depth) {758 LLT Ty = MRI.getType(R);759 APInt DemandedElts =760 Ty.isFixedVector() ? APInt::getAllOnes(Ty.getNumElements()) : APInt(1, 1);761 computeKnownFPClass(R, DemandedElts, InterestedClasses, Known, Depth);762}763 764void GISelValueTracking::computeKnownFPClassForFPTrunc(765 const MachineInstr &MI, const APInt &DemandedElts,766 FPClassTest InterestedClasses, KnownFPClass &Known, unsigned Depth) {767 if ((InterestedClasses & (KnownFPClass::OrderedLessThanZeroMask | fcNan)) ==768 fcNone)769 return;770 771 Register Val = MI.getOperand(1).getReg();772 KnownFPClass KnownSrc;773 computeKnownFPClass(Val, DemandedElts, InterestedClasses, KnownSrc,774 Depth + 1);775 776 // Sign should be preserved777 // TODO: Handle cannot be ordered greater than zero778 if (KnownSrc.cannotBeOrderedLessThanZero())779 Known.knownNot(KnownFPClass::OrderedLessThanZeroMask);780 781 Known.propagateNaN(KnownSrc, true);782 783 // Infinity needs a range check.784}785 786void GISelValueTracking::computeKnownFPClass(Register R,787 const APInt &DemandedElts,788 FPClassTest InterestedClasses,789 KnownFPClass &Known,790 unsigned Depth) {791 assert(Known.isUnknown() && "should not be called with known information");792 793 if (!DemandedElts) {794 // No demanded elts, better to assume we don't know anything.795 Known.resetAll();796 return;797 }798 799 assert(Depth <= MaxAnalysisRecursionDepth && "Limit Search Depth");800 801 MachineInstr &MI = *MRI.getVRegDef(R);802 unsigned Opcode = MI.getOpcode();803 LLT DstTy = MRI.getType(R);804 805 if (!DstTy.isValid()) {806 Known.resetAll();807 return;808 }809 810 if (auto Cst = GFConstant::getConstant(R, MRI)) {811 switch (Cst->getKind()) {812 case GFConstant::GFConstantKind::Scalar: {813 auto APF = Cst->getScalarValue();814 Known.KnownFPClasses = APF.classify();815 Known.SignBit = APF.isNegative();816 break;817 }818 case GFConstant::GFConstantKind::FixedVector: {819 Known.KnownFPClasses = fcNone;820 bool SignBitAllZero = true;821 bool SignBitAllOne = true;822 823 for (auto C : *Cst) {824 Known.KnownFPClasses |= C.classify();825 if (C.isNegative())826 SignBitAllZero = false;827 else828 SignBitAllOne = false;829 }830 831 if (SignBitAllOne != SignBitAllZero)832 Known.SignBit = SignBitAllOne;833 834 break;835 }836 case GFConstant::GFConstantKind::ScalableVector: {837 Known.resetAll();838 break;839 }840 }841 842 return;843 }844 845 FPClassTest KnownNotFromFlags = fcNone;846 if (MI.getFlag(MachineInstr::MIFlag::FmNoNans))847 KnownNotFromFlags |= fcNan;848 if (MI.getFlag(MachineInstr::MIFlag::FmNoInfs))849 KnownNotFromFlags |= fcInf;850 851 // We no longer need to find out about these bits from inputs if we can852 // assume this from flags/attributes.853 InterestedClasses &= ~KnownNotFromFlags;854 855 auto ClearClassesFromFlags =856 make_scope_exit([=, &Known] { Known.knownNot(KnownNotFromFlags); });857 858 // All recursive calls that increase depth must come after this.859 if (Depth == MaxAnalysisRecursionDepth)860 return;861 862 const MachineFunction *MF = MI.getMF();863 864 switch (Opcode) {865 default:866 TL.computeKnownFPClassForTargetInstr(*this, R, Known, DemandedElts, MRI,867 Depth);868 break;869 case TargetOpcode::G_FNEG: {870 Register Val = MI.getOperand(1).getReg();871 computeKnownFPClass(Val, DemandedElts, InterestedClasses, Known, Depth + 1);872 Known.fneg();873 break;874 }875 case TargetOpcode::G_SELECT: {876 GSelect &SelMI = cast<GSelect>(MI);877 Register Cond = SelMI.getCondReg();878 Register LHS = SelMI.getTrueReg();879 Register RHS = SelMI.getFalseReg();880 881 FPClassTest FilterLHS = fcAllFlags;882 FPClassTest FilterRHS = fcAllFlags;883 884 Register TestedValue;885 FPClassTest MaskIfTrue = fcAllFlags;886 FPClassTest MaskIfFalse = fcAllFlags;887 FPClassTest ClassVal = fcNone;888 889 CmpInst::Predicate Pred;890 Register CmpLHS, CmpRHS;891 if (mi_match(Cond, MRI,892 m_GFCmp(m_Pred(Pred), m_Reg(CmpLHS), m_Reg(CmpRHS)))) {893 // If the select filters out a value based on the class, it no longer894 // participates in the class of the result895 896 // TODO: In some degenerate cases we can infer something if we try again897 // without looking through sign operations.898 bool LookThroughFAbsFNeg = CmpLHS != LHS && CmpLHS != RHS;899 std::tie(TestedValue, MaskIfTrue, MaskIfFalse) =900 fcmpImpliesClass(Pred, *MF, CmpLHS, CmpRHS, LookThroughFAbsFNeg);901 } else if (mi_match(902 Cond, MRI,903 m_GIsFPClass(m_Reg(TestedValue), m_FPClassTest(ClassVal)))) {904 FPClassTest TestedMask = ClassVal;905 MaskIfTrue = TestedMask;906 MaskIfFalse = ~TestedMask;907 }908 909 if (TestedValue == LHS) {910 // match !isnan(x) ? x : y911 FilterLHS = MaskIfTrue;912 } else if (TestedValue == RHS) { // && IsExactClass913 // match !isnan(x) ? y : x914 FilterRHS = MaskIfFalse;915 }916 917 KnownFPClass Known2;918 computeKnownFPClass(LHS, DemandedElts, InterestedClasses & FilterLHS, Known,919 Depth + 1);920 Known.KnownFPClasses &= FilterLHS;921 922 computeKnownFPClass(RHS, DemandedElts, InterestedClasses & FilterRHS,923 Known2, Depth + 1);924 Known2.KnownFPClasses &= FilterRHS;925 926 Known |= Known2;927 break;928 }929 case TargetOpcode::G_FCOPYSIGN: {930 Register Magnitude = MI.getOperand(1).getReg();931 Register Sign = MI.getOperand(2).getReg();932 933 KnownFPClass KnownSign;934 935 computeKnownFPClass(Magnitude, DemandedElts, InterestedClasses, Known,936 Depth + 1);937 computeKnownFPClass(Sign, DemandedElts, InterestedClasses, KnownSign,938 Depth + 1);939 Known.copysign(KnownSign);940 break;941 }942 case TargetOpcode::G_FMA:943 case TargetOpcode::G_STRICT_FMA:944 case TargetOpcode::G_FMAD: {945 if ((InterestedClasses & fcNegative) == fcNone)946 break;947 948 Register A = MI.getOperand(1).getReg();949 Register B = MI.getOperand(2).getReg();950 Register C = MI.getOperand(3).getReg();951 952 if (A != B)953 break;954 955 // The multiply cannot be -0 and therefore the add can't be -0956 Known.knownNot(fcNegZero);957 958 // x * x + y is non-negative if y is non-negative.959 KnownFPClass KnownAddend;960 computeKnownFPClass(C, DemandedElts, InterestedClasses, KnownAddend,961 Depth + 1);962 963 if (KnownAddend.cannotBeOrderedLessThanZero())964 Known.knownNot(fcNegative);965 break;966 }967 case TargetOpcode::G_FSQRT:968 case TargetOpcode::G_STRICT_FSQRT: {969 KnownFPClass KnownSrc;970 FPClassTest InterestedSrcs = InterestedClasses;971 if (InterestedClasses & fcNan)972 InterestedSrcs |= KnownFPClass::OrderedLessThanZeroMask;973 974 Register Val = MI.getOperand(1).getReg();975 976 computeKnownFPClass(Val, DemandedElts, InterestedSrcs, KnownSrc, Depth + 1);977 978 if (KnownSrc.isKnownNeverPosInfinity())979 Known.knownNot(fcPosInf);980 if (KnownSrc.isKnownNever(fcSNan))981 Known.knownNot(fcSNan);982 983 // Any negative value besides -0 returns a nan.984 if (KnownSrc.isKnownNeverNaN() && KnownSrc.cannotBeOrderedLessThanZero())985 Known.knownNot(fcNan);986 987 // The only negative value that can be returned is -0 for -0 inputs.988 Known.knownNot(fcNegInf | fcNegSubnormal | fcNegNormal);989 break;990 }991 case TargetOpcode::G_FABS: {992 if ((InterestedClasses & (fcNan | fcPositive)) != fcNone) {993 Register Val = MI.getOperand(1).getReg();994 // If we only care about the sign bit we don't need to inspect the995 // operand.996 computeKnownFPClass(Val, DemandedElts, InterestedClasses, Known,997 Depth + 1);998 }999 Known.fabs();1000 break;1001 }1002 case TargetOpcode::G_FSIN:1003 case TargetOpcode::G_FCOS:1004 case TargetOpcode::G_FSINCOS: {1005 // Return NaN on infinite inputs.1006 Register Val = MI.getOperand(1).getReg();1007 KnownFPClass KnownSrc;1008 1009 computeKnownFPClass(Val, DemandedElts, InterestedClasses, KnownSrc,1010 Depth + 1);1011 Known.knownNot(fcInf);1012 1013 if (KnownSrc.isKnownNeverNaN() && KnownSrc.isKnownNeverInfinity())1014 Known.knownNot(fcNan);1015 break;1016 }1017 case TargetOpcode::G_FMAXNUM:1018 case TargetOpcode::G_FMINNUM:1019 case TargetOpcode::G_FMINNUM_IEEE:1020 case TargetOpcode::G_FMAXIMUM:1021 case TargetOpcode::G_FMINIMUM:1022 case TargetOpcode::G_FMAXNUM_IEEE:1023 case TargetOpcode::G_FMAXIMUMNUM:1024 case TargetOpcode::G_FMINIMUMNUM: {1025 Register LHS = MI.getOperand(1).getReg();1026 Register RHS = MI.getOperand(2).getReg();1027 KnownFPClass KnownLHS, KnownRHS;1028 1029 computeKnownFPClass(LHS, DemandedElts, InterestedClasses, KnownLHS,1030 Depth + 1);1031 computeKnownFPClass(RHS, DemandedElts, InterestedClasses, KnownRHS,1032 Depth + 1);1033 1034 bool NeverNaN = KnownLHS.isKnownNeverNaN() || KnownRHS.isKnownNeverNaN();1035 Known = KnownLHS | KnownRHS;1036 1037 // If either operand is not NaN, the result is not NaN.1038 if (NeverNaN && (Opcode == TargetOpcode::G_FMINNUM ||1039 Opcode == TargetOpcode::G_FMAXNUM ||1040 Opcode == TargetOpcode::G_FMINIMUMNUM ||1041 Opcode == TargetOpcode::G_FMAXIMUMNUM))1042 Known.knownNot(fcNan);1043 1044 if (Opcode == TargetOpcode::G_FMAXNUM ||1045 Opcode == TargetOpcode::G_FMAXIMUMNUM ||1046 Opcode == TargetOpcode::G_FMAXNUM_IEEE) {1047 // If at least one operand is known to be positive, the result must be1048 // positive.1049 if ((KnownLHS.cannotBeOrderedLessThanZero() &&1050 KnownLHS.isKnownNeverNaN()) ||1051 (KnownRHS.cannotBeOrderedLessThanZero() &&1052 KnownRHS.isKnownNeverNaN()))1053 Known.knownNot(KnownFPClass::OrderedLessThanZeroMask);1054 } else if (Opcode == TargetOpcode::G_FMAXIMUM) {1055 // If at least one operand is known to be positive, the result must be1056 // positive.1057 if (KnownLHS.cannotBeOrderedLessThanZero() ||1058 KnownRHS.cannotBeOrderedLessThanZero())1059 Known.knownNot(KnownFPClass::OrderedLessThanZeroMask);1060 } else if (Opcode == TargetOpcode::G_FMINNUM ||1061 Opcode == TargetOpcode::G_FMINIMUMNUM ||1062 Opcode == TargetOpcode::G_FMINNUM_IEEE) {1063 // If at least one operand is known to be negative, the result must be1064 // negative.1065 if ((KnownLHS.cannotBeOrderedGreaterThanZero() &&1066 KnownLHS.isKnownNeverNaN()) ||1067 (KnownRHS.cannotBeOrderedGreaterThanZero() &&1068 KnownRHS.isKnownNeverNaN()))1069 Known.knownNot(KnownFPClass::OrderedGreaterThanZeroMask);1070 } else if (Opcode == TargetOpcode::G_FMINIMUM) {1071 // If at least one operand is known to be negative, the result must be1072 // negative.1073 if (KnownLHS.cannotBeOrderedGreaterThanZero() ||1074 KnownRHS.cannotBeOrderedGreaterThanZero())1075 Known.knownNot(KnownFPClass::OrderedGreaterThanZeroMask);1076 } else {1077 llvm_unreachable("unhandled intrinsic");1078 }1079 1080 // Fixup zero handling if denormals could be returned as a zero.1081 //1082 // As there's no spec for denormal flushing, be conservative with the1083 // treatment of denormals that could be flushed to zero. For older1084 // subtargets on AMDGPU the min/max instructions would not flush the1085 // output and return the original value.1086 //1087 if ((Known.KnownFPClasses & fcZero) != fcNone &&1088 !Known.isKnownNeverSubnormal()) {1089 DenormalMode Mode =1090 MF->getDenormalMode(getFltSemanticForLLT(DstTy.getScalarType()));1091 if (Mode != DenormalMode::getIEEE())1092 Known.KnownFPClasses |= fcZero;1093 }1094 1095 if (Known.isKnownNeverNaN()) {1096 if (KnownLHS.SignBit && KnownRHS.SignBit &&1097 *KnownLHS.SignBit == *KnownRHS.SignBit) {1098 if (*KnownLHS.SignBit)1099 Known.signBitMustBeOne();1100 else1101 Known.signBitMustBeZero();1102 } else if ((Opcode == TargetOpcode::G_FMAXIMUM ||1103 Opcode == TargetOpcode::G_FMINIMUM) ||1104 Opcode == TargetOpcode::G_FMAXIMUMNUM ||1105 Opcode == TargetOpcode::G_FMINIMUMNUM ||1106 Opcode == TargetOpcode::G_FMAXNUM_IEEE ||1107 Opcode == TargetOpcode::G_FMINNUM_IEEE ||1108 // FIXME: Should be using logical zero versions1109 ((KnownLHS.isKnownNeverNegZero() ||1110 KnownRHS.isKnownNeverPosZero()) &&1111 (KnownLHS.isKnownNeverPosZero() ||1112 KnownRHS.isKnownNeverNegZero()))) {1113 if ((Opcode == TargetOpcode::G_FMAXIMUM ||1114 Opcode == TargetOpcode::G_FMAXNUM ||1115 Opcode == TargetOpcode::G_FMAXIMUMNUM ||1116 Opcode == TargetOpcode::G_FMAXNUM_IEEE) &&1117 (KnownLHS.SignBit == false || KnownRHS.SignBit == false))1118 Known.signBitMustBeZero();1119 else if ((Opcode == TargetOpcode::G_FMINIMUM ||1120 Opcode == TargetOpcode::G_FMINNUM ||1121 Opcode == TargetOpcode::G_FMINIMUMNUM ||1122 Opcode == TargetOpcode::G_FMINNUM_IEEE) &&1123 (KnownLHS.SignBit == true || KnownRHS.SignBit == true))1124 Known.signBitMustBeOne();1125 }1126 }1127 break;1128 }1129 case TargetOpcode::G_FCANONICALIZE: {1130 Register Val = MI.getOperand(1).getReg();1131 KnownFPClass KnownSrc;1132 computeKnownFPClass(Val, DemandedElts, InterestedClasses, KnownSrc,1133 Depth + 1);1134 1135 // This is essentially a stronger form of1136 // propagateCanonicalizingSrc. Other "canonicalizing" operations don't1137 // actually have an IR canonicalization guarantee.1138 1139 // Canonicalize may flush denormals to zero, so we have to consider the1140 // denormal mode to preserve known-not-0 knowledge.1141 Known.KnownFPClasses = KnownSrc.KnownFPClasses | fcZero | fcQNan;1142 1143 // Stronger version of propagateNaN1144 // Canonicalize is guaranteed to quiet signaling nans.1145 if (KnownSrc.isKnownNeverNaN())1146 Known.knownNot(fcNan);1147 else1148 Known.knownNot(fcSNan);1149 1150 // If the parent function flushes denormals, the canonical output cannot1151 // be a denormal.1152 LLT Ty = MRI.getType(Val).getScalarType();1153 const fltSemantics &FPType = getFltSemanticForLLT(Ty);1154 DenormalMode DenormMode = MF->getDenormalMode(FPType);1155 if (DenormMode == DenormalMode::getIEEE()) {1156 if (KnownSrc.isKnownNever(fcPosZero))1157 Known.knownNot(fcPosZero);1158 if (KnownSrc.isKnownNever(fcNegZero))1159 Known.knownNot(fcNegZero);1160 break;1161 }1162 1163 if (DenormMode.inputsAreZero() || DenormMode.outputsAreZero())1164 Known.knownNot(fcSubnormal);1165 1166 if (DenormMode.Input == DenormalMode::PositiveZero ||1167 (DenormMode.Output == DenormalMode::PositiveZero &&1168 DenormMode.Input == DenormalMode::IEEE))1169 Known.knownNot(fcNegZero);1170 1171 break;1172 }1173 case TargetOpcode::G_VECREDUCE_FMAX:1174 case TargetOpcode::G_VECREDUCE_FMIN:1175 case TargetOpcode::G_VECREDUCE_FMAXIMUM:1176 case TargetOpcode::G_VECREDUCE_FMINIMUM: {1177 Register Val = MI.getOperand(1).getReg();1178 // reduce min/max will choose an element from one of the vector elements,1179 // so we can infer and class information that is common to all elements.1180 1181 Known =1182 computeKnownFPClass(Val, MI.getFlags(), InterestedClasses, Depth + 1);1183 // Can only propagate sign if output is never NaN.1184 if (!Known.isKnownNeverNaN())1185 Known.SignBit.reset();1186 break;1187 }1188 case TargetOpcode::G_TRUNC:1189 case TargetOpcode::G_FFLOOR:1190 case TargetOpcode::G_FCEIL:1191 case TargetOpcode::G_FRINT:1192 case TargetOpcode::G_FNEARBYINT:1193 case TargetOpcode::G_INTRINSIC_FPTRUNC_ROUND:1194 case TargetOpcode::G_INTRINSIC_ROUND: {1195 Register Val = MI.getOperand(1).getReg();1196 KnownFPClass KnownSrc;1197 FPClassTest InterestedSrcs = InterestedClasses;1198 if (InterestedSrcs & fcPosFinite)1199 InterestedSrcs |= fcPosFinite;1200 if (InterestedSrcs & fcNegFinite)1201 InterestedSrcs |= fcNegFinite;1202 computeKnownFPClass(Val, DemandedElts, InterestedSrcs, KnownSrc, Depth + 1);1203 1204 // Integer results cannot be subnormal.1205 Known.knownNot(fcSubnormal);1206 1207 Known.propagateNaN(KnownSrc, true);1208 1209 // TODO: handle multi unit FPTypes once LLT FPInfo lands1210 1211 // Negative round ups to 0 produce -01212 if (KnownSrc.isKnownNever(fcPosFinite))1213 Known.knownNot(fcPosFinite);1214 if (KnownSrc.isKnownNever(fcNegFinite))1215 Known.knownNot(fcNegFinite);1216 1217 break;1218 }1219 case TargetOpcode::G_FEXP:1220 case TargetOpcode::G_FEXP2:1221 case TargetOpcode::G_FEXP10: {1222 Known.knownNot(fcNegative);1223 if ((InterestedClasses & fcNan) == fcNone)1224 break;1225 1226 Register Val = MI.getOperand(1).getReg();1227 KnownFPClass KnownSrc;1228 computeKnownFPClass(Val, DemandedElts, InterestedClasses, KnownSrc,1229 Depth + 1);1230 if (KnownSrc.isKnownNeverNaN()) {1231 Known.knownNot(fcNan);1232 Known.signBitMustBeZero();1233 }1234 1235 break;1236 }1237 case TargetOpcode::G_FLOG:1238 case TargetOpcode::G_FLOG2:1239 case TargetOpcode::G_FLOG10: {1240 // log(+inf) -> +inf1241 // log([+-]0.0) -> -inf1242 // log(-inf) -> nan1243 // log(-x) -> nan1244 if ((InterestedClasses & (fcNan | fcInf)) == fcNone)1245 break;1246 1247 FPClassTest InterestedSrcs = InterestedClasses;1248 if ((InterestedClasses & fcNegInf) != fcNone)1249 InterestedSrcs |= fcZero | fcSubnormal;1250 if ((InterestedClasses & fcNan) != fcNone)1251 InterestedSrcs |= fcNan | (fcNegative & ~fcNan);1252 1253 Register Val = MI.getOperand(1).getReg();1254 KnownFPClass KnownSrc;1255 computeKnownFPClass(Val, DemandedElts, InterestedSrcs, KnownSrc, Depth + 1);1256 1257 if (KnownSrc.isKnownNeverPosInfinity())1258 Known.knownNot(fcPosInf);1259 1260 if (KnownSrc.isKnownNeverNaN() && KnownSrc.cannotBeOrderedLessThanZero())1261 Known.knownNot(fcNan);1262 1263 LLT Ty = MRI.getType(Val).getScalarType();1264 const fltSemantics &FltSem = getFltSemanticForLLT(Ty);1265 DenormalMode Mode = MF->getDenormalMode(FltSem);1266 1267 if (KnownSrc.isKnownNeverLogicalZero(Mode))1268 Known.knownNot(fcNegInf);1269 1270 break;1271 }1272 case TargetOpcode::G_FPOWI: {1273 if ((InterestedClasses & fcNegative) == fcNone)1274 break;1275 1276 Register Exp = MI.getOperand(2).getReg();1277 LLT ExpTy = MRI.getType(Exp);1278 KnownBits ExponentKnownBits = getKnownBits(1279 Exp, ExpTy.isVector() ? DemandedElts : APInt(1, 1), Depth + 1);1280 1281 if (ExponentKnownBits.Zero[0]) { // Is even1282 Known.knownNot(fcNegative);1283 break;1284 }1285 1286 // Given that exp is an integer, here are the1287 // ways that pow can return a negative value:1288 //1289 // pow(-x, exp) --> negative if exp is odd and x is negative.1290 // pow(-0, exp) --> -inf if exp is negative odd.1291 // pow(-0, exp) --> -0 if exp is positive odd.1292 // pow(-inf, exp) --> -0 if exp is negative odd.1293 // pow(-inf, exp) --> -inf if exp is positive odd.1294 Register Val = MI.getOperand(1).getReg();1295 KnownFPClass KnownSrc;1296 computeKnownFPClass(Val, DemandedElts, fcNegative, KnownSrc, Depth + 1);1297 if (KnownSrc.isKnownNever(fcNegative))1298 Known.knownNot(fcNegative);1299 break;1300 }1301 case TargetOpcode::G_FLDEXP:1302 case TargetOpcode::G_STRICT_FLDEXP: {1303 Register Val = MI.getOperand(1).getReg();1304 KnownFPClass KnownSrc;1305 computeKnownFPClass(Val, DemandedElts, InterestedClasses, KnownSrc,1306 Depth + 1);1307 Known.propagateNaN(KnownSrc, /*PropagateSign=*/true);1308 1309 // Sign is preserved, but underflows may produce zeroes.1310 if (KnownSrc.isKnownNever(fcNegative))1311 Known.knownNot(fcNegative);1312 else if (KnownSrc.cannotBeOrderedLessThanZero())1313 Known.knownNot(KnownFPClass::OrderedLessThanZeroMask);1314 1315 if (KnownSrc.isKnownNever(fcPositive))1316 Known.knownNot(fcPositive);1317 else if (KnownSrc.cannotBeOrderedGreaterThanZero())1318 Known.knownNot(KnownFPClass::OrderedGreaterThanZeroMask);1319 1320 // Can refine inf/zero handling based on the exponent operand.1321 const FPClassTest ExpInfoMask = fcZero | fcSubnormal | fcInf;1322 if ((InterestedClasses & ExpInfoMask) == fcNone)1323 break;1324 if ((KnownSrc.KnownFPClasses & ExpInfoMask) == fcNone)1325 break;1326 1327 // TODO: Handle constant range of Exp1328 1329 break;1330 }1331 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: {1332 computeKnownFPClassForFPTrunc(MI, DemandedElts, InterestedClasses, Known,1333 Depth);1334 break;1335 }1336 case TargetOpcode::G_FADD:1337 case TargetOpcode::G_STRICT_FADD:1338 case TargetOpcode::G_FSUB:1339 case TargetOpcode::G_STRICT_FSUB: {1340 Register LHS = MI.getOperand(1).getReg();1341 Register RHS = MI.getOperand(2).getReg();1342 KnownFPClass KnownLHS, KnownRHS;1343 bool WantNegative =1344 (Opcode == TargetOpcode::G_FADD ||1345 Opcode == TargetOpcode::G_STRICT_FADD) &&1346 (InterestedClasses & KnownFPClass::OrderedLessThanZeroMask) != fcNone;1347 bool WantNaN = (InterestedClasses & fcNan) != fcNone;1348 bool WantNegZero = (InterestedClasses & fcNegZero) != fcNone;1349 1350 if (!WantNaN && !WantNegative && !WantNegZero)1351 break;1352 1353 FPClassTest InterestedSrcs = InterestedClasses;1354 if (WantNegative)1355 InterestedSrcs |= KnownFPClass::OrderedLessThanZeroMask;1356 if (InterestedClasses & fcNan)1357 InterestedSrcs |= fcInf;1358 computeKnownFPClass(RHS, DemandedElts, InterestedSrcs, KnownRHS, Depth + 1);1359 1360 if ((WantNaN && KnownRHS.isKnownNeverNaN()) ||1361 (WantNegative && KnownRHS.cannotBeOrderedLessThanZero()) ||1362 WantNegZero ||1363 (Opcode == TargetOpcode::G_FSUB ||1364 Opcode == TargetOpcode::G_STRICT_FSUB)) {1365 1366 // RHS is canonically cheaper to compute. Skip inspecting the LHS if1367 // there's no point.1368 computeKnownFPClass(LHS, DemandedElts, InterestedSrcs, KnownLHS,1369 Depth + 1);1370 // Adding positive and negative infinity produces NaN.1371 // TODO: Check sign of infinities.1372 if (KnownLHS.isKnownNeverNaN() && KnownRHS.isKnownNeverNaN() &&1373 (KnownLHS.isKnownNeverInfinity() || KnownRHS.isKnownNeverInfinity()))1374 Known.knownNot(fcNan);1375 1376 if (Opcode == Instruction::FAdd) {1377 if (KnownLHS.cannotBeOrderedLessThanZero() &&1378 KnownRHS.cannotBeOrderedLessThanZero())1379 Known.knownNot(KnownFPClass::OrderedLessThanZeroMask);1380 1381 // (fadd x, 0.0) is guaranteed to return +0.0, not -0.0.1382 if ((KnownLHS.isKnownNeverLogicalNegZero(MF->getDenormalMode(1383 getFltSemanticForLLT(DstTy.getScalarType()))) ||1384 KnownRHS.isKnownNeverLogicalNegZero(MF->getDenormalMode(1385 getFltSemanticForLLT(DstTy.getScalarType())))) &&1386 // Make sure output negative denormal can't flush to -01387 outputDenormalIsIEEEOrPosZero(*MF, DstTy))1388 Known.knownNot(fcNegZero);1389 } else {1390 // Only fsub -0, +0 can return -01391 if ((KnownLHS.isKnownNeverLogicalNegZero(MF->getDenormalMode(1392 getFltSemanticForLLT(DstTy.getScalarType()))) ||1393 KnownRHS.isKnownNeverLogicalPosZero(MF->getDenormalMode(1394 getFltSemanticForLLT(DstTy.getScalarType())))) &&1395 // Make sure output negative denormal can't flush to -01396 outputDenormalIsIEEEOrPosZero(*MF, DstTy))1397 Known.knownNot(fcNegZero);1398 }1399 }1400 1401 break;1402 }1403 case TargetOpcode::G_FMUL:1404 case TargetOpcode::G_STRICT_FMUL: {1405 Register LHS = MI.getOperand(1).getReg();1406 Register RHS = MI.getOperand(2).getReg();1407 // X * X is always non-negative or a NaN.1408 if (LHS == RHS)1409 Known.knownNot(fcNegative);1410 1411 if ((InterestedClasses & fcNan) != fcNan)1412 break;1413 1414 // fcSubnormal is only needed in case of DAZ.1415 const FPClassTest NeedForNan = fcNan | fcInf | fcZero | fcSubnormal;1416 1417 KnownFPClass KnownLHS, KnownRHS;1418 computeKnownFPClass(RHS, DemandedElts, NeedForNan, KnownRHS, Depth + 1);1419 if (!KnownRHS.isKnownNeverNaN())1420 break;1421 1422 computeKnownFPClass(LHS, DemandedElts, NeedForNan, KnownLHS, Depth + 1);1423 if (!KnownLHS.isKnownNeverNaN())1424 break;1425 1426 if (KnownLHS.SignBit && KnownRHS.SignBit) {1427 if (*KnownLHS.SignBit == *KnownRHS.SignBit)1428 Known.signBitMustBeZero();1429 else1430 Known.signBitMustBeOne();1431 }1432 1433 // If 0 * +/-inf produces NaN.1434 if (KnownLHS.isKnownNeverInfinity() && KnownRHS.isKnownNeverInfinity()) {1435 Known.knownNot(fcNan);1436 break;1437 }1438 1439 if ((KnownRHS.isKnownNeverInfinity() ||1440 KnownLHS.isKnownNeverLogicalZero(MF->getDenormalMode(1441 getFltSemanticForLLT(DstTy.getScalarType())))) &&1442 (KnownLHS.isKnownNeverInfinity() ||1443 KnownRHS.isKnownNeverLogicalZero(1444 MF->getDenormalMode(getFltSemanticForLLT(DstTy.getScalarType())))))1445 Known.knownNot(fcNan);1446 1447 break;1448 }1449 case TargetOpcode::G_FDIV:1450 case TargetOpcode::G_FREM: {1451 Register LHS = MI.getOperand(1).getReg();1452 Register RHS = MI.getOperand(2).getReg();1453 1454 if (LHS == RHS) {1455 // TODO: Could filter out snan if we inspect the operand1456 if (Opcode == TargetOpcode::G_FDIV) {1457 // X / X is always exactly 1.0 or a NaN.1458 Known.KnownFPClasses = fcNan | fcPosNormal;1459 } else {1460 // X % X is always exactly [+-]0.0 or a NaN.1461 Known.KnownFPClasses = fcNan | fcZero;1462 }1463 1464 break;1465 }1466 1467 const bool WantNan = (InterestedClasses & fcNan) != fcNone;1468 const bool WantNegative = (InterestedClasses & fcNegative) != fcNone;1469 const bool WantPositive = Opcode == TargetOpcode::G_FREM &&1470 (InterestedClasses & fcPositive) != fcNone;1471 if (!WantNan && !WantNegative && !WantPositive)1472 break;1473 1474 KnownFPClass KnownLHS, KnownRHS;1475 1476 computeKnownFPClass(RHS, DemandedElts, fcNan | fcInf | fcZero | fcNegative,1477 KnownRHS, Depth + 1);1478 1479 bool KnowSomethingUseful =1480 KnownRHS.isKnownNeverNaN() || KnownRHS.isKnownNever(fcNegative);1481 1482 if (KnowSomethingUseful || WantPositive) {1483 const FPClassTest InterestedLHS =1484 WantPositive ? fcAllFlags1485 : fcNan | fcInf | fcZero | fcSubnormal | fcNegative;1486 1487 computeKnownFPClass(LHS, DemandedElts, InterestedClasses & InterestedLHS,1488 KnownLHS, Depth + 1);1489 }1490 1491 if (Opcode == Instruction::FDiv) {1492 // Only 0/0, Inf/Inf produce NaN.1493 if (KnownLHS.isKnownNeverNaN() && KnownRHS.isKnownNeverNaN() &&1494 (KnownLHS.isKnownNeverInfinity() ||1495 KnownRHS.isKnownNeverInfinity()) &&1496 ((KnownLHS.isKnownNeverLogicalZero(MF->getDenormalMode(1497 getFltSemanticForLLT(DstTy.getScalarType())))) ||1498 (KnownRHS.isKnownNeverLogicalZero(MF->getDenormalMode(1499 getFltSemanticForLLT(DstTy.getScalarType())))))) {1500 Known.knownNot(fcNan);1501 }1502 1503 // X / -0.0 is -Inf (or NaN).1504 // +X / +X is +X1505 if (KnownLHS.isKnownNever(fcNegative) &&1506 KnownRHS.isKnownNever(fcNegative))1507 Known.knownNot(fcNegative);1508 } else {1509 // Inf REM x and x REM 0 produce NaN.1510 if (KnownLHS.isKnownNeverNaN() && KnownRHS.isKnownNeverNaN() &&1511 KnownLHS.isKnownNeverInfinity() &&1512 KnownRHS.isKnownNeverLogicalZero(MF->getDenormalMode(1513 getFltSemanticForLLT(DstTy.getScalarType())))) {1514 Known.knownNot(fcNan);1515 }1516 1517 // The sign for frem is the same as the first operand.1518 if (KnownLHS.cannotBeOrderedLessThanZero())1519 Known.knownNot(KnownFPClass::OrderedLessThanZeroMask);1520 if (KnownLHS.cannotBeOrderedGreaterThanZero())1521 Known.knownNot(KnownFPClass::OrderedGreaterThanZeroMask);1522 1523 // See if we can be more aggressive about the sign of 0.1524 if (KnownLHS.isKnownNever(fcNegative))1525 Known.knownNot(fcNegative);1526 if (KnownLHS.isKnownNever(fcPositive))1527 Known.knownNot(fcPositive);1528 }1529 1530 break;1531 }1532 case TargetOpcode::G_FPEXT: {1533 Register Dst = MI.getOperand(0).getReg();1534 Register Src = MI.getOperand(1).getReg();1535 // Infinity, nan and zero propagate from source.1536 computeKnownFPClass(R, DemandedElts, InterestedClasses, Known, Depth + 1);1537 1538 LLT DstTy = MRI.getType(Dst).getScalarType();1539 const fltSemantics &DstSem = getFltSemanticForLLT(DstTy);1540 LLT SrcTy = MRI.getType(Src).getScalarType();1541 const fltSemantics &SrcSem = getFltSemanticForLLT(SrcTy);1542 1543 // All subnormal inputs should be in the normal range in the result type.1544 if (APFloat::isRepresentableAsNormalIn(SrcSem, DstSem)) {1545 if (Known.KnownFPClasses & fcPosSubnormal)1546 Known.KnownFPClasses |= fcPosNormal;1547 if (Known.KnownFPClasses & fcNegSubnormal)1548 Known.KnownFPClasses |= fcNegNormal;1549 Known.knownNot(fcSubnormal);1550 }1551 1552 // Sign bit of a nan isn't guaranteed.1553 if (!Known.isKnownNeverNaN())1554 Known.SignBit = std::nullopt;1555 break;1556 }1557 case TargetOpcode::G_FPTRUNC: {1558 computeKnownFPClassForFPTrunc(MI, DemandedElts, InterestedClasses, Known,1559 Depth);1560 break;1561 }1562 case TargetOpcode::G_SITOFP:1563 case TargetOpcode::G_UITOFP: {1564 // Cannot produce nan1565 Known.knownNot(fcNan);1566 1567 // Integers cannot be subnormal1568 Known.knownNot(fcSubnormal);1569 1570 // sitofp and uitofp turn into +0.0 for zero.1571 Known.knownNot(fcNegZero);1572 if (Opcode == TargetOpcode::G_UITOFP)1573 Known.signBitMustBeZero();1574 1575 Register Val = MI.getOperand(1).getReg();1576 LLT Ty = MRI.getType(Val);1577 1578 if (InterestedClasses & fcInf) {1579 // Get width of largest magnitude integer (remove a bit if signed).1580 // This still works for a signed minimum value because the largest FP1581 // value is scaled by some fraction close to 2.0 (1.0 + 0.xxxx).;1582 int IntSize = Ty.getScalarSizeInBits();1583 if (Opcode == TargetOpcode::G_SITOFP)1584 --IntSize;1585 1586 // If the exponent of the largest finite FP value can hold the largest1587 // integer, the result of the cast must be finite.1588 LLT FPTy = DstTy.getScalarType();1589 const fltSemantics &FltSem = getFltSemanticForLLT(FPTy);1590 if (ilogb(APFloat::getLargest(FltSem)) >= IntSize)1591 Known.knownNot(fcInf);1592 }1593 1594 break;1595 }1596 // case TargetOpcode::G_MERGE_VALUES:1597 case TargetOpcode::G_BUILD_VECTOR:1598 case TargetOpcode::G_CONCAT_VECTORS: {1599 GMergeLikeInstr &Merge = cast<GMergeLikeInstr>(MI);1600 1601 if (!DstTy.isFixedVector())1602 break;1603 1604 bool First = true;1605 for (unsigned Idx = 0; Idx < Merge.getNumSources(); ++Idx) {1606 // We know the index we are inserting to, so clear it from Vec check.1607 bool NeedsElt = DemandedElts[Idx];1608 1609 // Do we demand the inserted element?1610 if (NeedsElt) {1611 Register Src = Merge.getSourceReg(Idx);1612 if (First) {1613 computeKnownFPClass(Src, Known, InterestedClasses, Depth + 1);1614 First = false;1615 } else {1616 KnownFPClass Known2;1617 computeKnownFPClass(Src, Known2, InterestedClasses, Depth + 1);1618 Known |= Known2;1619 }1620 1621 // If we don't know any bits, early out.1622 if (Known.isUnknown())1623 break;1624 }1625 }1626 1627 break;1628 }1629 case TargetOpcode::G_EXTRACT_VECTOR_ELT: {1630 // Look through extract element. If the index is non-constant or1631 // out-of-range demand all elements, otherwise just the extracted1632 // element.1633 GExtractVectorElement &Extract = cast<GExtractVectorElement>(MI);1634 Register Vec = Extract.getVectorReg();1635 Register Idx = Extract.getIndexReg();1636 1637 auto CIdx = getIConstantVRegVal(Idx, MRI);1638 1639 LLT VecTy = MRI.getType(Vec);1640 1641 if (VecTy.isFixedVector()) {1642 unsigned NumElts = VecTy.getNumElements();1643 APInt DemandedVecElts = APInt::getAllOnes(NumElts);1644 if (CIdx && CIdx->ult(NumElts))1645 DemandedVecElts = APInt::getOneBitSet(NumElts, CIdx->getZExtValue());1646 return computeKnownFPClass(Vec, DemandedVecElts, InterestedClasses, Known,1647 Depth + 1);1648 }1649 1650 break;1651 }1652 case TargetOpcode::G_INSERT_VECTOR_ELT: {1653 GInsertVectorElement &Insert = cast<GInsertVectorElement>(MI);1654 Register Vec = Insert.getVectorReg();1655 Register Elt = Insert.getElementReg();1656 Register Idx = Insert.getIndexReg();1657 1658 LLT VecTy = MRI.getType(Vec);1659 1660 if (VecTy.isScalableVector())1661 return;1662 1663 auto CIdx = getIConstantVRegVal(Idx, MRI);1664 1665 unsigned NumElts = DemandedElts.getBitWidth();1666 APInt DemandedVecElts = DemandedElts;1667 bool NeedsElt = true;1668 // If we know the index we are inserting to, clear it from Vec check.1669 if (CIdx && CIdx->ult(NumElts)) {1670 DemandedVecElts.clearBit(CIdx->getZExtValue());1671 NeedsElt = DemandedElts[CIdx->getZExtValue()];1672 }1673 1674 // Do we demand the inserted element?1675 if (NeedsElt) {1676 computeKnownFPClass(Elt, Known, InterestedClasses, Depth + 1);1677 // If we don't know any bits, early out.1678 if (Known.isUnknown())1679 break;1680 } else {1681 Known.KnownFPClasses = fcNone;1682 }1683 1684 // Do we need anymore elements from Vec?1685 if (!DemandedVecElts.isZero()) {1686 KnownFPClass Known2;1687 computeKnownFPClass(Vec, DemandedVecElts, InterestedClasses, Known2,1688 Depth + 1);1689 Known |= Known2;1690 }1691 1692 break;1693 }1694 case TargetOpcode::G_SHUFFLE_VECTOR: {1695 // For undef elements, we don't know anything about the common state of1696 // the shuffle result.1697 GShuffleVector &Shuf = cast<GShuffleVector>(MI);1698 APInt DemandedLHS, DemandedRHS;1699 if (DstTy.isScalableVector()) {1700 assert(DemandedElts == APInt(1, 1));1701 DemandedLHS = DemandedRHS = DemandedElts;1702 } else {1703 if (!llvm::getShuffleDemandedElts(DstTy.getNumElements(), Shuf.getMask(),1704 DemandedElts, DemandedLHS,1705 DemandedRHS)) {1706 Known.resetAll();1707 return;1708 }1709 }1710 1711 if (!!DemandedLHS) {1712 Register LHS = Shuf.getSrc1Reg();1713 computeKnownFPClass(LHS, DemandedLHS, InterestedClasses, Known,1714 Depth + 1);1715 1716 // If we don't know any bits, early out.1717 if (Known.isUnknown())1718 break;1719 } else {1720 Known.KnownFPClasses = fcNone;1721 }1722 1723 if (!!DemandedRHS) {1724 KnownFPClass Known2;1725 Register RHS = Shuf.getSrc2Reg();1726 computeKnownFPClass(RHS, DemandedRHS, InterestedClasses, Known2,1727 Depth + 1);1728 Known |= Known2;1729 }1730 break;1731 }1732 case TargetOpcode::COPY: {1733 Register Src = MI.getOperand(1).getReg();1734 1735 if (!Src.isVirtual())1736 return;1737 1738 computeKnownFPClass(Src, DemandedElts, InterestedClasses, Known, Depth + 1);1739 break;1740 }1741 }1742}1743 1744KnownFPClass1745GISelValueTracking::computeKnownFPClass(Register R, const APInt &DemandedElts,1746 FPClassTest InterestedClasses,1747 unsigned Depth) {1748 KnownFPClass KnownClasses;1749 computeKnownFPClass(R, DemandedElts, InterestedClasses, KnownClasses, Depth);1750 return KnownClasses;1751}1752 1753KnownFPClass GISelValueTracking::computeKnownFPClass(1754 Register R, FPClassTest InterestedClasses, unsigned Depth) {1755 KnownFPClass Known;1756 computeKnownFPClass(R, Known, InterestedClasses, Depth);1757 return Known;1758}1759 1760KnownFPClass GISelValueTracking::computeKnownFPClass(1761 Register R, const APInt &DemandedElts, uint32_t Flags,1762 FPClassTest InterestedClasses, unsigned Depth) {1763 if (Flags & MachineInstr::MIFlag::FmNoNans)1764 InterestedClasses &= ~fcNan;1765 if (Flags & MachineInstr::MIFlag::FmNoInfs)1766 InterestedClasses &= ~fcInf;1767 1768 KnownFPClass Result =1769 computeKnownFPClass(R, DemandedElts, InterestedClasses, Depth);1770 1771 if (Flags & MachineInstr::MIFlag::FmNoNans)1772 Result.KnownFPClasses &= ~fcNan;1773 if (Flags & MachineInstr::MIFlag::FmNoInfs)1774 Result.KnownFPClasses &= ~fcInf;1775 return Result;1776}1777 1778KnownFPClass GISelValueTracking::computeKnownFPClass(1779 Register R, uint32_t Flags, FPClassTest InterestedClasses, unsigned Depth) {1780 LLT Ty = MRI.getType(R);1781 APInt DemandedElts =1782 Ty.isFixedVector() ? APInt::getAllOnes(Ty.getNumElements()) : APInt(1, 1);1783 return computeKnownFPClass(R, DemandedElts, Flags, InterestedClasses, Depth);1784}1785 1786/// Compute number of sign bits for the intersection of \p Src0 and \p Src11787unsigned GISelValueTracking::computeNumSignBitsMin(Register Src0, Register Src1,1788 const APInt &DemandedElts,1789 unsigned Depth) {1790 // Test src1 first, since we canonicalize simpler expressions to the RHS.1791 unsigned Src1SignBits = computeNumSignBits(Src1, DemandedElts, Depth);1792 if (Src1SignBits == 1)1793 return 1;1794 return std::min(computeNumSignBits(Src0, DemandedElts, Depth), Src1SignBits);1795}1796 1797/// Compute the known number of sign bits with attached range metadata in the1798/// memory operand. If this is an extending load, accounts for the behavior of1799/// the high bits.1800static unsigned computeNumSignBitsFromRangeMetadata(const GAnyLoad *Ld,1801 unsigned TyBits) {1802 const MDNode *Ranges = Ld->getRanges();1803 if (!Ranges)1804 return 1;1805 1806 ConstantRange CR = getConstantRangeFromMetadata(*Ranges);1807 if (TyBits > CR.getBitWidth()) {1808 switch (Ld->getOpcode()) {1809 case TargetOpcode::G_SEXTLOAD:1810 CR = CR.signExtend(TyBits);1811 break;1812 case TargetOpcode::G_ZEXTLOAD:1813 CR = CR.zeroExtend(TyBits);1814 break;1815 default:1816 break;1817 }1818 }1819 1820 return std::min(CR.getSignedMin().getNumSignBits(),1821 CR.getSignedMax().getNumSignBits());1822}1823 1824unsigned GISelValueTracking::computeNumSignBits(Register R,1825 const APInt &DemandedElts,1826 unsigned Depth) {1827 MachineInstr &MI = *MRI.getVRegDef(R);1828 unsigned Opcode = MI.getOpcode();1829 1830 if (Opcode == TargetOpcode::G_CONSTANT)1831 return MI.getOperand(1).getCImm()->getValue().getNumSignBits();1832 1833 if (Depth == getMaxDepth())1834 return 1;1835 1836 if (!DemandedElts)1837 return 1; // No demanded elts, better to assume we don't know anything.1838 1839 LLT DstTy = MRI.getType(R);1840 const unsigned TyBits = DstTy.getScalarSizeInBits();1841 1842 // Handle the case where this is called on a register that does not have a1843 // type constraint. This is unlikely to occur except by looking through copies1844 // but it is possible for the initial register being queried to be in this1845 // state.1846 if (!DstTy.isValid())1847 return 1;1848 1849 unsigned FirstAnswer = 1;1850 switch (Opcode) {1851 case TargetOpcode::COPY: {1852 MachineOperand &Src = MI.getOperand(1);1853 if (Src.getReg().isVirtual() && Src.getSubReg() == 0 &&1854 MRI.getType(Src.getReg()).isValid()) {1855 // Don't increment Depth for this one since we didn't do any work.1856 return computeNumSignBits(Src.getReg(), DemandedElts, Depth);1857 }1858 1859 return 1;1860 }1861 case TargetOpcode::G_SEXT: {1862 Register Src = MI.getOperand(1).getReg();1863 LLT SrcTy = MRI.getType(Src);1864 unsigned Tmp = DstTy.getScalarSizeInBits() - SrcTy.getScalarSizeInBits();1865 return computeNumSignBits(Src, DemandedElts, Depth + 1) + Tmp;1866 }1867 case TargetOpcode::G_ASSERT_SEXT:1868 case TargetOpcode::G_SEXT_INREG: {1869 // Max of the input and what this extends.1870 Register Src = MI.getOperand(1).getReg();1871 unsigned SrcBits = MI.getOperand(2).getImm();1872 unsigned InRegBits = TyBits - SrcBits + 1;1873 return std::max(computeNumSignBits(Src, DemandedElts, Depth + 1),1874 InRegBits);1875 }1876 case TargetOpcode::G_LOAD: {1877 GLoad *Ld = cast<GLoad>(&MI);1878 if (DemandedElts != 1 || !getDataLayout().isLittleEndian())1879 break;1880 1881 return computeNumSignBitsFromRangeMetadata(Ld, TyBits);1882 }1883 case TargetOpcode::G_SEXTLOAD: {1884 GSExtLoad *Ld = cast<GSExtLoad>(&MI);1885 1886 // FIXME: We need an in-memory type representation.1887 if (DstTy.isVector())1888 return 1;1889 1890 unsigned NumBits = computeNumSignBitsFromRangeMetadata(Ld, TyBits);1891 if (NumBits != 1)1892 return NumBits;1893 1894 // e.g. i16->i32 = '17' bits known.1895 const MachineMemOperand *MMO = *MI.memoperands_begin();1896 return TyBits - MMO->getSizeInBits().getValue() + 1;1897 }1898 case TargetOpcode::G_ZEXTLOAD: {1899 GZExtLoad *Ld = cast<GZExtLoad>(&MI);1900 1901 // FIXME: We need an in-memory type representation.1902 if (DstTy.isVector())1903 return 1;1904 1905 unsigned NumBits = computeNumSignBitsFromRangeMetadata(Ld, TyBits);1906 if (NumBits != 1)1907 return NumBits;1908 1909 // e.g. i16->i32 = '16' bits known.1910 const MachineMemOperand *MMO = *MI.memoperands_begin();1911 return TyBits - MMO->getSizeInBits().getValue();1912 }1913 case TargetOpcode::G_AND:1914 case TargetOpcode::G_OR:1915 case TargetOpcode::G_XOR: {1916 Register Src1 = MI.getOperand(1).getReg();1917 unsigned Src1NumSignBits =1918 computeNumSignBits(Src1, DemandedElts, Depth + 1);1919 if (Src1NumSignBits != 1) {1920 Register Src2 = MI.getOperand(2).getReg();1921 unsigned Src2NumSignBits =1922 computeNumSignBits(Src2, DemandedElts, Depth + 1);1923 FirstAnswer = std::min(Src1NumSignBits, Src2NumSignBits);1924 }1925 break;1926 }1927 case TargetOpcode::G_ASHR: {1928 Register Src1 = MI.getOperand(1).getReg();1929 Register Src2 = MI.getOperand(2).getReg();1930 FirstAnswer = computeNumSignBits(Src1, DemandedElts, Depth + 1);1931 if (auto C = getValidMinimumShiftAmount(Src2, DemandedElts, Depth + 1))1932 FirstAnswer = std::min<uint64_t>(FirstAnswer + *C, TyBits);1933 break;1934 }1935 case TargetOpcode::G_SHL: {1936 Register Src1 = MI.getOperand(1).getReg();1937 Register Src2 = MI.getOperand(2).getReg();1938 if (std::optional<ConstantRange> ShAmtRange =1939 getValidShiftAmountRange(Src2, DemandedElts, Depth + 1)) {1940 uint64_t MaxShAmt = ShAmtRange->getUnsignedMax().getZExtValue();1941 uint64_t MinShAmt = ShAmtRange->getUnsignedMin().getZExtValue();1942 1943 MachineInstr &ExtMI = *MRI.getVRegDef(Src1);1944 unsigned ExtOpc = ExtMI.getOpcode();1945 1946 // Try to look through ZERO/SIGN/ANY_EXTEND. If all extended bits are1947 // shifted out, then we can compute the number of sign bits for the1948 // operand being extended. A future improvement could be to pass along the1949 // "shifted left by" information in the recursive calls to1950 // ComputeKnownSignBits. Allowing us to handle this more generically.1951 if (ExtOpc == TargetOpcode::G_SEXT || ExtOpc == TargetOpcode::G_ZEXT ||1952 ExtOpc == TargetOpcode::G_ANYEXT) {1953 LLT ExtTy = MRI.getType(Src1);1954 Register Extendee = ExtMI.getOperand(1).getReg();1955 LLT ExtendeeTy = MRI.getType(Extendee);1956 uint64_t SizeDiff =1957 ExtTy.getScalarSizeInBits() - ExtendeeTy.getScalarSizeInBits();1958 1959 if (SizeDiff <= MinShAmt) {1960 unsigned Tmp =1961 SizeDiff + computeNumSignBits(Extendee, DemandedElts, Depth + 1);1962 if (MaxShAmt < Tmp)1963 return Tmp - MaxShAmt;1964 }1965 }1966 // shl destroys sign bits, ensure it doesn't shift out all sign bits.1967 unsigned Tmp = computeNumSignBits(Src1, DemandedElts, Depth + 1);1968 if (MaxShAmt < Tmp)1969 return Tmp - MaxShAmt;1970 }1971 break;1972 }1973 case TargetOpcode::G_TRUNC: {1974 Register Src = MI.getOperand(1).getReg();1975 LLT SrcTy = MRI.getType(Src);1976 1977 // Check if the sign bits of source go down as far as the truncated value.1978 unsigned DstTyBits = DstTy.getScalarSizeInBits();1979 unsigned NumSrcBits = SrcTy.getScalarSizeInBits();1980 unsigned NumSrcSignBits = computeNumSignBits(Src, DemandedElts, Depth + 1);1981 if (NumSrcSignBits > (NumSrcBits - DstTyBits))1982 return NumSrcSignBits - (NumSrcBits - DstTyBits);1983 break;1984 }1985 case TargetOpcode::G_SELECT: {1986 return computeNumSignBitsMin(MI.getOperand(2).getReg(),1987 MI.getOperand(3).getReg(), DemandedElts,1988 Depth + 1);1989 }1990 case TargetOpcode::G_SMIN:1991 case TargetOpcode::G_SMAX:1992 case TargetOpcode::G_UMIN:1993 case TargetOpcode::G_UMAX:1994 // TODO: Handle clamp pattern with number of sign bits for SMIN/SMAX.1995 return computeNumSignBitsMin(MI.getOperand(1).getReg(),1996 MI.getOperand(2).getReg(), DemandedElts,1997 Depth + 1);1998 case TargetOpcode::G_SADDO:1999 case TargetOpcode::G_SADDE:2000 case TargetOpcode::G_UADDO:2001 case TargetOpcode::G_UADDE:2002 case TargetOpcode::G_SSUBO:2003 case TargetOpcode::G_SSUBE:2004 case TargetOpcode::G_USUBO:2005 case TargetOpcode::G_USUBE:2006 case TargetOpcode::G_SMULO:2007 case TargetOpcode::G_UMULO: {2008 // If compares returns 0/-1, all bits are sign bits.2009 // We know that we have an integer-based boolean since these operations2010 // are only available for integer.2011 if (MI.getOperand(1).getReg() == R) {2012 if (TL.getBooleanContents(DstTy.isVector(), false) ==2013 TargetLowering::ZeroOrNegativeOneBooleanContent)2014 return TyBits;2015 }2016 2017 break;2018 }2019 case TargetOpcode::G_SUB: {2020 Register Src2 = MI.getOperand(2).getReg();2021 unsigned Src2NumSignBits =2022 computeNumSignBits(Src2, DemandedElts, Depth + 1);2023 if (Src2NumSignBits == 1)2024 return 1; // Early out.2025 2026 // Handle NEG.2027 Register Src1 = MI.getOperand(1).getReg();2028 KnownBits Known1 = getKnownBits(Src1, DemandedElts, Depth);2029 if (Known1.isZero()) {2030 KnownBits Known2 = getKnownBits(Src2, DemandedElts, Depth);2031 // If the input is known to be 0 or 1, the output is 0/-1, which is all2032 // sign bits set.2033 if ((Known2.Zero | 1).isAllOnes())2034 return TyBits;2035 2036 // If the input is known to be positive (the sign bit is known clear),2037 // the output of the NEG has, at worst, the same number of sign bits as2038 // the input.2039 if (Known2.isNonNegative()) {2040 FirstAnswer = Src2NumSignBits;2041 break;2042 }2043 2044 // Otherwise, we treat this like a SUB.2045 }2046 2047 unsigned Src1NumSignBits =2048 computeNumSignBits(Src1, DemandedElts, Depth + 1);2049 if (Src1NumSignBits == 1)2050 return 1; // Early Out.2051 2052 // Sub can have at most one carry bit. Thus we know that the output2053 // is, at worst, one more bit than the inputs.2054 FirstAnswer = std::min(Src1NumSignBits, Src2NumSignBits) - 1;2055 break;2056 }2057 case TargetOpcode::G_ADD: {2058 Register Src2 = MI.getOperand(2).getReg();2059 unsigned Src2NumSignBits =2060 computeNumSignBits(Src2, DemandedElts, Depth + 1);2061 if (Src2NumSignBits <= 2)2062 return 1; // Early out.2063 2064 Register Src1 = MI.getOperand(1).getReg();2065 unsigned Src1NumSignBits =2066 computeNumSignBits(Src1, DemandedElts, Depth + 1);2067 if (Src1NumSignBits == 1)2068 return 1; // Early Out.2069 2070 // Special case decrementing a value (ADD X, -1):2071 KnownBits Known2 = getKnownBits(Src2, DemandedElts, Depth);2072 if (Known2.isAllOnes()) {2073 KnownBits Known1 = getKnownBits(Src1, DemandedElts, Depth);2074 // If the input is known to be 0 or 1, the output is 0/-1, which is all2075 // sign bits set.2076 if ((Known1.Zero | 1).isAllOnes())2077 return TyBits;2078 2079 // If we are subtracting one from a positive number, there is no carry2080 // out of the result.2081 if (Known1.isNonNegative()) {2082 FirstAnswer = Src1NumSignBits;2083 break;2084 }2085 2086 // Otherwise, we treat this like an ADD.2087 }2088 2089 // Add can have at most one carry bit. Thus we know that the output2090 // is, at worst, one more bit than the inputs.2091 FirstAnswer = std::min(Src1NumSignBits, Src2NumSignBits) - 1;2092 break;2093 }2094 case TargetOpcode::G_FCMP:2095 case TargetOpcode::G_ICMP: {2096 bool IsFP = Opcode == TargetOpcode::G_FCMP;2097 if (TyBits == 1)2098 break;2099 auto BC = TL.getBooleanContents(DstTy.isVector(), IsFP);2100 if (BC == TargetLoweringBase::ZeroOrNegativeOneBooleanContent)2101 return TyBits; // All bits are sign bits.2102 if (BC == TargetLowering::ZeroOrOneBooleanContent)2103 return TyBits - 1; // Every always-zero bit is a sign bit.2104 break;2105 }2106 case TargetOpcode::G_BUILD_VECTOR: {2107 // Collect the known bits that are shared by every demanded vector element.2108 FirstAnswer = TyBits;2109 APInt SingleDemandedElt(1, 1);2110 for (const auto &[I, MO] : enumerate(drop_begin(MI.operands()))) {2111 if (!DemandedElts[I])2112 continue;2113 2114 unsigned Tmp2 =2115 computeNumSignBits(MO.getReg(), SingleDemandedElt, Depth + 1);2116 FirstAnswer = std::min(FirstAnswer, Tmp2);2117 2118 // If we don't know any bits, early out.2119 if (FirstAnswer == 1)2120 break;2121 }2122 break;2123 }2124 case TargetOpcode::G_CONCAT_VECTORS: {2125 if (MRI.getType(MI.getOperand(0).getReg()).isScalableVector())2126 break;2127 FirstAnswer = TyBits;2128 // Determine the minimum number of sign bits across all demanded2129 // elts of the input vectors. Early out if the result is already 1.2130 unsigned NumSubVectorElts =2131 MRI.getType(MI.getOperand(1).getReg()).getNumElements();2132 for (const auto &[I, MO] : enumerate(drop_begin(MI.operands()))) {2133 APInt DemandedSub =2134 DemandedElts.extractBits(NumSubVectorElts, I * NumSubVectorElts);2135 if (!DemandedSub)2136 continue;2137 unsigned Tmp2 = computeNumSignBits(MO.getReg(), DemandedSub, Depth + 1);2138 2139 FirstAnswer = std::min(FirstAnswer, Tmp2);2140 2141 // If we don't know any bits, early out.2142 if (FirstAnswer == 1)2143 break;2144 }2145 break;2146 }2147 case TargetOpcode::G_SHUFFLE_VECTOR: {2148 // Collect the minimum number of sign bits that are shared by every vector2149 // element referenced by the shuffle.2150 APInt DemandedLHS, DemandedRHS;2151 Register Src1 = MI.getOperand(1).getReg();2152 unsigned NumElts = MRI.getType(Src1).getNumElements();2153 if (!getShuffleDemandedElts(NumElts, MI.getOperand(3).getShuffleMask(),2154 DemandedElts, DemandedLHS, DemandedRHS))2155 return 1;2156 2157 if (!!DemandedLHS)2158 FirstAnswer = computeNumSignBits(Src1, DemandedLHS, Depth + 1);2159 // If we don't know anything, early out and try computeKnownBits fall-back.2160 if (FirstAnswer == 1)2161 break;2162 if (!!DemandedRHS) {2163 unsigned Tmp2 =2164 computeNumSignBits(MI.getOperand(2).getReg(), DemandedRHS, Depth + 1);2165 FirstAnswer = std::min(FirstAnswer, Tmp2);2166 }2167 break;2168 }2169 case TargetOpcode::G_SPLAT_VECTOR: {2170 // Check if the sign bits of source go down as far as the truncated value.2171 Register Src = MI.getOperand(1).getReg();2172 unsigned NumSrcSignBits = computeNumSignBits(Src, APInt(1, 1), Depth + 1);2173 unsigned NumSrcBits = MRI.getType(Src).getSizeInBits();2174 if (NumSrcSignBits > (NumSrcBits - TyBits))2175 return NumSrcSignBits - (NumSrcBits - TyBits);2176 break;2177 }2178 case TargetOpcode::G_INTRINSIC:2179 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:2180 case TargetOpcode::G_INTRINSIC_CONVERGENT:2181 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:2182 default: {2183 unsigned NumBits =2184 TL.computeNumSignBitsForTargetInstr(*this, R, DemandedElts, MRI, Depth);2185 if (NumBits > 1)2186 FirstAnswer = std::max(FirstAnswer, NumBits);2187 break;2188 }2189 }2190 2191 // Finally, if we can prove that the top bits of the result are 0's or 1's,2192 // use this information.2193 KnownBits Known = getKnownBits(R, DemandedElts, Depth);2194 APInt Mask;2195 if (Known.isNonNegative()) { // sign bit is 02196 Mask = Known.Zero;2197 } else if (Known.isNegative()) { // sign bit is 1;2198 Mask = Known.One;2199 } else {2200 // Nothing known.2201 return FirstAnswer;2202 }2203 2204 // Okay, we know that the sign bit in Mask is set. Use CLO to determine2205 // the number of identical bits in the top of the input value.2206 Mask <<= Mask.getBitWidth() - TyBits;2207 return std::max(FirstAnswer, Mask.countl_one());2208}2209 2210unsigned GISelValueTracking::computeNumSignBits(Register R, unsigned Depth) {2211 LLT Ty = MRI.getType(R);2212 APInt DemandedElts =2213 Ty.isFixedVector() ? APInt::getAllOnes(Ty.getNumElements()) : APInt(1, 1);2214 return computeNumSignBits(R, DemandedElts, Depth);2215}2216 2217std::optional<ConstantRange> GISelValueTracking::getValidShiftAmountRange(2218 Register R, const APInt &DemandedElts, unsigned Depth) {2219 // Shifting more than the bitwidth is not valid.2220 MachineInstr &MI = *MRI.getVRegDef(R);2221 unsigned Opcode = MI.getOpcode();2222 2223 LLT Ty = MRI.getType(R);2224 unsigned BitWidth = Ty.getScalarSizeInBits();2225 2226 if (Opcode == TargetOpcode::G_CONSTANT) {2227 const APInt &ShAmt = MI.getOperand(1).getCImm()->getValue();2228 if (ShAmt.uge(BitWidth))2229 return std::nullopt;2230 return ConstantRange(ShAmt);2231 }2232 2233 if (Opcode == TargetOpcode::G_BUILD_VECTOR) {2234 const APInt *MinAmt = nullptr, *MaxAmt = nullptr;2235 for (unsigned I = 0, E = MI.getNumOperands() - 1; I != E; ++I) {2236 if (!DemandedElts[I])2237 continue;2238 MachineInstr *Op = MRI.getVRegDef(MI.getOperand(I + 1).getReg());2239 if (Op->getOpcode() != TargetOpcode::G_CONSTANT) {2240 MinAmt = MaxAmt = nullptr;2241 break;2242 }2243 2244 const APInt &ShAmt = Op->getOperand(1).getCImm()->getValue();2245 if (ShAmt.uge(BitWidth))2246 return std::nullopt;2247 if (!MinAmt || MinAmt->ugt(ShAmt))2248 MinAmt = &ShAmt;2249 if (!MaxAmt || MaxAmt->ult(ShAmt))2250 MaxAmt = &ShAmt;2251 }2252 assert(((!MinAmt && !MaxAmt) || (MinAmt && MaxAmt)) &&2253 "Failed to find matching min/max shift amounts");2254 if (MinAmt && MaxAmt)2255 return ConstantRange(*MinAmt, *MaxAmt + 1);2256 }2257 2258 // Use computeKnownBits to find a hidden constant/knownbits (usually type2259 // legalized). e.g. Hidden behind multiple bitcasts/build_vector/casts etc.2260 KnownBits KnownAmt = getKnownBits(R, DemandedElts, Depth);2261 if (KnownAmt.getMaxValue().ult(BitWidth))2262 return ConstantRange::fromKnownBits(KnownAmt, /*IsSigned=*/false);2263 2264 return std::nullopt;2265}2266 2267std::optional<uint64_t> GISelValueTracking::getValidMinimumShiftAmount(2268 Register R, const APInt &DemandedElts, unsigned Depth) {2269 if (std::optional<ConstantRange> AmtRange =2270 getValidShiftAmountRange(R, DemandedElts, Depth))2271 return AmtRange->getUnsignedMin().getZExtValue();2272 return std::nullopt;2273}2274 2275void GISelValueTrackingAnalysisLegacy::getAnalysisUsage(2276 AnalysisUsage &AU) const {2277 AU.setPreservesAll();2278 MachineFunctionPass::getAnalysisUsage(AU);2279}2280 2281bool GISelValueTrackingAnalysisLegacy::runOnMachineFunction(2282 MachineFunction &MF) {2283 return false;2284}2285 2286GISelValueTracking &GISelValueTrackingAnalysisLegacy::get(MachineFunction &MF) {2287 if (!Info) {2288 unsigned MaxDepth =2289 MF.getTarget().getOptLevel() == CodeGenOptLevel::None ? 2 : 6;2290 Info = std::make_unique<GISelValueTracking>(MF, MaxDepth);2291 }2292 return *Info;2293}2294 2295AnalysisKey GISelValueTrackingAnalysis::Key;2296 2297GISelValueTracking2298GISelValueTrackingAnalysis::run(MachineFunction &MF,2299 MachineFunctionAnalysisManager &MFAM) {2300 return Result(MF);2301}2302 2303PreservedAnalyses2304GISelValueTrackingPrinterPass::run(MachineFunction &MF,2305 MachineFunctionAnalysisManager &MFAM) {2306 auto &VTA = MFAM.getResult<GISelValueTrackingAnalysis>(MF);2307 const auto &MRI = MF.getRegInfo();2308 OS << "name: ";2309 MF.getFunction().printAsOperand(OS, /*PrintType=*/false);2310 OS << '\n';2311 2312 for (MachineBasicBlock &BB : MF) {2313 for (MachineInstr &MI : BB) {2314 for (MachineOperand &MO : MI.defs()) {2315 if (!MO.isReg() || MO.getReg().isPhysical())2316 continue;2317 Register Reg = MO.getReg();2318 if (!MRI.getType(Reg).isValid())2319 continue;2320 KnownBits Known = VTA.getKnownBits(Reg);2321 unsigned SignedBits = VTA.computeNumSignBits(Reg);2322 OS << " " << MO << " KnownBits:" << Known << " SignBits:" << SignedBits2323 << '\n';2324 };2325 }2326 }2327 return PreservedAnalyses::all();2328}2329