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1//===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// Methods common to all machine instructions.10//11//===----------------------------------------------------------------------===//12 13#include "llvm/CodeGen/MachineInstr.h"14#include "llvm/ADT/ArrayRef.h"15#include "llvm/ADT/Hashing.h"16#include "llvm/ADT/STLExtras.h"17#include "llvm/ADT/SmallBitVector.h"18#include "llvm/ADT/SmallVector.h"19#include "llvm/Analysis/AliasAnalysis.h"20#include "llvm/Analysis/MemoryLocation.h"21#include "llvm/CodeGen/LiveRegUnits.h"22#include "llvm/CodeGen/MachineBasicBlock.h"23#include "llvm/CodeGen/MachineFrameInfo.h"24#include "llvm/CodeGen/MachineFunction.h"25#include "llvm/CodeGen/MachineInstrBuilder.h"26#include "llvm/CodeGen/MachineInstrBundle.h"27#include "llvm/CodeGen/MachineMemOperand.h"28#include "llvm/CodeGen/MachineModuleInfo.h"29#include "llvm/CodeGen/MachineOperand.h"30#include "llvm/CodeGen/MachineRegisterInfo.h"31#include "llvm/CodeGen/PseudoSourceValue.h"32#include "llvm/CodeGen/Register.h"33#include "llvm/CodeGen/StackMaps.h"34#include "llvm/CodeGen/TargetInstrInfo.h"35#include "llvm/CodeGen/TargetRegisterInfo.h"36#include "llvm/CodeGen/TargetSubtargetInfo.h"37#include "llvm/CodeGenTypes/LowLevelType.h"38#include "llvm/IR/Constants.h"39#include "llvm/IR/DebugInfoMetadata.h"40#include "llvm/IR/DebugLoc.h"41#include "llvm/IR/Function.h"42#include "llvm/IR/InlineAsm.h"43#include "llvm/IR/Instructions.h"44#include "llvm/IR/LLVMContext.h"45#include "llvm/IR/Metadata.h"46#include "llvm/IR/Module.h"47#include "llvm/IR/ModuleSlotTracker.h"48#include "llvm/IR/Operator.h"49#include "llvm/MC/MCInstrDesc.h"50#include "llvm/MC/MCRegisterInfo.h"51#include "llvm/Support/Casting.h"52#include "llvm/Support/Compiler.h"53#include "llvm/Support/Debug.h"54#include "llvm/Support/ErrorHandling.h"55#include "llvm/Support/FormattedStream.h"56#include "llvm/Support/raw_ostream.h"57#include "llvm/Target/TargetMachine.h"58#include <algorithm>59#include <cassert>60#include <cstdint>61#include <cstring>62#include <utility>63 64using namespace llvm;65 66static cl::opt<bool>67    PrintMIAddrs("print-mi-addrs", cl::Hidden,68                 cl::desc("Print addresses of MachineInstrs when dumping"));69 70static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) {71  if (const MachineBasicBlock *MBB = MI.getParent())72    if (const MachineFunction *MF = MBB->getParent())73      return MF;74  return nullptr;75}76 77// Try to crawl up to the machine function and get TRI/MRI/TII from it.78static void tryToGetTargetInfo(const MachineInstr &MI,79                               const TargetRegisterInfo *&TRI,80                               const MachineRegisterInfo *&MRI,81                               const TargetInstrInfo *&TII) {82 83  if (const MachineFunction *MF = getMFIfAvailable(MI)) {84    TRI = MF->getSubtarget().getRegisterInfo();85    MRI = &MF->getRegInfo();86    TII = MF->getSubtarget().getInstrInfo();87  }88}89 90void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {91  for (MCPhysReg ImpDef : MCID->implicit_defs())92    addOperand(MF, MachineOperand::CreateReg(ImpDef, true, true));93  for (MCPhysReg ImpUse : MCID->implicit_uses())94    addOperand(MF, MachineOperand::CreateReg(ImpUse, false, true));95}96 97/// MachineInstr ctor - This constructor creates a MachineInstr and adds the98/// implicit operands. It reserves space for the number of operands specified by99/// the MCInstrDesc.100MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &TID,101                           DebugLoc DL, bool NoImp)102    : MCID(&TID), NumOperands(0), Flags(0), AsmPrinterFlags(0),103      DbgLoc(std::move(DL)), DebugInstrNum(0), Opcode(TID.Opcode) {104  assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");105 106  // Reserve space for the expected number of operands.107  if (unsigned NumOps = MCID->getNumOperands() + MCID->implicit_defs().size() +108                        MCID->implicit_uses().size()) {109    CapOperands = OperandCapacity::get(NumOps);110    Operands = MF.allocateOperandArray(CapOperands);111  }112 113  if (!NoImp)114    addImplicitDefUseOperands(MF);115}116 117/// MachineInstr ctor - Copies MachineInstr arg exactly.118/// Does not copy the number from debug instruction numbering, to preserve119/// uniqueness.120MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)121    : MCID(&MI.getDesc()), NumOperands(0), Flags(0), AsmPrinterFlags(0),122      Info(MI.Info), DbgLoc(MI.getDebugLoc()), DebugInstrNum(0),123      Opcode(MI.getOpcode()) {124  assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");125 126  CapOperands = OperandCapacity::get(MI.getNumOperands());127  Operands = MF.allocateOperandArray(CapOperands);128 129  // Copy operands.130  for (const MachineOperand &MO : MI.operands())131    addOperand(MF, MO);132 133  // Replicate ties between the operands, which addOperand was not134  // able to do reliably.135  for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {136    MachineOperand &NewMO = getOperand(i);137    const MachineOperand &OrigMO = MI.getOperand(i);138    NewMO.TiedTo = OrigMO.TiedTo;139  }140 141  // Copy all the sensible flags.142  setFlags(MI.Flags);143}144 145void MachineInstr::setDesc(const MCInstrDesc &TID) {146  if (getParent())147    getMF()->handleChangeDesc(*this, TID);148  MCID = &TID;149  Opcode = TID.Opcode;150}151 152void MachineInstr::moveBefore(MachineInstr *MovePos) {153  MovePos->getParent()->splice(MovePos, getParent(), getIterator());154}155 156/// getRegInfo - If this instruction is embedded into a MachineFunction,157/// return the MachineRegisterInfo object for the current function, otherwise158/// return null.159MachineRegisterInfo *MachineInstr::getRegInfo() {160  if (MachineBasicBlock *MBB = getParent())161    return &MBB->getParent()->getRegInfo();162  return nullptr;163}164 165const MachineRegisterInfo *MachineInstr::getRegInfo() const {166  if (const MachineBasicBlock *MBB = getParent())167    return &MBB->getParent()->getRegInfo();168  return nullptr;169}170 171void MachineInstr::removeRegOperandsFromUseLists(MachineRegisterInfo &MRI) {172  for (MachineOperand &MO : operands())173    if (MO.isReg())174      MRI.removeRegOperandFromUseList(&MO);175}176 177void MachineInstr::addRegOperandsToUseLists(MachineRegisterInfo &MRI) {178  for (MachineOperand &MO : operands())179    if (MO.isReg())180      MRI.addRegOperandToUseList(&MO);181}182 183void MachineInstr::addOperand(const MachineOperand &Op) {184  MachineBasicBlock *MBB = getParent();185  assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");186  MachineFunction *MF = MBB->getParent();187  assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");188  addOperand(*MF, Op);189}190 191/// Move NumOps MachineOperands from Src to Dst, with support for overlapping192/// ranges. If MRI is non-null also update use-def chains.193static void moveOperands(MachineOperand *Dst, MachineOperand *Src,194                         unsigned NumOps, MachineRegisterInfo *MRI) {195  if (MRI)196    return MRI->moveOperands(Dst, Src, NumOps);197  // MachineOperand is a trivially copyable type so we can just use memmove.198  assert(Dst && Src && "Unknown operands");199  std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));200}201 202/// addOperand - Add the specified operand to the instruction.  If it is an203/// implicit operand, it is added to the end of the operand list.  If it is204/// an explicit operand it is added at the end of the explicit operand list205/// (before the first implicit operand).206void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {207  assert(isUInt<LLVM_MI_NUMOPERANDS_BITS>(NumOperands + 1) &&208         "Cannot add more operands.");209  assert(MCID && "Cannot add operands before providing an instr descriptor");210 211  // Check if we're adding one of our existing operands.212  if (&Op >= Operands && &Op < Operands + NumOperands) {213    // This is unusual: MI->addOperand(MI->getOperand(i)).214    // If adding Op requires reallocating or moving existing operands around,215    // the Op reference could go stale. Support it by copying Op.216    MachineOperand CopyOp(Op);217    return addOperand(MF, CopyOp);218  }219 220  // Find the insert location for the new operand.  Implicit registers go at221  // the end, everything else goes before the implicit regs.222  //223  // FIXME: Allow mixed explicit and implicit operands on inline asm.224  // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as225  // implicit-defs, but they must not be moved around.  See the FIXME in226  // InstrEmitter.cpp.227  unsigned OpNo = getNumOperands();228  bool isImpReg = Op.isReg() && Op.isImplicit();229  if (!isImpReg && !isInlineAsm()) {230    while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {231      --OpNo;232      assert(!Operands[OpNo].isTied() && "Cannot move tied operands");233    }234  }235 236  // OpNo now points as the desired insertion point.  Unless this is a variadic237  // instruction, only implicit regs are allowed beyond MCID->getNumOperands().238  // RegMask operands go between the explicit and implicit operands.239  MachineRegisterInfo *MRI = getRegInfo();240 241  // Determine if the Operands array needs to be reallocated.242  // Save the old capacity and operand array.243  OperandCapacity OldCap = CapOperands;244  MachineOperand *OldOperands = Operands;245  if (!OldOperands || OldCap.getSize() == getNumOperands()) {246    CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);247    Operands = MF.allocateOperandArray(CapOperands);248    // Move the operands before the insertion point.249    if (OpNo)250      moveOperands(Operands, OldOperands, OpNo, MRI);251  }252 253  // Move the operands following the insertion point.254  if (OpNo != NumOperands)255    moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,256                 MRI);257  ++NumOperands;258 259  // Deallocate the old operand array.260  if (OldOperands != Operands && OldOperands)261    MF.deallocateOperandArray(OldCap, OldOperands);262 263  // Copy Op into place. It still needs to be inserted into the MRI use lists.264  MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);265  NewMO->ParentMI = this;266 267  // When adding a register operand, tell MRI about it.268  if (NewMO->isReg()) {269    // Ensure isOnRegUseList() returns false, regardless of Op's status.270    NewMO->Contents.Reg.Prev = nullptr;271    // Ignore existing ties. This is not a property that can be copied.272    NewMO->TiedTo = 0;273    // Add the new operand to MRI, but only for instructions in an MBB.274    if (MRI)275      MRI->addRegOperandToUseList(NewMO);276    // The MCID operand information isn't accurate until we start adding277    // explicit operands. The implicit operands are added first, then the278    // explicits are inserted before them.279    if (!isImpReg) {280      // Tie uses to defs as indicated in MCInstrDesc.281      if (NewMO->isUse()) {282        int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);283        if (DefIdx != -1)284          tieOperands(DefIdx, OpNo);285      }286      // If the register operand is flagged as early, mark the operand as such.287      if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)288        NewMO->setIsEarlyClobber(true);289    }290    // Ensure debug instructions set debug flag on register uses.291    if (NewMO->isUse() && isDebugInstr())292      NewMO->setIsDebug();293  }294}295 296void MachineInstr::removeOperand(unsigned OpNo) {297  assert(OpNo < getNumOperands() && "Invalid operand number");298  untieRegOperand(OpNo);299 300#ifndef NDEBUG301  // Moving tied operands would break the ties.302  for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)303    if (Operands[i].isReg())304      assert(!Operands[i].isTied() && "Cannot move tied operands");305#endif306 307  MachineRegisterInfo *MRI = getRegInfo();308  if (MRI && Operands[OpNo].isReg())309    MRI->removeRegOperandFromUseList(Operands + OpNo);310 311  // Don't call the MachineOperand destructor. A lot of this code depends on312  // MachineOperand having a trivial destructor anyway, and adding a call here313  // wouldn't make it 'destructor-correct'.314 315  if (unsigned N = NumOperands - 1 - OpNo)316    moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);317  --NumOperands;318}319 320void MachineInstr::setExtraInfo(MachineFunction &MF,321                                ArrayRef<MachineMemOperand *> MMOs,322                                MCSymbol *PreInstrSymbol,323                                MCSymbol *PostInstrSymbol,324                                MDNode *HeapAllocMarker, MDNode *PCSections,325                                uint32_t CFIType, MDNode *MMRAs, Value *DS) {326  bool HasPreInstrSymbol = PreInstrSymbol != nullptr;327  bool HasPostInstrSymbol = PostInstrSymbol != nullptr;328  bool HasHeapAllocMarker = HeapAllocMarker != nullptr;329  bool HasPCSections = PCSections != nullptr;330  bool HasCFIType = CFIType != 0;331  bool HasMMRAs = MMRAs != nullptr;332  bool HasDS = DS != nullptr;333  int NumPointers = MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol +334                    HasHeapAllocMarker + HasPCSections + HasCFIType + HasMMRAs +335                    HasDS;336 337  // Drop all extra info if there is none.338  if (NumPointers <= 0) {339    Info.clear();340    return;341  }342 343  // If more than one pointer, then store out of line. Store heap alloc markers344  // out of line because PointerSumType cannot hold more than 4 tag types with345  // 32-bit pointers.346  // FIXME: Maybe we should make the symbols in the extra info mutable?347  else if (NumPointers > 1 || HasMMRAs || HasHeapAllocMarker || HasPCSections ||348           HasCFIType || HasDS) {349    Info.set<EIIK_OutOfLine>(350        MF.createMIExtraInfo(MMOs, PreInstrSymbol, PostInstrSymbol,351                             HeapAllocMarker, PCSections, CFIType, MMRAs, DS));352    return;353  }354 355  // Otherwise store the single pointer inline.356  if (HasPreInstrSymbol)357    Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);358  else if (HasPostInstrSymbol)359    Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);360  else361    Info.set<EIIK_MMO>(MMOs[0]);362}363 364void MachineInstr::dropMemRefs(MachineFunction &MF) {365  if (memoperands_empty())366    return;367 368  setExtraInfo(MF, {}, getPreInstrSymbol(), getPostInstrSymbol(),369               getHeapAllocMarker(), getPCSections(), getCFIType(),370               getMMRAMetadata(), getDeactivationSymbol());371}372 373void MachineInstr::setMemRefs(MachineFunction &MF,374                              ArrayRef<MachineMemOperand *> MMOs) {375  if (MMOs.empty()) {376    dropMemRefs(MF);377    return;378  }379 380  setExtraInfo(MF, MMOs, getPreInstrSymbol(), getPostInstrSymbol(),381               getHeapAllocMarker(), getPCSections(), getCFIType(),382               getMMRAMetadata(), getDeactivationSymbol());383}384 385void MachineInstr::addMemOperand(MachineFunction &MF,386                                 MachineMemOperand *MO) {387  SmallVector<MachineMemOperand *, 2> MMOs;388  MMOs.append(memoperands_begin(), memoperands_end());389  MMOs.push_back(MO);390  setMemRefs(MF, MMOs);391}392 393void MachineInstr::cloneMemRefs(MachineFunction &MF, const MachineInstr &MI) {394  if (this == &MI)395    // Nothing to do for a self-clone!396    return;397 398  assert(&MF == MI.getMF() &&399         "Invalid machine functions when cloning memory refrences!");400  // See if we can just steal the extra info already allocated for the401  // instruction. We can do this whenever the pre- and post-instruction symbols402  // are the same (including null).403  if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&404      getPostInstrSymbol() == MI.getPostInstrSymbol() &&405      getHeapAllocMarker() == MI.getHeapAllocMarker() &&406      getPCSections() == MI.getPCSections() && getMMRAMetadata() &&407      MI.getMMRAMetadata()) {408    Info = MI.Info;409    return;410  }411 412  // Otherwise, fall back on a copy-based clone.413  setMemRefs(MF, MI.memoperands());414}415 416/// Check to see if the MMOs pointed to by the two MemRefs arrays are417/// identical.418static bool hasIdenticalMMOs(ArrayRef<MachineMemOperand *> LHS,419                             ArrayRef<MachineMemOperand *> RHS) {420  if (LHS.size() != RHS.size())421    return false;422 423  auto LHSPointees = make_pointee_range(LHS);424  auto RHSPointees = make_pointee_range(RHS);425  return std::equal(LHSPointees.begin(), LHSPointees.end(),426                    RHSPointees.begin());427}428 429void MachineInstr::cloneMergedMemRefs(MachineFunction &MF,430                                      ArrayRef<const MachineInstr *> MIs) {431  // Try handling easy numbers of MIs with simpler mechanisms.432  if (MIs.empty()) {433    dropMemRefs(MF);434    return;435  }436  if (MIs.size() == 1) {437    cloneMemRefs(MF, *MIs[0]);438    return;439  }440  // Because an empty memoperands list provides *no* information and must be441  // handled conservatively (assuming the instruction can do anything), the only442  // way to merge with it is to drop all other memoperands.443  if (MIs[0]->memoperands_empty()) {444    dropMemRefs(MF);445    return;446  }447 448  // Handle the general case.449  SmallVector<MachineMemOperand *, 2> MergedMMOs;450  // Start with the first instruction.451  assert(&MF == MIs[0]->getMF() &&452         "Invalid machine functions when cloning memory references!");453  MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());454  // Now walk all the other instructions and accumulate any different MMOs.455  for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {456    assert(&MF == MI.getMF() &&457           "Invalid machine functions when cloning memory references!");458 459    // Skip MIs with identical operands to the first. This is a somewhat460    // arbitrary hack but will catch common cases without being quadratic.461    // TODO: We could fully implement merge semantics here if needed.462    if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))463      continue;464 465    // Because an empty memoperands list provides *no* information and must be466    // handled conservatively (assuming the instruction can do anything), the467    // only way to merge with it is to drop all other memoperands.468    if (MI.memoperands_empty()) {469      dropMemRefs(MF);470      return;471    }472 473    // Otherwise accumulate these into our temporary buffer of the merged state.474    MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());475  }476 477  setMemRefs(MF, MergedMMOs);478}479 480void MachineInstr::setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {481  // Do nothing if old and new symbols are the same.482  if (Symbol == getPreInstrSymbol())483    return;484 485  // If there was only one symbol and we're removing it, just clear info.486  if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {487    Info.clear();488    return;489  }490 491  setExtraInfo(MF, memoperands(), Symbol, getPostInstrSymbol(),492               getHeapAllocMarker(), getPCSections(), getCFIType(),493               getMMRAMetadata(), getDeactivationSymbol());494}495 496void MachineInstr::setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {497  // Do nothing if old and new symbols are the same.498  if (Symbol == getPostInstrSymbol())499    return;500 501  // If there was only one symbol and we're removing it, just clear info.502  if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {503    Info.clear();504    return;505  }506 507  setExtraInfo(MF, memoperands(), getPreInstrSymbol(), Symbol,508               getHeapAllocMarker(), getPCSections(), getCFIType(),509               getMMRAMetadata(), getDeactivationSymbol());510}511 512void MachineInstr::setHeapAllocMarker(MachineFunction &MF, MDNode *Marker) {513  // Do nothing if old and new symbols are the same.514  if (Marker == getHeapAllocMarker())515    return;516 517  setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),518               Marker, getPCSections(), getCFIType(), getMMRAMetadata(),519               getDeactivationSymbol());520}521 522void MachineInstr::setPCSections(MachineFunction &MF, MDNode *PCSections) {523  // Do nothing if old and new symbols are the same.524  if (PCSections == getPCSections())525    return;526 527  setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),528               getHeapAllocMarker(), PCSections, getCFIType(),529               getMMRAMetadata(), getDeactivationSymbol());530}531 532void MachineInstr::setCFIType(MachineFunction &MF, uint32_t Type) {533  // Do nothing if old and new types are the same.534  if (Type == getCFIType())535    return;536 537  setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),538               getHeapAllocMarker(), getPCSections(), Type, getMMRAMetadata(),539               getDeactivationSymbol());540}541 542void MachineInstr::setMMRAMetadata(MachineFunction &MF, MDNode *MMRAs) {543  // Do nothing if old and new symbols are the same.544  if (MMRAs == getMMRAMetadata())545    return;546 547  setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),548               getHeapAllocMarker(), getPCSections(), getCFIType(), MMRAs,549               getDeactivationSymbol());550}551 552void MachineInstr::setDeactivationSymbol(MachineFunction &MF, Value *DS) {553  // Do nothing if old and new symbols are the same.554  if (DS == getDeactivationSymbol())555    return;556 557  setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),558               getHeapAllocMarker(), getPCSections(), getCFIType(),559               getMMRAMetadata(), DS);560}561 562void MachineInstr::cloneInstrSymbols(MachineFunction &MF,563                                     const MachineInstr &MI) {564  if (this == &MI)565    // Nothing to do for a self-clone!566    return;567 568  assert(&MF == MI.getMF() &&569         "Invalid machine functions when cloning instruction symbols!");570 571  setPreInstrSymbol(MF, MI.getPreInstrSymbol());572  setPostInstrSymbol(MF, MI.getPostInstrSymbol());573  setHeapAllocMarker(MF, MI.getHeapAllocMarker());574  setPCSections(MF, MI.getPCSections());575  setMMRAMetadata(MF, MI.getMMRAMetadata());576}577 578uint32_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const {579  // For now, the just return the union of the flags. If the flags get more580  // complicated over time, we might need more logic here.581  return getFlags() | Other.getFlags();582}583 584uint32_t MachineInstr::copyFlagsFromInstruction(const Instruction &I) {585  uint32_t MIFlags = 0;586  // Copy the wrapping flags.587  if (const OverflowingBinaryOperator *OB =588          dyn_cast<OverflowingBinaryOperator>(&I)) {589    if (OB->hasNoSignedWrap())590      MIFlags |= MachineInstr::MIFlag::NoSWrap;591    if (OB->hasNoUnsignedWrap())592      MIFlags |= MachineInstr::MIFlag::NoUWrap;593  } else if (const TruncInst *TI = dyn_cast<TruncInst>(&I)) {594    if (TI->hasNoSignedWrap())595      MIFlags |= MachineInstr::MIFlag::NoSWrap;596    if (TI->hasNoUnsignedWrap())597      MIFlags |= MachineInstr::MIFlag::NoUWrap;598  } else if (const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(&I)) {599    if (GEP->hasNoUnsignedSignedWrap())600      MIFlags |= MachineInstr::MIFlag::NoUSWrap;601    if (GEP->hasNoUnsignedWrap())602      MIFlags |= MachineInstr::MIFlag::NoUWrap;603    if (GEP->isInBounds())604      MIFlags |= MachineInstr::MIFlag::InBounds;605  }606 607  // Copy the nonneg flag.608  if (const PossiblyNonNegInst *PNI = dyn_cast<PossiblyNonNegInst>(&I)) {609    if (PNI->hasNonNeg())610      MIFlags |= MachineInstr::MIFlag::NonNeg;611    // Copy the disjoint flag.612  } else if (const PossiblyDisjointInst *PD =613                 dyn_cast<PossiblyDisjointInst>(&I)) {614    if (PD->isDisjoint())615      MIFlags |= MachineInstr::MIFlag::Disjoint;616  }617 618  // Copy the samesign flag.619  if (const ICmpInst *ICmp = dyn_cast<ICmpInst>(&I))620    if (ICmp->hasSameSign())621      MIFlags |= MachineInstr::MIFlag::SameSign;622 623  // Copy the exact flag.624  if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))625    if (PE->isExact())626      MIFlags |= MachineInstr::MIFlag::IsExact;627 628  // Copy the fast-math flags.629  if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {630    const FastMathFlags Flags = FP->getFastMathFlags();631    if (Flags.noNaNs())632      MIFlags |= MachineInstr::MIFlag::FmNoNans;633    if (Flags.noInfs())634      MIFlags |= MachineInstr::MIFlag::FmNoInfs;635    if (Flags.noSignedZeros())636      MIFlags |= MachineInstr::MIFlag::FmNsz;637    if (Flags.allowReciprocal())638      MIFlags |= MachineInstr::MIFlag::FmArcp;639    if (Flags.allowContract())640      MIFlags |= MachineInstr::MIFlag::FmContract;641    if (Flags.approxFunc())642      MIFlags |= MachineInstr::MIFlag::FmAfn;643    if (Flags.allowReassoc())644      MIFlags |= MachineInstr::MIFlag::FmReassoc;645  }646 647  if (I.getMetadata(LLVMContext::MD_unpredictable))648    MIFlags |= MachineInstr::MIFlag::Unpredictable;649 650  return MIFlags;651}652 653void MachineInstr::copyIRFlags(const Instruction &I) {654  Flags = copyFlagsFromInstruction(I);655}656 657bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {658  assert(!isBundledWithPred() && "Must be called on bundle header");659  for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {660    if (MII->getDesc().getFlags() & Mask) {661      if (Type == AnyInBundle)662        return true;663    } else {664      if (Type == AllInBundle && !MII->isBundle())665        return false;666    }667    // This was the last instruction in the bundle.668    if (!MII->isBundledWithSucc())669      return Type == AllInBundle;670  }671}672 673bool MachineInstr::isIdenticalTo(const MachineInstr &Other,674                                 MICheckType Check) const {675  // If opcodes or number of operands are not the same then the two676  // instructions are obviously not identical.677  if (Other.getOpcode() != getOpcode() ||678      Other.getNumOperands() != getNumOperands())679    return false;680 681  if (isBundle()) {682    // We have passed the test above that both instructions have the same683    // opcode, so we know that both instructions are bundles here. Let's compare684    // MIs inside the bundle.685    assert(Other.isBundle() && "Expected that both instructions are bundles.");686    MachineBasicBlock::const_instr_iterator I1 = getIterator();687    MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();688    // Loop until we analysed the last intruction inside at least one of the689    // bundles.690    while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {691      ++I1;692      ++I2;693      if (!I1->isIdenticalTo(*I2, Check))694        return false;695    }696    // If we've reached the end of just one of the two bundles, but not both,697    // the instructions are not identical.698    if (I1->isBundledWithSucc() || I2->isBundledWithSucc())699      return false;700  }701 702  // Check operands to make sure they match.703  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {704    const MachineOperand &MO = getOperand(i);705    const MachineOperand &OMO = Other.getOperand(i);706    if (!MO.isReg()) {707      if (!MO.isIdenticalTo(OMO))708        return false;709      continue;710    }711 712    // Clients may or may not want to ignore defs when testing for equality.713    // For example, machine CSE pass only cares about finding common714    // subexpressions, so it's safe to ignore virtual register defs.715    if (MO.isDef()) {716      if (Check == IgnoreDefs)717        continue;718      else if (Check == IgnoreVRegDefs) {719        if (!MO.getReg().isVirtual() || !OMO.getReg().isVirtual())720          if (!MO.isIdenticalTo(OMO))721            return false;722      } else {723        if (!MO.isIdenticalTo(OMO))724          return false;725        if (Check == CheckKillDead && MO.isDead() != OMO.isDead())726          return false;727      }728    } else {729      if (!MO.isIdenticalTo(OMO))730        return false;731      if (Check == CheckKillDead && MO.isKill() != OMO.isKill())732        return false;733    }734  }735  // If DebugLoc does not match then two debug instructions are not identical.736  if (isDebugInstr())737    if (getDebugLoc() && Other.getDebugLoc() &&738        getDebugLoc() != Other.getDebugLoc())739      return false;740  // If pre- or post-instruction symbols do not match then the two instructions741  // are not identical.742  if (getPreInstrSymbol() != Other.getPreInstrSymbol() ||743      getPostInstrSymbol() != Other.getPostInstrSymbol())744    return false;745  // Call instructions with different CFI types are not identical.746  if (isCall() && getCFIType() != Other.getCFIType())747    return false;748  if (getDeactivationSymbol() != Other.getDeactivationSymbol())749    return false;750 751  return true;752}753 754bool MachineInstr::isEquivalentDbgInstr(const MachineInstr &Other) const {755  if (!isDebugValueLike() || !Other.isDebugValueLike())756    return false;757  if (getDebugLoc() != Other.getDebugLoc())758    return false;759  if (getDebugVariable() != Other.getDebugVariable())760    return false;761  if (getNumDebugOperands() != Other.getNumDebugOperands())762    return false;763  for (unsigned OpIdx = 0; OpIdx < getNumDebugOperands(); ++OpIdx)764    if (!getDebugOperand(OpIdx).isIdenticalTo(Other.getDebugOperand(OpIdx)))765      return false;766  if (!DIExpression::isEqualExpression(767          getDebugExpression(), isIndirectDebugValue(),768          Other.getDebugExpression(), Other.isIndirectDebugValue()))769    return false;770  return true;771}772 773const MachineFunction *MachineInstr::getMF() const {774  return getParent()->getParent();775}776 777MachineInstr *MachineInstr::removeFromParent() {778  assert(getParent() && "Not embedded in a basic block!");779  return getParent()->remove(this);780}781 782MachineInstr *MachineInstr::removeFromBundle() {783  assert(getParent() && "Not embedded in a basic block!");784  return getParent()->remove_instr(this);785}786 787void MachineInstr::eraseFromParent() {788  assert(getParent() && "Not embedded in a basic block!");789  getParent()->erase(this);790}791 792void MachineInstr::eraseFromBundle() {793  assert(getParent() && "Not embedded in a basic block!");794  getParent()->erase_instr(this);795}796 797bool MachineInstr::isCandidateForAdditionalCallInfo(QueryType Type) const {798  if (!isCall(Type))799    return false;800  switch (getOpcode()) {801  case TargetOpcode::PATCHPOINT:802  case TargetOpcode::STACKMAP:803  case TargetOpcode::STATEPOINT:804  case TargetOpcode::FENTRY_CALL:805    return false;806  }807  return true;808}809 810bool MachineInstr::shouldUpdateAdditionalCallInfo() const {811  if (isBundle())812    return isCandidateForAdditionalCallInfo(MachineInstr::AnyInBundle);813  return isCandidateForAdditionalCallInfo();814}815 816template <typename Operand, typename Instruction>817static iterator_range<818    filter_iterator<Operand *, std::function<bool(Operand &Op)>>>819getDebugOperandsForRegHelper(Instruction *MI, Register Reg) {820  std::function<bool(Operand & Op)> OpUsesReg(821      [Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; });822  return make_filter_range(MI->debug_operands(), OpUsesReg);823}824 825iterator_range<filter_iterator<const MachineOperand *,826                               std::function<bool(const MachineOperand &Op)>>>827MachineInstr::getDebugOperandsForReg(Register Reg) const {828  return getDebugOperandsForRegHelper<const MachineOperand, const MachineInstr>(829      this, Reg);830}831 832iterator_range<833    filter_iterator<MachineOperand *, std::function<bool(MachineOperand &Op)>>>834MachineInstr::getDebugOperandsForReg(Register Reg) {835  return getDebugOperandsForRegHelper<MachineOperand, MachineInstr>(this, Reg);836}837 838unsigned MachineInstr::getNumExplicitOperands() const {839  unsigned NumOperands = MCID->getNumOperands();840  if (!MCID->isVariadic())841    return NumOperands;842 843  for (const MachineOperand &MO : operands_impl().drop_front(NumOperands)) {844    // The operands must always be in the following order:845    // - explicit reg defs,846    // - other explicit operands (reg uses, immediates, etc.),847    // - implicit reg defs848    // - implicit reg uses849    if (MO.isReg() && MO.isImplicit())850      break;851    ++NumOperands;852  }853  return NumOperands;854}855 856unsigned MachineInstr::getNumExplicitDefs() const {857  unsigned NumDefs = MCID->getNumDefs();858  if (!MCID->isVariadic())859    return NumDefs;860 861  for (const MachineOperand &MO : operands_impl().drop_front(NumDefs)) {862    if (!MO.isReg() || !MO.isDef() || MO.isImplicit())863      break;864    ++NumDefs;865  }866  return NumDefs;867}868 869void MachineInstr::bundleWithPred() {870  assert(!isBundledWithPred() && "MI is already bundled with its predecessor");871  setFlag(BundledPred);872  MachineBasicBlock::instr_iterator Pred = getIterator();873  --Pred;874  assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");875  Pred->setFlag(BundledSucc);876}877 878void MachineInstr::bundleWithSucc() {879  assert(!isBundledWithSucc() && "MI is already bundled with its successor");880  setFlag(BundledSucc);881  MachineBasicBlock::instr_iterator Succ = getIterator();882  ++Succ;883  assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");884  Succ->setFlag(BundledPred);885}886 887void MachineInstr::unbundleFromPred() {888  assert(isBundledWithPred() && "MI isn't bundled with its predecessor");889  clearFlag(BundledPred);890  MachineBasicBlock::instr_iterator Pred = getIterator();891  --Pred;892  assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");893  Pred->clearFlag(BundledSucc);894}895 896void MachineInstr::unbundleFromSucc() {897  assert(isBundledWithSucc() && "MI isn't bundled with its successor");898  clearFlag(BundledSucc);899  MachineBasicBlock::instr_iterator Succ = getIterator();900  ++Succ;901  assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");902  Succ->clearFlag(BundledPred);903}904 905bool MachineInstr::isStackAligningInlineAsm() const {906  if (isInlineAsm()) {907    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();908    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)909      return true;910  }911  return false;912}913 914InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {915  assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");916  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();917  return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);918}919 920int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,921                                       unsigned *GroupNo) const {922  assert(isInlineAsm() && "Expected an inline asm instruction");923  assert(OpIdx < getNumOperands() && "OpIdx out of range");924 925  // Ignore queries about the initial operands.926  if (OpIdx < InlineAsm::MIOp_FirstOperand)927    return -1;928 929  unsigned Group = 0;930  unsigned NumOps;931  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;932       i += NumOps) {933    const MachineOperand &FlagMO = getOperand(i);934    // If we reach the implicit register operands, stop looking.935    if (!FlagMO.isImm())936      return -1;937    const InlineAsm::Flag F(FlagMO.getImm());938    NumOps = 1 + F.getNumOperandRegisters();939    if (i + NumOps > OpIdx) {940      if (GroupNo)941        *GroupNo = Group;942      return i;943    }944    ++Group;945  }946  return -1;947}948 949const DILabel *MachineInstr::getDebugLabel() const {950  assert(isDebugLabel() && "not a DBG_LABEL");951  return cast<DILabel>(getOperand(0).getMetadata());952}953 954const MachineOperand &MachineInstr::getDebugVariableOp() const {955  assert((isDebugValueLike()) && "not a DBG_VALUE*");956  unsigned VariableOp = isNonListDebugValue() ? 2 : 0;957  return getOperand(VariableOp);958}959 960MachineOperand &MachineInstr::getDebugVariableOp() {961  assert((isDebugValueLike()) && "not a DBG_VALUE*");962  unsigned VariableOp = isNonListDebugValue() ? 2 : 0;963  return getOperand(VariableOp);964}965 966const DILocalVariable *MachineInstr::getDebugVariable() const {967  return cast<DILocalVariable>(getDebugVariableOp().getMetadata());968}969 970const MachineOperand &MachineInstr::getDebugExpressionOp() const {971  assert((isDebugValueLike()) && "not a DBG_VALUE*");972  unsigned ExpressionOp = isNonListDebugValue() ? 3 : 1;973  return getOperand(ExpressionOp);974}975 976MachineOperand &MachineInstr::getDebugExpressionOp() {977  assert((isDebugValueLike()) && "not a DBG_VALUE*");978  unsigned ExpressionOp = isNonListDebugValue() ? 3 : 1;979  return getOperand(ExpressionOp);980}981 982const DIExpression *MachineInstr::getDebugExpression() const {983  return cast<DIExpression>(getDebugExpressionOp().getMetadata());984}985 986bool MachineInstr::isDebugEntryValue() const {987  return isDebugValue() && getDebugExpression()->isEntryValue();988}989 990const TargetRegisterClass*991MachineInstr::getRegClassConstraint(unsigned OpIdx,992                                    const TargetInstrInfo *TII,993                                    const TargetRegisterInfo *TRI) const {994  assert(getParent() && "Can't have an MBB reference here!");995  assert(getMF() && "Can't have an MF reference here!");996  // Most opcodes have fixed constraints in their MCInstrDesc.997  if (!isInlineAsm())998    return TII->getRegClass(getDesc(), OpIdx);999 1000  if (!getOperand(OpIdx).isReg())1001    return nullptr;1002 1003  // For tied uses on inline asm, get the constraint from the def.1004  unsigned DefIdx;1005  if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))1006    OpIdx = DefIdx;1007 1008  // Inline asm stores register class constraints in the flag word.1009  int FlagIdx = findInlineAsmFlagIdx(OpIdx);1010  if (FlagIdx < 0)1011    return nullptr;1012 1013  const InlineAsm::Flag F(getOperand(FlagIdx).getImm());1014  unsigned RCID;1015  if ((F.isRegUseKind() || F.isRegDefKind() || F.isRegDefEarlyClobberKind()) &&1016      F.hasRegClassConstraint(RCID))1017    return TRI->getRegClass(RCID);1018 1019  // Assume that all registers in a memory operand are pointers.1020  if (F.isMemKind())1021    return TRI->getPointerRegClass();1022 1023  return nullptr;1024}1025 1026const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(1027    Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,1028    const TargetRegisterInfo *TRI, bool ExploreBundle) const {1029  // Check every operands inside the bundle if we have1030  // been asked to.1031  if (ExploreBundle)1032    for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;1033         ++OpndIt)1034      CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(1035          OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);1036  else1037    // Otherwise, just check the current operands.1038    for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)1039      CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);1040  return CurRC;1041}1042 1043const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(1044    unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,1045    const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {1046  assert(CurRC && "Invalid initial register class");1047  // Check if Reg is constrained by some of its use/def from MI.1048  const MachineOperand &MO = getOperand(OpIdx);1049  if (!MO.isReg() || MO.getReg() != Reg)1050    return CurRC;1051  // If yes, accumulate the constraints through the operand.1052  return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);1053}1054 1055const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(1056    unsigned OpIdx, const TargetRegisterClass *CurRC,1057    const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {1058  const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);1059  const MachineOperand &MO = getOperand(OpIdx);1060  assert(MO.isReg() &&1061         "Cannot get register constraints for non-register operand");1062  assert(CurRC && "Invalid initial register class");1063  if (unsigned SubIdx = MO.getSubReg()) {1064    if (OpRC)1065      CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);1066    else1067      CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);1068  } else if (OpRC)1069    CurRC = TRI->getCommonSubClass(CurRC, OpRC);1070  return CurRC;1071}1072 1073/// Return the number of instructions inside the MI bundle, not counting the1074/// header instruction.1075unsigned MachineInstr::getBundleSize() const {1076  MachineBasicBlock::const_instr_iterator I = getIterator();1077  unsigned Size = 0;1078  while (I->isBundledWithSucc()) {1079    ++Size;1080    ++I;1081  }1082  return Size;1083}1084 1085/// Returns true if the MachineInstr has an implicit-use operand of exactly1086/// the given register (not considering sub/super-registers).1087bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const {1088  for (const MachineOperand &MO : implicit_operands()) {1089    if (MO.isReg() && MO.isUse() && MO.getReg() == Reg)1090      return true;1091  }1092  return false;1093}1094 1095/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of1096/// the specific register or -1 if it is not found. It further tightens1097/// the search criteria to a use that kills the register if isKill is true.1098int MachineInstr::findRegisterUseOperandIdx(Register Reg,1099                                            const TargetRegisterInfo *TRI,1100                                            bool isKill) const {1101  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {1102    const MachineOperand &MO = getOperand(i);1103    if (!MO.isReg() || !MO.isUse())1104      continue;1105    Register MOReg = MO.getReg();1106    if (!MOReg)1107      continue;1108    if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))1109      if (!isKill || MO.isKill())1110        return i;1111  }1112  return -1;1113}1114 1115/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)1116/// indicating if this instruction reads or writes Reg. This also considers1117/// partial defines.1118std::pair<bool,bool>1119MachineInstr::readsWritesVirtualRegister(Register Reg,1120                                         SmallVectorImpl<unsigned> *Ops) const {1121  bool PartDef = false; // Partial redefine.1122  bool FullDef = false; // Full define.1123  bool Use = false;1124 1125  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {1126    const MachineOperand &MO = getOperand(i);1127    if (!MO.isReg() || MO.getReg() != Reg)1128      continue;1129    if (Ops)1130      Ops->push_back(i);1131    if (MO.isUse())1132      Use |= !MO.isUndef();1133    else if (MO.getSubReg() && !MO.isUndef())1134      // A partial def undef doesn't count as reading the register.1135      PartDef = true;1136    else1137      FullDef = true;1138  }1139  // A partial redefine uses Reg unless there is also a full define.1140  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);1141}1142 1143/// findRegisterDefOperandIdx() - Returns the operand index that is a def of1144/// the specified register or -1 if it is not found. If isDead is true, defs1145/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it1146/// also checks if there is a def of a super-register.1147int MachineInstr::findRegisterDefOperandIdx(Register Reg,1148                                            const TargetRegisterInfo *TRI,1149                                            bool isDead, bool Overlap) const {1150  bool isPhys = Reg.isPhysical();1151  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {1152    const MachineOperand &MO = getOperand(i);1153    // Accept regmask operands when Overlap is set.1154    // Ignore them when looking for a specific def operand (Overlap == false).1155    if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))1156      return i;1157    if (!MO.isReg() || !MO.isDef())1158      continue;1159    Register MOReg = MO.getReg();1160    bool Found = (MOReg == Reg);1161    if (!Found && TRI && isPhys && MOReg.isPhysical()) {1162      if (Overlap)1163        Found = TRI->regsOverlap(MOReg, Reg);1164      else1165        Found = TRI->isSubRegister(MOReg, Reg);1166    }1167    if (Found && (!isDead || MO.isDead()))1168      return i;1169  }1170  return -1;1171}1172 1173/// findFirstPredOperandIdx() - Find the index of the first operand in the1174/// operand list that is used to represent the predicate. It returns -1 if1175/// none is found.1176int MachineInstr::findFirstPredOperandIdx() const {1177  // Don't call MCID.findFirstPredOperandIdx() because this variant1178  // is sometimes called on an instruction that's not yet complete, and1179  // so the number of operands is less than the MCID indicates. In1180  // particular, the PTX target does this.1181  const MCInstrDesc &MCID = getDesc();1182  if (MCID.isPredicable()) {1183    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)1184      if (MCID.operands()[i].isPredicate())1185        return i;1186  }1187 1188  return -1;1189}1190 1191// MachineOperand::TiedTo is 4 bits wide.1192const unsigned TiedMax = 15;1193 1194/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.1195///1196/// Use and def operands can be tied together, indicated by a non-zero TiedTo1197/// field. TiedTo can have these values:1198///1199/// 0:              Operand is not tied to anything.1200/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).1201/// TiedMax:        Tied to an operand >= TiedMax-1.1202///1203/// The tied def must be one of the first TiedMax operands on a normal1204/// instruction. INLINEASM instructions allow more tied defs.1205///1206void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {1207  MachineOperand &DefMO = getOperand(DefIdx);1208  MachineOperand &UseMO = getOperand(UseIdx);1209  assert(DefMO.isDef() && "DefIdx must be a def operand");1210  assert(UseMO.isUse() && "UseIdx must be a use operand");1211  assert(!DefMO.isTied() && "Def is already tied to another use");1212  assert(!UseMO.isTied() && "Use is already tied to another def");1213 1214  if (DefIdx < TiedMax) {1215    UseMO.TiedTo = DefIdx + 1;1216  } else {1217    // Inline asm can use the group descriptors to find tied operands,1218    // statepoint tied operands are trivial to match (1-1 reg def with reg use),1219    // but on normal instruction, the tied def must be within the first TiedMax1220    // operands.1221    assert((isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) &&1222           "DefIdx out of range");1223    UseMO.TiedTo = TiedMax;1224  }1225 1226  // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().1227  DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);1228}1229 1230/// Given the index of a tied register operand, find the operand it is tied to.1231/// Defs are tied to uses and vice versa. Returns the index of the tied operand1232/// which must exist.1233unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {1234  const MachineOperand &MO = getOperand(OpIdx);1235  assert(MO.isTied() && "Operand isn't tied");1236 1237  // Normally TiedTo is in range.1238  if (MO.TiedTo < TiedMax)1239    return MO.TiedTo - 1;1240 1241  // Uses on normal instructions can be out of range.1242  if (!isInlineAsm() && getOpcode() != TargetOpcode::STATEPOINT) {1243    // Normal tied defs must be in the 0..TiedMax-1 range.1244    if (MO.isUse())1245      return TiedMax - 1;1246    // MO is a def. Search for the tied use.1247    for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {1248      const MachineOperand &UseMO = getOperand(i);1249      if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)1250        return i;1251    }1252    llvm_unreachable("Can't find tied use");1253  }1254 1255  if (getOpcode() == TargetOpcode::STATEPOINT) {1256    // In STATEPOINT defs correspond 1-1 to GC pointer operands passed1257    // on registers.1258    StatepointOpers SO(this);1259    unsigned CurUseIdx = SO.getFirstGCPtrIdx();1260    assert(CurUseIdx != -1U && "only gc pointer statepoint operands can be tied");1261    unsigned NumDefs = getNumDefs();1262    for (unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {1263      while (!getOperand(CurUseIdx).isReg())1264        CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);1265      if (OpIdx == CurDefIdx)1266        return CurUseIdx;1267      if (OpIdx == CurUseIdx)1268        return CurDefIdx;1269      CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);1270    }1271    llvm_unreachable("Can't find tied use");1272  }1273 1274  // Now deal with inline asm by parsing the operand group descriptor flags.1275  // Find the beginning of each operand group.1276  SmallVector<unsigned, 8> GroupIdx;1277  unsigned OpIdxGroup = ~0u;1278  unsigned NumOps;1279  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;1280       i += NumOps) {1281    const MachineOperand &FlagMO = getOperand(i);1282    assert(FlagMO.isImm() && "Invalid tied operand on inline asm");1283    unsigned CurGroup = GroupIdx.size();1284    GroupIdx.push_back(i);1285    const InlineAsm::Flag F(FlagMO.getImm());1286    NumOps = 1 + F.getNumOperandRegisters();1287    // OpIdx belongs to this operand group.1288    if (OpIdx > i && OpIdx < i + NumOps)1289      OpIdxGroup = CurGroup;1290    unsigned TiedGroup;1291    if (!F.isUseOperandTiedToDef(TiedGroup))1292      continue;1293    // Operands in this group are tied to operands in TiedGroup which must be1294    // earlier. Find the number of operands between the two groups.1295    unsigned Delta = i - GroupIdx[TiedGroup];1296 1297    // OpIdx is a use tied to TiedGroup.1298    if (OpIdxGroup == CurGroup)1299      return OpIdx - Delta;1300 1301    // OpIdx is a def tied to this use group.1302    if (OpIdxGroup == TiedGroup)1303      return OpIdx + Delta;1304  }1305  llvm_unreachable("Invalid tied operand on inline asm");1306}1307 1308/// clearKillInfo - Clears kill flags on all operands.1309///1310void MachineInstr::clearKillInfo() {1311  for (MachineOperand &MO : operands()) {1312    if (MO.isReg() && MO.isUse())1313      MO.setIsKill(false);1314  }1315}1316 1317void MachineInstr::substituteRegister(Register FromReg, Register ToReg,1318                                      unsigned SubIdx,1319                                      const TargetRegisterInfo &RegInfo) {1320  if (ToReg.isPhysical()) {1321    if (SubIdx)1322      ToReg = RegInfo.getSubReg(ToReg, SubIdx);1323    for (MachineOperand &MO : operands()) {1324      if (!MO.isReg() || MO.getReg() != FromReg)1325        continue;1326      MO.substPhysReg(ToReg, RegInfo);1327    }1328  } else {1329    for (MachineOperand &MO : operands()) {1330      if (!MO.isReg() || MO.getReg() != FromReg)1331        continue;1332      MO.substVirtReg(ToReg, SubIdx, RegInfo);1333    }1334  }1335}1336 1337/// isSafeToMove - Return true if it is safe to move this instruction. If1338/// SawStore is set to true, it means that there is a store (or call) between1339/// the instruction's location and its intended destination.1340bool MachineInstr::isSafeToMove(bool &SawStore) const {1341  // Ignore stuff that we obviously can't move.1342  //1343  // Treat volatile loads as stores. This is not strictly necessary for1344  // volatiles, but it is required for atomic loads. It is not allowed to move1345  // a load across an atomic load with Ordering > Monotonic.1346  if (mayStore() || isCall() || isPHI() ||1347      (mayLoad() && hasOrderedMemoryRef())) {1348    SawStore = true;1349    return false;1350  }1351 1352  // Don't touch instructions that have non-trivial invariants.  For example,1353  // terminators have to be at the end of a basic block.1354  if (isPosition() || isDebugInstr() || isTerminator() ||1355      isJumpTableDebugInfo())1356    return false;1357 1358  // Don't touch instructions which can have non-load/store effects.1359  //1360  // Inline asm has a "sideeffect" marker to indicate whether the asm has1361  // intentional side-effects. Even if an inline asm is not "sideeffect",1362  // though, it still can't be speculatively executed: the operation might1363  // not be valid on the current target, or for some combinations of operands.1364  // (Some transforms that move an instruction don't speculatively execute it;1365  // we currently don't try to handle that distinction here.)1366  //1367  // Other instructions handled here include those that can raise FP1368  // exceptions, x86 "DIV" instructions which trap on divide by zero, and1369  // stack adjustments.1370  if (mayRaiseFPException() || hasProperty(MCID::UnmodeledSideEffects) ||1371      isInlineAsm())1372    return false;1373 1374  // See if this instruction does a load.  If so, we have to guarantee that the1375  // loaded value doesn't change between the load and the its intended1376  // destination. The check for isInvariantLoad gives the target the chance to1377  // classify the load as always returning a constant, e.g. a constant pool1378  // load.1379  if (mayLoad() && !isDereferenceableInvariantLoad())1380    // Otherwise, this is a real load.  If there is a store between the load and1381    // end of block, we can't move it.1382    return !SawStore;1383 1384  return true;1385}1386 1387bool MachineInstr::wouldBeTriviallyDead() const {1388  // Don't delete frame allocation labels.1389  // FIXME: Why is LOCAL_ESCAPE not considered in MachineInstr::isLabel?1390  if (getOpcode() == TargetOpcode::LOCAL_ESCAPE)1391    return false;1392 1393  // Don't delete FAKE_USE.1394  // FIXME: Why is FAKE_USE not considered in MachineInstr::isPosition?1395  if (isFakeUse())1396    return false;1397 1398  // LIFETIME markers should be preserved.1399  // FIXME: Why are LIFETIME markers not considered in MachineInstr::isPosition?1400  if (isLifetimeMarker())1401    return false;1402 1403  // If we can move an instruction, we can remove it.  Otherwise, it has1404  // a side-effect of some sort.1405  bool SawStore = false;1406  return isPHI() || isSafeToMove(SawStore);1407}1408 1409bool MachineInstr::isDead(const MachineRegisterInfo &MRI,1410                          LiveRegUnits *LivePhysRegs) const {1411  // Instructions without side-effects are dead iff they only define dead regs.1412  // This function is hot and this loop returns early in the common case,1413  // so only perform additional checks before this if absolutely necessary.1414  for (const MachineOperand &MO : all_defs()) {1415    Register Reg = MO.getReg();1416    if (Reg.isPhysical()) {1417      // Don't delete live physreg defs, or any reserved register defs.1418      if (!LivePhysRegs || !LivePhysRegs->available(Reg) || MRI.isReserved(Reg))1419        return false;1420    } else {1421      if (MO.isDead())1422        continue;1423      for (const MachineInstr &Use : MRI.use_nodbg_instructions(Reg)) {1424        if (&Use != this)1425          // This def has a non-debug use. Don't delete the instruction!1426          return false;1427      }1428    }1429  }1430 1431  // Technically speaking inline asm without side effects and no defs can still1432  // be deleted. But there is so much bad inline asm code out there, we should1433  // let them be.1434  if (isInlineAsm())1435    return false;1436 1437  // FIXME: See issue #105950 for why LIFETIME markers are considered dead here.1438  if (isLifetimeMarker())1439    return true;1440 1441  // If there are no defs with uses, then we call the instruction dead so long1442  // as we do not suspect it may have sideeffects.1443  return wouldBeTriviallyDead();1444}1445 1446static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI,1447                                 BatchAAResults *AA, bool UseTBAA,1448                                 const MachineMemOperand *MMOa,1449                                 const MachineMemOperand *MMOb) {1450  // The following interface to AA is fashioned after DAGCombiner::isAlias and1451  // operates with MachineMemOperand offset with some important assumptions:1452  //   - LLVM fundamentally assumes flat address spaces.1453  //   - MachineOperand offset can *only* result from legalization and cannot1454  //     affect queries other than the trivial case of overlap checking.1455  //   - These offsets never wrap and never step outside of allocated objects.1456  //   - There should never be any negative offsets here.1457  //1458  // FIXME: Modify API to hide this math from "user"1459  // Even before we go to AA we can reason locally about some memory objects. It1460  // can save compile time, and possibly catch some corner cases not currently1461  // covered.1462 1463  int64_t OffsetA = MMOa->getOffset();1464  int64_t OffsetB = MMOb->getOffset();1465  int64_t MinOffset = std::min(OffsetA, OffsetB);1466 1467  LocationSize WidthA = MMOa->getSize();1468  LocationSize WidthB = MMOb->getSize();1469  bool KnownWidthA = WidthA.hasValue();1470  bool KnownWidthB = WidthB.hasValue();1471  bool BothMMONonScalable = !WidthA.isScalable() && !WidthB.isScalable();1472 1473  const Value *ValA = MMOa->getValue();1474  const Value *ValB = MMOb->getValue();1475  bool SameVal = (ValA && ValB && (ValA == ValB));1476  if (!SameVal) {1477    const PseudoSourceValue *PSVa = MMOa->getPseudoValue();1478    const PseudoSourceValue *PSVb = MMOb->getPseudoValue();1479    if (PSVa && ValB && !PSVa->mayAlias(&MFI))1480      return false;1481    if (PSVb && ValA && !PSVb->mayAlias(&MFI))1482      return false;1483    if (PSVa && PSVb && (PSVa == PSVb))1484      SameVal = true;1485  }1486 1487  if (SameVal && BothMMONonScalable) {1488    if (!KnownWidthA || !KnownWidthB)1489      return true;1490    int64_t MaxOffset = std::max(OffsetA, OffsetB);1491    int64_t LowWidth = (MinOffset == OffsetA)1492                           ? WidthA.getValue().getKnownMinValue()1493                           : WidthB.getValue().getKnownMinValue();1494    return (MinOffset + LowWidth > MaxOffset);1495  }1496 1497  if (!AA)1498    return true;1499 1500  if (!ValA || !ValB)1501    return true;1502 1503  assert((OffsetA >= 0) && "Negative MachineMemOperand offset");1504  assert((OffsetB >= 0) && "Negative MachineMemOperand offset");1505 1506  // If Scalable Location Size has non-zero offset, Width + Offset does not work1507  // at the moment1508  if ((WidthA.isScalable() && OffsetA > 0) ||1509      (WidthB.isScalable() && OffsetB > 0))1510    return true;1511 1512  int64_t OverlapA =1513      KnownWidthA ? WidthA.getValue().getKnownMinValue() + OffsetA - MinOffset1514                  : MemoryLocation::UnknownSize;1515  int64_t OverlapB =1516      KnownWidthB ? WidthB.getValue().getKnownMinValue() + OffsetB - MinOffset1517                  : MemoryLocation::UnknownSize;1518 1519  LocationSize LocA = (WidthA.isScalable() || !KnownWidthA)1520                          ? WidthA1521                          : LocationSize::precise(OverlapA);1522  LocationSize LocB = (WidthB.isScalable() || !KnownWidthB)1523                          ? WidthB1524                          : LocationSize::precise(OverlapB);1525 1526  return !AA->isNoAlias(1527      MemoryLocation(ValA, LocA, UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),1528      MemoryLocation(ValB, LocB, UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));1529}1530 1531bool MachineInstr::mayAlias(BatchAAResults *AA, const MachineInstr &Other,1532                            bool UseTBAA) const {1533  const MachineFunction *MF = getMF();1534  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();1535  const MachineFrameInfo &MFI = MF->getFrameInfo();1536 1537  // Exclude call instruction which may alter the memory but can not be handled1538  // by this function.1539  if (isCall() || Other.isCall())1540    return true;1541 1542  // If neither instruction stores to memory, they can't alias in any1543  // meaningful way, even if they read from the same address.1544  if (!mayStore() && !Other.mayStore())1545    return false;1546 1547  // Both instructions must be memory operations to be able to alias.1548  if (!mayLoadOrStore() || !Other.mayLoadOrStore())1549    return false;1550 1551  // Let the target decide if memory accesses cannot possibly overlap.1552  if (TII->areMemAccessesTriviallyDisjoint(*this, Other))1553    return false;1554 1555  // Memory operations without memory operands may access anything. Be1556  // conservative and assume `MayAlias`.1557  if (memoperands_empty() || Other.memoperands_empty())1558    return true;1559 1560  // Skip if there are too many memory operands.1561  auto NumChecks = getNumMemOperands() * Other.getNumMemOperands();1562  if (NumChecks > TII->getMemOperandAACheckLimit())1563    return true;1564 1565  // Check each pair of memory operands from both instructions, which can't1566  // alias only if all pairs won't alias.1567  for (auto *MMOa : memoperands()) {1568    for (auto *MMOb : Other.memoperands()) {1569      if (!MMOa->isStore() && !MMOb->isStore())1570        continue;1571      if (MemOperandsHaveAlias(MFI, AA, UseTBAA, MMOa, MMOb))1572        return true;1573    }1574  }1575 1576  return false;1577}1578 1579bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other,1580                            bool UseTBAA) const {1581  if (AA) {1582    BatchAAResults BAA(*AA);1583    return mayAlias(&BAA, Other, UseTBAA);1584  }1585  return mayAlias(static_cast<BatchAAResults *>(nullptr), Other, UseTBAA);1586}1587 1588/// hasOrderedMemoryRef - Return true if this instruction may have an ordered1589/// or volatile memory reference, or if the information describing the memory1590/// reference is not available. Return false if it is known to have no ordered1591/// memory references.1592bool MachineInstr::hasOrderedMemoryRef() const {1593  // An instruction known never to access memory won't have a volatile access.1594  if (!mayStore() &&1595      !mayLoad() &&1596      !isCall() &&1597      !hasUnmodeledSideEffects())1598    return false;1599 1600  // Otherwise, if the instruction has no memory reference information,1601  // conservatively assume it wasn't preserved.1602  if (memoperands_empty())1603    return true;1604 1605  // Check if any of our memory operands are ordered.1606  return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {1607    return !MMO->isUnordered();1608  });1609}1610 1611/// isDereferenceableInvariantLoad - Return true if this instruction will never1612/// trap and is loading from a location whose value is invariant across a run of1613/// this function.1614bool MachineInstr::isDereferenceableInvariantLoad() const {1615  // If the instruction doesn't load at all, it isn't an invariant load.1616  if (!mayLoad())1617    return false;1618 1619  // If the instruction has lost its memoperands, conservatively assume that1620  // it may not be an invariant load.1621  if (memoperands_empty())1622    return false;1623 1624  const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();1625 1626  for (MachineMemOperand *MMO : memoperands()) {1627    if (!MMO->isUnordered())1628      // If the memory operand has ordering side effects, we can't move the1629      // instruction.  Such an instruction is technically an invariant load,1630      // but the caller code would need updated to expect that.1631      return false;1632    if (MMO->isStore()) return false;1633    if (MMO->isInvariant() && MMO->isDereferenceable())1634      continue;1635 1636    // A load from a constant PseudoSourceValue is invariant.1637    if (const PseudoSourceValue *PSV = MMO->getPseudoValue()) {1638      if (PSV->isConstant(&MFI))1639        continue;1640    }1641 1642    // Otherwise assume conservatively.1643    return false;1644  }1645 1646  // Everything checks out.1647  return true;1648}1649 1650Register MachineInstr::isConstantValuePHI() const {1651  if (!isPHI())1652    return {};1653  assert(getNumOperands() >= 3 &&1654         "It's illegal to have a PHI without source operands");1655 1656  Register Reg = getOperand(1).getReg();1657  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)1658    if (getOperand(i).getReg() != Reg)1659      return {};1660  return Reg;1661}1662 1663bool MachineInstr::hasUnmodeledSideEffects() const {1664  if (hasProperty(MCID::UnmodeledSideEffects))1665    return true;1666  if (isInlineAsm()) {1667    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();1668    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)1669      return true;1670  }1671 1672  return false;1673}1674 1675bool MachineInstr::isLoadFoldBarrier() const {1676  return mayStore() || isCall() ||1677         (hasUnmodeledSideEffects() && !isPseudoProbe());1678}1679 1680/// allDefsAreDead - Return true if all the defs of this instruction are dead.1681///1682bool MachineInstr::allDefsAreDead() const {1683  for (const MachineOperand &MO : operands()) {1684    if (!MO.isReg() || MO.isUse())1685      continue;1686    if (!MO.isDead())1687      return false;1688  }1689  return true;1690}1691 1692bool MachineInstr::allImplicitDefsAreDead() const {1693  for (const MachineOperand &MO : implicit_operands()) {1694    if (!MO.isReg() || MO.isUse())1695      continue;1696    if (!MO.isDead())1697      return false;1698  }1699  return true;1700}1701 1702/// copyImplicitOps - Copy implicit register operands from specified1703/// instruction to this instruction.1704void MachineInstr::copyImplicitOps(MachineFunction &MF,1705                                   const MachineInstr &MI) {1706  for (const MachineOperand &MO :1707       llvm::drop_begin(MI.operands(), MI.getDesc().getNumOperands()))1708    if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())1709      addOperand(MF, MO);1710}1711 1712bool MachineInstr::hasComplexRegisterTies() const {1713  const MCInstrDesc &MCID = getDesc();1714  if (MCID.Opcode == TargetOpcode::STATEPOINT)1715    return true;1716  for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {1717    const auto &Operand = getOperand(I);1718    if (!Operand.isReg() || Operand.isDef())1719      // Ignore the defined registers as MCID marks only the uses as tied.1720      continue;1721    int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);1722    int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;1723    if (ExpectedTiedIdx != TiedIdx)1724      return true;1725  }1726  return false;1727}1728 1729LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,1730                                 const MachineRegisterInfo &MRI) const {1731  const MachineOperand &Op = getOperand(OpIdx);1732  if (!Op.isReg())1733    return LLT{};1734 1735  if (isVariadic() || OpIdx >= getNumExplicitOperands())1736    return MRI.getType(Op.getReg());1737 1738  auto &OpInfo = getDesc().operands()[OpIdx];1739  if (!OpInfo.isGenericType())1740    return MRI.getType(Op.getReg());1741 1742  if (PrintedTypes[OpInfo.getGenericTypeIndex()])1743    return LLT{};1744 1745  LLT TypeToPrint = MRI.getType(Op.getReg());1746  // Don't mark the type index printed if it wasn't actually printed: maybe1747  // another operand with the same type index has an actual type attached:1748  if (TypeToPrint.isValid())1749    PrintedTypes.set(OpInfo.getGenericTypeIndex());1750  return TypeToPrint;1751}1752 1753#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)1754LLVM_DUMP_METHOD void MachineInstr::dump() const {1755  dbgs() << "  ";1756  print(dbgs());1757}1758 1759LLVM_DUMP_METHOD void MachineInstr::dumprImpl(1760    const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,1761    SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const {1762  if (Depth >= MaxDepth)1763    return;1764  if (!AlreadySeenInstrs.insert(this).second)1765    return;1766  // PadToColumn always inserts at least one space.1767  // Don't mess up the alignment if we don't want any space.1768  if (Depth)1769    fdbgs().PadToColumn(Depth * 2);1770  print(fdbgs());1771  for (const MachineOperand &MO : operands()) {1772    if (!MO.isReg() || MO.isDef())1773      continue;1774    Register Reg = MO.getReg();1775    if (Reg.isPhysical())1776      continue;1777    const MachineInstr *NewMI = MRI.getUniqueVRegDef(Reg);1778    if (NewMI == nullptr)1779      continue;1780    NewMI->dumprImpl(MRI, Depth + 1, MaxDepth, AlreadySeenInstrs);1781  }1782}1783 1784LLVM_DUMP_METHOD void MachineInstr::dumpr(const MachineRegisterInfo &MRI,1785                                          unsigned MaxDepth) const {1786  SmallPtrSet<const MachineInstr *, 16> AlreadySeenInstrs;1787  dumprImpl(MRI, 0, MaxDepth, AlreadySeenInstrs);1788}1789#endif1790 1791void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,1792                         bool SkipDebugLoc, bool AddNewLine,1793                         const TargetInstrInfo *TII) const {1794  const Module *M = nullptr;1795  const Function *F = nullptr;1796  if (const MachineFunction *MF = getMFIfAvailable(*this)) {1797    F = &MF->getFunction();1798    M = F->getParent();1799    if (!TII)1800      TII = MF->getSubtarget().getInstrInfo();1801  }1802 1803  ModuleSlotTracker MST(M);1804  if (F)1805    MST.incorporateFunction(*F);1806  print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);1807}1808 1809void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,1810                         bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,1811                         bool AddNewLine, const TargetInstrInfo *TII) const {1812  // We can be a bit tidier if we know the MachineFunction.1813  const TargetRegisterInfo *TRI = nullptr;1814  const MachineRegisterInfo *MRI = nullptr;1815  tryToGetTargetInfo(*this, TRI, MRI, TII);1816 1817  if (isCFIInstruction())1818    assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");1819 1820  SmallBitVector PrintedTypes(8);1821  bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();1822  auto getTiedOperandIdx = [&](unsigned OpIdx) {1823    if (!ShouldPrintRegisterTies)1824      return 0U;1825    const MachineOperand &MO = getOperand(OpIdx);1826    if (MO.isReg() && MO.isTied() && !MO.isDef())1827      return findTiedOperandIdx(OpIdx);1828    return 0U;1829  };1830  unsigned StartOp = 0;1831  unsigned e = getNumOperands();1832 1833  // Print explicitly defined operands on the left of an assignment syntax.1834  while (StartOp < e) {1835    const MachineOperand &MO = getOperand(StartOp);1836    if (!MO.isReg() || !MO.isDef() || MO.isImplicit())1837      break;1838 1839    if (StartOp != 0)1840      OS << ", ";1841 1842    LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};1843    unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);1844    MO.print(OS, MST, TypeToPrint, StartOp, /*PrintDef=*/false, IsStandalone,1845             ShouldPrintRegisterTies, TiedOperandIdx, TRI);1846    ++StartOp;1847  }1848 1849  if (StartOp != 0)1850    OS << " = ";1851 1852  if (getFlag(MachineInstr::FrameSetup))1853    OS << "frame-setup ";1854  if (getFlag(MachineInstr::FrameDestroy))1855    OS << "frame-destroy ";1856  if (getFlag(MachineInstr::FmNoNans))1857    OS << "nnan ";1858  if (getFlag(MachineInstr::FmNoInfs))1859    OS << "ninf ";1860  if (getFlag(MachineInstr::FmNsz))1861    OS << "nsz ";1862  if (getFlag(MachineInstr::FmArcp))1863    OS << "arcp ";1864  if (getFlag(MachineInstr::FmContract))1865    OS << "contract ";1866  if (getFlag(MachineInstr::FmAfn))1867    OS << "afn ";1868  if (getFlag(MachineInstr::FmReassoc))1869    OS << "reassoc ";1870  if (getFlag(MachineInstr::NoUWrap))1871    OS << "nuw ";1872  if (getFlag(MachineInstr::NoSWrap))1873    OS << "nsw ";1874  if (getFlag(MachineInstr::IsExact))1875    OS << "exact ";1876  if (getFlag(MachineInstr::NoFPExcept))1877    OS << "nofpexcept ";1878  if (getFlag(MachineInstr::NoMerge))1879    OS << "nomerge ";1880  if (getFlag(MachineInstr::NonNeg))1881    OS << "nneg ";1882  if (getFlag(MachineInstr::Disjoint))1883    OS << "disjoint ";1884  if (getFlag(MachineInstr::NoUSWrap))1885    OS << "nusw ";1886  if (getFlag(MachineInstr::SameSign))1887    OS << "samesign ";1888  if (getFlag(MachineInstr::InBounds))1889    OS << "inbounds ";1890 1891  // Print the opcode name.1892  if (TII)1893    OS << TII->getName(getOpcode());1894  else1895    OS << "UNKNOWN";1896 1897  if (SkipOpers)1898    return;1899 1900  // Print the rest of the operands.1901  bool FirstOp = true;1902  unsigned AsmDescOp = ~0u;1903  unsigned AsmOpCount = 0;1904 1905  if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {1906    // Print asm string.1907    OS << " ";1908    const unsigned OpIdx = InlineAsm::MIOp_AsmString;1909    LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};1910    unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);1911    getOperand(OpIdx).print(OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true,1912                            IsStandalone, ShouldPrintRegisterTies,1913                            TiedOperandIdx, TRI);1914 1915    // Print HasSideEffects, MayLoad, MayStore, IsAlignStack1916    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();1917    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)1918      OS << " [sideeffect]";1919    if (ExtraInfo & InlineAsm::Extra_MayLoad)1920      OS << " [mayload]";1921    if (ExtraInfo & InlineAsm::Extra_MayStore)1922      OS << " [maystore]";1923    if (ExtraInfo & InlineAsm::Extra_IsConvergent)1924      OS << " [isconvergent]";1925    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)1926      OS << " [alignstack]";1927    if (getInlineAsmDialect() == InlineAsm::AD_ATT)1928      OS << " [attdialect]";1929    if (getInlineAsmDialect() == InlineAsm::AD_Intel)1930      OS << " [inteldialect]";1931 1932    StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;1933    FirstOp = false;1934  }1935 1936  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {1937    const MachineOperand &MO = getOperand(i);1938 1939    if (FirstOp) FirstOp = false; else OS << ",";1940    OS << " ";1941 1942    if (isDebugValueLike() && MO.isMetadata()) {1943      // Pretty print DBG_VALUE* instructions.1944      auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());1945      if (DIV && !DIV->getName().empty())1946        OS << "!\"" << DIV->getName() << '\"';1947      else {1948        LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};1949        unsigned TiedOperandIdx = getTiedOperandIdx(i);1950        MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,1951                 ShouldPrintRegisterTies, TiedOperandIdx, TRI);1952      }1953    } else if (isDebugLabel() && MO.isMetadata()) {1954      // Pretty print DBG_LABEL instructions.1955      auto *DIL = dyn_cast<DILabel>(MO.getMetadata());1956      if (DIL && !DIL->getName().empty())1957        OS << "\"" << DIL->getName() << '\"';1958      else {1959        LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};1960        unsigned TiedOperandIdx = getTiedOperandIdx(i);1961        MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,1962                 ShouldPrintRegisterTies, TiedOperandIdx, TRI);1963      }1964    } else if (i == AsmDescOp && MO.isImm()) {1965      // Pretty print the inline asm operand descriptor.1966      OS << '$' << AsmOpCount++;1967      unsigned Flag = MO.getImm();1968      const InlineAsm::Flag F(Flag);1969      OS << ":[";1970      OS << F.getKindName();1971 1972      unsigned RCID;1973      if (!F.isImmKind() && !F.isMemKind() && F.hasRegClassConstraint(RCID)) {1974        if (TRI) {1975          OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));1976        } else1977          OS << ":RC" << RCID;1978      }1979 1980      if (F.isMemKind()) {1981        const InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();1982        OS << ":" << InlineAsm::getMemConstraintName(MCID);1983      }1984 1985      unsigned TiedTo;1986      if (F.isUseOperandTiedToDef(TiedTo))1987        OS << " tiedto:$" << TiedTo;1988 1989      if ((F.isRegDefKind() || F.isRegDefEarlyClobberKind() ||1990           F.isRegUseKind()) &&1991          F.getRegMayBeFolded()) {1992        OS << " foldable";1993      }1994 1995      OS << ']';1996 1997      // Compute the index of the next operand descriptor.1998      AsmDescOp += 1 + F.getNumOperandRegisters();1999    } else {2000      LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};2001      unsigned TiedOperandIdx = getTiedOperandIdx(i);2002      if (MO.isImm() && isOperandSubregIdx(i))2003        MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI);2004      else2005        MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,2006                 ShouldPrintRegisterTies, TiedOperandIdx, TRI);2007    }2008  }2009 2010  // Print any optional symbols attached to this instruction as-if they were2011  // operands.2012  if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {2013    if (!FirstOp) {2014      FirstOp = false;2015      OS << ',';2016    }2017    OS << " pre-instr-symbol ";2018    MachineOperand::printSymbol(OS, *PreInstrSymbol);2019  }2020  if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {2021    if (!FirstOp) {2022      FirstOp = false;2023      OS << ',';2024    }2025    OS << " post-instr-symbol ";2026    MachineOperand::printSymbol(OS, *PostInstrSymbol);2027  }2028  if (MDNode *HeapAllocMarker = getHeapAllocMarker()) {2029    if (!FirstOp) {2030      FirstOp = false;2031      OS << ',';2032    }2033    OS << " heap-alloc-marker ";2034    HeapAllocMarker->printAsOperand(OS, MST);2035  }2036  if (MDNode *PCSections = getPCSections()) {2037    if (!FirstOp) {2038      FirstOp = false;2039      OS << ',';2040    }2041    OS << " pcsections ";2042    PCSections->printAsOperand(OS, MST);2043  }2044  if (MDNode *MMRA = getMMRAMetadata()) {2045    if (!FirstOp) {2046      FirstOp = false;2047      OS << ',';2048    }2049    OS << " mmra ";2050    MMRA->printAsOperand(OS, MST);2051  }2052  if (uint32_t CFIType = getCFIType()) {2053    if (!FirstOp)2054      OS << ',';2055    OS << " cfi-type " << CFIType;2056  }2057  if (getDeactivationSymbol())2058    OS << ", deactivation-symbol " << getDeactivationSymbol()->getName();2059 2060  if (DebugInstrNum) {2061    if (!FirstOp)2062      OS << ",";2063    OS << " debug-instr-number " << DebugInstrNum;2064  }2065 2066  if (!SkipDebugLoc) {2067    if (const DebugLoc &DL = getDebugLoc()) {2068      if (!FirstOp)2069        OS << ',';2070      OS << " debug-location ";2071      DL->printAsOperand(OS, MST);2072    }2073  }2074 2075  if (!memoperands_empty()) {2076    SmallVector<StringRef, 0> SSNs;2077    const LLVMContext *Context = nullptr;2078    std::unique_ptr<LLVMContext> CtxPtr;2079    const MachineFrameInfo *MFI = nullptr;2080    if (const MachineFunction *MF = getMFIfAvailable(*this)) {2081      MFI = &MF->getFrameInfo();2082      Context = &MF->getFunction().getContext();2083    } else {2084      CtxPtr = std::make_unique<LLVMContext>();2085      Context = CtxPtr.get();2086    }2087 2088    OS << " :: ";2089    bool NeedComma = false;2090    for (const MachineMemOperand *Op : memoperands()) {2091      if (NeedComma)2092        OS << ", ";2093      Op->print(OS, MST, SSNs, *Context, MFI, TII);2094      NeedComma = true;2095    }2096  }2097 2098  if (SkipDebugLoc)2099    return;2100 2101  bool HaveSemi = false;2102 2103  // Print debug location information.2104  if (const DebugLoc &DL = getDebugLoc()) {2105    if (!HaveSemi) {2106      OS << ';';2107      HaveSemi = true;2108    }2109    OS << ' ';2110    DL.print(OS);2111  }2112 2113  // Print extra comments for DEBUG_VALUE and friends if they are well-formed.2114  if ((isNonListDebugValue() && getNumOperands() >= 4) ||2115      (isDebugValueList() && getNumOperands() >= 2) ||2116      (isDebugRef() && getNumOperands() >= 3)) {2117    if (getDebugVariableOp().isMetadata()) {2118      if (!HaveSemi) {2119        OS << ";";2120        HaveSemi = true;2121      }2122      auto *DV = getDebugVariable();2123      OS << " line no:" << DV->getLine();2124      if (isIndirectDebugValue())2125        OS << " indirect";2126    }2127  }2128  // TODO: DBG_LABEL2129 2130  if (PrintMIAddrs)2131    OS << " ; " << this;2132 2133  if (AddNewLine)2134    OS << '\n';2135}2136 2137bool MachineInstr::addRegisterKilled(Register IncomingReg,2138                                     const TargetRegisterInfo *RegInfo,2139                                     bool AddIfNotFound) {2140  bool isPhysReg = IncomingReg.isPhysical();2141  bool hasAliases = isPhysReg &&2142    MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();2143  bool Found = false;2144  SmallVector<unsigned,4> DeadOps;2145  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {2146    MachineOperand &MO = getOperand(i);2147    if (!MO.isReg() || !MO.isUse() || MO.isUndef())2148      continue;2149 2150    // DEBUG_VALUE nodes do not contribute to code generation and should2151    // always be ignored. Failure to do so may result in trying to modify2152    // KILL flags on DEBUG_VALUE nodes.2153    if (MO.isDebug())2154      continue;2155 2156    Register Reg = MO.getReg();2157    if (!Reg)2158      continue;2159 2160    if (Reg == IncomingReg) {2161      if (!Found) {2162        if (MO.isKill())2163          // The register is already marked kill.2164          return true;2165        if (isPhysReg && isRegTiedToDefOperand(i))2166          // Two-address uses of physregs must not be marked kill.2167          return true;2168        MO.setIsKill();2169        Found = true;2170      }2171    } else if (hasAliases && MO.isKill() && Reg.isPhysical()) {2172      // A super-register kill already exists.2173      if (RegInfo->isSuperRegister(IncomingReg, Reg))2174        return true;2175      if (RegInfo->isSubRegister(IncomingReg, Reg))2176        DeadOps.push_back(i);2177    }2178  }2179 2180  // Trim unneeded kill operands.2181  while (!DeadOps.empty()) {2182    unsigned OpIdx = DeadOps.back();2183    if (getOperand(OpIdx).isImplicit() &&2184        (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))2185      removeOperand(OpIdx);2186    else2187      getOperand(OpIdx).setIsKill(false);2188    DeadOps.pop_back();2189  }2190 2191  // If not found, this means an alias of one of the operands is killed. Add a2192  // new implicit operand if required.2193  if (!Found && AddIfNotFound) {2194    addOperand(MachineOperand::CreateReg(IncomingReg,2195                                         false /*IsDef*/,2196                                         true  /*IsImp*/,2197                                         true  /*IsKill*/));2198    return true;2199  }2200  return Found;2201}2202 2203void MachineInstr::clearRegisterKills(Register Reg,2204                                      const TargetRegisterInfo *RegInfo) {2205  if (!Reg.isPhysical())2206    RegInfo = nullptr;2207  for (MachineOperand &MO : operands()) {2208    if (!MO.isReg() || !MO.isUse() || !MO.isKill())2209      continue;2210    Register OpReg = MO.getReg();2211    if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)2212      MO.setIsKill(false);2213  }2214}2215 2216bool MachineInstr::addRegisterDead(Register Reg,2217                                   const TargetRegisterInfo *RegInfo,2218                                   bool AddIfNotFound) {2219  bool isPhysReg = Reg.isPhysical();2220  bool hasAliases = isPhysReg &&2221    MCRegAliasIterator(Reg, RegInfo, false).isValid();2222  bool Found = false;2223  SmallVector<unsigned,4> DeadOps;2224  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {2225    MachineOperand &MO = getOperand(i);2226    if (!MO.isReg() || !MO.isDef())2227      continue;2228    Register MOReg = MO.getReg();2229    if (!MOReg)2230      continue;2231 2232    if (MOReg == Reg) {2233      MO.setIsDead();2234      Found = true;2235    } else if (hasAliases && MO.isDead() && MOReg.isPhysical()) {2236      // There exists a super-register that's marked dead.2237      if (RegInfo->isSuperRegister(Reg, MOReg))2238        return true;2239      if (RegInfo->isSubRegister(Reg, MOReg))2240        DeadOps.push_back(i);2241    }2242  }2243 2244  // Trim unneeded dead operands.2245  while (!DeadOps.empty()) {2246    unsigned OpIdx = DeadOps.back();2247    if (getOperand(OpIdx).isImplicit() &&2248        (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))2249      removeOperand(OpIdx);2250    else2251      getOperand(OpIdx).setIsDead(false);2252    DeadOps.pop_back();2253  }2254 2255  // If not found, this means an alias of one of the operands is dead. Add a2256  // new implicit operand if required.2257  if (Found || !AddIfNotFound)2258    return Found;2259 2260  addOperand(MachineOperand::CreateReg(Reg,2261                                       true  /*IsDef*/,2262                                       true  /*IsImp*/,2263                                       false /*IsKill*/,2264                                       true  /*IsDead*/));2265  return true;2266}2267 2268void MachineInstr::clearRegisterDeads(Register Reg) {2269  for (MachineOperand &MO : all_defs())2270    if (MO.getReg() == Reg)2271      MO.setIsDead(false);2272}2273 2274void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) {2275  for (MachineOperand &MO : all_defs())2276    if (MO.getReg() == Reg && MO.getSubReg() != 0)2277      MO.setIsUndef(IsUndef);2278}2279 2280void MachineInstr::addRegisterDefined(Register Reg,2281                                      const TargetRegisterInfo *RegInfo) {2282  if (Reg.isPhysical()) {2283    MachineOperand *MO = findRegisterDefOperand(Reg, RegInfo, false, false);2284    if (MO)2285      return;2286  } else {2287    for (const MachineOperand &MO : all_defs()) {2288      if (MO.getReg() == Reg && MO.getSubReg() == 0)2289        return;2290    }2291  }2292  addOperand(MachineOperand::CreateReg(Reg,2293                                       true  /*IsDef*/,2294                                       true  /*IsImp*/));2295}2296 2297void MachineInstr::setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,2298                                         const TargetRegisterInfo &TRI) {2299  bool HasRegMask = false;2300  for (MachineOperand &MO : operands()) {2301    if (MO.isRegMask()) {2302      HasRegMask = true;2303      continue;2304    }2305    if (!MO.isReg() || !MO.isDef()) continue;2306    Register Reg = MO.getReg();2307    if (!Reg.isPhysical())2308      continue;2309    // If there are no uses, including partial uses, the def is dead.2310    if (llvm::none_of(UsedRegs,2311                      [&](MCRegister Use) { return TRI.regsOverlap(Use, Reg); }))2312      MO.setIsDead();2313  }2314 2315  // This is a call with a register mask operand.2316  // Mask clobbers are always dead, so add defs for the non-dead defines.2317  if (HasRegMask)2318    for (const Register &UsedReg : UsedRegs)2319      addRegisterDefined(UsedReg, &TRI);2320}2321 2322unsigned2323MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {2324  // Build up a buffer of hash code components.2325  SmallVector<size_t, 16> HashComponents;2326  HashComponents.reserve(MI->getNumOperands() + 1);2327  HashComponents.push_back(MI->getOpcode());2328  for (const MachineOperand &MO : MI->operands()) {2329    if (MO.isReg() && MO.isDef() && MO.getReg().isVirtual())2330      continue;  // Skip virtual register defs.2331 2332    HashComponents.push_back(hash_value(MO));2333  }2334  return hash_combine_range(HashComponents);2335}2336 2337const MDNode *MachineInstr::getLocCookieMD() const {2338  // Find the source location cookie.2339  const MDNode *LocMD = nullptr;2340  for (unsigned i = getNumOperands(); i != 0; --i) {2341    if (getOperand(i-1).isMetadata() &&2342        (LocMD = getOperand(i-1).getMetadata()) &&2343        LocMD->getNumOperands() != 0) {2344      if (mdconst::hasa<ConstantInt>(LocMD->getOperand(0)))2345        return LocMD;2346    }2347  }2348 2349  return nullptr;2350}2351 2352void MachineInstr::emitInlineAsmError(const Twine &Msg) const {2353  assert(isInlineAsm());2354  const MDNode *LocMD = getLocCookieMD();2355  uint64_t LocCookie =2356      LocMD2357          ? mdconst::extract<ConstantInt>(LocMD->getOperand(0))->getZExtValue()2358          : 0;2359  LLVMContext &Ctx = getMF()->getFunction().getContext();2360  Ctx.diagnose(DiagnosticInfoInlineAsm(LocCookie, Msg));2361}2362 2363void MachineInstr::emitGenericError(const Twine &Msg) const {2364  const Function &Fn = getMF()->getFunction();2365  Fn.getContext().diagnose(2366      DiagnosticInfoGenericWithLoc(Msg, Fn, getDebugLoc()));2367}2368 2369MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,2370                                  const MCInstrDesc &MCID, bool IsIndirect,2371                                  Register Reg, const MDNode *Variable,2372                                  const MDNode *Expr) {2373  assert(isa<DILocalVariable>(Variable) && "not a variable");2374  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");2375  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&2376         "Expected inlined-at fields to agree");2377  auto MIB = BuildMI(MF, DL, MCID).addReg(Reg);2378  if (IsIndirect)2379    MIB.addImm(0U);2380  else2381    MIB.addReg(0U);2382  return MIB.addMetadata(Variable).addMetadata(Expr);2383}2384 2385MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,2386                                  const MCInstrDesc &MCID, bool IsIndirect,2387                                  ArrayRef<MachineOperand> DebugOps,2388                                  const MDNode *Variable, const MDNode *Expr) {2389  assert(isa<DILocalVariable>(Variable) && "not a variable");2390  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");2391  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&2392         "Expected inlined-at fields to agree");2393  if (MCID.Opcode == TargetOpcode::DBG_VALUE) {2394    assert(DebugOps.size() == 1 &&2395           "DBG_VALUE must contain exactly one debug operand");2396    MachineOperand DebugOp = DebugOps[0];2397    if (DebugOp.isReg())2398      return BuildMI(MF, DL, MCID, IsIndirect, DebugOp.getReg(), Variable,2399                     Expr);2400 2401    auto MIB = BuildMI(MF, DL, MCID).add(DebugOp);2402    if (IsIndirect)2403      MIB.addImm(0U);2404    else2405      MIB.addReg(0U);2406    return MIB.addMetadata(Variable).addMetadata(Expr);2407  }2408 2409  auto MIB = BuildMI(MF, DL, MCID);2410  MIB.addMetadata(Variable).addMetadata(Expr);2411  for (const MachineOperand &DebugOp : DebugOps)2412    if (DebugOp.isReg())2413      MIB.addReg(DebugOp.getReg());2414    else2415      MIB.add(DebugOp);2416  return MIB;2417}2418 2419MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,2420                                  MachineBasicBlock::iterator I,2421                                  const DebugLoc &DL, const MCInstrDesc &MCID,2422                                  bool IsIndirect, Register Reg,2423                                  const MDNode *Variable, const MDNode *Expr) {2424  MachineFunction &MF = *BB.getParent();2425  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);2426  BB.insert(I, MI);2427  return MachineInstrBuilder(MF, MI);2428}2429 2430MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,2431                                  MachineBasicBlock::iterator I,2432                                  const DebugLoc &DL, const MCInstrDesc &MCID,2433                                  bool IsIndirect,2434                                  ArrayRef<MachineOperand> DebugOps,2435                                  const MDNode *Variable, const MDNode *Expr) {2436  MachineFunction &MF = *BB.getParent();2437  MachineInstr *MI =2438      BuildMI(MF, DL, MCID, IsIndirect, DebugOps, Variable, Expr);2439  BB.insert(I, MI);2440  return MachineInstrBuilder(MF, *MI);2441}2442 2443/// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.2444/// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.2445static const DIExpression *computeExprForSpill(2446    const MachineInstr &MI,2447    const SmallVectorImpl<const MachineOperand *> &SpilledOperands) {2448  assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&2449         "Expected inlined-at fields to agree");2450 2451  const DIExpression *Expr = MI.getDebugExpression();2452  if (MI.isIndirectDebugValue()) {2453    assert(MI.getDebugOffset().getImm() == 0 &&2454           "DBG_VALUE with nonzero offset");2455    Expr = DIExpression::prepend(Expr, DIExpression::DerefBefore);2456  } else if (MI.isDebugValueList()) {2457    // We will replace the spilled register with a frame index, so2458    // immediately deref all references to the spilled register.2459    std::array<uint64_t, 1> Ops{{dwarf::DW_OP_deref}};2460    for (const MachineOperand *Op : SpilledOperands) {2461      unsigned OpIdx = MI.getDebugOperandIndex(Op);2462      Expr = DIExpression::appendOpsToArg(Expr, Ops, OpIdx);2463    }2464  }2465  return Expr;2466}2467static const DIExpression *computeExprForSpill(const MachineInstr &MI,2468                                               Register SpillReg) {2469  assert(MI.hasDebugOperandForReg(SpillReg) && "Spill Reg is not used in MI.");2470  SmallVector<const MachineOperand *> SpillOperands(2471      llvm::make_pointer_range(MI.getDebugOperandsForReg(SpillReg)));2472  return computeExprForSpill(MI, SpillOperands);2473}2474 2475MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,2476                                          MachineBasicBlock::iterator I,2477                                          const MachineInstr &Orig,2478                                          int FrameIndex, Register SpillReg) {2479  assert(!Orig.isDebugRef() &&2480         "DBG_INSTR_REF should not reference a virtual register.");2481  const DIExpression *Expr = computeExprForSpill(Orig, SpillReg);2482  MachineInstrBuilder NewMI =2483      BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());2484  // Non-Variadic Operands: Location, Offset, Variable, Expression2485  // Variadic Operands:     Variable, Expression, Locations...2486  if (Orig.isNonListDebugValue())2487    NewMI.addFrameIndex(FrameIndex).addImm(0U);2488  NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);2489  if (Orig.isDebugValueList()) {2490    for (const MachineOperand &Op : Orig.debug_operands())2491      if (Op.isReg() && Op.getReg() == SpillReg)2492        NewMI.addFrameIndex(FrameIndex);2493      else2494        NewMI.add(MachineOperand(Op));2495  }2496  return NewMI;2497}2498MachineInstr *llvm::buildDbgValueForSpill(2499    MachineBasicBlock &BB, MachineBasicBlock::iterator I,2500    const MachineInstr &Orig, int FrameIndex,2501    const SmallVectorImpl<const MachineOperand *> &SpilledOperands) {2502  const DIExpression *Expr = computeExprForSpill(Orig, SpilledOperands);2503  MachineInstrBuilder NewMI =2504      BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());2505  // Non-Variadic Operands: Location, Offset, Variable, Expression2506  // Variadic Operands:     Variable, Expression, Locations...2507  if (Orig.isNonListDebugValue())2508    NewMI.addFrameIndex(FrameIndex).addImm(0U);2509  NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);2510  if (Orig.isDebugValueList()) {2511    for (const MachineOperand &Op : Orig.debug_operands())2512      if (is_contained(SpilledOperands, &Op))2513        NewMI.addFrameIndex(FrameIndex);2514      else2515        NewMI.add(MachineOperand(Op));2516  }2517  return NewMI;2518}2519 2520void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex,2521                                  Register Reg) {2522  const DIExpression *Expr = computeExprForSpill(Orig, Reg);2523  if (Orig.isNonListDebugValue())2524    Orig.getDebugOffset().ChangeToImmediate(0U);2525  for (MachineOperand &Op : Orig.getDebugOperandsForReg(Reg))2526    Op.ChangeToFrameIndex(FrameIndex);2527  Orig.getDebugExpressionOp().setMetadata(Expr);2528}2529 2530void MachineInstr::collectDebugValues(2531                                SmallVectorImpl<MachineInstr *> &DbgValues) {2532  MachineInstr &MI = *this;2533  if (!MI.getOperand(0).isReg())2534    return;2535 2536  MachineBasicBlock::iterator DI = MI; ++DI;2537  for (MachineBasicBlock::iterator DE = MI.getParent()->end();2538       DI != DE; ++DI) {2539    if (!DI->isDebugValue())2540      return;2541    if (DI->hasDebugOperandForReg(MI.getOperand(0).getReg()))2542      DbgValues.push_back(&*DI);2543  }2544}2545 2546void MachineInstr::changeDebugValuesDefReg(Register Reg) {2547  // Collect matching debug values.2548  SmallVector<MachineInstr *, 2> DbgValues;2549 2550  if (!getOperand(0).isReg())2551    return;2552 2553  Register DefReg = getOperand(0).getReg();2554  auto *MRI = getRegInfo();2555  for (auto &MO : MRI->use_operands(DefReg)) {2556    auto *DI = MO.getParent();2557    if (!DI->isDebugValue())2558      continue;2559    if (DI->hasDebugOperandForReg(DefReg)) {2560      DbgValues.push_back(DI);2561    }2562  }2563 2564  // Propagate Reg to debug value instructions.2565  for (auto *DBI : DbgValues)2566    for (MachineOperand &Op : DBI->getDebugOperandsForReg(DefReg))2567      Op.setReg(Reg);2568}2569 2570using MMOList = SmallVector<const MachineMemOperand *, 2>;2571 2572static LocationSize getSpillSlotSize(const MMOList &Accesses,2573                                     const MachineFrameInfo &MFI) {2574  std::optional<TypeSize> Size;2575  for (const auto *A : Accesses) {2576    if (MFI.isSpillSlotObjectIndex(2577            cast<FixedStackPseudoSourceValue>(A->getPseudoValue())2578                ->getFrameIndex())) {2579      LocationSize S = A->getSize();2580      if (!S.hasValue())2581        return LocationSize::beforeOrAfterPointer();2582      if (!Size)2583        Size = S.getValue();2584      else2585        Size = *Size + S.getValue();2586    }2587  }2588  if (!Size)2589    return LocationSize::precise(0);2590  return LocationSize::precise(*Size);2591}2592 2593std::optional<LocationSize>2594MachineInstr::getSpillSize(const TargetInstrInfo *TII) const {2595  int FI;2596  if (TII->isStoreToStackSlotPostFE(*this, FI)) {2597    const MachineFrameInfo &MFI = getMF()->getFrameInfo();2598    if (MFI.isSpillSlotObjectIndex(FI))2599      return (*memoperands_begin())->getSize();2600  }2601  return std::nullopt;2602}2603 2604std::optional<LocationSize>2605MachineInstr::getFoldedSpillSize(const TargetInstrInfo *TII) const {2606  MMOList Accesses;2607  if (TII->hasStoreToStackSlot(*this, Accesses))2608    return getSpillSlotSize(Accesses, getMF()->getFrameInfo());2609  return std::nullopt;2610}2611 2612std::optional<LocationSize>2613MachineInstr::getRestoreSize(const TargetInstrInfo *TII) const {2614  int FI;2615  if (TII->isLoadFromStackSlotPostFE(*this, FI)) {2616    const MachineFrameInfo &MFI = getMF()->getFrameInfo();2617    if (MFI.isSpillSlotObjectIndex(FI))2618      return (*memoperands_begin())->getSize();2619  }2620  return std::nullopt;2621}2622 2623std::optional<LocationSize>2624MachineInstr::getFoldedRestoreSize(const TargetInstrInfo *TII) const {2625  MMOList Accesses;2626  if (TII->hasLoadFromStackSlot(*this, Accesses))2627    return getSpillSlotSize(Accesses, getMF()->getFrameInfo());2628  return std::nullopt;2629}2630 2631unsigned MachineInstr::getDebugInstrNum() {2632  if (DebugInstrNum == 0)2633    DebugInstrNum = getParent()->getParent()->getNewDebugInstrNum();2634  return DebugInstrNum;2635}2636 2637unsigned MachineInstr::getDebugInstrNum(MachineFunction &MF) {2638  if (DebugInstrNum == 0)2639    DebugInstrNum = MF.getNewDebugInstrNum();2640  return DebugInstrNum;2641}2642 2643std::tuple<LLT, LLT> MachineInstr::getFirst2LLTs() const {2644  return std::tuple(getRegInfo()->getType(getOperand(0).getReg()),2645                    getRegInfo()->getType(getOperand(1).getReg()));2646}2647 2648std::tuple<LLT, LLT, LLT> MachineInstr::getFirst3LLTs() const {2649  return std::tuple(getRegInfo()->getType(getOperand(0).getReg()),2650                    getRegInfo()->getType(getOperand(1).getReg()),2651                    getRegInfo()->getType(getOperand(2).getReg()));2652}2653 2654std::tuple<LLT, LLT, LLT, LLT> MachineInstr::getFirst4LLTs() const {2655  return std::tuple(getRegInfo()->getType(getOperand(0).getReg()),2656                    getRegInfo()->getType(getOperand(1).getReg()),2657                    getRegInfo()->getType(getOperand(2).getReg()),2658                    getRegInfo()->getType(getOperand(3).getReg()));2659}2660 2661std::tuple<LLT, LLT, LLT, LLT, LLT> MachineInstr::getFirst5LLTs() const {2662  return std::tuple(getRegInfo()->getType(getOperand(0).getReg()),2663                    getRegInfo()->getType(getOperand(1).getReg()),2664                    getRegInfo()->getType(getOperand(2).getReg()),2665                    getRegInfo()->getType(getOperand(3).getReg()),2666                    getRegInfo()->getType(getOperand(4).getReg()));2667}2668 2669std::tuple<Register, LLT, Register, LLT>2670MachineInstr::getFirst2RegLLTs() const {2671  Register Reg0 = getOperand(0).getReg();2672  Register Reg1 = getOperand(1).getReg();2673  return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1,2674                    getRegInfo()->getType(Reg1));2675}2676 2677std::tuple<Register, LLT, Register, LLT, Register, LLT>2678MachineInstr::getFirst3RegLLTs() const {2679  Register Reg0 = getOperand(0).getReg();2680  Register Reg1 = getOperand(1).getReg();2681  Register Reg2 = getOperand(2).getReg();2682  return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1,2683                    getRegInfo()->getType(Reg1), Reg2,2684                    getRegInfo()->getType(Reg2));2685}2686 2687std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT>2688MachineInstr::getFirst4RegLLTs() const {2689  Register Reg0 = getOperand(0).getReg();2690  Register Reg1 = getOperand(1).getReg();2691  Register Reg2 = getOperand(2).getReg();2692  Register Reg3 = getOperand(3).getReg();2693  return std::tuple(2694      Reg0, getRegInfo()->getType(Reg0), Reg1, getRegInfo()->getType(Reg1),2695      Reg2, getRegInfo()->getType(Reg2), Reg3, getRegInfo()->getType(Reg3));2696}2697 2698std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT, Register,2699           LLT>2700MachineInstr::getFirst5RegLLTs() const {2701  Register Reg0 = getOperand(0).getReg();2702  Register Reg1 = getOperand(1).getReg();2703  Register Reg2 = getOperand(2).getReg();2704  Register Reg3 = getOperand(3).getReg();2705  Register Reg4 = getOperand(4).getReg();2706  return std::tuple(2707      Reg0, getRegInfo()->getType(Reg0), Reg1, getRegInfo()->getType(Reg1),2708      Reg2, getRegInfo()->getType(Reg2), Reg3, getRegInfo()->getType(Reg3),2709      Reg4, getRegInfo()->getType(Reg4));2710}2711 2712void MachineInstr::insert(mop_iterator InsertBefore,2713                          ArrayRef<MachineOperand> Ops) {2714  assert(InsertBefore != nullptr && "invalid iterator");2715  assert(InsertBefore->getParent() == this &&2716         "iterator points to operand of other inst");2717  if (Ops.empty())2718    return;2719 2720  // Do one pass to untie operands.2721  SmallDenseMap<unsigned, unsigned> TiedOpIndices;2722  for (const MachineOperand &MO : operands()) {2723    if (MO.isReg() && MO.isTied()) {2724      unsigned OpNo = getOperandNo(&MO);2725      unsigned TiedTo = findTiedOperandIdx(OpNo);2726      TiedOpIndices[OpNo] = TiedTo;2727      untieRegOperand(OpNo);2728    }2729  }2730 2731  unsigned OpIdx = getOperandNo(InsertBefore);2732  unsigned NumOperands = getNumOperands();2733  unsigned OpsToMove = NumOperands - OpIdx;2734 2735  SmallVector<MachineOperand> MovingOps;2736  MovingOps.reserve(OpsToMove);2737 2738  for (unsigned I = 0; I < OpsToMove; ++I) {2739    MovingOps.emplace_back(getOperand(OpIdx));2740    removeOperand(OpIdx);2741  }2742  for (const MachineOperand &MO : Ops)2743    addOperand(MO);2744  for (const MachineOperand &OpMoved : MovingOps)2745    addOperand(OpMoved);2746 2747  // Re-tie operands.2748  for (auto [Tie1, Tie2] : TiedOpIndices) {2749    if (Tie1 >= OpIdx)2750      Tie1 += Ops.size();2751    if (Tie2 >= OpIdx)2752      Tie2 += Ops.size();2753    tieOperands(Tie1, Tie2);2754  }2755}2756 2757bool MachineInstr::mayFoldInlineAsmRegOp(unsigned OpId) const {2758  assert(OpId && "expected non-zero operand id");2759  assert(isInlineAsm() && "should only be used on inline asm");2760 2761  if (!getOperand(OpId).isReg())2762    return false;2763 2764  const MachineOperand &MD = getOperand(OpId - 1);2765  if (!MD.isImm())2766    return false;2767 2768  InlineAsm::Flag F(MD.getImm());2769  if (F.isRegUseKind() || F.isRegDefKind() || F.isRegDefEarlyClobberKind())2770    return F.getRegMayBeFolded();2771  return false;2772}2773 2774unsigned MachineInstr::removePHIIncomingValueFor(const MachineBasicBlock &MBB) {2775  assert(isPHI());2776 2777  // Phi might have multiple entries for MBB. Need to remove them all.2778  unsigned RemovedCount = 0;2779  for (unsigned N = getNumOperands(); N > 2; N -= 2) {2780    if (getOperand(N - 1).getMBB() == &MBB) {2781      removeOperand(N - 1);2782      removeOperand(N - 2);2783      RemovedCount += 2;2784    }2785  }2786  return RemovedCount;2787}2788