1306 lines · cpp
1//===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9/// \file Methods common to all machine operands.10//11//===----------------------------------------------------------------------===//12 13#include "llvm/CodeGen/MachineOperand.h"14#include "llvm/ADT/StableHashing.h"15#include "llvm/ADT/StringExtras.h"16#include "llvm/Analysis/Loads.h"17#include "llvm/CodeGen/MIRFormatter.h"18#include "llvm/CodeGen/MachineFrameInfo.h"19#include "llvm/CodeGen/MachineJumpTableInfo.h"20#include "llvm/CodeGen/MachineRegisterInfo.h"21#include "llvm/CodeGen/PseudoSourceValueManager.h"22#include "llvm/CodeGen/TargetInstrInfo.h"23#include "llvm/CodeGen/TargetRegisterInfo.h"24#include "llvm/Config/llvm-config.h"25#include "llvm/IR/Constants.h"26#include "llvm/IR/IRPrintingPasses.h"27#include "llvm/IR/Instructions.h"28#include "llvm/IR/ModuleSlotTracker.h"29#include "llvm/MC/MCDwarf.h"30#include "llvm/Target/TargetMachine.h"31#include <optional>32 33using namespace llvm;34 35static cl::opt<int>36 PrintRegMaskNumRegs("print-regmask-num-regs",37 cl::desc("Number of registers to limit to when "38 "printing regmask operands in IR dumps. "39 "unlimited = -1"),40 cl::init(32), cl::Hidden);41 42static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {43 if (const MachineInstr *MI = MO.getParent())44 if (const MachineBasicBlock *MBB = MI->getParent())45 if (const MachineFunction *MF = MBB->getParent())46 return MF;47 return nullptr;48}49 50static MachineFunction *getMFIfAvailable(MachineOperand &MO) {51 return const_cast<MachineFunction *>(52 getMFIfAvailable(const_cast<const MachineOperand &>(MO)));53}54 55unsigned MachineOperand::getOperandNo() const {56 assert(getParent() && "Operand does not belong to any instruction!");57 return getParent()->getOperandNo(this);58}59 60void MachineOperand::setReg(Register Reg) {61 if (getReg() == Reg)62 return; // No change.63 64 // Clear the IsRenamable bit to keep it conservatively correct.65 IsRenamable = false;66 67 // Otherwise, we have to change the register. If this operand is embedded68 // into a machine function, we need to update the old and new register's69 // use/def lists.70 if (MachineFunction *MF = getMFIfAvailable(*this)) {71 MachineRegisterInfo &MRI = MF->getRegInfo();72 MRI.removeRegOperandFromUseList(this);73 SmallContents.RegNo = Reg.id();74 MRI.addRegOperandToUseList(this);75 return;76 }77 78 // Otherwise, just change the register, no problem. :)79 SmallContents.RegNo = Reg.id();80}81 82void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx,83 const TargetRegisterInfo &TRI) {84 assert(Reg.isVirtual());85 if (SubIdx && getSubReg())86 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());87 setReg(Reg);88 if (SubIdx)89 setSubReg(SubIdx);90}91 92void MachineOperand::substPhysReg(MCRegister Reg, const TargetRegisterInfo &TRI) {93 assert(Reg.isPhysical());94 if (getSubReg()) {95 Reg = TRI.getSubReg(Reg, getSubReg());96 // Note that getSubReg() may return 0 if the sub-register doesn't exist.97 // That won't happen in legal code.98 setSubReg(0);99 if (isDef())100 setIsUndef(false);101 }102 setReg(Reg);103}104 105/// Change a def to a use, or a use to a def.106void MachineOperand::setIsDef(bool Val) {107 assert(isReg() && "Wrong MachineOperand accessor");108 assert((!Val || !isDebug()) && "Marking a debug operation as def");109 if (IsDef == Val)110 return;111 assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");112 // MRI may keep uses and defs in different list positions.113 if (MachineFunction *MF = getMFIfAvailable(*this)) {114 MachineRegisterInfo &MRI = MF->getRegInfo();115 MRI.removeRegOperandFromUseList(this);116 IsDef = Val;117 MRI.addRegOperandToUseList(this);118 return;119 }120 IsDef = Val;121}122 123bool MachineOperand::isRenamable() const {124 assert(isReg() && "Wrong MachineOperand accessor");125 assert(getReg().isPhysical() &&126 "isRenamable should only be checked on physical registers");127 if (!IsRenamable)128 return false;129 130 const MachineInstr *MI = getParent();131 if (!MI)132 return true;133 134 if (isDef())135 return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);136 137 assert(isUse() && "Reg is not def or use");138 return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);139}140 141void MachineOperand::setIsRenamable(bool Val) {142 assert(isReg() && "Wrong MachineOperand accessor");143 assert(getReg().isPhysical() &&144 "setIsRenamable should only be called on physical registers");145 IsRenamable = Val;146}147 148// If this operand is currently a register operand, and if this is in a149// function, deregister the operand from the register's use/def list.150void MachineOperand::removeRegFromUses() {151 if (!isReg() || !isOnRegUseList())152 return;153 154 if (MachineFunction *MF = getMFIfAvailable(*this))155 MF->getRegInfo().removeRegOperandFromUseList(this);156}157 158/// ChangeToImmediate - Replace this operand with a new immediate operand of159/// the specified value. If an operand is known to be an immediate already,160/// the setImm method should be used.161void MachineOperand::ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags) {162 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");163 164 removeRegFromUses();165 166 OpKind = MO_Immediate;167 Contents.ImmVal = ImmVal;168 setTargetFlags(TargetFlags);169}170 171void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm,172 unsigned TargetFlags) {173 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");174 175 removeRegFromUses();176 177 OpKind = MO_FPImmediate;178 Contents.CFP = FPImm;179 setTargetFlags(TargetFlags);180}181 182void MachineOperand::ChangeToES(const char *SymName,183 unsigned TargetFlags) {184 assert((!isReg() || !isTied()) &&185 "Cannot change a tied operand into an external symbol");186 187 removeRegFromUses();188 189 OpKind = MO_ExternalSymbol;190 Contents.OffsetedInfo.Val.SymbolName = SymName;191 setOffset(0); // Offset is always 0.192 setTargetFlags(TargetFlags);193}194 195void MachineOperand::ChangeToGA(const GlobalValue *GV, int64_t Offset,196 unsigned TargetFlags) {197 assert((!isReg() || !isTied()) &&198 "Cannot change a tied operand into a global address");199 200 removeRegFromUses();201 202 OpKind = MO_GlobalAddress;203 Contents.OffsetedInfo.Val.GV = GV;204 setOffset(Offset);205 setTargetFlags(TargetFlags);206}207 208void MachineOperand::ChangeToBA(const BlockAddress *BA, int64_t Offset,209 unsigned TargetFlags) {210 assert((!isReg() || !isTied()) &&211 "Cannot change a tied operand into a block address");212 213 removeRegFromUses();214 215 OpKind = MO_BlockAddress;216 Contents.OffsetedInfo.Val.BA = BA;217 setOffset(Offset);218 setTargetFlags(TargetFlags);219}220 221void MachineOperand::ChangeToCPI(unsigned Idx, int Offset,222 unsigned TargetFlags) {223 assert((!isReg() || !isTied()) &&224 "Cannot change a tied operand into a constant pool index");225 226 removeRegFromUses();227 228 OpKind = MO_ConstantPoolIndex;229 setIndex(Idx);230 setOffset(Offset);231 setTargetFlags(TargetFlags);232}233 234void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags) {235 assert((!isReg() || !isTied()) &&236 "Cannot change a tied operand into an MCSymbol");237 238 removeRegFromUses();239 240 OpKind = MO_MCSymbol;241 Contents.Sym = Sym;242 setTargetFlags(TargetFlags);243}244 245void MachineOperand::ChangeToFrameIndex(int Idx, unsigned TargetFlags) {246 assert((!isReg() || !isTied()) &&247 "Cannot change a tied operand into a FrameIndex");248 249 removeRegFromUses();250 251 OpKind = MO_FrameIndex;252 setIndex(Idx);253 setTargetFlags(TargetFlags);254}255 256void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,257 unsigned TargetFlags) {258 assert((!isReg() || !isTied()) &&259 "Cannot change a tied operand into a FrameIndex");260 261 removeRegFromUses();262 263 OpKind = MO_TargetIndex;264 setIndex(Idx);265 setOffset(Offset);266 setTargetFlags(TargetFlags);267}268 269void MachineOperand::ChangeToDbgInstrRef(unsigned InstrIdx, unsigned OpIdx,270 unsigned TargetFlags) {271 assert((!isReg() || !isTied()) &&272 "Cannot change a tied operand into a DbgInstrRef");273 274 removeRegFromUses();275 276 OpKind = MO_DbgInstrRef;277 setInstrRefInstrIndex(InstrIdx);278 setInstrRefOpIndex(OpIdx);279 setTargetFlags(TargetFlags);280}281 282/// ChangeToRegister - Replace this operand with a new register operand of283/// the specified value. If an operand is known to be an register already,284/// the setReg method should be used.285void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,286 bool isKill, bool isDead, bool isUndef,287 bool isDebug) {288 MachineRegisterInfo *RegInfo = nullptr;289 if (MachineFunction *MF = getMFIfAvailable(*this))290 RegInfo = &MF->getRegInfo();291 // If this operand is already a register operand, remove it from the292 // register's use/def lists.293 bool WasReg = isReg();294 if (RegInfo && WasReg)295 RegInfo->removeRegOperandFromUseList(this);296 297 // Ensure debug instructions set debug flag on register uses.298 const MachineInstr *MI = getParent();299 if (!isDef && MI && MI->isDebugInstr())300 isDebug = true;301 302 // Change this to a register and set the reg#.303 assert(!(isDead && !isDef) && "Dead flag on non-def");304 assert(!(isKill && isDef) && "Kill flag on def");305 OpKind = MO_Register;306 SmallContents.RegNo = Reg.id();307 SubReg_TargetFlags = 0;308 IsDef = isDef;309 IsImp = isImp;310 IsDeadOrKill = isKill | isDead;311 IsRenamable = false;312 IsUndef = isUndef;313 IsInternalRead = false;314 IsEarlyClobber = false;315 IsDebug = isDebug;316 // Ensure isOnRegUseList() returns false.317 Contents.Reg.Prev = nullptr;318 // Preserve the tie when the operand was already a register.319 if (!WasReg)320 TiedTo = 0;321 322 // If this operand is embedded in a function, add the operand to the323 // register's use/def list.324 if (RegInfo)325 RegInfo->addRegOperandToUseList(this);326}327 328/// isIdenticalTo - Return true if this operand is identical to the specified329/// operand. Note that this should stay in sync with the hash_value overload330/// below.331bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {332 if (getType() != Other.getType() ||333 getTargetFlags() != Other.getTargetFlags())334 return false;335 336 switch (getType()) {337 case MachineOperand::MO_Register:338 return getReg() == Other.getReg() && isDef() == Other.isDef() &&339 getSubReg() == Other.getSubReg();340 case MachineOperand::MO_Immediate:341 return getImm() == Other.getImm();342 case MachineOperand::MO_CImmediate:343 return getCImm() == Other.getCImm();344 case MachineOperand::MO_FPImmediate:345 return getFPImm() == Other.getFPImm();346 case MachineOperand::MO_MachineBasicBlock:347 return getMBB() == Other.getMBB();348 case MachineOperand::MO_FrameIndex:349 return getIndex() == Other.getIndex();350 case MachineOperand::MO_ConstantPoolIndex:351 case MachineOperand::MO_TargetIndex:352 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();353 case MachineOperand::MO_JumpTableIndex:354 return getIndex() == Other.getIndex();355 case MachineOperand::MO_GlobalAddress:356 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();357 case MachineOperand::MO_ExternalSymbol:358 return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&359 getOffset() == Other.getOffset();360 case MachineOperand::MO_BlockAddress:361 return getBlockAddress() == Other.getBlockAddress() &&362 getOffset() == Other.getOffset();363 case MachineOperand::MO_RegisterMask:364 case MachineOperand::MO_RegisterLiveOut: {365 // Shallow compare of the two RegMasks366 const uint32_t *RegMask = isRegMask() ? getRegMask() : getRegLiveOut();367 const uint32_t *OtherRegMask =368 isRegMask() ? Other.getRegMask() : Other.getRegLiveOut();369 if (RegMask == OtherRegMask)370 return true;371 372 if (const MachineFunction *MF = getMFIfAvailable(*this)) {373 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();374 unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());375 // Deep compare of the two RegMasks376 return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);377 }378 // We don't know the size of the RegMask, so we can't deep compare the two379 // reg masks.380 return false;381 }382 case MachineOperand::MO_MCSymbol:383 return getMCSymbol() == Other.getMCSymbol();384 case MachineOperand::MO_DbgInstrRef:385 return getInstrRefInstrIndex() == Other.getInstrRefInstrIndex() &&386 getInstrRefOpIndex() == Other.getInstrRefOpIndex();387 case MachineOperand::MO_CFIIndex:388 return getCFIIndex() == Other.getCFIIndex();389 case MachineOperand::MO_Metadata:390 return getMetadata() == Other.getMetadata();391 case MachineOperand::MO_IntrinsicID:392 return getIntrinsicID() == Other.getIntrinsicID();393 case MachineOperand::MO_Predicate:394 return getPredicate() == Other.getPredicate();395 case MachineOperand::MO_ShuffleMask:396 return getShuffleMask() == Other.getShuffleMask();397 }398 llvm_unreachable("Invalid machine operand type");399}400 401// Note: this must stay exactly in sync with isIdenticalTo above.402hash_code llvm::hash_value(const MachineOperand &MO) {403 switch (MO.getType()) {404 case MachineOperand::MO_Register:405 // Register operands don't have target flags.406 return hash_combine(MO.getType(), MO.getReg().id(), MO.getSubReg(),407 MO.isDef());408 case MachineOperand::MO_Immediate:409 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());410 case MachineOperand::MO_CImmediate:411 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());412 case MachineOperand::MO_FPImmediate:413 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());414 case MachineOperand::MO_MachineBasicBlock:415 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());416 case MachineOperand::MO_FrameIndex:417 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());418 case MachineOperand::MO_ConstantPoolIndex:419 case MachineOperand::MO_TargetIndex:420 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),421 MO.getOffset());422 case MachineOperand::MO_JumpTableIndex:423 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());424 case MachineOperand::MO_ExternalSymbol:425 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),426 StringRef(MO.getSymbolName()));427 case MachineOperand::MO_GlobalAddress:428 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),429 MO.getOffset());430 case MachineOperand::MO_BlockAddress:431 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),432 MO.getOffset());433 case MachineOperand::MO_RegisterMask:434 case MachineOperand::MO_RegisterLiveOut: {435 if (const MachineFunction *MF = getMFIfAvailable(MO)) {436 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();437 unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());438 const uint32_t *RegMask =439 MO.isRegMask() ? MO.getRegMask() : MO.getRegLiveOut();440 std::vector<stable_hash> RegMaskHashes(RegMask, RegMask + RegMaskSize);441 return hash_combine(MO.getType(), MO.getTargetFlags(),442 stable_hash_combine(RegMaskHashes));443 }444 445 assert(0 && "MachineOperand not associated with any MachineFunction");446 return hash_combine(MO.getType(), MO.getTargetFlags());447 }448 case MachineOperand::MO_Metadata:449 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());450 case MachineOperand::MO_MCSymbol:451 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());452 case MachineOperand::MO_DbgInstrRef:453 return hash_combine(MO.getType(), MO.getTargetFlags(),454 MO.getInstrRefInstrIndex(), MO.getInstrRefOpIndex());455 case MachineOperand::MO_CFIIndex:456 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());457 case MachineOperand::MO_IntrinsicID:458 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());459 case MachineOperand::MO_Predicate:460 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());461 case MachineOperand::MO_ShuffleMask:462 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());463 }464 llvm_unreachable("Invalid machine operand type");465}466 467// Try to crawl up to the machine function and get TRI from it.468static void tryToGetTargetInfo(const MachineOperand &MO,469 const TargetRegisterInfo *&TRI) {470 if (const MachineFunction *MF = getMFIfAvailable(MO)) {471 TRI = MF->getSubtarget().getRegisterInfo();472 }473}474 475static const char *getTargetIndexName(const MachineFunction &MF, int Index) {476 const auto *TII = MF.getSubtarget().getInstrInfo();477 assert(TII && "expected instruction info");478 auto Indices = TII->getSerializableTargetIndices();479 auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {480 return I.first == Index;481 });482 if (Found != Indices.end())483 return Found->second;484 return nullptr;485}486 487const char *MachineOperand::getTargetIndexName() const {488 const MachineFunction *MF = getMFIfAvailable(*this);489 return MF ? ::getTargetIndexName(*MF, this->getIndex()) : nullptr;490}491 492static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {493 auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();494 for (const auto &I : Flags) {495 if (I.first == TF) {496 return I.second;497 }498 }499 return nullptr;500}501 502static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,503 const TargetRegisterInfo *TRI) {504 if (!TRI) {505 OS << "%dwarfreg." << DwarfReg;506 return;507 }508 509 if (std::optional<MCRegister> Reg = TRI->getLLVMRegNum(DwarfReg, true))510 OS << printReg(*Reg, TRI);511 else512 OS << "<badreg>";513}514 515static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,516 ModuleSlotTracker &MST) {517 OS << "%ir-block.";518 if (BB.hasName()) {519 printLLVMNameWithoutPrefix(OS, BB.getName());520 return;521 }522 std::optional<int> Slot;523 if (const Function *F = BB.getParent()) {524 if (F == MST.getCurrentFunction()) {525 Slot = MST.getLocalSlot(&BB);526 } else if (const Module *M = F->getParent()) {527 ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);528 CustomMST.incorporateFunction(*F);529 Slot = CustomMST.getLocalSlot(&BB);530 }531 }532 if (Slot)533 MachineOperand::printIRSlotNumber(OS, *Slot);534 else535 OS << "<unknown>";536}537 538static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,539 SyncScope::ID SSID,540 SmallVectorImpl<StringRef> &SSNs) {541 switch (SSID) {542 case SyncScope::System:543 break;544 default:545 if (SSNs.empty())546 Context.getSyncScopeNames(SSNs);547 548 OS << "syncscope(\"";549 printEscapedString(SSNs[SSID], OS);550 OS << "\") ";551 break;552 }553}554 555static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,556 unsigned TMMOFlag) {557 auto Flags = TII.getSerializableMachineMemOperandTargetFlags();558 for (const auto &I : Flags) {559 if (I.first == TMMOFlag) {560 return I.second;561 }562 }563 return nullptr;564}565 566static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,567 const MachineFrameInfo *MFI) {568 StringRef Name;569 if (MFI) {570 IsFixed = MFI->isFixedObjectIndex(FrameIndex);571 if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))572 if (Alloca->hasName())573 Name = Alloca->getName();574 if (IsFixed)575 FrameIndex -= MFI->getObjectIndexBegin();576 }577 MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);578}579 580void MachineOperand::printSubRegIdx(raw_ostream &OS, uint64_t Index,581 const TargetRegisterInfo *TRI) {582 OS << "%subreg.";583 if (TRI && Index != 0 && Index < TRI->getNumSubRegIndices())584 OS << TRI->getSubRegIndexName(Index);585 else586 OS << Index;587}588 589void MachineOperand::printTargetFlags(raw_ostream &OS,590 const MachineOperand &Op) {591 if (!Op.getTargetFlags())592 return;593 const MachineFunction *MF = getMFIfAvailable(Op);594 if (!MF)595 return;596 597 const auto *TII = MF->getSubtarget().getInstrInfo();598 assert(TII && "expected instruction info");599 auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());600 OS << "target-flags(";601 const bool HasDirectFlags = Flags.first;602 const bool HasBitmaskFlags = Flags.second;603 if (!HasDirectFlags && !HasBitmaskFlags) {604 OS << "<unknown>) ";605 return;606 }607 if (HasDirectFlags) {608 if (const auto *Name = getTargetFlagName(TII, Flags.first))609 OS << Name;610 else611 OS << "<unknown target flag>";612 }613 if (!HasBitmaskFlags) {614 OS << ") ";615 return;616 }617 bool IsCommaNeeded = HasDirectFlags;618 unsigned BitMask = Flags.second;619 auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();620 for (const auto &Mask : BitMasks) {621 // Check if the flag's bitmask has the bits of the current mask set.622 if ((BitMask & Mask.first) == Mask.first) {623 if (IsCommaNeeded)624 OS << ", ";625 IsCommaNeeded = true;626 OS << Mask.second;627 // Clear the bits which were serialized from the flag's bitmask.628 BitMask &= ~(Mask.first);629 }630 }631 if (BitMask) {632 // When the resulting flag's bitmask isn't zero, we know that we didn't633 // serialize all of the bit flags.634 if (IsCommaNeeded)635 OS << ", ";636 OS << "<unknown bitmask target flag>";637 }638 OS << ") ";639}640 641void MachineOperand::printSymbol(raw_ostream &OS, MCSymbol &Sym) {642 OS << "<mcsymbol " << Sym << ">";643}644 645void MachineOperand::printStackObjectReference(raw_ostream &OS,646 unsigned FrameIndex,647 bool IsFixed, StringRef Name) {648 if (IsFixed) {649 OS << "%fixed-stack." << FrameIndex;650 return;651 }652 653 OS << "%stack." << FrameIndex;654 if (!Name.empty())655 OS << '.' << Name;656}657 658void MachineOperand::printOperandOffset(raw_ostream &OS, int64_t Offset) {659 if (Offset == 0)660 return;661 if (Offset < 0) {662 OS << " - " << -Offset;663 return;664 }665 OS << " + " << Offset;666}667 668void MachineOperand::printIRSlotNumber(raw_ostream &OS, int Slot) {669 if (Slot == -1)670 OS << "<badref>";671 else672 OS << Slot;673}674 675static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,676 const TargetRegisterInfo *TRI) {677 switch (CFI.getOperation()) {678 case MCCFIInstruction::OpSameValue:679 OS << "same_value ";680 if (MCSymbol *Label = CFI.getLabel())681 MachineOperand::printSymbol(OS, *Label);682 printCFIRegister(CFI.getRegister(), OS, TRI);683 break;684 case MCCFIInstruction::OpRememberState:685 OS << "remember_state ";686 if (MCSymbol *Label = CFI.getLabel())687 MachineOperand::printSymbol(OS, *Label);688 break;689 case MCCFIInstruction::OpRestoreState:690 OS << "restore_state ";691 if (MCSymbol *Label = CFI.getLabel())692 MachineOperand::printSymbol(OS, *Label);693 break;694 case MCCFIInstruction::OpOffset:695 OS << "offset ";696 if (MCSymbol *Label = CFI.getLabel())697 MachineOperand::printSymbol(OS, *Label);698 printCFIRegister(CFI.getRegister(), OS, TRI);699 OS << ", " << CFI.getOffset();700 break;701 case MCCFIInstruction::OpDefCfaRegister:702 OS << "def_cfa_register ";703 if (MCSymbol *Label = CFI.getLabel())704 MachineOperand::printSymbol(OS, *Label);705 printCFIRegister(CFI.getRegister(), OS, TRI);706 break;707 case MCCFIInstruction::OpDefCfaOffset:708 OS << "def_cfa_offset ";709 if (MCSymbol *Label = CFI.getLabel())710 MachineOperand::printSymbol(OS, *Label);711 OS << CFI.getOffset();712 break;713 case MCCFIInstruction::OpDefCfa:714 OS << "def_cfa ";715 if (MCSymbol *Label = CFI.getLabel())716 MachineOperand::printSymbol(OS, *Label);717 printCFIRegister(CFI.getRegister(), OS, TRI);718 OS << ", " << CFI.getOffset();719 break;720 case MCCFIInstruction::OpLLVMDefAspaceCfa:721 OS << "llvm_def_aspace_cfa ";722 if (MCSymbol *Label = CFI.getLabel())723 MachineOperand::printSymbol(OS, *Label);724 printCFIRegister(CFI.getRegister(), OS, TRI);725 OS << ", " << CFI.getOffset();726 OS << ", " << CFI.getAddressSpace();727 break;728 case MCCFIInstruction::OpRelOffset:729 OS << "rel_offset ";730 if (MCSymbol *Label = CFI.getLabel())731 MachineOperand::printSymbol(OS, *Label);732 printCFIRegister(CFI.getRegister(), OS, TRI);733 OS << ", " << CFI.getOffset();734 break;735 case MCCFIInstruction::OpAdjustCfaOffset:736 OS << "adjust_cfa_offset ";737 if (MCSymbol *Label = CFI.getLabel())738 MachineOperand::printSymbol(OS, *Label);739 OS << CFI.getOffset();740 break;741 case MCCFIInstruction::OpRestore:742 OS << "restore ";743 if (MCSymbol *Label = CFI.getLabel())744 MachineOperand::printSymbol(OS, *Label);745 printCFIRegister(CFI.getRegister(), OS, TRI);746 break;747 case MCCFIInstruction::OpEscape: {748 OS << "escape ";749 if (MCSymbol *Label = CFI.getLabel())750 MachineOperand::printSymbol(OS, *Label);751 if (!CFI.getValues().empty()) {752 size_t e = CFI.getValues().size() - 1;753 for (size_t i = 0; i < e; ++i)754 OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";755 OS << format("0x%02x", uint8_t(CFI.getValues()[e]));756 }757 break;758 }759 case MCCFIInstruction::OpUndefined:760 OS << "undefined ";761 if (MCSymbol *Label = CFI.getLabel())762 MachineOperand::printSymbol(OS, *Label);763 printCFIRegister(CFI.getRegister(), OS, TRI);764 break;765 case MCCFIInstruction::OpRegister:766 OS << "register ";767 if (MCSymbol *Label = CFI.getLabel())768 MachineOperand::printSymbol(OS, *Label);769 printCFIRegister(CFI.getRegister(), OS, TRI);770 OS << ", ";771 printCFIRegister(CFI.getRegister2(), OS, TRI);772 break;773 case MCCFIInstruction::OpWindowSave:774 OS << "window_save ";775 if (MCSymbol *Label = CFI.getLabel())776 MachineOperand::printSymbol(OS, *Label);777 break;778 case MCCFIInstruction::OpNegateRAState:779 OS << "negate_ra_sign_state ";780 if (MCSymbol *Label = CFI.getLabel())781 MachineOperand::printSymbol(OS, *Label);782 break;783 case MCCFIInstruction::OpNegateRAStateWithPC:784 OS << "negate_ra_sign_state_with_pc ";785 if (MCSymbol *Label = CFI.getLabel())786 MachineOperand::printSymbol(OS, *Label);787 break;788 default:789 // TODO: Print the other CFI Operations.790 OS << "<unserializable cfi directive>";791 break;792 }793}794 795void MachineOperand::print(raw_ostream &OS,796 const TargetRegisterInfo *TRI) const {797 print(OS, LLT{}, TRI);798}799 800void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,801 const TargetRegisterInfo *TRI) const {802 tryToGetTargetInfo(*this, TRI);803 ModuleSlotTracker DummyMST(nullptr);804 print(OS, DummyMST, TypeToPrint, std::nullopt, /*PrintDef=*/false,805 /*IsStandalone=*/true,806 /*ShouldPrintRegisterTies=*/true,807 /*TiedOperandIdx=*/0, TRI);808}809 810void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,811 LLT TypeToPrint, std::optional<unsigned> OpIdx,812 bool PrintDef, bool IsStandalone,813 bool ShouldPrintRegisterTies,814 unsigned TiedOperandIdx,815 const TargetRegisterInfo *TRI) const {816 printTargetFlags(OS, *this);817 switch (getType()) {818 case MachineOperand::MO_Register: {819 Register Reg = getReg();820 if (isImplicit())821 OS << (isDef() ? "implicit-def " : "implicit ");822 else if (PrintDef && isDef())823 // Print the 'def' flag only when the operand is defined after '='.824 OS << "def ";825 if (isInternalRead())826 OS << "internal ";827 if (isDead())828 OS << "dead ";829 if (isKill())830 OS << "killed ";831 if (isUndef())832 OS << "undef ";833 if (isEarlyClobber())834 OS << "early-clobber ";835 if (getReg().isPhysical() && isRenamable())836 OS << "renamable ";837 // isDebug() is exactly true for register operands of a DBG_VALUE. So we838 // simply infer it when parsing and do not need to print it.839 840 const MachineRegisterInfo *MRI = nullptr;841 if (Reg.isVirtual()) {842 if (const MachineFunction *MF = getMFIfAvailable(*this)) {843 MRI = &MF->getRegInfo();844 }845 }846 847 OS << printReg(Reg, TRI, 0, MRI);848 // Print the sub register.849 if (unsigned SubReg = getSubReg()) {850 if (TRI)851 OS << '.' << TRI->getSubRegIndexName(SubReg);852 else853 OS << ".subreg" << SubReg;854 }855 // Print the register class / bank.856 if (Reg.isVirtual()) {857 if (const MachineFunction *MF = getMFIfAvailable(*this)) {858 const MachineRegisterInfo &MRI = MF->getRegInfo();859 if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {860 OS << ':';861 OS << printRegClassOrBank(Reg, MRI, TRI);862 }863 }864 }865 // Print ties.866 if (ShouldPrintRegisterTies && isTied() && !isDef())867 OS << "(tied-def " << TiedOperandIdx << ")";868 // Print types.869 if (TypeToPrint.isValid())870 OS << '(' << TypeToPrint << ')';871 break;872 }873 case MachineOperand::MO_Immediate: {874 const MIRFormatter *Formatter = nullptr;875 if (const MachineFunction *MF = getMFIfAvailable(*this)) {876 const auto *TII = MF->getSubtarget().getInstrInfo();877 assert(TII && "expected instruction info");878 Formatter = TII->getMIRFormatter();879 }880 if (Formatter)881 Formatter->printImm(OS, *getParent(), OpIdx, getImm());882 else883 OS << getImm();884 break;885 }886 case MachineOperand::MO_CImmediate:887 getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);888 break;889 case MachineOperand::MO_FPImmediate:890 getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);891 break;892 case MachineOperand::MO_MachineBasicBlock:893 OS << printMBBReference(*getMBB());894 break;895 case MachineOperand::MO_FrameIndex: {896 int FrameIndex = getIndex();897 bool IsFixed = false;898 const MachineFrameInfo *MFI = nullptr;899 if (const MachineFunction *MF = getMFIfAvailable(*this))900 MFI = &MF->getFrameInfo();901 printFrameIndex(OS, FrameIndex, IsFixed, MFI);902 break;903 }904 case MachineOperand::MO_ConstantPoolIndex:905 OS << "%const." << getIndex();906 printOperandOffset(OS, getOffset());907 break;908 case MachineOperand::MO_TargetIndex: {909 OS << "target-index(";910 const char *Name = "<unknown>";911 if (const MachineFunction *MF = getMFIfAvailable(*this))912 if (const auto *TargetIndexName = ::getTargetIndexName(*MF, getIndex()))913 Name = TargetIndexName;914 OS << Name << ')';915 printOperandOffset(OS, getOffset());916 break;917 }918 case MachineOperand::MO_JumpTableIndex:919 OS << printJumpTableEntryReference(getIndex());920 break;921 case MachineOperand::MO_GlobalAddress:922 if (auto *GV = getGlobal())923 GV->printAsOperand(OS, /*PrintType=*/false, MST);924 else // Invalid, but may appear in debugging scenarios.925 OS << "globaladdress(null)";926 927 printOperandOffset(OS, getOffset());928 break;929 case MachineOperand::MO_ExternalSymbol: {930 StringRef Name = getSymbolName();931 OS << '&';932 if (Name.empty()) {933 OS << "\"\"";934 } else {935 printLLVMNameWithoutPrefix(OS, Name);936 }937 printOperandOffset(OS, getOffset());938 break;939 }940 case MachineOperand::MO_BlockAddress: {941 OS << "blockaddress(";942 getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,943 MST);944 OS << ", ";945 printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);946 OS << ')';947 MachineOperand::printOperandOffset(OS, getOffset());948 break;949 }950 case MachineOperand::MO_RegisterMask: {951 OS << "<regmask";952 if (TRI) {953 unsigned NumRegsInMask = 0;954 unsigned NumRegsEmitted = 0;955 for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {956 unsigned MaskWord = i / 32;957 unsigned MaskBit = i % 32;958 if (getRegMask()[MaskWord] & (1 << MaskBit)) {959 if (PrintRegMaskNumRegs < 0 ||960 NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {961 OS << " " << printReg(i, TRI);962 NumRegsEmitted++;963 }964 NumRegsInMask++;965 }966 }967 if (NumRegsEmitted != NumRegsInMask)968 OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";969 } else {970 OS << " ...";971 }972 OS << ">";973 break;974 }975 case MachineOperand::MO_RegisterLiveOut: {976 const uint32_t *RegMask = getRegLiveOut();977 OS << "liveout(";978 if (!TRI) {979 OS << "<unknown>";980 } else {981 bool IsCommaNeeded = false;982 for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {983 if (RegMask[Reg / 32] & (1U << (Reg % 32))) {984 if (IsCommaNeeded)985 OS << ", ";986 OS << printReg(Reg, TRI);987 IsCommaNeeded = true;988 }989 }990 }991 OS << ")";992 break;993 }994 case MachineOperand::MO_Metadata:995 getMetadata()->printAsOperand(OS, MST);996 break;997 case MachineOperand::MO_MCSymbol:998 printSymbol(OS, *getMCSymbol());999 break;1000 case MachineOperand::MO_DbgInstrRef: {1001 OS << "dbg-instr-ref(" << getInstrRefInstrIndex() << ", "1002 << getInstrRefOpIndex() << ')';1003 break;1004 }1005 case MachineOperand::MO_CFIIndex: {1006 if (const MachineFunction *MF = getMFIfAvailable(*this))1007 printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);1008 else1009 OS << "<cfi directive>";1010 break;1011 }1012 case MachineOperand::MO_IntrinsicID: {1013 Intrinsic::ID ID = getIntrinsicID();1014 if (ID < Intrinsic::num_intrinsics)1015 OS << "intrinsic(@" << Intrinsic::getBaseName(ID) << ')';1016 else1017 OS << "intrinsic(" << ID << ')';1018 break;1019 }1020 case MachineOperand::MO_Predicate: {1021 auto Pred = static_cast<CmpInst::Predicate>(getPredicate());1022 OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("1023 << Pred << ')';1024 break;1025 }1026 case MachineOperand::MO_ShuffleMask:1027 OS << "shufflemask(";1028 ArrayRef<int> Mask = getShuffleMask();1029 StringRef Separator;1030 for (int Elt : Mask) {1031 if (Elt == -1)1032 OS << Separator << "undef";1033 else1034 OS << Separator << Elt;1035 Separator = ", ";1036 }1037 1038 OS << ')';1039 break;1040 }1041}1042 1043#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)1044LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }1045#endif1046 1047//===----------------------------------------------------------------------===//1048// MachineMemOperand Implementation1049//===----------------------------------------------------------------------===//1050 1051/// getAddrSpace - Return the LLVM IR address space number that this pointer1052/// points into.1053unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }1054 1055/// isDereferenceable - Return true if V is always dereferenceable for1056/// Offset + Size byte.1057bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,1058 const DataLayout &DL) const {1059 if (!isa<const Value *>(V))1060 return false;1061 1062 const Value *BasePtr = cast<const Value *>(V);1063 if (BasePtr == nullptr)1064 return false;1065 1066 return isDereferenceableAndAlignedPointer(1067 BasePtr, Align(1), APInt(DL.getPointerSizeInBits(), Offset + Size), DL,1068 dyn_cast<Instruction>(BasePtr));1069}1070 1071/// getConstantPool - Return a MachinePointerInfo record that refers to the1072/// constant pool.1073MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {1074 return MachinePointerInfo(MF.getPSVManager().getConstantPool());1075}1076 1077/// getFixedStack - Return a MachinePointerInfo record that refers to the1078/// the specified FrameIndex.1079MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,1080 int FI, int64_t Offset) {1081 return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);1082}1083 1084MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {1085 return MachinePointerInfo(MF.getPSVManager().getJumpTable());1086}1087 1088MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {1089 return MachinePointerInfo(MF.getPSVManager().getGOT());1090}1091 1092MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,1093 int64_t Offset, uint8_t ID) {1094 return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);1095}1096 1097MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {1098 return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());1099}1100 1101MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,1102 LLT type, Align a, const AAMDNodes &AAInfo,1103 const MDNode *Ranges, SyncScope::ID SSID,1104 AtomicOrdering Ordering,1105 AtomicOrdering FailureOrdering)1106 : PtrInfo(ptrinfo), MemoryType(type), FlagVals(f), BaseAlign(a),1107 AAInfo(AAInfo), Ranges(Ranges) {1108 assert((PtrInfo.V.isNull() || isa<const PseudoSourceValue *>(PtrInfo.V) ||1109 isa<PointerType>(cast<const Value *>(PtrInfo.V)->getType())) &&1110 "invalid pointer value");1111 assert((isLoad() || isStore()) && "Not a load/store!");1112 1113 AtomicInfo.SSID = static_cast<unsigned>(SSID);1114 assert(getSyncScopeID() == SSID && "Value truncated");1115 AtomicInfo.Ordering = static_cast<unsigned>(Ordering);1116 assert(getSuccessOrdering() == Ordering && "Value truncated");1117 AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);1118 assert(getFailureOrdering() == FailureOrdering && "Value truncated");1119}1120 1121MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags F,1122 LocationSize TS, Align BaseAlignment,1123 const AAMDNodes &AAInfo,1124 const MDNode *Ranges, SyncScope::ID SSID,1125 AtomicOrdering Ordering,1126 AtomicOrdering FailureOrdering)1127 : MachineMemOperand(1128 ptrinfo, F,1129 !TS.hasValue() ? LLT()1130 : TS.isScalable()1131 ? LLT::scalable_vector(1, 8 * TS.getValue().getKnownMinValue())1132 : LLT::scalar(8 * TS.getValue().getKnownMinValue()),1133 BaseAlignment, AAInfo, Ranges, SSID, Ordering, FailureOrdering) {}1134 1135void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {1136 // The Value and Offset may differ due to CSE. But the flags and size1137 // should be the same.1138 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");1139 assert((!MMO->getSize().hasValue() || !getSize().hasValue() ||1140 MMO->getSize() == getSize()) &&1141 "Size mismatch!");1142 if (MMO->getBaseAlign() >= getBaseAlign()) {1143 // Update the alignment value.1144 BaseAlign = MMO->getBaseAlign();1145 // Also update the base and offset, because the new alignment may1146 // not be applicable with the old ones.1147 PtrInfo = MMO->PtrInfo;1148 }1149}1150 1151/// getAlign - Return the minimum known alignment in bytes of the1152/// actual memory reference.1153Align MachineMemOperand::getAlign() const {1154 return commonAlignment(getBaseAlign(), getOffset());1155}1156 1157void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,1158 SmallVectorImpl<StringRef> &SSNs,1159 const LLVMContext &Context,1160 const MachineFrameInfo *MFI,1161 const TargetInstrInfo *TII) const {1162 OS << '(';1163 if (isVolatile())1164 OS << "volatile ";1165 if (isNonTemporal())1166 OS << "non-temporal ";1167 if (isDereferenceable())1168 OS << "dereferenceable ";1169 if (isInvariant())1170 OS << "invariant ";1171 if (TII) {1172 if (getFlags() & MachineMemOperand::MOTargetFlag1)1173 OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag1)1174 << "\" ";1175 if (getFlags() & MachineMemOperand::MOTargetFlag2)1176 OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag2)1177 << "\" ";1178 if (getFlags() & MachineMemOperand::MOTargetFlag3)1179 OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag3)1180 << "\" ";1181 if (getFlags() & MachineMemOperand::MOTargetFlag4)1182 OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag4)1183 << "\" ";1184 } else {1185 if (getFlags() & MachineMemOperand::MOTargetFlag1)1186 OS << "\"MOTargetFlag1\" ";1187 if (getFlags() & MachineMemOperand::MOTargetFlag2)1188 OS << "\"MOTargetFlag2\" ";1189 if (getFlags() & MachineMemOperand::MOTargetFlag3)1190 OS << "\"MOTargetFlag3\" ";1191 if (getFlags() & MachineMemOperand::MOTargetFlag4)1192 OS << "\"MOTargetFlag4\" ";1193 }1194 1195 assert((isLoad() || isStore()) &&1196 "machine memory operand must be a load or store (or both)");1197 if (isLoad())1198 OS << "load ";1199 if (isStore())1200 OS << "store ";1201 1202 printSyncScope(OS, Context, getSyncScopeID(), SSNs);1203 1204 if (getSuccessOrdering() != AtomicOrdering::NotAtomic)1205 OS << toIRString(getSuccessOrdering()) << ' ';1206 if (getFailureOrdering() != AtomicOrdering::NotAtomic)1207 OS << toIRString(getFailureOrdering()) << ' ';1208 1209 if (getMemoryType().isValid())1210 OS << '(' << getMemoryType() << ')';1211 else1212 OS << "unknown-size";1213 1214 if (const Value *Val = getValue()) {1215 OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");1216 MIRFormatter::printIRValue(OS, *Val, MST);1217 } else if (const PseudoSourceValue *PVal = getPseudoValue()) {1218 OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");1219 assert(PVal && "Expected a pseudo source value");1220 switch (PVal->kind()) {1221 case PseudoSourceValue::Stack:1222 OS << "stack";1223 break;1224 case PseudoSourceValue::GOT:1225 OS << "got";1226 break;1227 case PseudoSourceValue::JumpTable:1228 OS << "jump-table";1229 break;1230 case PseudoSourceValue::ConstantPool:1231 OS << "constant-pool";1232 break;1233 case PseudoSourceValue::FixedStack: {1234 int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();1235 bool IsFixed = true;1236 printFrameIndex(OS, FrameIndex, IsFixed, MFI);1237 break;1238 }1239 case PseudoSourceValue::GlobalValueCallEntry:1240 OS << "call-entry ";1241 cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(1242 OS, /*PrintType=*/false, MST);1243 break;1244 case PseudoSourceValue::ExternalSymbolCallEntry:1245 OS << "call-entry &";1246 printLLVMNameWithoutPrefix(1247 OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());1248 break;1249 default: {1250 // FIXME: This is not necessarily the correct MIR serialization format for1251 // a custom pseudo source value, but at least it allows1252 // MIR printing to work on a target with custom pseudo source1253 // values.1254 OS << "custom \"";1255 if (TII) {1256 const MIRFormatter *Formatter = TII->getMIRFormatter();1257 Formatter->printCustomPseudoSourceValue(OS, MST, *PVal);1258 } else {1259 PVal->printCustom(OS);1260 }1261 OS << '\"';1262 break;1263 }1264 }1265 } else if (getOpaqueValue() == nullptr && getOffset() != 0) {1266 OS << ((isLoad() && isStore()) ? " on "1267 : isLoad() ? " from "1268 : " into ")1269 << "unknown-address";1270 }1271 MachineOperand::printOperandOffset(OS, getOffset());1272 if (!getSize().hasValue() ||1273 (!getSize().isZero() &&1274 getAlign() != getSize().getValue().getKnownMinValue()))1275 OS << ", align " << getAlign().value();1276 if (getAlign() != getBaseAlign())1277 OS << ", basealign " << getBaseAlign().value();1278 auto AAInfo = getAAInfo();1279 if (AAInfo.TBAA) {1280 OS << ", !tbaa ";1281 AAInfo.TBAA->printAsOperand(OS, MST);1282 }1283 if (AAInfo.Scope) {1284 OS << ", !alias.scope ";1285 AAInfo.Scope->printAsOperand(OS, MST);1286 }1287 if (AAInfo.NoAlias) {1288 OS << ", !noalias ";1289 AAInfo.NoAlias->printAsOperand(OS, MST);1290 }1291 if (AAInfo.NoAliasAddrSpace) {1292 OS << ", !noalias.addrspace ";1293 AAInfo.NoAliasAddrSpace->printAsOperand(OS, MST);1294 }1295 if (getRanges()) {1296 OS << ", !range ";1297 getRanges()->printAsOperand(OS, MST);1298 }1299 // FIXME: Implement addrspace printing/parsing in MIR.1300 // For now, print this even though parsing it is not available in MIR.1301 if (unsigned AS = getAddrSpace())1302 OS << ", addrspace " << AS;1303 1304 OS << ')';1305}1306