677 lines · cpp
1//===- lib/Codegen/MachineRegisterInfo.cpp --------------------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// Implementation of the MachineRegisterInfo class.10//11//===----------------------------------------------------------------------===//12 13#include "llvm/CodeGen/MachineRegisterInfo.h"14#include "llvm/ADT/iterator_range.h"15#include "llvm/CodeGen/MachineBasicBlock.h"16#include "llvm/CodeGen/MachineFunction.h"17#include "llvm/CodeGen/MachineInstr.h"18#include "llvm/CodeGen/MachineInstrBuilder.h"19#include "llvm/CodeGen/MachineOperand.h"20#include "llvm/CodeGen/TargetInstrInfo.h"21#include "llvm/CodeGen/TargetRegisterInfo.h"22#include "llvm/CodeGen/TargetSubtargetInfo.h"23#include "llvm/Config/llvm-config.h"24#include "llvm/IR/Attributes.h"25#include "llvm/IR/DebugLoc.h"26#include "llvm/IR/Function.h"27#include "llvm/MC/MCRegisterInfo.h"28#include "llvm/Support/Casting.h"29#include "llvm/Support/CommandLine.h"30#include "llvm/Support/Compiler.h"31#include "llvm/Support/ErrorHandling.h"32#include "llvm/Support/raw_ostream.h"33#include <cassert>34 35using namespace llvm;36 37static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,38 cl::init(true), cl::desc("Enable subregister liveness tracking."));39 40// Pin the vtable to this file.41void MachineRegisterInfo::Delegate::anchor() {}42 43MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF)44 : MF(MF),45 TracksSubRegLiveness(EnableSubRegLiveness.getNumOccurrences()46 ? EnableSubRegLiveness47 : MF->getSubtarget().enableSubRegLiveness()) {48 unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();49 VRegInfo.reserve(256);50 UsedPhysRegMask.resize(NumRegs);51 PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());52 TheDelegates.clear();53}54 55/// setRegClass - Set the register class of the specified virtual register.56///57void58MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) {59 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");60 VRegInfo[Reg].first = RC;61}62 63void MachineRegisterInfo::setRegBank(Register Reg,64 const RegisterBank &RegBank) {65 VRegInfo[Reg].first = &RegBank;66}67 68static const TargetRegisterClass *69constrainRegClass(MachineRegisterInfo &MRI, Register Reg,70 const TargetRegisterClass *OldRC,71 const TargetRegisterClass *RC, unsigned MinNumRegs) {72 if (OldRC == RC)73 return RC;74 const TargetRegisterClass *NewRC =75 MRI.getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);76 if (!NewRC || NewRC == OldRC)77 return NewRC;78 if (NewRC->getNumRegs() < MinNumRegs)79 return nullptr;80 MRI.setRegClass(Reg, NewRC);81 return NewRC;82}83 84const TargetRegisterClass *MachineRegisterInfo::constrainRegClass(85 Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) {86 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs);87}88 89bool90MachineRegisterInfo::constrainRegAttrs(Register Reg,91 Register ConstrainingReg,92 unsigned MinNumRegs) {93 const LLT RegTy = getType(Reg);94 const LLT ConstrainingRegTy = getType(ConstrainingReg);95 if (RegTy.isValid() && ConstrainingRegTy.isValid() &&96 RegTy != ConstrainingRegTy)97 return false;98 const auto &ConstrainingRegCB = getRegClassOrRegBank(ConstrainingReg);99 if (!ConstrainingRegCB.isNull()) {100 const auto &RegCB = getRegClassOrRegBank(Reg);101 if (RegCB.isNull())102 setRegClassOrRegBank(Reg, ConstrainingRegCB);103 else if (isa<const TargetRegisterClass *>(RegCB) !=104 isa<const TargetRegisterClass *>(ConstrainingRegCB))105 return false;106 else if (isa<const TargetRegisterClass *>(RegCB)) {107 if (!::constrainRegClass(108 *this, Reg, cast<const TargetRegisterClass *>(RegCB),109 cast<const TargetRegisterClass *>(ConstrainingRegCB), MinNumRegs))110 return false;111 } else if (RegCB != ConstrainingRegCB)112 return false;113 }114 if (ConstrainingRegTy.isValid())115 setType(Reg, ConstrainingRegTy);116 return true;117}118 119bool120MachineRegisterInfo::recomputeRegClass(Register Reg) {121 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();122 const TargetRegisterClass *OldRC = getRegClass(Reg);123 const TargetRegisterInfo *TRI = getTargetRegisterInfo();124 const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC, *MF);125 126 // Stop early if there is no room to grow.127 if (NewRC == OldRC)128 return false;129 130 // Accumulate constraints from all uses.131 for (MachineOperand &MO : reg_nodbg_operands(Reg)) {132 // Apply the effect of the given operand to NewRC.133 MachineInstr *MI = MO.getParent();134 unsigned OpNo = &MO - &MI->getOperand(0);135 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII, TRI);136 if (!NewRC || NewRC == OldRC)137 return false;138 }139 setRegClass(Reg, NewRC);140 return true;141}142 143Register MachineRegisterInfo::createIncompleteVirtualRegister(StringRef Name) {144 Register Reg = Register::index2VirtReg(getNumVirtRegs());145 VRegInfo.grow(Reg);146 insertVRegByName(Name, Reg);147 return Reg;148}149 150/// createVirtualRegister - Create and return a new virtual register in the151/// function with the specified register class.152///153Register154MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass,155 StringRef Name) {156 assert(RegClass && "Cannot create register without RegClass!");157 assert(RegClass->isAllocatable() &&158 "Virtual register RegClass must be allocatable.");159 160 // New virtual register number.161 Register Reg = createIncompleteVirtualRegister(Name);162 VRegInfo[Reg].first = RegClass;163 noteNewVirtualRegister(Reg);164 return Reg;165}166 167Register MachineRegisterInfo::createVirtualRegister(VRegAttrs RegAttr,168 StringRef Name) {169 Register Reg = createIncompleteVirtualRegister(Name);170 VRegInfo[Reg].first = RegAttr.RCOrRB;171 setType(Reg, RegAttr.Ty);172 noteNewVirtualRegister(Reg);173 return Reg;174}175 176Register MachineRegisterInfo::cloneVirtualRegister(Register VReg,177 StringRef Name) {178 Register Reg = createIncompleteVirtualRegister(Name);179 VRegInfo[Reg].first = VRegInfo[VReg].first;180 setType(Reg, getType(VReg));181 noteCloneVirtualRegister(Reg, VReg);182 return Reg;183}184 185void MachineRegisterInfo::setType(Register VReg, LLT Ty) {186 VRegToType.grow(VReg);187 VRegToType[VReg] = Ty;188}189 190Register191MachineRegisterInfo::createGenericVirtualRegister(LLT Ty, StringRef Name) {192 // New virtual register number.193 Register Reg = createIncompleteVirtualRegister(Name);194 // FIXME: Should we use a dummy register class?195 VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr);196 setType(Reg, Ty);197 noteNewVirtualRegister(Reg);198 return Reg;199}200 201void MachineRegisterInfo::clearVirtRegTypes() { VRegToType.clear(); }202 203/// clearVirtRegs - Remove all virtual registers (after physreg assignment).204void MachineRegisterInfo::clearVirtRegs() {205#ifndef NDEBUG206 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {207 Register Reg = Register::index2VirtReg(i);208 if (!VRegInfo[Reg].second)209 continue;210 verifyUseList(Reg);211 errs() << "Remaining virtual register "212 << printReg(Reg, getTargetRegisterInfo()) << "...\n";213 for (MachineInstr &MI : reg_instructions(Reg))214 errs() << "...in instruction: " << MI << "\n";215 std::abort();216 }217#endif218 VRegInfo.clear();219 for (auto &I : LiveIns)220 I.second = 0;221}222 223void MachineRegisterInfo::verifyUseList(Register Reg) const {224#ifndef NDEBUG225 bool Valid = true;226 for (MachineOperand &M : reg_operands(Reg)) {227 MachineOperand *MO = &M;228 MachineInstr *MI = MO->getParent();229 if (!MI) {230 errs() << printReg(Reg, getTargetRegisterInfo())231 << " use list MachineOperand " << MO232 << " has no parent instruction.\n";233 Valid = false;234 continue;235 }236 MachineOperand *MO0 = &MI->getOperand(0);237 unsigned NumOps = MI->getNumOperands();238 if (!(MO >= MO0 && MO < MO0+NumOps)) {239 errs() << printReg(Reg, getTargetRegisterInfo())240 << " use list MachineOperand " << MO241 << " doesn't belong to parent MI: " << *MI;242 Valid = false;243 }244 if (!MO->isReg()) {245 errs() << printReg(Reg, getTargetRegisterInfo())246 << " MachineOperand " << MO << ": " << *MO247 << " is not a register\n";248 Valid = false;249 }250 if (MO->getReg() != Reg) {251 errs() << printReg(Reg, getTargetRegisterInfo())252 << " use-list MachineOperand " << MO << ": "253 << *MO << " is the wrong register\n";254 Valid = false;255 }256 }257 assert(Valid && "Invalid use list");258#endif259}260 261void MachineRegisterInfo::verifyUseLists() const {262#ifndef NDEBUG263 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)264 verifyUseList(Register::index2VirtReg(i));265 for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)266 verifyUseList(i);267#endif268}269 270/// Add MO to the linked list of operands for its register.271void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) {272 assert(!MO->isOnRegUseList() && "Already on list");273 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());274 MachineOperand *const Head = HeadRef;275 276 // Head points to the first list element.277 // Next is NULL on the last list element.278 // Prev pointers are circular, so Head->Prev == Last.279 280 // Head is NULL for an empty list.281 if (!Head) {282 MO->Contents.Reg.Prev = MO;283 MO->Contents.Reg.Next = nullptr;284 HeadRef = MO;285 return;286 }287 assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");288 289 // Insert MO between Last and Head in the circular Prev chain.290 MachineOperand *Last = Head->Contents.Reg.Prev;291 assert(Last && "Inconsistent use list");292 assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");293 Head->Contents.Reg.Prev = MO;294 MO->Contents.Reg.Prev = Last;295 296 // Def operands always precede uses. This allows def_iterator to stop early.297 // Insert def operands at the front, and use operands at the back.298 if (MO->isDef()) {299 // Insert def at the front.300 MO->Contents.Reg.Next = Head;301 HeadRef = MO;302 } else {303 // Insert use at the end.304 MO->Contents.Reg.Next = nullptr;305 Last->Contents.Reg.Next = MO;306 }307}308 309/// Remove MO from its use-def list.310void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) {311 assert(MO->isOnRegUseList() && "Operand not on use list");312 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());313 MachineOperand *const Head = HeadRef;314 assert(Head && "List already empty");315 316 // Unlink this from the doubly linked list of operands.317 MachineOperand *Next = MO->Contents.Reg.Next;318 MachineOperand *Prev = MO->Contents.Reg.Prev;319 320 // Prev links are circular, next link is NULL instead of looping back to Head.321 if (MO == Head)322 HeadRef = Next;323 else324 Prev->Contents.Reg.Next = Next;325 326 (Next ? Next : Head)->Contents.Reg.Prev = Prev;327 328 MO->Contents.Reg.Prev = nullptr;329 MO->Contents.Reg.Next = nullptr;330}331 332/// Move NumOps operands from Src to Dst, updating use-def lists as needed.333///334/// The Dst range is assumed to be uninitialized memory. (Or it may contain335/// operands that won't be destroyed, which is OK because the MO destructor is336/// trivial anyway).337///338/// The Src and Dst ranges may overlap.339void MachineRegisterInfo::moveOperands(MachineOperand *Dst,340 MachineOperand *Src,341 unsigned NumOps) {342 assert(Src != Dst && NumOps && "Noop moveOperands");343 344 // Copy backwards if Dst is within the Src range.345 int Stride = 1;346 if (Dst >= Src && Dst < Src + NumOps) {347 Stride = -1;348 Dst += NumOps - 1;349 Src += NumOps - 1;350 }351 352 // Copy one operand at a time.353 do {354 new (Dst) MachineOperand(*Src);355 356 // Dst takes Src's place in the use-def chain.357 if (Src->isReg()) {358 MachineOperand *&Head = getRegUseDefListHead(Src->getReg());359 MachineOperand *Prev = Src->Contents.Reg.Prev;360 MachineOperand *Next = Src->Contents.Reg.Next;361 assert(Head && "List empty, but operand is chained");362 assert(Prev && "Operand was not on use-def list");363 364 // Prev links are circular, next link is NULL instead of looping back to365 // Head.366 if (Src == Head)367 Head = Dst;368 else369 Prev->Contents.Reg.Next = Dst;370 371 // Update Prev pointer. This also works when Src was pointing to itself372 // in a 1-element list. In that case Head == Dst.373 (Next ? Next : Head)->Contents.Reg.Prev = Dst;374 }375 376 Dst += Stride;377 Src += Stride;378 } while (--NumOps);379}380 381/// replaceRegWith - Replace all instances of FromReg with ToReg in the382/// machine function. This is like llvm-level X->replaceAllUsesWith(Y),383/// except that it also changes any definitions of the register as well.384/// If ToReg is a physical register we apply the sub register to obtain the385/// final/proper physical register.386void MachineRegisterInfo::replaceRegWith(Register FromReg, Register ToReg) {387 assert(FromReg != ToReg && "Cannot replace a reg with itself");388 389 const TargetRegisterInfo *TRI = getTargetRegisterInfo();390 391 // TODO: This could be more efficient by bulk changing the operands.392 for (MachineOperand &O : llvm::make_early_inc_range(reg_operands(FromReg))) {393 if (ToReg.isPhysical()) {394 O.substPhysReg(ToReg, *TRI);395 } else {396 O.setReg(ToReg);397 }398 }399}400 401/// getVRegDef - Return the machine instr that defines the specified virtual402/// register or null if none is found. This assumes that the code is in SSA403/// form, so there should only be one definition.404MachineInstr *MachineRegisterInfo::getVRegDef(Register Reg) const {405 // Since we are in SSA form, we can use the first definition.406 def_instr_iterator I = def_instr_begin(Reg);407 if (I == def_instr_end())408 return nullptr;409 assert(std::next(I) == def_instr_end() &&410 "getVRegDef assumes at most one definition");411 return &*I;412}413 414/// getUniqueVRegDef - Return the unique machine instr that defines the415/// specified virtual register or null if none is found. If there are416/// multiple definitions or no definition, return null.417MachineInstr *MachineRegisterInfo::getUniqueVRegDef(Register Reg) const {418 if (def_empty(Reg)) return nullptr;419 def_instr_iterator I = def_instr_begin(Reg);420 if (std::next(I) != def_instr_end())421 return nullptr;422 return &*I;423}424 425bool MachineRegisterInfo::hasOneNonDBGUse(Register RegNo) const {426 return hasSingleElement(use_nodbg_operands(RegNo));427}428 429bool MachineRegisterInfo::hasOneNonDBGUser(Register RegNo) const {430 return hasSingleElement(use_nodbg_instructions(RegNo));431}432 433MachineOperand *MachineRegisterInfo::getOneNonDBGUse(Register RegNo) const {434 auto RegNoDbgUses = use_nodbg_operands(RegNo);435 return hasSingleElement(RegNoDbgUses) ? &*RegNoDbgUses.begin() : nullptr;436}437 438MachineInstr *MachineRegisterInfo::getOneNonDBGUser(Register RegNo) const {439 auto RegNoDbgUsers = use_nodbg_instructions(RegNo);440 return hasSingleElement(RegNoDbgUsers) ? &*RegNoDbgUsers.begin() : nullptr;441}442 443bool MachineRegisterInfo::hasAtMostUserInstrs(Register Reg,444 unsigned MaxUsers) const {445 return hasNItemsOrLess(use_instr_nodbg_begin(Reg), use_instr_nodbg_end(),446 MaxUsers);447}448 449/// clearKillFlags - Iterate over all the uses of the given register and450/// clear the kill flag from the MachineOperand. This function is used by451/// optimization passes which extend register lifetimes and need only452/// preserve conservative kill flag information.453void MachineRegisterInfo::clearKillFlags(Register Reg) const {454 for (MachineOperand &MO : use_operands(Reg))455 MO.setIsKill(false);456}457 458bool MachineRegisterInfo::isLiveIn(Register Reg) const {459 for (const std::pair<MCRegister, Register> &LI : liveins())460 if ((Register)LI.first == Reg || LI.second == Reg)461 return true;462 return false;463}464 465/// getLiveInPhysReg - If VReg is a live-in virtual register, return the466/// corresponding live-in physical register.467MCRegister MachineRegisterInfo::getLiveInPhysReg(Register VReg) const {468 for (const std::pair<MCRegister, Register> &LI : liveins())469 if (LI.second == VReg)470 return LI.first;471 return MCRegister();472}473 474/// getLiveInVirtReg - If PReg is a live-in physical register, return the475/// corresponding live-in physical register.476Register MachineRegisterInfo::getLiveInVirtReg(MCRegister PReg) const {477 for (const std::pair<MCRegister, Register> &LI : liveins())478 if (LI.first == PReg)479 return LI.second;480 return Register();481}482 483/// EmitLiveInCopies - Emit copies to initialize livein virtual registers484/// into the given entry block.485void486MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,487 const TargetRegisterInfo &TRI,488 const TargetInstrInfo &TII) {489 // Emit the copies into the top of the block.490 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)491 if (LiveIns[i].second) {492 if (use_nodbg_empty(LiveIns[i].second)) {493 // The livein has no non-dbg uses. Drop it.494 //495 // It would be preferable to have isel avoid creating live-in496 // records for unused arguments in the first place, but it's497 // complicated by the debug info code for arguments.498 LiveIns.erase(LiveIns.begin() + i);499 --i; --e;500 } else {501 // Emit a copy.502 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),503 TII.get(TargetOpcode::COPY), LiveIns[i].second)504 .addReg(LiveIns[i].first);505 506 // Add the register to the entry block live-in set.507 EntryMBB->addLiveIn(LiveIns[i].first);508 }509 } else {510 // Add the register to the entry block live-in set.511 EntryMBB->addLiveIn(LiveIns[i].first);512 }513}514 515LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(Register Reg) const {516 // Lane masks are only defined for vregs.517 assert(Reg.isVirtual());518 const TargetRegisterClass &TRC = *getRegClass(Reg);519 return TRC.getLaneMask();520}521 522#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)523LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses(Register Reg) const {524 for (MachineInstr &I : use_instructions(Reg))525 I.dump();526}527#endif528 529void MachineRegisterInfo::freezeReservedRegs() {530 ReservedRegs = getTargetRegisterInfo()->getReservedRegs(*MF);531 assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&532 "Invalid ReservedRegs vector from target");533}534 535bool MachineRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {536 assert(PhysReg.isPhysical());537 538 const TargetRegisterInfo *TRI = getTargetRegisterInfo();539 if (TRI->isConstantPhysReg(PhysReg))540 return true;541 542 // Check if any overlapping register is modified, or allocatable so it may be543 // used later.544 for (MCRegAliasIterator AI(PhysReg, TRI, true);545 AI.isValid(); ++AI)546 if (!def_empty(*AI) || isAllocatable(*AI))547 return false;548 return true;549}550 551/// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the552/// specified register as undefined which causes the DBG_VALUE to be553/// deleted during LiveDebugVariables analysis.554void MachineRegisterInfo::markUsesInDebugValueAsUndef(Register Reg) const {555 // Mark any DBG_VALUE* that uses Reg as undef (but don't delete it.)556 // We use make_early_inc_range because setReg invalidates the iterator.557 for (MachineInstr &UseMI : llvm::make_early_inc_range(use_instructions(Reg))) {558 if (UseMI.isDebugValue() && UseMI.hasDebugOperandForReg(Reg))559 UseMI.setDebugValueUndef();560 }561}562 563static const Function *getCalledFunction(const MachineInstr &MI) {564 for (const MachineOperand &MO : MI.operands()) {565 if (!MO.isGlobal())566 continue;567 const Function *Func = dyn_cast<Function>(MO.getGlobal());568 if (Func != nullptr)569 return Func;570 }571 return nullptr;572}573 574static bool isNoReturnDef(const MachineOperand &MO) {575 // Anything which is not a noreturn function is a real def.576 const MachineInstr &MI = *MO.getParent();577 if (!MI.isCall())578 return false;579 const MachineBasicBlock &MBB = *MI.getParent();580 if (!MBB.succ_empty())581 return false;582 const MachineFunction &MF = *MBB.getParent();583 // We need to keep correct unwind information even if the function will584 // not return, since the runtime may need it.585 if (MF.getFunction().hasFnAttribute(Attribute::UWTable))586 return false;587 const Function *Called = getCalledFunction(MI);588 return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) ||589 !Called->hasFnAttribute(Attribute::NoUnwind));590}591 592bool MachineRegisterInfo::isPhysRegModified(MCRegister PhysReg,593 bool SkipNoReturnDef) const {594 if (UsedPhysRegMask.test(PhysReg.id()))595 return true;596 const TargetRegisterInfo *TRI = getTargetRegisterInfo();597 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {598 for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) {599 if (!SkipNoReturnDef && isNoReturnDef(MO))600 continue;601 return true;602 }603 }604 return false;605}606 607bool MachineRegisterInfo::isPhysRegUsed(MCRegister PhysReg,608 bool SkipRegMaskTest) const {609 if (!SkipRegMaskTest && UsedPhysRegMask.test(PhysReg.id()))610 return true;611 const TargetRegisterInfo *TRI = getTargetRegisterInfo();612 for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid();613 ++AliasReg) {614 if (!reg_nodbg_empty(*AliasReg))615 return true;616 }617 return false;618}619 620void MachineRegisterInfo::disableCalleeSavedRegister(MCRegister Reg) {621 622 const TargetRegisterInfo *TRI = getTargetRegisterInfo();623 assert(Reg && (Reg < TRI->getNumRegs()) &&624 "Trying to disable an invalid register");625 626 if (!IsUpdatedCSRsInitialized) {627 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);628 for (const MCPhysReg *I = CSR; *I; ++I)629 UpdatedCSRs.push_back(*I);630 631 // Zero value represents the end of the register list632 // (no more registers should be pushed).633 UpdatedCSRs.push_back(0);634 635 IsUpdatedCSRsInitialized = true;636 }637 638 // Remove the register (and its aliases from the list).639 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)640 llvm::erase(UpdatedCSRs, *AI);641}642 643const MCPhysReg *MachineRegisterInfo::getCalleeSavedRegs() const {644 if (IsUpdatedCSRsInitialized)645 return UpdatedCSRs.data();646 647 const MCPhysReg *Regs = getTargetRegisterInfo()->getCalleeSavedRegs(MF);648 649 for (unsigned I = 0; Regs[I]; ++I)650 if (MF->getSubtarget().isRegisterReservedByUser(Regs[I]))651 MF->getRegInfo().disableCalleeSavedRegister(Regs[I]);652 653 return Regs;654}655 656void MachineRegisterInfo::setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs) {657 if (IsUpdatedCSRsInitialized)658 UpdatedCSRs.clear();659 660 append_range(UpdatedCSRs, CSRs);661 662 // Zero value represents the end of the register list663 // (no more registers should be pushed).664 UpdatedCSRs.push_back(0);665 IsUpdatedCSRsInitialized = true;666}667 668bool MachineRegisterInfo::isReservedRegUnit(MCRegUnit Unit) const {669 const TargetRegisterInfo *TRI = getTargetRegisterInfo();670 for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {671 if (all_of(TRI->superregs_inclusive(*Root),672 [&](MCPhysReg Super) { return isReserved(Super); }))673 return true;674 }675 return false;676}677